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GET /api/patches/74058/?format=api
{ "id": 74058, "url": "http://patches.dpdk.org/api/patches/74058/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1594794114-16313-17-git-send-email-viacheslavo@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1594794114-16313-17-git-send-email-viacheslavo@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1594794114-16313-17-git-send-email-viacheslavo@mellanox.com", "date": "2020-07-15T06:21:53", "name": "[v2,16/17] common/mlx5: add register access DevX routine", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "fc131ce85f721b4eb8d43da22027d415732e10d7", "submitter": { "id": 1102, "url": "http://patches.dpdk.org/api/people/1102/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1594794114-16313-17-git-send-email-viacheslavo@mellanox.com/mbox/", "series": [ { "id": 11032, "url": "http://patches.dpdk.org/api/series/11032/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11032", "date": "2020-07-15T06:21:37", "name": "net/mlx5: introduce accurate packet Tx scheduling", "version": 2, "mbox": "http://patches.dpdk.org/series/11032/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/74058/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/74058/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9BA89A0540;\n\tWed, 15 Jul 2020 08:24:44 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 494C61C1D0;\n\tWed, 15 Jul 2020 08:22:33 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id BAE321C19C\n for <dev@dpdk.org>; Wed, 15 Jul 2020 08:22:22 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n viacheslavo@mellanox.com) with SMTP; 15 Jul 2020 09:22:20 +0300", "from pegasus12.mtr.labs.mlnx (pegasus12.mtr.labs.mlnx\n [10.210.17.40])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 06F6MKZm007088;\n Wed, 15 Jul 2020 09:22:20 +0300", "from pegasus12.mtr.labs.mlnx (localhost [127.0.0.1])\n by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id 06F6MKUF016470;\n Wed, 15 Jul 2020 06:22:20 GMT", "(from viacheslavo@localhost)\n by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id 06F6MJe3016469;\n Wed, 15 Jul 2020 06:22:19 GMT" ], "X-Authentication-Warning": "pegasus12.mtr.labs.mlnx: viacheslavo set sender to\n viacheslavo@mellanox.com using -f", "From": "Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "To": "dev@dpdk.org", "Cc": "matan@mellanox.com, rasland@mellanox.com, olivier.matz@6wind.com,\n thomas@monjalon.net, ferruh.yigit@intel.com", "Date": "Wed, 15 Jul 2020 06:21:53 +0000", "Message-Id": "<1594794114-16313-17-git-send-email-viacheslavo@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1594794114-16313-1-git-send-email-viacheslavo@mellanox.com>", "References": "<1591771085-24959-1-git-send-email-viacheslavo@mellanox.com>\n <1594794114-16313-1-git-send-email-viacheslavo@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v2 16/17] common/mlx5: add register access DevX\n\troutine", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The DevX routine to read/write NIC registers via DevX API is added.\nThis is the preparation step to check timestamp modes and units\nand gather the extended statistics.\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 60 +++++++++++++++++++++++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 3 ++\n drivers/common/mlx5/mlx5_prm.h | 52 +++++++++++++++++++++\n drivers/common/mlx5/rte_common_mlx5_version.map | 1 +\n 4 files changed, 116 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 093636c..13cd76a 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -12,6 +12,66 @@\n \n \n /**\n+ * Perform read access to the registers. Reads data from register\n+ * and writes ones to the specified buffer.\n+ *\n+ * @param[in] ctx\n+ * Context returned from mlx5 open_device() glue function.\n+ * @param[in] reg_id\n+ * Register identifier according to the PRM.\n+ * @param[in] arg\n+ * Register access auxiliary parameter according to the PRM.\n+ * @param[out] data\n+ * Pointer to the buffer to store read data.\n+ * @param[in] dw_cnt\n+ * Buffer size in double words.\n+ *\n+ * @return\n+ * 0 on success, a negative value otherwise.\n+ */\n+int\n+mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,\n+\t\t\t uint32_t *data, uint32_t dw_cnt)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(access_register_out) +\n+\t\t MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};\n+\tint status, rc;\n+\n+\tMLX5_ASSERT(data && dw_cnt);\n+\tMLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);\n+\tif (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {\n+\t\tDRV_LOG(ERR, \"Not enough buffer for register read data\");\n+\t\treturn -1;\n+\t}\n+\tMLX5_SET(access_register_in, in, opcode, MLX5_CMD_OP_ACCESS_REGISTER);\n+\tMLX5_SET(access_register_in, in, op_mod,\n+\t\t\t\t\tMLX5_ACCESS_REGISTER_IN_OP_MOD_READ);\n+\tMLX5_SET(access_register_in, in, register_id, reg_id);\n+\tMLX5_SET(access_register_in, in, argument, arg);\n+\trc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,\n+\t\t\t\t\t MLX5_ST_SZ_DW(access_register_out) *\n+\t\t\t\t\t sizeof(uint32_t) + dw_cnt);\n+\tif (rc)\n+\t\tgoto error;\n+\tstatus = MLX5_GET(access_register_out, out, status);\n+\tif (status) {\n+\t\tint syndrome = MLX5_GET(access_register_out, out, syndrome);\n+\n+\t\tDRV_LOG(DEBUG, \"Failed to access NIC register 0x%X, \"\n+\t\t\t \"status %x, syndrome = %x\",\n+\t\t\t reg_id, status, syndrome);\n+\t\treturn -1;\n+\t}\n+\tmemcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],\n+\t dw_cnt * sizeof(uint32_t));\n+\treturn 0;\n+error:\n+\trc = (rc > 0) ? -rc : rc;\n+\treturn rc;\n+}\n+\n+/**\n * Allocate flow counters via devx interface.\n *\n * @param[in] ctx\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex c79b349..34482e1 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -383,6 +383,9 @@ int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,\n int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,\n \t\t\t struct mlx5_devx_rqt_attr *rqt_attr);\n \n+__rte_internal\n+int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id,\n+\t\t\t\tuint32_t arg, uint32_t *data, uint32_t dw_cnt);\n /**\n * Create virtio queue counters object DevX API.\n *\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex cf47103..b37be30 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -776,6 +776,7 @@ enum {\n \tMLX5_CMD_OP_SUSPEND_QP = 0x50F,\n \tMLX5_CMD_OP_RESUME_QP = 0x510,\n \tMLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,\n+\tMLX5_CMD_OP_ACCESS_REGISTER = 0x805,\n \tMLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,\n \tMLX5_CMD_OP_CREATE_TIR = 0x900,\n \tMLX5_CMD_OP_CREATE_SQ = 0X904,\n@@ -2545,6 +2546,57 @@ struct mlx5_ifc_set_pp_rate_limit_context_bits {\n \tu8 reserved_at_60[0x120];\n };\n \n+#define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u\n+\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic ignored \"-Wpedantic\"\n+#endif\n+struct mlx5_ifc_access_register_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x40];\n+\tu8 register_data[0][0x20];\n+};\n+\n+struct mlx5_ifc_access_register_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 reserved_at_10[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x10];\n+\tu8 register_id[0x10];\n+\tu8 argument[0x20];\n+\tu8 register_data[0][0x20];\n+};\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic error \"-Wpedantic\"\n+#endif\n+\n+enum {\n+\tMLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,\n+\tMLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,\n+};\n+\n+enum {\n+\tMLX5_REGISTER_ID_MTUTC = 0x9055,\n+};\n+\n+struct mlx5_ifc_register_mtutc_bits {\n+\tu8 time_stamp_mode[0x2];\n+\tu8 time_stamp_state[0x2];\n+\tu8 reserved_at_4[0x18];\n+\tu8 operation[0x4];\n+\tu8 freq_adjustment[0x20];\n+\tu8 reserved_at_40[0x40];\n+\tu8 utc_sec[0x20];\n+\tu8 utc_nsec[0x20];\n+\tu8 time_adjustment[0x20];\n+};\n+\n+#define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0\n+#define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1\n+\n /* CQE format mask. */\n #define MLX5E_CQE_FORMAT_MASK 0xc\n \ndiff --git a/drivers/common/mlx5/rte_common_mlx5_version.map b/drivers/common/mlx5/rte_common_mlx5_version.map\nindex ae57ebd..68007ef 100644\n--- a/drivers/common/mlx5/rte_common_mlx5_version.map\n+++ b/drivers/common/mlx5/rte_common_mlx5_version.map\n@@ -34,6 +34,7 @@ INTERNAL {\n \tmlx5_devx_cmd_query_hca_attr;\n \tmlx5_devx_cmd_query_virtio_q_counters;\n \tmlx5_devx_cmd_query_virtq;\n+\tmlx5_devx_cmd_register_read;\n \tmlx5_devx_get_out_command_status;\n \n \tmlx5_get_ifname_sysfs;\n", "prefixes": [ "v2", "16/17" ] }