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GET /api/patches/74057/?format=api
{ "id": 74057, "url": "http://patches.dpdk.org/api/patches/74057/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1594794114-16313-14-git-send-email-viacheslavo@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1594794114-16313-14-git-send-email-viacheslavo@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1594794114-16313-14-git-send-email-viacheslavo@mellanox.com", "date": "2020-07-15T06:21:50", "name": "[v2,13/17] net/mlx5: add scheduling support to send routine template", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "bc0f4df5002106bf06fa75a92539a9137569709f", "submitter": { "id": 1102, "url": "http://patches.dpdk.org/api/people/1102/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1594794114-16313-14-git-send-email-viacheslavo@mellanox.com/mbox/", "series": [ { "id": 11032, "url": "http://patches.dpdk.org/api/series/11032/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11032", "date": "2020-07-15T06:21:37", "name": "net/mlx5: introduce accurate packet Tx scheduling", "version": 2, "mbox": "http://patches.dpdk.org/series/11032/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/74057/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/74057/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 658E1A0540;\n\tWed, 15 Jul 2020 08:24:36 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id EA7A91C1C6;\n\tWed, 15 Jul 2020 08:22:31 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id A153A1C199\n for <dev@dpdk.org>; Wed, 15 Jul 2020 08:22:22 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n viacheslavo@mellanox.com) with SMTP; 15 Jul 2020 09:22:17 +0300", "from pegasus12.mtr.labs.mlnx (pegasus12.mtr.labs.mlnx\n [10.210.17.40])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 06F6MHai007065;\n Wed, 15 Jul 2020 09:22:17 +0300", "from pegasus12.mtr.labs.mlnx (localhost [127.0.0.1])\n by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id 06F6MHfS016455;\n Wed, 15 Jul 2020 06:22:17 GMT", "(from viacheslavo@localhost)\n by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id 06F6MHch016454;\n Wed, 15 Jul 2020 06:22:17 GMT" ], "X-Authentication-Warning": "pegasus12.mtr.labs.mlnx: viacheslavo set sender to\n viacheslavo@mellanox.com using -f", "From": "Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "To": "dev@dpdk.org", "Cc": "matan@mellanox.com, rasland@mellanox.com, olivier.matz@6wind.com,\n thomas@monjalon.net, ferruh.yigit@intel.com", "Date": "Wed, 15 Jul 2020 06:21:50 +0000", "Message-Id": "<1594794114-16313-14-git-send-email-viacheslavo@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1594794114-16313-1-git-send-email-viacheslavo@mellanox.com>", "References": "<1591771085-24959-1-git-send-email-viacheslavo@mellanox.com>\n <1594794114-16313-1-git-send-email-viacheslavo@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v2 13/17] net/mlx5: add scheduling support to\n\tsend routine template", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds send scheduling on timestamps into tx_burst\nroutine template. The feature is controlled by static configuration\nflag, the actual routines supporting the new feature are generated\nover this updated template.\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/net/mlx5/mlx5_rxtx.c | 162 ++++++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 161 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex 76fe12b..e511142 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -2404,6 +2404,37 @@ enum mlx5_txcmp_code {\n }\n \n /**\n+ * Build the Synchronize Queue Segment with specified completion index.\n+ *\n+ * @param txq\n+ * Pointer to TX queue structure.\n+ * @param loc\n+ * Pointer to burst routine local context.\n+ * @param wqe\n+ * Pointer to WQE to fill with built Control Segment.\n+ * @param wci\n+ * Completion index in Clock Queue to wait.\n+ * @param olx\n+ * Configured Tx offloads mask. It is fully defined at\n+ * compile time and may be used for optimization.\n+ */\n+static __rte_always_inline void\n+mlx5_tx_wseg_init(struct mlx5_txq_data *restrict txq,\n+\t\t struct mlx5_txq_local *restrict loc __rte_unused,\n+\t\t struct mlx5_wqe *restrict wqe,\n+\t\t unsigned int wci,\n+\t\t unsigned int olx __rte_unused)\n+{\n+\tstruct mlx5_wqe_qseg *qs;\n+\n+\tqs = RTE_PTR_ADD(wqe, MLX5_WSEG_SIZE);\n+\tqs->max_index = rte_cpu_to_be_32(wci);\n+\tqs->qpn_cqn = rte_cpu_to_be_32(txq->sh->txpp.clock_queue.cq->id);\n+\tqs->reserved0 = RTE_BE32(0);\n+\tqs->reserved1 = RTE_BE32(0);\n+}\n+\n+/**\n * Build the Ethernet Segment without inlined data.\n * Supports Software Parser, Checksums and VLAN\n * insertion Tx offload features.\n@@ -3241,6 +3272,59 @@ enum mlx5_txcmp_code {\n }\n \n /**\n+ * The routine checks timestamp flag in the current packet,\n+ * and push WAIT WQE into the queue if scheduling is required.\n+ *\n+ * @param txq\n+ * Pointer to TX queue structure.\n+ * @param loc\n+ * Pointer to burst routine local context.\n+ * @param olx\n+ * Configured Tx offloads mask. It is fully defined at\n+ * compile time and may be used for optimization.\n+ *\n+ * @return\n+ * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.\n+ * MLX5_TXCMP_CODE_SINGLE - continue processing with the packet.\n+ * MLX5_TXCMP_CODE_MULTI - the WAIT inserted, continue processing.\n+ * Local context variables partially updated.\n+ */\n+static __rte_always_inline enum mlx5_txcmp_code\n+mlx5_tx_schedule_send(struct mlx5_txq_data *restrict txq,\n+\t\t struct mlx5_txq_local *restrict loc,\n+\t\t unsigned int olx)\n+{\n+\tif (MLX5_TXOFF_CONFIG(TXPP) &&\n+\t loc->mbuf->ol_flags & txq->ts_mask) {\n+\t\tstruct mlx5_wqe *wqe;\n+\t\tuint64_t ts;\n+\t\tint32_t wci;\n+\n+\t\t/*\n+\t\t * Estimate the required space quickly and roughly.\n+\t\t * We would like to ensure the packet can be pushed\n+\t\t * to the queue and we won't get the orphan WAIT WQE.\n+\t\t */\n+\t\tif (loc->wqe_free <= MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE ||\n+\t\t loc->elts_free < NB_SEGS(loc->mbuf))\n+\t\t\treturn MLX5_TXCMP_CODE_EXIT;\n+\t\t/* Convert the timestamp into completion to wait. */\n+\t\tts = *RTE_MBUF_DYNFIELD(loc->mbuf, txq->ts_offset, uint64_t *);\n+\t\twci = mlx5_txpp_convert_tx_ts(txq->sh, ts);\n+\t\tif (unlikely(wci < 0))\n+\t\t\treturn MLX5_TXCMP_CODE_SINGLE;\n+\t\t/* Build the WAIT WQE with specified completion. */\n+\t\twqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);\n+\t\tmlx5_tx_cseg_init(txq, loc, wqe, 2, MLX5_OPCODE_WAIT, olx);\n+\t\tmlx5_tx_wseg_init(txq, loc, wqe, wci, olx);\n+\t\t++txq->wqe_ci;\n+\t\t--loc->wqe_free;\n+\t\treturn MLX5_TXCMP_CODE_MULTI;\n+\t}\n+\treturn MLX5_TXCMP_CODE_SINGLE;\n+}\n+\n+/**\n * Tx one packet function for multi-segment TSO. Supports all\n * types of Tx offloads, uses MLX5_OPCODE_TSO to build WQEs,\n * sends one packet per WQE.\n@@ -3269,6 +3353,16 @@ enum mlx5_txcmp_code {\n \tstruct mlx5_wqe *__rte_restrict wqe;\n \tunsigned int ds, dlen, inlen, ntcp, vlan = 0;\n \n+\tif (MLX5_TXOFF_CONFIG(TXPP)) {\n+\t\tenum mlx5_txcmp_code wret;\n+\n+\t\t/* Generate WAIT for scheduling if requested. */\n+\t\twret = mlx5_tx_schedule_send(txq, loc, olx);\n+\t\tif (wret == MLX5_TXCMP_CODE_EXIT)\n+\t\t\treturn MLX5_TXCMP_CODE_EXIT;\n+\t\tif (wret == MLX5_TXCMP_CODE_ERROR)\n+\t\t\treturn MLX5_TXCMP_CODE_ERROR;\n+\t}\n \t/*\n \t * Calculate data length to be inlined to estimate\n \t * the required space in WQE ring buffer.\n@@ -3360,6 +3454,16 @@ enum mlx5_txcmp_code {\n \tunsigned int ds, nseg;\n \n \tMLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);\n+\tif (MLX5_TXOFF_CONFIG(TXPP)) {\n+\t\tenum mlx5_txcmp_code wret;\n+\n+\t\t/* Generate WAIT for scheduling if requested. */\n+\t\twret = mlx5_tx_schedule_send(txq, loc, olx);\n+\t\tif (wret == MLX5_TXCMP_CODE_EXIT)\n+\t\t\treturn MLX5_TXCMP_CODE_EXIT;\n+\t\tif (wret == MLX5_TXCMP_CODE_ERROR)\n+\t\t\treturn MLX5_TXCMP_CODE_ERROR;\n+\t}\n \t/*\n \t * No inline at all, it means the CPU cycles saving\n \t * is prioritized at configuration, we should not\n@@ -3468,6 +3572,16 @@ enum mlx5_txcmp_code {\n \n \tMLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));\n \tMLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);\n+\tif (MLX5_TXOFF_CONFIG(TXPP)) {\n+\t\tenum mlx5_txcmp_code wret;\n+\n+\t\t/* Generate WAIT for scheduling if requested. */\n+\t\twret = mlx5_tx_schedule_send(txq, loc, olx);\n+\t\tif (wret == MLX5_TXCMP_CODE_EXIT)\n+\t\t\treturn MLX5_TXCMP_CODE_EXIT;\n+\t\tif (wret == MLX5_TXCMP_CODE_ERROR)\n+\t\t\treturn MLX5_TXCMP_CODE_ERROR;\n+\t}\n \t/*\n \t * First calculate data length to be inlined\n \t * to estimate the required space for WQE.\n@@ -3730,6 +3844,16 @@ enum mlx5_txcmp_code {\n \t\tuint8_t *dptr;\n \n \t\tMLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);\n+\t\tif (MLX5_TXOFF_CONFIG(TXPP)) {\n+\t\t\tenum mlx5_txcmp_code wret;\n+\n+\t\t\t/* Generate WAIT for scheduling if requested. */\n+\t\t\twret = mlx5_tx_schedule_send(txq, loc, olx);\n+\t\t\tif (wret == MLX5_TXCMP_CODE_EXIT)\n+\t\t\t\treturn MLX5_TXCMP_CODE_EXIT;\n+\t\t\tif (wret == MLX5_TXCMP_CODE_ERROR)\n+\t\t\t\treturn MLX5_TXCMP_CODE_ERROR;\n+\t\t}\n \t\tdlen = rte_pktmbuf_data_len(loc->mbuf);\n \t\tif (MLX5_TXOFF_CONFIG(VLAN) &&\n \t\t loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {\n@@ -3892,7 +4016,7 @@ enum mlx5_txcmp_code {\n * false - no match, eMPW should be restarted.\n */\n static __rte_always_inline bool\n-mlx5_tx_match_empw(struct mlx5_txq_data *__rte_restrict txq __rte_unused,\n+mlx5_tx_match_empw(struct mlx5_txq_data *__rte_restrict txq,\n \t\t struct mlx5_wqe_eseg *__rte_restrict es,\n \t\t struct mlx5_txq_local *__rte_restrict loc,\n \t\t uint32_t dlen,\n@@ -3921,6 +4045,10 @@ enum mlx5_txcmp_code {\n \t/* There must be no VLAN packets in eMPW loop. */\n \tif (MLX5_TXOFF_CONFIG(VLAN))\n \t\tMLX5_ASSERT(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));\n+\t/* Check if the scheduling is requested. */\n+\tif (MLX5_TXOFF_CONFIG(TXPP) &&\n+\t loc->mbuf->ol_flags & txq->ts_mask)\n+\t\treturn false;\n \treturn true;\n }\n \n@@ -4106,6 +4234,16 @@ enum mlx5_txcmp_code {\n \n next_empw:\n \t\tMLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);\n+\t\tif (MLX5_TXOFF_CONFIG(TXPP)) {\n+\t\t\tenum mlx5_txcmp_code wret;\n+\n+\t\t\t/* Generate WAIT for scheduling if requested. */\n+\t\t\twret = mlx5_tx_schedule_send(txq, loc, olx);\n+\t\t\tif (wret == MLX5_TXCMP_CODE_EXIT)\n+\t\t\t\treturn MLX5_TXCMP_CODE_EXIT;\n+\t\t\tif (wret == MLX5_TXCMP_CODE_ERROR)\n+\t\t\t\treturn MLX5_TXCMP_CODE_ERROR;\n+\t\t}\n \t\tpart = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?\n \t\t\t\t MLX5_MPW_MAX_PACKETS :\n \t\t\t\t MLX5_EMPW_MAX_PACKETS);\n@@ -4201,6 +4339,7 @@ enum mlx5_txcmp_code {\n \t\t\t * - metadata value\n \t\t\t * - software parser settings\n \t\t\t * - packets length (legacy MPW only)\n+\t\t\t * - scheduling is not required\n \t\t\t */\n \t\t\tif (!mlx5_tx_match_empw(txq, eseg, loc, dlen, olx)) {\n \t\t\t\tMLX5_ASSERT(loop);\n@@ -4271,6 +4410,16 @@ enum mlx5_txcmp_code {\n \t\tunsigned int slen = 0;\n \n \t\tMLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);\n+\t\tif (MLX5_TXOFF_CONFIG(TXPP)) {\n+\t\t\tenum mlx5_txcmp_code wret;\n+\n+\t\t\t/* Generate WAIT for scheduling if requested. */\n+\t\t\twret = mlx5_tx_schedule_send(txq, loc, olx);\n+\t\t\tif (wret == MLX5_TXCMP_CODE_EXIT)\n+\t\t\t\treturn MLX5_TXCMP_CODE_EXIT;\n+\t\t\tif (wret == MLX5_TXCMP_CODE_ERROR)\n+\t\t\t\treturn MLX5_TXCMP_CODE_ERROR;\n+\t\t}\n \t\t/*\n \t\t * Limits the amount of packets in one WQE\n \t\t * to improve CQE latency generation.\n@@ -4496,6 +4645,7 @@ enum mlx5_txcmp_code {\n \t\t\t * - metadata value\n \t\t\t * - software parser settings\n \t\t\t * - packets length (legacy MPW only)\n+\t\t\t * - scheduling is not required\n \t\t\t */\n \t\t\tif (!mlx5_tx_match_empw(txq, &wqem->eseg,\n \t\t\t\t\t\tloc, dlen, olx))\n@@ -4545,6 +4695,16 @@ enum mlx5_txcmp_code {\n \t\tenum mlx5_txcmp_code ret;\n \n \t\tMLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);\n+\t\tif (MLX5_TXOFF_CONFIG(TXPP)) {\n+\t\t\tenum mlx5_txcmp_code wret;\n+\n+\t\t\t/* Generate WAIT for scheduling if requested. */\n+\t\t\twret = mlx5_tx_schedule_send(txq, loc, olx);\n+\t\t\tif (wret == MLX5_TXCMP_CODE_EXIT)\n+\t\t\t\treturn MLX5_TXCMP_CODE_EXIT;\n+\t\t\tif (wret == MLX5_TXCMP_CODE_ERROR)\n+\t\t\t\treturn MLX5_TXCMP_CODE_ERROR;\n+\t\t}\n \t\tif (MLX5_TXOFF_CONFIG(INLINE)) {\n \t\t\tunsigned int inlen, vlan = 0;\n \n", "prefixes": [ "v2", "13/17" ] }