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GET /api/patches/74056/?format=api
{ "id": 74056, "url": "http://patches.dpdk.org/api/patches/74056/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1594794114-16313-16-git-send-email-viacheslavo@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1594794114-16313-16-git-send-email-viacheslavo@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1594794114-16313-16-git-send-email-viacheslavo@mellanox.com", "date": "2020-07-15T06:21:52", "name": "[v2,15/17] net/mlx5: provide the send scheduling error statistics", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b29a41d69a41f0fa1bff3b0c9fdda465c62a1711", "submitter": { "id": 1102, "url": "http://patches.dpdk.org/api/people/1102/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1594794114-16313-16-git-send-email-viacheslavo@mellanox.com/mbox/", "series": [ { "id": 11032, "url": "http://patches.dpdk.org/api/series/11032/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11032", "date": "2020-07-15T06:21:37", "name": "net/mlx5: introduce accurate packet Tx scheduling", "version": 2, "mbox": "http://patches.dpdk.org/series/11032/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/74056/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/74056/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 613A2A0540;\n\tWed, 15 Jul 2020 08:24:26 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B3EB51C1BD;\n\tWed, 15 Jul 2020 08:22:30 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id B02FC1C19B\n for <dev@dpdk.org>; Wed, 15 Jul 2020 08:22:22 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n viacheslavo@mellanox.com) with SMTP; 15 Jul 2020 09:22:19 +0300", "from pegasus12.mtr.labs.mlnx (pegasus12.mtr.labs.mlnx\n [10.210.17.40])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 06F6MJHT007073;\n Wed, 15 Jul 2020 09:22:19 +0300", "from pegasus12.mtr.labs.mlnx (localhost [127.0.0.1])\n by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id 06F6MJw1016468;\n Wed, 15 Jul 2020 06:22:19 GMT", "(from viacheslavo@localhost)\n by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id 06F6MJdi016467;\n Wed, 15 Jul 2020 06:22:19 GMT" ], "X-Authentication-Warning": "pegasus12.mtr.labs.mlnx: viacheslavo set sender to\n viacheslavo@mellanox.com using -f", "From": "Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "To": "dev@dpdk.org", "Cc": "matan@mellanox.com, rasland@mellanox.com, olivier.matz@6wind.com,\n thomas@monjalon.net, ferruh.yigit@intel.com", "Date": "Wed, 15 Jul 2020 06:21:52 +0000", "Message-Id": "<1594794114-16313-16-git-send-email-viacheslavo@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1594794114-16313-1-git-send-email-viacheslavo@mellanox.com>", "References": "<1591771085-24959-1-git-send-email-viacheslavo@mellanox.com>\n <1594794114-16313-1-git-send-email-viacheslavo@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v2 15/17] net/mlx5: provide the send scheduling\n\terror statistics", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The mlx5 PMD exposes the following new introduced\nextended statistics counter to report the errors\nof packet send scheduling on timestamps:\n\n - txpp_err_miss_int - rearm queue interrupt was not handled\n was not handled in time and service routine might miss\n the completions\n\n - txpp_err_rearm_queue - reports errors in rearm queue\n - txpp_err_clock_queue - reports errors in clock queue\n\n - txpp_err_ts_past - timestamps in the packet being sent\n were found in the past, timestamps were ignored\n\n - txpp_err_ts_future - timestamps in the packet being sent\n were found in the too distant future (beyond HW/clock queue\n capabilities to schedule, typically it is about 16M of\n tx_pp devarg periods)\n\n - txpp_jitter - estimated jitter in device clocks between\n 8K completions of Clock Queue.\n\n - txpp_wander - estimated wander in device clocks between\n 16M completions of Clock Queue.\n\n - txpp_sync_lost - error flag, the Clock Queue completions\n synchronization is lost, accurate packet scheduling can\n not be handled, timestamps are being ignored, the restart\n of all ports using scheduling must be performed.\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/net/mlx5/mlx5.h | 7 ++\n drivers/net/mlx5/mlx5_stats.c | 7 +-\n drivers/net/mlx5/mlx5_txpp.c | 220 ++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 232 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex f1246b8..97a14fb 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1011,5 +1011,12 @@ void mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb,\n int mlx5_txpp_start(struct rte_eth_dev *dev);\n void mlx5_txpp_stop(struct rte_eth_dev *dev);\n int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp);\n+int mlx5_txpp_xstats_get(struct rte_eth_dev *dev,\n+\t\t\t struct rte_eth_xstat *stats,\n+\t\t\t unsigned int n, unsigned int n_used);\n+int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev);\n+int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev,\n+\t\t\t struct rte_eth_xstat_name *xstats_names,\n+\t\t\t unsigned int n, unsigned int n_used);\n \n #endif /* RTE_PMD_MLX5_H_ */\ndiff --git a/drivers/net/mlx5/mlx5_stats.c b/drivers/net/mlx5/mlx5_stats.c\nindex a9b33ee..e30542e 100644\n--- a/drivers/net/mlx5/mlx5_stats.c\n+++ b/drivers/net/mlx5/mlx5_stats.c\n@@ -75,6 +75,7 @@\n \t\t\t}\n \t\t}\n \t}\n+\tmlx5_stats_n = mlx5_txpp_xstats_get(dev, stats, n, mlx5_stats_n);\n \treturn mlx5_stats_n;\n }\n \n@@ -237,7 +238,7 @@\n \t\txstats_ctrl->base[i] = counters[i];\n \t\txstats_ctrl->hw_stats[i] = 0;\n \t}\n-\n+\tmlx5_txpp_xstats_reset(dev);\n \treturn 0;\n }\n \n@@ -255,7 +256,7 @@\n * Number of xstats names.\n */\n int\n-mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,\n+mlx5_xstats_get_names(struct rte_eth_dev *dev,\n \t\t struct rte_eth_xstat_name *xstats_names, unsigned int n)\n {\n \tunsigned int i;\n@@ -271,5 +272,7 @@\n \t\t\txstats_names[i].name[RTE_ETH_XSTATS_NAME_SIZE - 1] = 0;\n \t\t}\n \t}\n+\tmlx5_xstats_n = mlx5_txpp_xstats_get_names(dev, xstats_names,\n+\t\t\t\t\t\t n, mlx5_xstats_n);\n \treturn mlx5_xstats_n;\n }\ndiff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c\nindex d0916de..5000e47 100644\n--- a/drivers/net/mlx5/mlx5_txpp.c\n+++ b/drivers/net/mlx5/mlx5_txpp.c\n@@ -15,6 +15,17 @@\n #include \"mlx5_rxtx.h\"\n #include \"mlx5_common_os.h\"\n \n+static const char * const mlx5_txpp_stat_names[] = {\n+\t\"txpp_err_miss_int\", /* Missed service interrupt. */\n+\t\"txpp_err_rearm_queue\",\t/* Rearm Queue errors. */\n+\t\"txpp_err_clock_queue\", /* Clock Queue errors. */\n+\t\"txpp_err_ts_past\", /* Timestamp in the past. */\n+\t\"txpp_err_ts_future\", /* Timestamp in the distant future. */\n+\t\"txpp_jitter\", /* Timestamp jitter (one Clock Queue completion). */\n+\t\"txpp_wander\", /* Timestamp jitter (half of Clock Queue completions). */\n+\t\"txpp_sync_lost\", /* Scheduling synchronization lost. */\n+};\n+\n /* Destroy Event Queue Notification Channel. */\n static void\n mlx5_txpp_destroy_eqn(struct mlx5_dev_ctx_shared *sh)\n@@ -1111,3 +1122,212 @@\n \tret = mlx5_read_clock(dev, timestamp);\n \treturn ret;\n }\n+\n+/**\n+ * DPDK callback to clear device extended statistics.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ *\n+ * @return\n+ * 0 on success and stats is reset, negative errno value otherwise and\n+ * rte_errno is set.\n+ */\n+int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n+\n+\trte_atomic32_set(&sh->txpp.err_miss_int, 0);\n+\trte_atomic32_set(&sh->txpp.err_rearm_queue, 0);\n+\trte_atomic32_set(&sh->txpp.err_clock_queue, 0);\n+\trte_atomic32_set(&sh->txpp.err_ts_past, 0);\n+\trte_atomic32_set(&sh->txpp.err_ts_future, 0);\n+\treturn 0;\n+}\n+\n+/**\n+ * Routine to retrieve names of extended device statistics\n+ * for packet send scheduling. It appends the specific stats names\n+ * after the parts filled by preceding modules (eth stats, etc.)\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ * @param[out] xstats_names\n+ * Buffer to insert names into.\n+ * @param n\n+ * Number of names.\n+ * @param n_used\n+ * Number of names filled by preceding statistics modules.\n+ *\n+ * @return\n+ * Number of xstats names.\n+ */\n+int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev __rte_unused,\n+\t\t\t struct rte_eth_xstat_name *xstats_names,\n+\t\t\t unsigned int n, unsigned int n_used)\n+{\n+\tunsigned int n_txpp = RTE_DIM(mlx5_txpp_stat_names);\n+\tunsigned int i;\n+\n+\tif (n >= n_used + n_txpp && xstats_names) {\n+\t\tfor (i = 0; i < n_txpp; ++i) {\n+\t\t\tstrncpy(xstats_names[i + n_used].name,\n+\t\t\t\tmlx5_txpp_stat_names[i],\n+\t\t\t\tRTE_ETH_XSTATS_NAME_SIZE);\n+\t\t\txstats_names[i + n_used].name\n+\t\t\t\t\t[RTE_ETH_XSTATS_NAME_SIZE - 1] = 0;\n+\t\t}\n+\t}\n+\treturn n_used + n_txpp;\n+}\n+\n+static inline void\n+mlx5_txpp_read_tsa(struct mlx5_dev_txpp *txpp,\n+\t\t struct mlx5_txpp_ts *tsa, uint16_t idx)\n+{\n+\tdo {\n+\t\tint64_t ts, ci;\n+\n+\t\tts = rte_atomic64_read(&txpp->tsa[idx].ts);\n+\t\tci = rte_atomic64_read(&txpp->tsa[idx].ci_ts);\n+\t\trte_compiler_barrier();\n+\t\tif ((ci ^ ts) << MLX5_CQ_INDEX_WIDTH != 0)\n+\t\t\tcontinue;\n+\t\tif (rte_atomic64_read(&txpp->tsa[idx].ts) != ts)\n+\t\t\tcontinue;\n+\t\tif (rte_atomic64_read(&txpp->tsa[idx].ci_ts) != ci)\n+\t\t\tcontinue;\n+\t\trte_atomic64_set(&tsa->ts, ts);\n+\t\trte_atomic64_set(&tsa->ci_ts, ci);\n+\t\treturn;\n+\t} while (true);\n+}\n+\n+/*\n+ * Jitter reflects the clock change between\n+ * neighbours Clock Queue completions.\n+ */\n+static uint64_t\n+mlx5_txpp_xstats_jitter(struct mlx5_dev_txpp *txpp)\n+{\n+\tstruct mlx5_txpp_ts tsa0, tsa1;\n+\tint64_t dts, dci;\n+\tuint16_t ts_p;\n+\n+\tif (txpp->ts_n < 2) {\n+\t\t/* No gathered enough reports yet. */\n+\t\treturn 0;\n+\t}\n+\tdo {\n+\t\tint ts_0, ts_1;\n+\n+\t\tts_p = txpp->ts_p;\n+\t\trte_compiler_barrier();\n+\t\tts_0 = ts_p - 2;\n+\t\tif (ts_0 < 0)\n+\t\t\tts_0 += MLX5_TXPP_REARM_SQ_SIZE;\n+\t\tts_1 = ts_p - 1;\n+\t\tif (ts_1 < 0)\n+\t\t\tts_1 += MLX5_TXPP_REARM_SQ_SIZE;\n+\t\tmlx5_txpp_read_tsa(txpp, &tsa0, ts_0);\n+\t\tmlx5_txpp_read_tsa(txpp, &tsa1, ts_1);\n+\t\trte_compiler_barrier();\n+\t} while (ts_p != txpp->ts_p);\n+\t/* We have two neighbor reports, calculate the jitter. */\n+\tdts = rte_atomic64_read(&tsa1.ts) - rte_atomic64_read(&tsa0.ts);\n+\tdci = (rte_atomic64_read(&tsa1.ci_ts) >> (64 - MLX5_CQ_INDEX_WIDTH)) -\n+\t (rte_atomic64_read(&tsa0.ci_ts) >> (64 - MLX5_CQ_INDEX_WIDTH));\n+\tif (dci < 0)\n+\t\tdci += 1 << MLX5_CQ_INDEX_WIDTH;\n+\tdci *= txpp->tick;\n+\treturn (dts > dci) ? dts - dci : dci - dts;\n+}\n+\n+/*\n+ * Wander reflects the long-term clock change\n+ * over the entire length of all Clock Queue completions.\n+ */\n+static uint64_t\n+mlx5_txpp_xstats_wander(struct mlx5_dev_txpp *txpp)\n+{\n+\tstruct mlx5_txpp_ts tsa0, tsa1;\n+\tint64_t dts, dci;\n+\tuint16_t ts_p;\n+\n+\tif (txpp->ts_n < MLX5_TXPP_REARM_SQ_SIZE) {\n+\t\t/* No gathered enough reports yet. */\n+\t\treturn 0;\n+\t}\n+\tdo {\n+\t\tint ts_0, ts_1;\n+\n+\t\tts_p = txpp->ts_p;\n+\t\trte_compiler_barrier();\n+\t\tts_0 = ts_p - MLX5_TXPP_REARM_SQ_SIZE / 2 - 1;\n+\t\tif (ts_0 < 0)\n+\t\t\tts_0 += MLX5_TXPP_REARM_SQ_SIZE;\n+\t\tts_1 = ts_p - 1;\n+\t\tif (ts_1 < 0)\n+\t\t\tts_1 += MLX5_TXPP_REARM_SQ_SIZE;\n+\t\tmlx5_txpp_read_tsa(txpp, &tsa0, ts_0);\n+\t\tmlx5_txpp_read_tsa(txpp, &tsa1, ts_1);\n+\t\trte_compiler_barrier();\n+\t} while (ts_p != txpp->ts_p);\n+\t/* We have two neighbor reports, calculate the jitter. */\n+\tdts = rte_atomic64_read(&tsa1.ts) - rte_atomic64_read(&tsa0.ts);\n+\tdci = (rte_atomic64_read(&tsa1.ci_ts) >> (64 - MLX5_CQ_INDEX_WIDTH)) -\n+\t (rte_atomic64_read(&tsa0.ci_ts) >> (64 - MLX5_CQ_INDEX_WIDTH));\n+\tdci += 1 << MLX5_CQ_INDEX_WIDTH;\n+\tdci *= txpp->tick;\n+\treturn (dts > dci) ? dts - dci : dci - dts;\n+}\n+\n+/**\n+ * Routine to retrieve extended device statistics\n+ * for packet send scheduling. It appends the specific statistics\n+ * after the parts filled by preceding modules (eth stats, etc.)\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device.\n+ * @param[out] stats\n+ * Pointer to rte extended stats table.\n+ * @param n\n+ * The size of the stats table.\n+ * @param n_used\n+ * Number of stats filled by preceding statistics modules.\n+ *\n+ * @return\n+ * Number of extended stats on success and stats is filled,\n+ * negative on error and rte_errno is set.\n+ */\n+int\n+mlx5_txpp_xstats_get(struct rte_eth_dev *dev,\n+\t\t struct rte_eth_xstat *stats,\n+\t\t unsigned int n, unsigned int n_used)\n+{\n+\tunsigned int n_txpp = RTE_DIM(mlx5_txpp_stat_names);\n+\n+\tif (n >= n_used + n_txpp && stats) {\n+\t\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\t\tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n+\t\tunsigned int i;\n+\n+\t\tfor (i = 0; i < n_txpp; ++i)\n+\t\t\tstats[n_used + i].id = n_used + i;\n+\t\tstats[n_used + 0].value =\n+\t\t\t\trte_atomic32_read(&sh->txpp.err_miss_int);\n+\t\tstats[n_used + 1].value =\n+\t\t\t\trte_atomic32_read(&sh->txpp.err_rearm_queue);\n+\t\tstats[n_used + 2].value =\n+\t\t\t\trte_atomic32_read(&sh->txpp.err_clock_queue);\n+\t\tstats[n_used + 3].value =\n+\t\t\t\trte_atomic32_read(&sh->txpp.err_ts_past);\n+\t\tstats[n_used + 4].value =\n+\t\t\t\trte_atomic32_read(&sh->txpp.err_ts_future);\n+\t\tstats[n_used + 5].value = mlx5_txpp_xstats_jitter(&sh->txpp);\n+\t\tstats[n_used + 6].value = mlx5_txpp_xstats_wander(&sh->txpp);\n+\t\tstats[n_used + 7].value = sh->txpp.sync_lost;\n+\t}\n+\treturn n_used + n_txpp;\n+}\n", "prefixes": [ "v2", "15/17" ] }