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GET /api/patches/74049/?format=api
{ "id": 74049, "url": "http://patches.dpdk.org/api/patches/74049/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1594794114-16313-7-git-send-email-viacheslavo@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1594794114-16313-7-git-send-email-viacheslavo@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1594794114-16313-7-git-send-email-viacheslavo@mellanox.com", "date": "2020-07-15T06:21:43", "name": "[v2,06/17] net/mlx5: create rearm queue for packet pacing", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "468bbf4288a99d4e19072eeafb9755448919973f", "submitter": { "id": 1102, "url": "http://patches.dpdk.org/api/people/1102/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1594794114-16313-7-git-send-email-viacheslavo@mellanox.com/mbox/", "series": [ { "id": 11032, "url": "http://patches.dpdk.org/api/series/11032/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11032", "date": "2020-07-15T06:21:37", "name": "net/mlx5: introduce accurate packet Tx scheduling", "version": 2, "mbox": "http://patches.dpdk.org/series/11032/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/74049/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/74049/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D9C6BA0540;\n\tWed, 15 Jul 2020 08:23:18 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DE3851C121;\n\tWed, 15 Jul 2020 08:22:18 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 822191C127\n for <dev@dpdk.org>; Wed, 15 Jul 2020 08:22:12 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n viacheslavo@mellanox.com) with SMTP; 15 Jul 2020 09:22:11 +0300", "from pegasus12.mtr.labs.mlnx (pegasus12.mtr.labs.mlnx\n [10.210.17.40])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 06F6MAvb007026;\n Wed, 15 Jul 2020 09:22:10 +0300", "from pegasus12.mtr.labs.mlnx (localhost [127.0.0.1])\n by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id 06F6MAik016438;\n Wed, 15 Jul 2020 06:22:10 GMT", "(from viacheslavo@localhost)\n by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id 06F6MA1g016437;\n Wed, 15 Jul 2020 06:22:10 GMT" ], "X-Authentication-Warning": "pegasus12.mtr.labs.mlnx: viacheslavo set sender to\n viacheslavo@mellanox.com using -f", "From": "Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "To": "dev@dpdk.org", "Cc": "matan@mellanox.com, rasland@mellanox.com, olivier.matz@6wind.com,\n thomas@monjalon.net, ferruh.yigit@intel.com", "Date": "Wed, 15 Jul 2020 06:21:43 +0000", "Message-Id": "<1594794114-16313-7-git-send-email-viacheslavo@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1594794114-16313-1-git-send-email-viacheslavo@mellanox.com>", "References": "<1591771085-24959-1-git-send-email-viacheslavo@mellanox.com>\n <1594794114-16313-1-git-send-email-viacheslavo@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v2 06/17] net/mlx5: create rearm queue for packet\n\tpacing", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The dedicated Rearm Queue is needed to fire the work requests to\nthe Clock Queue in realtime. The Clock Queue should never stop,\notherwise the clock synchronization mignt be broken and packet\nsend scheduling would fail. The Rearm Queue uses cross channel\nSEND_EN/WAIT operations to provides the requests to the\nCLock Queue in robust way.\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/net/mlx5/mlx5.h | 1 +\n drivers/net/mlx5/mlx5_defs.h | 5 +-\n drivers/net/mlx5/mlx5_txpp.c | 203 ++++++++++++++++++++++++++++++++++++++++++-\n 3 files changed, 205 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 0b73b2a..61a93f9 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -567,6 +567,7 @@ struct mlx5_dev_txpp {\n \tstruct rte_intr_handle intr_handle; /* Periodic interrupt. */\n \tstruct mlx5dv_devx_event_channel *echan; /* Event Channel. */\n \tstruct mlx5_txpp_wq clock_queue; /* Clock Queue. */\n+\tstruct mlx5_txpp_wq rearm_queue; /* Clock Queue. */\n };\n \n /*\ndiff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h\nindex 07a2b59..a8626a4 100644\n--- a/drivers/net/mlx5/mlx5_defs.h\n+++ b/drivers/net/mlx5/mlx5_defs.h\n@@ -173,11 +173,14 @@\n \n /* Tx accurate scheduling on timestamps parameters. */\n #define MLX5_TXPP_CLKQ_SIZE 1\n+#define MLX5_TXPP_REARM\t((1UL << MLX5_WQ_INDEX_WIDTH) / 4)\n+#define MLX5_TXPP_REARM_SQ_SIZE (((1UL << MLX5_CQ_INDEX_WIDTH) / \\\n+\t\t\t\t MLX5_TXPP_REARM) * 2)\n+#define MLX5_TXPP_REARM_CQ_SIZE (MLX5_TXPP_REARM_SQ_SIZE / 2)\n /* The minimal size test packet to put into one WQE, padded by HW. */\n #define MLX5_TXPP_TEST_PKT_SIZE (sizeof(struct rte_ether_hdr) +\t\\\n \t\t\t\t sizeof(struct rte_ipv4_hdr))\n \n-\n /* Size of the simple hash table for metadata register table. */\n #define MLX5_FLOW_MREG_HTABLE_SZ 4096\n #define MLX5_FLOW_MREG_HNAME \"MARK_COPY_TABLE\"\ndiff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c\nindex 382bd20..f600fc5 100644\n--- a/drivers/net/mlx5/mlx5_txpp.c\n+++ b/drivers/net/mlx5/mlx5_txpp.c\n@@ -9,6 +9,7 @@\n \n #include \"mlx5.h\"\n #include \"mlx5_rxtx.h\"\n+#include \"mlx5_common_os.h\"\n \n /* Destroy Event Queue Notification Channel. */\n static void\n@@ -48,10 +49,8 @@\n }\n \n static void\n-mlx5_txpp_destroy_clock_queue(struct mlx5_dev_ctx_shared *sh)\n+mlx5_txpp_destroy_send_queue(struct mlx5_txpp_wq *wq)\n {\n-\tstruct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;\n-\n \tif (wq->sq)\n \t\tclaim_zero(mlx5_devx_cmd_destroy(wq->sq));\n \tif (wq->sq_umem)\n@@ -68,6 +67,199 @@\n }\n \n static void\n+mlx5_txpp_destroy_rearm_queue(struct mlx5_dev_ctx_shared *sh)\n+{\n+\tstruct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;\n+\n+\tmlx5_txpp_destroy_send_queue(wq);\n+}\n+\n+static void\n+mlx5_txpp_destroy_clock_queue(struct mlx5_dev_ctx_shared *sh)\n+{\n+\tstruct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;\n+\n+\tmlx5_txpp_destroy_send_queue(wq);\n+}\n+\n+static void\n+mlx5_txpp_fill_cqe_rearm_queue(struct mlx5_dev_ctx_shared *sh)\n+{\n+\tstruct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;\n+\tstruct mlx5_cqe *cqe = (struct mlx5_cqe *)(uintptr_t)wq->cqes;\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < MLX5_TXPP_REARM_CQ_SIZE; i++) {\n+\t\tcqe->op_own = (MLX5_CQE_INVALID << 4) | MLX5_CQE_OWNER_MASK;\n+\t\t++cqe;\n+\t}\n+}\n+\n+static void\n+mlx5_txpp_fill_wqe_rearm_queue(struct mlx5_dev_ctx_shared *sh)\n+{\n+\tstruct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;\n+\tstruct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->wqes;\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < wq->sq_size; i += 2) {\n+\t\tstruct mlx5_wqe_cseg *cs;\n+\t\tstruct mlx5_wqe_qseg *qs;\n+\t\tuint32_t index;\n+\n+\t\t/* Build SEND_EN request with slave WQE index. */\n+\t\tcs = &wqe[i + 0].cseg;\n+\t\tcs->opcode = RTE_BE32(MLX5_OPCODE_SEND_EN | 0);\n+\t\tcs->sq_ds = rte_cpu_to_be_32((wq->sq->id << 8) | 2);\n+\t\tcs->flags = RTE_BE32(MLX5_COMP_ALWAYS <<\n+\t\t\t\t MLX5_COMP_MODE_OFFSET);\n+\t\tcs->misc = RTE_BE32(0);\n+\t\tqs = RTE_PTR_ADD(cs, sizeof(struct mlx5_wqe_cseg));\n+\t\tindex = (i * MLX5_TXPP_REARM / 2 + MLX5_TXPP_REARM) &\n+\t\t\t((1 << MLX5_WQ_INDEX_WIDTH) - 1);\n+\t\tqs->max_index = rte_cpu_to_be_32(index);\n+\t\tqs->qpn_cqn = rte_cpu_to_be_32(sh->txpp.clock_queue.sq->id);\n+\t\t/* Build WAIT request with slave CQE index. */\n+\t\tcs = &wqe[i + 1].cseg;\n+\t\tcs->opcode = RTE_BE32(MLX5_OPCODE_WAIT | 0);\n+\t\tcs->sq_ds = rte_cpu_to_be_32((wq->sq->id << 8) | 2);\n+\t\tcs->flags = RTE_BE32(MLX5_COMP_ONLY_ERR <<\n+\t\t\t\t MLX5_COMP_MODE_OFFSET);\n+\t\tcs->misc = RTE_BE32(0);\n+\t\tqs = RTE_PTR_ADD(cs, sizeof(struct mlx5_wqe_cseg));\n+\t\tindex = (i * MLX5_TXPP_REARM / 2 + MLX5_TXPP_REARM / 2) &\n+\t\t\t((1 << MLX5_CQ_INDEX_WIDTH) - 1);\n+\t\tqs->max_index = rte_cpu_to_be_32(index);\n+\t\tqs->qpn_cqn = rte_cpu_to_be_32(sh->txpp.clock_queue.cq->id);\n+\t}\n+}\n+\n+/* Creates the Rearm Queue to fire the requests to Clock Queue in realtime. */\n+static int\n+mlx5_txpp_create_rearm_queue(struct mlx5_dev_ctx_shared *sh)\n+{\n+\tstruct mlx5_devx_create_sq_attr sq_attr = { 0 };\n+\tstruct mlx5_devx_modify_sq_attr msq_attr = { 0 };\n+\tstruct mlx5_devx_cq_attr cq_attr = { 0 };\n+\tstruct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;\n+\tsize_t page_size = sysconf(_SC_PAGESIZE);\n+\tuint32_t umem_size, umem_dbrec;\n+\tint ret;\n+\n+\t/* Allocate memory buffer for CQEs and doorbell record. */\n+\tumem_size = sizeof(struct mlx5_cqe) * MLX5_TXPP_REARM_CQ_SIZE;\n+\tumem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);\n+\tumem_size += MLX5_DBR_SIZE;\n+\twq->cq_buf = rte_zmalloc_socket(__func__, umem_size,\n+\t\t\t\t\tpage_size, sh->numa_node);\n+\tif (!wq->cq_buf) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate memory for Rearm Queue.\");\n+\t\treturn -ENOMEM;\n+\t}\n+\t/* Register allocated buffer in user space with DevX. */\n+\twq->cq_umem = mlx5_glue->devx_umem_reg(sh->ctx,\n+\t\t\t\t\t (void *)(uintptr_t)wq->cq_buf,\n+\t\t\t\t\t umem_size,\n+\t\t\t\t\t IBV_ACCESS_LOCAL_WRITE);\n+\tif (!wq->cq_umem) {\n+\t\trte_errno = errno;\n+\t\tDRV_LOG(ERR, \"Failed to register umem for Rearm Queue.\");\n+\t\tgoto error;\n+\t}\n+\t/* Create completion queue object for Rearm Queue. */\n+\tcq_attr.cqe_size = (sizeof(struct mlx5_cqe) == 128) ?\n+\t\t\t MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B;\n+\tcq_attr.uar_page_id = sh->tx_uar->page_id;\n+\tcq_attr.eqn = sh->txpp.eqn;\n+\tcq_attr.q_umem_valid = 1;\n+\tcq_attr.q_umem_offset = 0;\n+\tcq_attr.q_umem_id = mlx5_os_get_umem_id(wq->cq_umem);\n+\tcq_attr.db_umem_valid = 1;\n+\tcq_attr.db_umem_offset = umem_dbrec;\n+\tcq_attr.db_umem_id = mlx5_os_get_umem_id(wq->cq_umem);\n+\tcq_attr.log_cq_size = rte_log2_u32(MLX5_TXPP_REARM_CQ_SIZE);\n+\tcq_attr.log_page_size = rte_log2_u32(page_size);\n+\twq->cq = mlx5_devx_cmd_create_cq(sh->ctx, &cq_attr);\n+\tif (!wq->cq) {\n+\t\trte_errno = errno;\n+\t\tDRV_LOG(ERR, \"Failed to create CQ for Rearm Queue.\");\n+\t\tgoto error;\n+\t}\n+\twq->cq_dbrec = RTE_PTR_ADD(wq->cq_buf, umem_dbrec);\n+\twq->cq_ci = 0;\n+\twq->arm_sn = 0;\n+\t/* Mark all CQEs initially as invalid. */\n+\tmlx5_txpp_fill_cqe_rearm_queue(sh);\n+\t/*\n+\t * Allocate memory buffer for Send Queue WQEs.\n+\t * There should be no WQE leftovers in the cyclic queue.\n+\t */\n+\twq->sq_size = MLX5_TXPP_REARM_SQ_SIZE;\n+\tMLX5_ASSERT(wq->sq_size == (1 << log2above(wq->sq_size)));\n+\tumem_size = MLX5_WQE_SIZE * wq->sq_size;\n+\tumem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);\n+\tumem_size += MLX5_DBR_SIZE;\n+\twq->sq_buf = rte_zmalloc_socket(__func__, umem_size,\n+\t\t\t\t\tpage_size, sh->numa_node);\n+\tif (!wq->sq_buf) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate memory for Rearm Queue.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\t/* Register allocated buffer in user space with DevX. */\n+\twq->sq_umem = mlx5_glue->devx_umem_reg(sh->ctx,\n+\t\t\t\t\t (void *)(uintptr_t)wq->sq_buf,\n+\t\t\t\t\t umem_size,\n+\t\t\t\t\t IBV_ACCESS_LOCAL_WRITE);\n+\tif (!wq->sq_umem) {\n+\t\trte_errno = errno;\n+\t\tDRV_LOG(ERR, \"Failed to register umem for Rearm Queue.\");\n+\t\tgoto error;\n+\t}\n+\t/* Create send queue object for Rearm Queue. */\n+\tsq_attr.state = MLX5_SQC_STATE_RST;\n+\tsq_attr.tis_lst_sz = 1;\n+\tsq_attr.tis_num = sh->tis->id;\n+\tsq_attr.cqn = wq->cq->id;\n+\tsq_attr.cd_master = 1;\n+\tsq_attr.wq_attr.uar_page = sh->tx_uar->page_id;\n+\tsq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;\n+\tsq_attr.wq_attr.pd = sh->pdn;\n+\tsq_attr.wq_attr.log_wq_stride = rte_log2_u32(MLX5_WQE_SIZE);\n+\tsq_attr.wq_attr.log_wq_sz = rte_log2_u32(wq->sq_size);\n+\tsq_attr.wq_attr.dbr_umem_valid = 1;\n+\tsq_attr.wq_attr.dbr_addr = umem_dbrec;\n+\tsq_attr.wq_attr.dbr_umem_id = mlx5_os_get_umem_id(wq->sq_umem);\n+\tsq_attr.wq_attr.wq_umem_valid = 1;\n+\tsq_attr.wq_attr.wq_umem_id = mlx5_os_get_umem_id(wq->sq_umem);\n+\tsq_attr.wq_attr.wq_umem_offset = 0;\n+\twq->sq = mlx5_devx_cmd_create_sq(sh->ctx, &sq_attr);\n+\tif (!wq->sq) {\n+\t\trte_errno = errno;\n+\t\tDRV_LOG(ERR, \"Failed to create SQ for Rearm Queue.\");\n+\t\tgoto error;\n+\t}\n+\twq->sq_dbrec = RTE_PTR_ADD(wq->sq_buf, umem_dbrec +\n+\t\t\t\t MLX5_SND_DBR * sizeof(uint32_t));\n+\t/* Build the WQEs in the Send Queue before goto Ready state. */\n+\tmlx5_txpp_fill_wqe_rearm_queue(sh);\n+\t/* Change queue state to ready. */\n+\tmsq_attr.sq_state = MLX5_SQC_STATE_RST;\n+\tmsq_attr.state = MLX5_SQC_STATE_RDY;\n+\tret = mlx5_devx_cmd_modify_sq(wq->sq, &msq_attr);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Failed to set SQ ready state Rearm Queue.\");\n+\t\tgoto error;\n+\t}\n+\treturn 0;\n+error:\n+\tret = -rte_errno;\n+\tmlx5_txpp_destroy_rearm_queue(sh);\n+\trte_errno = -ret;\n+\treturn ret;\n+}\n+\n+static void\n mlx5_txpp_fill_wqe_clock_queue(struct mlx5_dev_ctx_shared *sh)\n {\n \tstruct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;\n@@ -331,8 +523,12 @@\n \tret = mlx5_txpp_create_clock_queue(sh);\n \tif (ret)\n \t\tgoto exit;\n+\tret = mlx5_txpp_create_rearm_queue(sh);\n+\tif (ret)\n+\t\tgoto exit;\n exit:\n \tif (ret) {\n+\t\tmlx5_txpp_destroy_rearm_queue(sh);\n \t\tmlx5_txpp_destroy_clock_queue(sh);\n \t\tmlx5_txpp_destroy_eqn(sh);\n \t\tsh->txpp.tick = 0;\n@@ -352,6 +548,7 @@\n static void\n mlx5_txpp_destroy(struct mlx5_dev_ctx_shared *sh)\n {\n+\tmlx5_txpp_destroy_rearm_queue(sh);\n \tmlx5_txpp_destroy_clock_queue(sh);\n \tmlx5_txpp_destroy_eqn(sh);\n \tsh->txpp.tick = 0;\n", "prefixes": [ "v2", "06/17" ] }