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GET /api/patches/74045/?format=api
{ "id": 74045, "url": "http://patches.dpdk.org/api/patches/74045/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1594794114-16313-3-git-send-email-viacheslavo@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1594794114-16313-3-git-send-email-viacheslavo@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1594794114-16313-3-git-send-email-viacheslavo@mellanox.com", "date": "2020-07-15T06:21:39", "name": "[v2,02/17] net/mlx5: introduce send scheduling devargs", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "adbbcd526af8b6fc64f35370dd32bd103c5ca1c6", "submitter": { "id": 1102, "url": "http://patches.dpdk.org/api/people/1102/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1594794114-16313-3-git-send-email-viacheslavo@mellanox.com/mbox/", "series": [ { "id": 11032, "url": "http://patches.dpdk.org/api/series/11032/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11032", "date": "2020-07-15T06:21:37", "name": "net/mlx5: introduce accurate packet Tx scheduling", "version": 2, "mbox": "http://patches.dpdk.org/series/11032/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/74045/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/74045/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A4E00A0540;\n\tWed, 15 Jul 2020 08:22:36 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E4D0E1C119;\n\tWed, 15 Jul 2020 08:22:10 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 85B241C0B1\n for <dev@dpdk.org>; Wed, 15 Jul 2020 08:22:07 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n viacheslavo@mellanox.com) with SMTP; 15 Jul 2020 09:22:04 +0300", "from pegasus12.mtr.labs.mlnx (pegasus12.mtr.labs.mlnx\n [10.210.17.40])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 06F6M4Em007004;\n Wed, 15 Jul 2020 09:22:04 +0300", "from pegasus12.mtr.labs.mlnx (localhost [127.0.0.1])\n by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id 06F6M4cL016428;\n Wed, 15 Jul 2020 06:22:04 GMT", "(from viacheslavo@localhost)\n by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id 06F6M4LT016427;\n Wed, 15 Jul 2020 06:22:04 GMT" ], "X-Authentication-Warning": "pegasus12.mtr.labs.mlnx: viacheslavo set sender to\n viacheslavo@mellanox.com using -f", "From": "Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "To": "dev@dpdk.org", "Cc": "matan@mellanox.com, rasland@mellanox.com, olivier.matz@6wind.com,\n thomas@monjalon.net, ferruh.yigit@intel.com", "Date": "Wed, 15 Jul 2020 06:21:39 +0000", "Message-Id": "<1594794114-16313-3-git-send-email-viacheslavo@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1594794114-16313-1-git-send-email-viacheslavo@mellanox.com>", "References": "<1591771085-24959-1-git-send-email-viacheslavo@mellanox.com>\n <1594794114-16313-1-git-send-email-viacheslavo@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v2 02/17] net/mlx5: introduce send scheduling\n\tdevargs", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch introduces the new devargs:\n\ntx_pp - enables accurate packet send scheduling on mbuf timestamps\n in the PMD. On the device start if \"rte_dynflag_timestamp\"\n dynamic flag is registered and this devarg non-zero value is\n specified, the driver initializes all necessary internal\n infrastructure to provide packet scheduling. The parameter\n value specifies scheduling granularity in nanoseconds.\n\ntx_skew - the parameter adjusts the send packet scheduling on\n timestamps and represents the average delay between beginning\n of the transmitting descriptor processing by the hardware and\n appearance of actual packet data on the wire. The value should\n be provided in nanoseconds and is valid only if tx_pp parameter\n is specified. The default value is zero.\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\n doc/guides/nics/mlx5.rst | 37 +++++++++++++++++++++++\n drivers/net/mlx5/linux/mlx5_os.c | 63 ++++++++++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5.c | 39 +++++++++++++++++++++++--\n drivers/net/mlx5/mlx5.h | 2 ++\n 4 files changed, 138 insertions(+), 3 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 4b6d8fb..9a57768 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -241,6 +241,24 @@ Limitations\n reduce the requested Tx size or adjust data inline settings with\n ``txq_inline_max`` and ``txq_inline_mpw`` devargs keys.\n \n+- To provide the packet send scheduling on mbuf timestamps the ``tx_pp``\n+ parameter should be specified, RTE_MBUF_DYNFIELD_TIMESTAMP_NAME and\n+ RTE_MBUF_DYNFLAG_TIMESTAMP_NAME should be registered by application.\n+ When PMD sees the RTE_MBUF_DYNFLAG_TIMESTAMP_NAME set on the packet\n+ being sent it tries to synchronize the time of packet appearing on\n+ the wire with the specified packet timestamp. It the specified one\n+ is in the past it should be ignored, if one is in the distant future\n+ it should be capped with some reasonable value (in range of seconds).\n+ These specific cases (\"too late\" and \"distant future\") can be optionally\n+ reported via device xstats to assist applications to detect the\n+ time-related problems.\n+\n+ There is no any packet reordering according timestamps is supposed,\n+ neither within packet burst, nor between packets, it is an entirely\n+ application responsibility to generate packets and its timestamps\n+ in desired order. The timestamps can be put only in the first packet\n+ in the burst providing the entire burst scheduling.\n+\n - E-Switch decapsulation Flow:\n \n - can be applied to PF port only.\n@@ -700,6 +718,25 @@ Driver options\n variable \"MLX5_SHUT_UP_BF\" value is used. If there is no \"MLX5_SHUT_UP_BF\",\n the default ``tx_db_nc`` value is zero for ARM64 hosts and one for others.\n \n+- ``tx_pp`` parameter [int]\n+\n+ If a nonzero value is specified the driver creates all necessary internal\n+ objects to provide accurate packet send scheduling on mbuf timestamps.\n+ The positive value specifies the scheduling granularity in nanoseconds,\n+ the packet send will be accurate up to specified digits. The allowed range is\n+ from 500 to 1 million of nanoseconds. The negative value specifies the module\n+ of granularity and engages the special test mode the check the schedule rate.\n+ By default (if the ``tx_pp`` is not specified) send scheduling on timestamps\n+ feature is disabled.\n+\n+- ``tx_skew`` parameter [int]\n+\n+ The parameter adjusts the send packet scheduling on timestamps and represents\n+ the average delay between beginning of the transmitting descriptor processing\n+ by the hardware and appearance of actual packet data on the wire. The value\n+ should be provided in nanoseconds and is valid only if ``tx_pp`` parameter is\n+ specified. The default value is zero.\n+\n - ``tx_vec_en`` parameter [int]\n \n A nonzero value enables Tx vector on ConnectX-5, ConnectX-6, ConnectX-6 Dx\ndiff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 2dc57b2..14af468 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -879,6 +879,69 @@\n \t\t}\n #endif\n \t}\n+\tif (config.tx_pp) {\n+\t\tDRV_LOG(DEBUG, \"Timestamp counter frequency %u kHz\",\n+\t\t\tconfig.hca_attr.dev_freq_khz);\n+\t\tDRV_LOG(DEBUG, \"Packet pacing is %ssupported\",\n+\t\t\tconfig.hca_attr.qos.packet_pacing ? \"\" : \"not \");\n+\t\tDRV_LOG(DEBUG, \"Cross channel ops are %ssupported\",\n+\t\t\tconfig.hca_attr.cross_channel ? \"\" : \"not \");\n+\t\tDRV_LOG(DEBUG, \"WQE index ignore is %ssupported\",\n+\t\t\tconfig.hca_attr.wqe_index_ignore ? \"\" : \"not \");\n+\t\tDRV_LOG(DEBUG, \"Non-wire SQ feature is %ssupported\",\n+\t\t\tconfig.hca_attr.non_wire_sq ? \"\" : \"not \");\n+\t\tDRV_LOG(DEBUG, \"Static WQE SQ feature is %ssupported (%d)\",\n+\t\t\tconfig.hca_attr.log_max_static_sq_wq ? \"\" : \"not \",\n+\t\t\tconfig.hca_attr.log_max_static_sq_wq);\n+\t\tDRV_LOG(DEBUG, \"WQE rate PP mode is %ssupported\",\n+\t\t\tconfig.hca_attr.qos.wqe_rate_pp ? \"\" : \"not \");\n+\t\tif (!config.devx) {\n+\t\t\tDRV_LOG(ERR, \"DevX is required for packet pacing\");\n+\t\t\terr = ENODEV;\n+\t\t\tgoto error;\n+\t\t}\n+\t\tif (!config.hca_attr.qos.packet_pacing) {\n+\t\t\tDRV_LOG(ERR, \"Packet pacing is not supported\");\n+\t\t\terr = ENODEV;\n+\t\t\tgoto error;\n+\t\t}\n+\t\tif (!config.hca_attr.cross_channel) {\n+\t\t\tDRV_LOG(ERR, \"Cross channel operations are\"\n+\t\t\t\t \" required for packet pacing\");\n+\t\t\terr = ENODEV;\n+\t\t\tgoto error;\n+\t\t}\n+\t\tif (!config.hca_attr.wqe_index_ignore) {\n+\t\t\tDRV_LOG(ERR, \"WQE index ignore feature is\"\n+\t\t\t\t \" required for packet pacing\");\n+\t\t\terr = ENODEV;\n+\t\t\tgoto error;\n+\t\t}\n+\t\tif (!config.hca_attr.non_wire_sq) {\n+\t\t\tDRV_LOG(ERR, \"Non-wire SQ feature is\"\n+\t\t\t\t \" required for packet pacing\");\n+\t\t\terr = ENODEV;\n+\t\t\tgoto error;\n+\t\t}\n+\t\tif (!config.hca_attr.log_max_static_sq_wq) {\n+\t\t\tDRV_LOG(ERR, \"Static WQE SQ feature is\"\n+\t\t\t\t \" required for packet pacing\");\n+\t\t\terr = ENODEV;\n+\t\t\tgoto error;\n+\t\t}\n+\t\tif (!config.hca_attr.qos.wqe_rate_pp) {\n+\t\t\tDRV_LOG(ERR, \"WQE rate mode is required\"\n+\t\t\t\t \" for packet pacing\");\n+\t\t\terr = ENODEV;\n+\t\t\tgoto error;\n+\t\t}\n+#ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET\n+\t\tDRV_LOG(ERR, \"DevX does not provide UAR offset,\"\n+\t\t\t \" can't create queues for packet pacing\");\n+\t\terr = ENODEV;\n+\t\tgoto error;\n+#endif\n+\t}\n \tif (config.mprq.enabled && mprq) {\n \t\tif (config.mprq.stride_num_n &&\n \t\t (config.mprq.stride_num_n > mprq_max_stride_num_n ||\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 0c654ed..72e0870 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -120,6 +120,19 @@\n #define MLX5_TXQ_MAX_INLINE_LEN \"txq_max_inline_len\"\n \n /*\n+ * Device parameter to enable Tx scheduling on timestamps\n+ * and specify the packet pacing granularity in nanoseconds.\n+ */\n+#define MLX5_TX_PP \"tx_pp\"\n+\n+/*\n+ * Device parameter to specify skew in nanoseconds on Tx datapath,\n+ * it represents the time between SQ start WQE processing and\n+ * appearing actual packet data on the wire.\n+ */\n+#define MLX5_TX_SKEW \"tx_skew\"\n+\n+/*\n * Device parameter to enable hardware Tx vector.\n * Deprecated, ignored (no vectorized Tx routines anymore).\n */\n@@ -1271,18 +1284,26 @@ struct mlx5_dev_ctx_shared *\n mlx5_args_check(const char *key, const char *val, void *opaque)\n {\n \tstruct mlx5_dev_config *config = opaque;\n-\tunsigned long tmp;\n+\tunsigned long mod;\n+\tsigned long tmp;\n \n \t/* No-op, port representors are processed in mlx5_dev_spawn(). */\n \tif (!strcmp(MLX5_REPRESENTOR, key))\n \t\treturn 0;\n \terrno = 0;\n-\ttmp = strtoul(val, NULL, 0);\n+\ttmp = strtol(val, NULL, 0);\n \tif (errno) {\n \t\trte_errno = errno;\n \t\tDRV_LOG(WARNING, \"%s: \\\"%s\\\" is not a valid integer\", key, val);\n \t\treturn -rte_errno;\n \t}\n+\tif (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {\n+\t\t/* Negative values are acceptable for some keys only. */\n+\t\trte_errno = EINVAL;\n+\t\tDRV_LOG(WARNING, \"%s: invalid negative value \\\"%s\\\"\", key, val);\n+\t\treturn -rte_errno;\n+\t}\n+\tmod = tmp >= 0 ? tmp : -tmp;\n \tif (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {\n \t\tconfig->cqe_comp = !!tmp;\n \t} else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {\n@@ -1333,6 +1354,15 @@ struct mlx5_dev_ctx_shared *\n \t\tconfig->txq_inline_mpw = tmp;\n \t} else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {\n \t\tDRV_LOG(WARNING, \"%s: deprecated parameter, ignored\", key);\n+\t} else if (strcmp(MLX5_TX_PP, key) == 0) {\n+\t\tif (!mod) {\n+\t\t\tDRV_LOG(ERR, \"Zero Tx packet pacing parameter\");\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn -rte_errno;\n+\t\t}\n+\t\tconfig->tx_pp = tmp;\n+\t} else if (strcmp(MLX5_TX_SKEW, key) == 0) {\n+\t\tconfig->tx_skew = tmp;\n \t} else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {\n \t\tconfig->rx_vec_en = !!tmp;\n \t} else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {\n@@ -1415,6 +1445,8 @@ struct mlx5_dev_ctx_shared *\n \t\tMLX5_TXQ_MPW_HDR_DSEG_EN,\n \t\tMLX5_TXQ_MAX_INLINE_LEN,\n \t\tMLX5_TX_DB_NC,\n+\t\tMLX5_TX_PP,\n+\t\tMLX5_TX_SKEW,\n \t\tMLX5_TX_VEC_EN,\n \t\tMLX5_RX_VEC_EN,\n \t\tMLX5_L3_VXLAN_EN,\n@@ -1693,7 +1725,8 @@ struct mlx5_dev_ctx_shared *\n {\n \tstatic const char *const dynf_names[] = {\n \t\tRTE_PMD_MLX5_FINE_GRANULARITY_INLINE,\n-\t\tRTE_MBUF_DYNFLAG_METADATA_NAME\n+\t\tRTE_MBUF_DYNFLAG_METADATA_NAME,\n+\t\tRTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME\n \t};\n \tunsigned int i;\n \ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 46e66eb..84cd3e1 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -240,6 +240,8 @@ struct mlx5_dev_config {\n \tint txq_inline_min; /* Minimal amount of data bytes to inline. */\n \tint txq_inline_max; /* Max packet size for inlining with SEND. */\n \tint txq_inline_mpw; /* Max packet size for inlining with eMPW. */\n+\tint tx_pp; /* Timestamp scheduling granularity in nanoseconds. */\n+\tint tx_skew; /* Tx scheduling skew between WQE and data on wire. */\n \tstruct mlx5_hca_attr hca_attr; /* HCA attributes. */\n \tstruct mlx5_lro_config lro; /* LRO configuration. */\n };\n", "prefixes": [ "v2", "02/17" ] }