Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/74044/?format=api
{ "id": 74044, "url": "http://patches.dpdk.org/api/patches/74044/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1594794114-16313-4-git-send-email-viacheslavo@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1594794114-16313-4-git-send-email-viacheslavo@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1594794114-16313-4-git-send-email-viacheslavo@mellanox.com", "date": "2020-07-15T06:21:40", "name": "[v2,03/17] net/mlx5: fix UAR lock sharing for multiport devices", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ca3d99f496968c145fb9eddab88606e4b78417f3", "submitter": { "id": 1102, "url": "http://patches.dpdk.org/api/people/1102/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1594794114-16313-4-git-send-email-viacheslavo@mellanox.com/mbox/", "series": [ { "id": 11032, "url": "http://patches.dpdk.org/api/series/11032/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11032", "date": "2020-07-15T06:21:37", "name": "net/mlx5: introduce accurate packet Tx scheduling", "version": 2, "mbox": "http://patches.dpdk.org/series/11032/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/74044/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/74044/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E3C95A0540;\n\tWed, 15 Jul 2020 08:22:25 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6FC551C0D0;\n\tWed, 15 Jul 2020 08:22:09 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 90F151C0B3\n for <dev@dpdk.org>; Wed, 15 Jul 2020 08:22:07 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n viacheslavo@mellanox.com) with SMTP; 15 Jul 2020 09:22:06 +0300", "from pegasus12.mtr.labs.mlnx (pegasus12.mtr.labs.mlnx\n [10.210.17.40])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 06F6M6Bm007010;\n Wed, 15 Jul 2020 09:22:06 +0300", "from pegasus12.mtr.labs.mlnx (localhost [127.0.0.1])\n by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id 06F6M6wl016431;\n Wed, 15 Jul 2020 06:22:06 GMT", "(from viacheslavo@localhost)\n by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id 06F6M6cN016430;\n Wed, 15 Jul 2020 06:22:06 GMT" ], "X-Authentication-Warning": "pegasus12.mtr.labs.mlnx: viacheslavo set sender to\n viacheslavo@mellanox.com using -f", "From": "Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "To": "dev@dpdk.org", "Cc": "matan@mellanox.com, rasland@mellanox.com, olivier.matz@6wind.com,\n thomas@monjalon.net, ferruh.yigit@intel.com, stable@dpdk.org", "Date": "Wed, 15 Jul 2020 06:21:40 +0000", "Message-Id": "<1594794114-16313-4-git-send-email-viacheslavo@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1594794114-16313-1-git-send-email-viacheslavo@mellanox.com>", "References": "<1591771085-24959-1-git-send-email-viacheslavo@mellanox.com>\n <1594794114-16313-1-git-send-email-viacheslavo@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v2 03/17] net/mlx5: fix UAR lock sharing for\n\tmultiport devices", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The master and representors might be created over the multiport\nInfiniband devices and the UAR resource allocated for sibling\nports might belong to the same underlying Infiniband device.\nHardware requires the write access to the UAR must be performed\nas atomic 64-bit write, on 32-bit systems this is two sequential\nwrites, protected by lock. Due to possibility to share the same\nUAR between sibling devices the locks must be moved to shared\ncontext.\n\nFixes: f048f3d479a6 (\"net/mlx5: switch to the shared IB device context\")\nCc: stable@dpdk.org\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 6 ------\n drivers/net/mlx5/mlx5.c | 6 ++++++\n drivers/net/mlx5/mlx5.h | 10 +++++-----\n drivers/net/mlx5/mlx5_rxq.c | 2 +-\n drivers/net/mlx5/mlx5_txq.c | 2 +-\n 5 files changed, 13 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 14af468..63e9350 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -630,12 +630,6 @@\n \tpriv->mtu = RTE_ETHER_MTU;\n \tpriv->mp_id.port_id = port_id;\n \tstrlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);\n-#ifndef RTE_ARCH_64\n-\t/* Initialize UAR access locks for 32bit implementations. */\n-\trte_spinlock_init(&priv->uar_lock_cq);\n-\tfor (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)\n-\t\trte_spinlock_init(&priv->uar_lock[i]);\n-#endif\n \t/* Some internal functions rely on Netlink sockets, open them now. */\n \tpriv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);\n \tpriv->nl_socket_route =\tmlx5_nl_init(NETLINK_ROUTE);\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 72e0870..0786945 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -717,6 +717,12 @@ struct mlx5_dev_ctx_shared *\n \t\terr = ENOMEM;\n \t\tgoto error;\n \t}\n+#ifndef RTE_ARCH_64\n+\t/* Initialize UAR access locks for 32bit implementations. */\n+\trte_spinlock_init(&sh->uar_lock_cq);\n+\tfor (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)\n+\t\trte_spinlock_init(&sh->uar_lock[i]);\n+#endif\n \t/*\n \t * Once the device is added to the list of memory event\n \t * callback, its global MR cache table cannot be expanded\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 84cd3e1..d01d7f3 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -559,6 +559,11 @@ struct mlx5_dev_ctx_shared {\n \tvoid *fdb_domain; /* FDB Direct Rules name space handle. */\n \tvoid *rx_domain; /* RX Direct Rules name space handle. */\n \tvoid *tx_domain; /* TX Direct Rules name space handle. */\n+#ifndef RTE_ARCH_64\n+\trte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */\n+\trte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];\n+\t/* UAR same-page access control required in 32bit implementations. */\n+#endif\n \tstruct mlx5_hlist *flow_tbls;\n \t/* Direct Rules tables for FDB, NIC TX+RX */\n \tvoid *esw_drop_action; /* Pointer to DR E-Switch drop action. */\n@@ -673,11 +678,6 @@ struct mlx5_priv {\n \tuint8_t mtr_color_reg; /* Meter color match REG_C. */\n \tstruct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */\n \tstruct mlx5_flow_meters flow_meters; /* MTR list. */\n-#ifndef RTE_ARCH_64\n-\trte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */\n-\trte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];\n-\t/* UAR same-page access control required in 32bit implementations. */\n-#endif\n \tuint8_t skip_default_rss_reta; /* Skip configuration of default reta. */\n \tuint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */\n \tstruct mlx5_mp_id mp_id; /* ID of a multi-process process */\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex b436f06..2681322 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -1997,7 +1997,7 @@ struct mlx5_rxq_ctrl *\n \ttmpl->rxq.elts =\n \t\t(struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);\n #ifndef RTE_ARCH_64\n-\ttmpl->rxq.uar_lock_cq = &priv->uar_lock_cq;\n+\ttmpl->rxq.uar_lock_cq = &priv->sh->uar_lock_cq;\n #endif\n \ttmpl->rxq.idx = idx;\n \trte_atomic32_inc(&tmpl->refcnt);\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex 35b3ade..e1fa24e 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -355,7 +355,7 @@\n \t/* Assign an UAR lock according to UAR page number */\n \tlock_idx = (txq_ctrl->uar_mmap_offset / page_size) &\n \t\t MLX5_UAR_PAGE_NUM_MASK;\n-\ttxq_ctrl->txq.uar_lock = &priv->uar_lock[lock_idx];\n+\ttxq_ctrl->txq.uar_lock = &priv->sh->uar_lock[lock_idx];\n #endif\n }\n \n", "prefixes": [ "v2", "03/17" ] }