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GET /api/patches/74043/?format=api
{ "id": 74043, "url": "http://patches.dpdk.org/api/patches/74043/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1594794114-16313-2-git-send-email-viacheslavo@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1594794114-16313-2-git-send-email-viacheslavo@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1594794114-16313-2-git-send-email-viacheslavo@mellanox.com", "date": "2020-07-15T06:21:38", "name": "[v2,01/17] common/mlx5: update common part to support packet pacing", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "58ddd383ea7e5e09a4b63fb220df2d57cb6e4fb1", "submitter": { "id": 1102, "url": "http://patches.dpdk.org/api/people/1102/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1594794114-16313-2-git-send-email-viacheslavo@mellanox.com/mbox/", "series": [ { "id": 11032, "url": "http://patches.dpdk.org/api/series/11032/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11032", "date": "2020-07-15T06:21:37", "name": "net/mlx5: introduce accurate packet Tx scheduling", "version": 2, "mbox": "http://patches.dpdk.org/series/11032/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/74043/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/74043/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C866CA0540;\n\tWed, 15 Jul 2020 08:22:16 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 632A81C0B3;\n\tWed, 15 Jul 2020 08:22:08 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 752701C0B0\n for <dev@dpdk.org>; Wed, 15 Jul 2020 08:22:07 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n viacheslavo@mellanox.com) with SMTP; 15 Jul 2020 09:22:03 +0300", "from pegasus12.mtr.labs.mlnx (pegasus12.mtr.labs.mlnx\n [10.210.17.40])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 06F6M2nI006995;\n Wed, 15 Jul 2020 09:22:03 +0300", "from pegasus12.mtr.labs.mlnx (localhost [127.0.0.1])\n by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id 06F6M2nF016425;\n Wed, 15 Jul 2020 06:22:02 GMT", "(from viacheslavo@localhost)\n by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id 06F6M2sP016424;\n Wed, 15 Jul 2020 06:22:02 GMT" ], "X-Authentication-Warning": "pegasus12.mtr.labs.mlnx: viacheslavo set sender to\n viacheslavo@mellanox.com using -f", "From": "Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "To": "dev@dpdk.org", "Cc": "matan@mellanox.com, rasland@mellanox.com, olivier.matz@6wind.com,\n thomas@monjalon.net, ferruh.yigit@intel.com", "Date": "Wed, 15 Jul 2020 06:21:38 +0000", "Message-Id": "<1594794114-16313-2-git-send-email-viacheslavo@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1594794114-16313-1-git-send-email-viacheslavo@mellanox.com>", "References": "<1591771085-24959-1-git-send-email-viacheslavo@mellanox.com>\n <1594794114-16313-1-git-send-email-viacheslavo@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v2 01/17] common/mlx5: update common part to\n\tsupport packet pacing", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch prepares the common part of the mlx5 PMDs to\nsupport packet send scheduling on mbuf timestamps:\n\n - the DevX routine to query the packet pacing HCA capabilities\n - packet pacing Send Queue attributes support\n - the hardware related definitions\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/common/mlx5/Makefile | 25 +++++++++++++\n drivers/common/mlx5/linux/meson.build | 10 +++++\n drivers/common/mlx5/linux/mlx5_glue.c | 31 +++++++++++++++-\n drivers/common/mlx5/linux/mlx5_glue.h | 5 +++\n drivers/common/mlx5/mlx5_devx_cmds.c | 19 +++++++++-\n drivers/common/mlx5/mlx5_devx_cmds.h | 10 +++++\n drivers/common/mlx5/mlx5_prm.h | 69 ++++++++++++++++++++++++++++++++---\n 7 files changed, 161 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/Makefile b/drivers/common/mlx5/Makefile\nindex f6c762b..f9dc376 100644\n--- a/drivers/common/mlx5/Makefile\n+++ b/drivers/common/mlx5/Makefile\n@@ -172,6 +172,16 @@ mlx5_autoconf.h.new: $(RTE_SDK)/buildtools/auto-config-h.sh\n \t\tfunc mlx5dv_devx_qp_query \\\n \t\t$(AUTOCONF_OUTPUT)\n \t$Q sh -- '$<' '$@' \\\n+\t\tHAVE_MLX5DV_DEVX_UAR_OFFSET \\\n+\t\tinfiniband/mlx5dv.h \\\n+\t\tfield \"struct mlx5dv_devx_uar.mmap_off\" \\\n+\t\t$(AUTOCONF_OUTPUT)\n+\t$Q sh -- '$<' '$@' \\\n+\t\tHAVE_MLX5DV_PP_ALLOC \\\n+\t\tinfiniband/mlx5dv.h \\\n+\t\tfunc mlx5dv_pp_alloc \\\n+\t\t$(AUTOCONF_OUTPUT)\n+\t$Q sh -- '$<' '$@' \\\n \t\tHAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR \\\n \t\tinfiniband/mlx5dv.h \\\n \t\tfunc mlx5dv_dr_action_create_dest_devx_tir \\\n@@ -207,6 +217,21 @@ mlx5_autoconf.h.new: $(RTE_SDK)/buildtools/auto-config-h.sh\n \t\tfunc mlx5dv_dr_domain_set_reclaim_device_memory \\\n \t\t$(AUTOCONF_OUTPUT)\n \t$Q sh -- '$<' '$@' \\\n+\t\tHAVE_MLX5_OPCODE_ENHANCED_MPSW \\\n+\t\tinfiniband/mlx5dv.h \\\n+\t\tenum MLX5_OPCODE_ENHANCED_MPSW \\\n+\t\t$(AUTOCONF_OUTPUT)\n+\t$Q sh -- '$<' '$@' \\\n+\t\tHAVE_MLX5_OPCODE_SEND_EN \\\n+\t\tinfiniband/mlx5dv.h \\\n+\t\tenum MLX5_OPCODE_SEND_EN \\\n+\t\t$(AUTOCONF_OUTPUT)\n+\t$Q sh -- '$<' '$@' \\\n+\t\tHAVE_MLX5_OPCODE_WAIT \\\n+\t\tinfiniband/mlx5dv.h \\\n+\t\tenum MLX5_OPCODE_WAIT \\\n+\t\t$(AUTOCONF_OUTPUT)\n+\t$Q sh -- '$<' '$@' \\\n \t\tHAVE_ETHTOOL_LINK_MODE_25G \\\n \t\t/usr/include/linux/ethtool.h \\\n \t\tenum ETHTOOL_LINK_MODE_25000baseCR_Full_BIT \\\ndiff --git a/drivers/common/mlx5/linux/meson.build b/drivers/common/mlx5/linux/meson.build\nindex 2294213..48e8ad6 100644\n--- a/drivers/common/mlx5/linux/meson.build\n+++ b/drivers/common/mlx5/linux/meson.build\n@@ -64,6 +64,8 @@ has_member_args = [\n \t'struct ibv_counter_set_init_attr', 'counter_set_id' ],\n \t[ 'HAVE_IBV_DEVICE_COUNTERS_SET_V45', 'infiniband/verbs.h',\n \t'struct ibv_counters_init_attr', 'comp_mask' ],\n+\t[ 'HAVE_MLX5DV_DEVX_UAR_OFFSET', 'infiniband/mlx5dv.h',\n+\t'struct mlx5dv_devx_uar', 'mmap_off' ],\n ]\n # input array for meson symbol search:\n # [ \"MACRO to define if found\", \"header for the search\",\n@@ -101,6 +103,8 @@ has_sym_args = [\n \t'mlx5dv_devx_obj_query_async' ],\n \t[ 'HAVE_IBV_DEVX_QP', 'infiniband/mlx5dv.h',\n \t'mlx5dv_devx_qp_query' ],\n+\t[ 'HAVE_MLX5DV_PP_ALLOC', 'infiniband/mlx5dv.h',\n+\t'mlx5dv_pp_alloc' ],\n \t[ 'HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR', 'infiniband/mlx5dv.h',\n \t'mlx5dv_dr_action_create_dest_devx_tir' ],\n \t[ 'HAVE_IBV_DEVX_EVENT', 'infiniband/mlx5dv.h',\n@@ -116,6 +120,12 @@ has_sym_args = [\n \t[ 'HAVE_MLX5DV_DR_VLAN', 'infiniband/mlx5dv.h',\n \t'mlx5dv_dr_action_create_push_vlan' ],\n \t[ 'HAVE_IBV_VAR', 'infiniband/mlx5dv.h', 'mlx5dv_alloc_var' ],\n+\t[ 'HAVE_MLX5_OPCODE_ENHANCED_MPSW', 'infiniband/mlx5dv.h',\n+\t'MLX5_OPCODE_ENHANCED_MPSW' ],\n+\t[ 'HAVE_MLX5_OPCODE_SEND_EN', 'infiniband/mlx5dv.h',\n+\t'MLX5_OPCODE_SEND_EN' ],\n+\t[ 'HAVE_MLX5_OPCODE_WAIT', 'infiniband/mlx5dv.h',\n+\t'MLX5_OPCODE_WAIT' ],\n \t[ 'HAVE_SUPPORTED_40000baseKR4_Full', 'linux/ethtool.h',\n \t'SUPPORTED_40000baseKR4_Full' ],\n \t[ 'HAVE_SUPPORTED_40000baseCR4_Full', 'linux/ethtool.h',\ndiff --git a/drivers/common/mlx5/linux/mlx5_glue.c b/drivers/common/mlx5/linux/mlx5_glue.c\nindex 395519d..4d3875f 100644\n--- a/drivers/common/mlx5/linux/mlx5_glue.c\n+++ b/drivers/common/mlx5/linux/mlx5_glue.c\n@@ -1195,7 +1195,6 @@\n #endif\n }\n \n-\n static void\n mlx5_glue_dr_reclaim_domain_memory(void *domain, uint32_t enable)\n {\n@@ -1207,6 +1206,34 @@\n #endif\n }\n \n+static struct mlx5dv_pp *\n+mlx5_glue_dv_alloc_pp(struct ibv_context *context,\n+\t\t size_t pp_context_sz,\n+\t\t const void *pp_context,\n+\t\t uint32_t flags)\n+{\n+#ifdef HAVE_MLX5DV_PP_ALLOC\n+\treturn mlx5dv_pp_alloc(context, pp_context_sz, pp_context, flags);\n+#else\n+\tRTE_SET_USED(context);\n+\tRTE_SET_USED(pp_context_sz);\n+\tRTE_SET_USED(pp_context);\n+\tRTE_SET_USED(flags);\n+\terrno = ENOTSUP;\n+\treturn NULL;\n+#endif\n+}\n+\n+static void\n+mlx5_glue_dv_free_pp(struct mlx5dv_pp *pp)\n+{\n+#ifdef HAVE_MLX5DV_PP_ALLOC\n+\tmlx5dv_pp_free(pp);\n+#else\n+\tRTE_SET_USED(pp);\n+#endif\n+}\n+\n __rte_cache_aligned\n const struct mlx5_glue *mlx5_glue = &(const struct mlx5_glue) {\n \t.version = MLX5_GLUE_VERSION,\n@@ -1319,4 +1346,6 @@\n \t.devx_free_uar = mlx5_glue_devx_free_uar,\n \t.dv_alloc_var = mlx5_glue_dv_alloc_var,\n \t.dv_free_var = mlx5_glue_dv_free_var,\n+\t.dv_alloc_pp = mlx5_glue_dv_alloc_pp,\n+\t.dv_free_pp = mlx5_glue_dv_free_pp,\n };\ndiff --git a/drivers/common/mlx5/linux/mlx5_glue.h b/drivers/common/mlx5/linux/mlx5_glue.h\nindex 069d854..c4f9b00 100644\n--- a/drivers/common/mlx5/linux/mlx5_glue.h\n+++ b/drivers/common/mlx5/linux/mlx5_glue.h\n@@ -304,6 +304,11 @@ struct mlx5_glue {\n \t\t\t struct mlx5dv_devx_async_event_hdr *event_data,\n \t\t\t size_t event_resp_len);\n \tvoid (*dr_reclaim_domain_memory)(void *domain, uint32_t enable);\n+\tstruct mlx5dv_pp *(*dv_alloc_pp)(struct ibv_context *context,\n+\t\t\t\t\t size_t pp_context_sz,\n+\t\t\t\t\t const void *pp_context,\n+\t\t\t\t\t uint32_t flags);\n+\tvoid (*dv_free_pp)(struct mlx5dv_pp *pp);\n };\n \n extern const struct mlx5_glue *mlx5_glue;\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 2179a83..093636c 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -467,6 +467,14 @@ struct mlx5_devx_obj *\n \tattr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,\n \t\t\t\t\t\t\tgeneral_obj_types) &\n \t\t\t\t MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);\n+\tattr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\t\t\t wqe_index_ignore_cap);\n+\tattr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);\n+\tattr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);\n+\tattr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\t\t\t log_max_static_sq_wq);\n+\tattr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\t\t device_frequency_khz);\n \tif (attr->qos.sup) {\n \t\tMLX5_SET(query_hca_cap_in, in, op_mod,\n \t\t\t MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |\n@@ -487,9 +495,13 @@ struct mlx5_devx_obj *\n \t\tattr->qos.log_max_flow_meter =\n \t\t\t\tMLX5_GET(qos_cap, hcattr, log_max_flow_meter);\n \t\tattr->qos.flow_meter_reg_c_ids =\n-\t\t\tMLX5_GET(qos_cap, hcattr, flow_meter_reg_id);\n+\t\t\t\tMLX5_GET(qos_cap, hcattr, flow_meter_reg_id);\n \t\tattr->qos.flow_meter_reg_share =\n-\t\t\tMLX5_GET(qos_cap, hcattr, flow_meter_reg_share);\n+\t\t\t\tMLX5_GET(qos_cap, hcattr, flow_meter_reg_share);\n+\t\tattr->qos.packet_pacing =\n+\t\t\t\tMLX5_GET(qos_cap, hcattr, packet_pacing);\n+\t\tattr->qos.wqe_rate_pp =\n+\t\t\t\tMLX5_GET(qos_cap, hcattr, wqe_rate_pp);\n \t}\n \tif (attr->vdpa.valid)\n \t\tmlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);\n@@ -971,6 +983,8 @@ struct mlx5_devx_obj *\n \tMLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);\n \tMLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);\n \tMLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);\n+\tMLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);\n+\tMLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);\n \tMLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);\n \tMLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);\n \tMLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,\n@@ -1185,6 +1199,7 @@ struct mlx5_devx_obj *\n \t} else {\n \t\tMLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);\n \t}\n+\tMLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size);\n \tMLX5_SET(cqc, cqctx, cc, attr->use_first_only);\n \tMLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);\n \tMLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 25704ef..c79b349 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -29,6 +29,8 @@ struct mlx5_devx_mkey_attr {\n struct mlx5_hca_qos_attr {\n \tuint32_t sup:1;\t/* Whether QOS is supported. */\n \tuint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */\n+\tuint32_t packet_pacing:1; /* Packet pacing is supported. */\n+\tuint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */\n \tuint32_t flow_meter_reg_share:1;\n \t/* Whether reg_c share is supported. */\n \tuint8_t log_max_flow_meter;\n@@ -90,6 +92,11 @@ struct mlx5_hca_attr {\n \tuint32_t vhca_id:16;\n \tuint32_t relaxed_ordering_write:1;\n \tuint32_t relaxed_ordering_read:1;\n+\tuint32_t wqe_index_ignore:1;\n+\tuint32_t cross_channel:1;\n+\tuint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */\n+\tuint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */\n+\tuint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */\n \tstruct mlx5_hca_qos_attr qos;\n \tstruct mlx5_hca_vdpa_attr vdpa;\n };\n@@ -207,6 +214,8 @@ struct mlx5_devx_create_sq_attr {\n \tuint32_t reg_umr:1;\n \tuint32_t allow_swp:1;\n \tuint32_t hairpin:1;\n+\tuint32_t non_wire:1;\n+\tuint32_t static_sq_wq:1;\n \tuint32_t user_index:24;\n \tuint32_t cqn:24;\n \tuint32_t packet_pacing_rate_limit_index:16;\n@@ -230,6 +239,7 @@ struct mlx5_devx_cq_attr {\n \tuint32_t db_umem_valid:1;\n \tuint32_t use_first_only:1;\n \tuint32_t overrun_ignore:1;\n+\tuint32_t cqe_size:3;\n \tuint32_t log_cq_size:5;\n \tuint32_t log_page_size:5;\n \tuint32_t uar_page_id;\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex c63795f..cf47103 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -41,6 +41,10 @@\n /* Invalidate a CQE. */\n #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)\n \n+/* Hardware index widths. */\n+#define MLX5_CQ_INDEX_WIDTH 24\n+#define MLX5_WQ_INDEX_WIDTH 16\n+\n /* WQE Segment sizes in bytes. */\n #define MLX5_WSEG_SIZE 16u\n #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)\n@@ -126,7 +130,17 @@\n \t\t\t\t MLX5_ESEG_MIN_INLINE_SIZE)\n \n /* Missed in mlv5dv.h, should define here. */\n+#ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW\n #define MLX5_OPCODE_ENHANCED_MPSW 0x29u\n+#endif\n+\n+#ifndef HAVE_MLX5_OPCODE_SEND_EN\n+#define MLX5_OPCODE_SEND_EN 0x17u\n+#endif\n+\n+#ifndef HAVE_MLX5_OPCODE_WAIT\n+#define MLX5_OPCODE_WAIT 0x0fu\n+#endif\n \n /* CQE value to inform that VLAN is stripped. */\n #define MLX5_CQE_VLAN_STRIPPED (1u << 0)\n@@ -255,6 +269,9 @@\n /* The alignment needed for WQ buffer. */\n #define MLX5_WQE_BUF_ALIGNMENT sysconf(_SC_PAGESIZE)\n \n+/* The alignment needed for CQ buffer. */\n+#define MLX5_CQE_BUF_ALIGNMENT sysconf(_SC_PAGESIZE)\n+\n /* Completion mode. */\n enum mlx5_completion_mode {\n \tMLX5_COMP_ONLY_ERR = 0x0,\n@@ -314,6 +331,13 @@ struct mlx5_wqe_eseg {\n \t};\n } __rte_packed;\n \n+struct mlx5_wqe_qseg {\n+\tuint32_t reserved0;\n+\tuint32_t reserved1;\n+\tuint32_t max_index;\n+\tuint32_t qpn_cqn;\n+} __rte_packed;\n+\n /* The title WQEBB, header of WQE. */\n struct mlx5_wqe {\n \tunion {\n@@ -373,6 +397,14 @@ struct mlx5_cqe {\n \tuint8_t op_own;\n };\n \n+struct mlx5_cqe_ts {\n+\tuint64_t timestamp;\n+\tuint32_t sop_drop_qpn;\n+\tuint16_t wqe_counter;\n+\tuint8_t rsvd5;\n+\tuint8_t op_own;\n+};\n+\n /* Adding direct verbs to data-path. */\n \n /* CQ sequence number mask. */\n@@ -992,7 +1024,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 reserved_at_40[0x40];\n \tu8 log_max_srq_sz[0x8];\n \tu8 log_max_qp_sz[0x8];\n-\tu8 reserved_at_90[0xb];\n+\tu8 reserved_at_90[0x9];\n+\tu8 wqe_index_ignore_cap[0x1];\n+\tu8 dynamic_qp_allocation[0x1];\n \tu8 log_max_qp[0x5];\n \tu8 reserved_at_a0[0xb];\n \tu8 log_max_srq[0x5];\n@@ -1018,9 +1052,12 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 umr_extended_translation_offset[0x1];\n \tu8 null_mkey[0x1];\n \tu8 log_max_klm_list_size[0x6];\n-\tu8 reserved_at_120[0xa];\n+\tu8 non_wire_sq[0x1];\n+\tu8 reserved_at_121[0x9];\n \tu8 log_max_ra_req_dc[0x6];\n-\tu8 reserved_at_130[0xa];\n+\tu8 reserved_at_130[0x3];\n+\tu8 log_max_static_sq_wq[0x5];\n+\tu8 reserved_at_138[0x2];\n \tu8 log_max_ra_res_dc[0x6];\n \tu8 reserved_at_140[0xa];\n \tu8 log_max_ra_req_qp[0x6];\n@@ -1271,7 +1308,8 @@ struct mlx5_ifc_qos_cap_bits {\n \tu8 reserved_at_8[0x8];\n \tu8 log_max_flow_meter[0x8];\n \tu8 flow_meter_reg_id[0x8];\n-\tu8 reserved_at_25[0x8];\n+\tu8 wqe_rate_pp[0x1];\n+\tu8 reserved_at_25[0x7];\n \tu8 flow_meter_reg_share[0x1];\n \tu8 reserved_at_2e[0x17];\n \tu8 packet_pacing_max_rate[0x20];\n@@ -1835,7 +1873,9 @@ struct mlx5_ifc_sqc_bits {\n \tu8 reg_umr[0x1];\n \tu8 allow_swp[0x1];\n \tu8 hairpin[0x1];\n-\tu8 reserved_at_f[0x11];\n+\tu8 non_wire[0x1];\n+\tu8 static_sq_wq[0x1];\n+\tu8 reserved_at_11[0xf];\n \tu8 reserved_at_20[0x8];\n \tu8 user_index[0x18];\n \tu8 reserved_at_40[0x8];\n@@ -1935,6 +1975,11 @@ struct mlx5_ifc_flow_meter_parameters_bits {\n \tu8 reserved_at_8[0x60];\t\t// 14h-1Ch\n };\n \n+enum {\n+\tMLX5_CQE_SIZE_64B = 0x0,\n+\tMLX5_CQE_SIZE_128B = 0x1,\n+};\n+\n struct mlx5_ifc_cqc_bits {\n \tu8 status[0x4];\n \tu8 as_notify[0x1];\n@@ -2486,6 +2531,20 @@ struct mlx5_ifc_query_qp_in_bits {\n \tu8 reserved_at_60[0x20];\n };\n \n+enum {\n+\tMLX5_DATA_RATE = 0x0,\n+\tMLX5_WQE_RATE = 0x1,\n+};\n+\n+struct mlx5_ifc_set_pp_rate_limit_context_bits {\n+\tu8 rate_limit[0x20];\n+\tu8 burst_upper_bound[0x20];\n+\tu8 reserved_at_40[0xC];\n+\tu8 rate_mode[0x4];\n+\tu8 typical_packet_size[0x10];\n+\tu8 reserved_at_60[0x120];\n+};\n+\n /* CQE format mask. */\n #define MLX5E_CQE_FORMAT_MASK 0xc\n \n", "prefixes": [ "v2", "01/17" ] }