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GET /api/patches/73959/?format=api
{ "id": 73959, "url": "http://patches.dpdk.org/api/patches/73959/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200713151319.17547-3-manishc@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200713151319.17547-3-manishc@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200713151319.17547-3-manishc@marvell.com", "date": "2020-07-13T15:13:14", "name": "[v2,2/7] drivers: add generic API to find PCI extended cap", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "5af68f9afcd510e8bf36ebf441d58ab188a844ef", "submitter": { "id": 1591, "url": "http://patches.dpdk.org/api/people/1591/?format=api", "name": "Manish Chopra", "email": "manishc@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200713151319.17547-3-manishc@marvell.com/mbox/", "series": [ { "id": 11003, "url": "http://patches.dpdk.org/api/series/11003/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11003", "date": "2020-07-13T15:13:12", "name": "qede: SR-IOV PF driver support", "version": 2, "mbox": "http://patches.dpdk.org/series/11003/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/73959/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/73959/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 22B5BA0540;\n\tMon, 13 Jul 2020 17:14:48 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 0A0191D700;\n\tMon, 13 Jul 2020 17:14:48 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id B04DC1D615\n for <dev@dpdk.org>; Mon, 13 Jul 2020 17:14:45 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n 06DF9gpw016477; Mon, 13 Jul 2020 08:14:45 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 328mmhh7qs-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 13 Jul 2020 08:14:45 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH01.marvell.com\n (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 13 Jul 2020 08:14:42 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 13 Jul 2020 08:14:43 -0700", "from dut1171.mv.qlogic.com (unknown [10.112.88.18])\n by maili.marvell.com (Postfix) with ESMTP id 2C2383F703F;\n Mon, 13 Jul 2020 08:14:43 -0700 (PDT)", "from dut1171.mv.qlogic.com (localhost [127.0.0.1])\n by dut1171.mv.qlogic.com (8.14.7/8.14.7) with ESMTP id 06DFEgHG017609;\n Mon, 13 Jul 2020 08:14:42 -0700", "(from root@localhost)\n by dut1171.mv.qlogic.com (8.14.7/8.14.7/Submit) id 06DFEgRD017599;\n Mon, 13 Jul 2020 08:14:42 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0818; bh=XIoRUEblCfX1RrVCbNyJAjMu+1I69ptwDJVyAe4zFTY=;\n b=DDELmNUZqQTjjYbna+wpfEr56bwnblvWJaWcTJJK1W99SfgyfCIn46gbQX+Io8YIXrON\n t2jGOJN6m0tgOMTfkYX5FJCXtDii2rUzkwoSc89RlG3syi/7G1JjhpAwBJVMDv0uGDcG\n JwjOmHPPTqgQYazd4n6D+TMuVw7vsI3wpYwTp00bXzoSjBfTByclmUCVvNg+m27YsP20\n sAyAxKtsK2coD+INjL1dw8gRV4j27Tksflf3fxQtd9ffwcQ8H8HMveYRAg81gHWiVIHP\n gPkLKqkbIbS+UerD89YDv9mAIb5rV58jf75Ei1a+h1vPF3V7gaA1Qhh3+xc7JQHQ1uG9 2A==", "From": "Manish Chopra <manishc@marvell.com>", "To": "<jerinjacobk@gmail.com>, <jerinj@marvell.com>, <ferruh.yigit@intel.com>,\n <grive@u256.net>", "CC": "<dev@dpdk.org>, <irusskikh@marvell.com>, <rmody@marvell.com>,\n <GR-Everest-DPDK-Dev@marvell.com>, <anatoly.burakov@intel.com>,\n <xavier.huwei@huawei.com>, <humin29@huawei.com>,\n <yisen.zhuang@huawei.com>, <xiao.w.wang@intel.com>,\n <qiming.yang@intel.com>, <qi.z.zhang@intel.com>,\n <heinrich.kuhn@netronome.com>", "Date": "Mon, 13 Jul 2020 08:13:14 -0700", "Message-ID": "<20200713151319.17547-3-manishc@marvell.com>", "X-Mailer": "git-send-email 2.12.0", "In-Reply-To": "<20200713151319.17547-1-manishc@marvell.com>", "References": "<20200713151319.17547-1-manishc@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687\n definitions=2020-07-13_14:2020-07-13,\n 2020-07-13 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 2/7] drivers: add generic API to find PCI\n\textended cap", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "By adding generic API, this patch removes individual\nfunctions/defines implemented by drivers to find PCI\nextended capability.\n\nSigned-off-by: Manish Chopra <manishc@marvell.com>\nSigned-off-by: Igor Russkikh <irusskikh@marvell.com>\n---\n drivers/bus/pci/pci_common.c | 41 +++++++++++++++++\n drivers/bus/pci/rte_bus_pci.h | 11 +++++\n drivers/net/ice/ice_ethdev.c | 53 ++--------------------\n drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c | 48 ++------------------\n lib/librte_pci/rte_pci_regs.h | 2 +-\n 5 files changed, 60 insertions(+), 95 deletions(-)", "diff": "diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c\nindex a8e5fd52c..5117c8e7b 100644\n--- a/drivers/bus/pci/pci_common.c\n+++ b/drivers/bus/pci/pci_common.c\n@@ -23,6 +23,7 @@\n #include <rte_common.h>\n #include <rte_devargs.h>\n #include <rte_vfio.h>\n+#include <rte_pci_regs.h>\n \n #include \"private.h\"\n \n@@ -665,6 +666,46 @@ rte_pci_get_iommu_class(void)\n \treturn iova_mode;\n }\n \n+int rte_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)\n+{\n+\tint pos = PCI_CFG_SPACE_SIZE;\n+\tuint32_t header;\n+\tint ttl;\n+\n+\t/* minimum 8 bytes per capability */\n+\tttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;\n+\n+\tif (rte_pci_read_config(dev, &header, 4, pos) < 0) {\n+\t\tRTE_LOG(ERR, EAL, \"error in reading extended capabilities\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/*\n+\t * If we have no capabilities, this is indicated by cap ID,\n+\t * cap version and next pointer all being 0.\n+\t */\n+\tif (header == 0)\n+\t\treturn 0;\n+\n+\twhile (ttl-- > 0) {\n+\t\tif (PCI_EXT_CAP_ID(header) == cap)\n+\t\t\treturn pos;\n+\n+\t\tpos = PCI_EXT_CAP_NEXT(header);\n+\n+\t\tif (pos < PCI_CFG_SPACE_SIZE)\n+\t\t\tbreak;\n+\n+\t\tif (rte_pci_read_config(dev, &header, 4, pos) < 0) {\n+\t\t\tRTE_LOG(ERR, EAL,\n+\t\t\t\t\"error in reading extended capabilities\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n struct rte_pci_bus rte_pci_bus = {\n \t.bus = {\n \t\t.scan = rte_pci_scan,\ndiff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h\nindex 29bea6d70..3cc66220a 100644\n--- a/drivers/bus/pci/rte_bus_pci.h\n+++ b/drivers/bus/pci/rte_bus_pci.h\n@@ -224,6 +224,17 @@ void rte_pci_unmap_device(struct rte_pci_device *dev);\n */\n void rte_pci_dump(FILE *f);\n \n+/**\n+ * Find device's extended capability\n+ *\n+ * @param dev\n+ * A pointer to rte_pci_device structure\n+ *\n+ * @param cap\n+ * Extended capability to find\n+ */\n+int rte_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap);\n+\n /**\n * Register a PCI driver.\n *\ndiff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c\nindex 3534d18ca..0724324d2 100644\n--- a/drivers/net/ice/ice_ethdev.c\n+++ b/drivers/net/ice/ice_ethdev.c\n@@ -4,6 +4,8 @@\n \n #include <rte_string_fns.h>\n #include <rte_ethdev_pci.h>\n+#include <rte_bus_pci.h>\n+#include <rte_pci_regs.h>\n \n #include <stdio.h>\n #include <sys/types.h>\n@@ -1730,53 +1732,6 @@ ice_pf_setup(struct ice_pf *pf)\n \treturn 0;\n }\n \n-/* PCIe configuration space setting */\n-#define PCI_CFG_SPACE_SIZE 256\n-#define PCI_CFG_SPACE_EXP_SIZE 4096\n-#define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff)\n-#define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc)\n-#define PCI_EXT_CAP_ID_DSN 0x03\n-\n-static int\n-ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)\n-{\n-\tuint32_t header;\n-\tint ttl;\n-\tint pos = PCI_CFG_SPACE_SIZE;\n-\n-\t/* minimum 8 bytes per capability */\n-\tttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;\n-\n-\tif (rte_pci_read_config(dev, &header, 4, pos) < 0) {\n-\t\tPMD_INIT_LOG(ERR, \"ice error reading extended capabilities\\n\");\n-\t\treturn -1;\n-\t}\n-\n-\t/*\n-\t * If we have no capabilities, this is indicated by cap ID,\n-\t * cap version and next pointer all being 0.\n-\t */\n-\tif (header == 0)\n-\t\treturn 0;\n-\n-\twhile (ttl-- > 0) {\n-\t\tif (PCI_EXT_CAP_ID(header) == cap)\n-\t\t\treturn pos;\n-\n-\t\tpos = PCI_EXT_CAP_NEXT(header);\n-\n-\t\tif (pos < PCI_CFG_SPACE_SIZE)\n-\t\t\tbreak;\n-\n-\t\tif (rte_pci_read_config(dev, &header, 4, pos) < 0) {\n-\t\t\tPMD_INIT_LOG(ERR, \"ice error reading extended capabilities\\n\");\n-\t\t\treturn -1;\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n /*\n * Extract device serial number from PCIe Configuration Space and\n * determine the pkg file path according to the DSN.\n@@ -1789,9 +1744,9 @@ ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)\n \tuint32_t dsn_low, dsn_high;\n \tmemset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);\n \n-\tpos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);\n+\tpos = rte_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);\n \n-\tif (pos) {\n+\tif (pos > 0) {\n \t\trte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);\n \t\trte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);\n \t\tsnprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,\ndiff --git a/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c b/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c\nindex 0b9db974e..b11d8148a 100644\n--- a/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c\n+++ b/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c\n@@ -35,6 +35,8 @@\n \n #include <rte_ethdev_pci.h>\n #include <rte_string_fns.h>\n+#include <rte_bus_pci.h>\n+#include <rte_pci_regs.h>\n \n #include \"nfp_cpp.h\"\n #include \"nfp_target.h\"\n@@ -746,50 +748,6 @@ nfp6000_set_interface(struct rte_pci_device *dev, struct nfp_cpp *cpp)\n \treturn 0;\n }\n \n-#define PCI_CFG_SPACE_SIZE\t256\n-#define PCI_CFG_SPACE_EXP_SIZE\t4096\n-#define PCI_EXT_CAP_ID(header)\t\t(int)(header & 0x0000ffff)\n-#define PCI_EXT_CAP_NEXT(header)\t((header >> 20) & 0xffc)\n-#define PCI_EXT_CAP_ID_DSN\t0x03\n-static int\n-nfp_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)\n-{\n-\tuint32_t header;\n-\tint ttl;\n-\tint pos = PCI_CFG_SPACE_SIZE;\n-\n-\t/* minimum 8 bytes per capability */\n-\tttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;\n-\n-\tif (rte_pci_read_config(dev, &header, 4, pos) < 0) {\n-\t\tprintf(\"nfp error reading extended capabilities\\n\");\n-\t\treturn -1;\n-\t}\n-\n-\t/*\n-\t * If we have no capabilities, this is indicated by cap ID,\n-\t * cap version and next pointer all being 0.\n-\t */\n-\tif (header == 0)\n-\t\treturn 0;\n-\n-\twhile (ttl-- > 0) {\n-\t\tif (PCI_EXT_CAP_ID(header) == cap)\n-\t\t\treturn pos;\n-\n-\t\tpos = PCI_EXT_CAP_NEXT(header);\n-\t\tif (pos < PCI_CFG_SPACE_SIZE)\n-\t\t\tbreak;\n-\n-\t\tif (rte_pci_read_config(dev, &header, 4, pos) < 0) {\n-\t\t\tprintf(\"nfp error reading extended capabilities\\n\");\n-\t\t\treturn -1;\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n static int\n nfp6000_set_serial(struct rte_pci_device *dev, struct nfp_cpp *cpp)\n {\n@@ -798,7 +756,7 @@ nfp6000_set_serial(struct rte_pci_device *dev, struct nfp_cpp *cpp)\n \tint serial_len = 6;\n \tint pos;\n \n-\tpos = nfp_pci_find_next_ext_capability(dev, PCI_EXT_CAP_ID_DSN);\n+\tpos = rte_pci_find_next_ext_capability(dev, PCI_EXT_CAP_ID_DSN);\n \tif (pos <= 0) {\n \t\tprintf(\"PCI_EXT_CAP_ID_DSN not found. nfp set serial failed\\n\");\n \t\treturn -1;\ndiff --git a/lib/librte_pci/rte_pci_regs.h b/lib/librte_pci/rte_pci_regs.h\nindex 1d11f4de5..108193049 100644\n--- a/lib/librte_pci/rte_pci_regs.h\n+++ b/lib/librte_pci/rte_pci_regs.h\n@@ -686,7 +686,7 @@\n #define PCI_EXP_SLTSTA2\t\t58\t/* Slot Status 2 */\n \n /* Extended Capabilities (PCI-X 2.0 and Express) */\n-#define PCI_EXT_CAP_ID(header)\t\t(header & 0x0000ffff)\n+#define PCI_EXT_CAP_ID(header)\t\t(int)(header & 0x0000ffff)\n #define PCI_EXT_CAP_VER(header)\t\t((header >> 16) & 0xf)\n #define PCI_EXT_CAP_NEXT(header)\t((header >> 20) & 0xffc)\n \n", "prefixes": [ "v2", "2/7" ] }