Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/73958/?format=api
{ "id": 73958, "url": "http://patches.dpdk.org/api/patches/73958/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200713151319.17547-2-manishc@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200713151319.17547-2-manishc@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200713151319.17547-2-manishc@marvell.com", "date": "2020-07-13T15:13:13", "name": "[v2,1/7] lib/librte_pci: add rte_pci_regs.h", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "dc84f9daf6fe809764f4eacea021aa0ec9541005", "submitter": { "id": 1591, "url": "http://patches.dpdk.org/api/people/1591/?format=api", "name": "Manish Chopra", "email": "manishc@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200713151319.17547-2-manishc@marvell.com/mbox/", "series": [ { "id": 11003, "url": "http://patches.dpdk.org/api/series/11003/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11003", "date": "2020-07-13T15:13:12", "name": "qede: SR-IOV PF driver support", "version": 2, "mbox": "http://patches.dpdk.org/series/11003/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/73958/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/73958/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 416A9A0540;\n\tMon, 13 Jul 2020 17:14:24 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1EC561D639;\n\tMon, 13 Jul 2020 17:14:24 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 7A3761D615\n for <dev@dpdk.org>; Mon, 13 Jul 2020 17:14:22 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n 06DF9w3h016724; Mon, 13 Jul 2020 08:14:21 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n by mx0b-0016f401.pphosted.com with ESMTP id 328mmhh7pr-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 13 Jul 2020 08:14:21 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH03.marvell.com\n (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 13 Jul 2020 08:14:18 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 13 Jul 2020 08:14:19 -0700", "from dut1171.mv.qlogic.com (unknown [10.112.88.18])\n by maili.marvell.com (Postfix) with ESMTP id EC6EB3F7044;\n Mon, 13 Jul 2020 08:14:18 -0700 (PDT)", "from dut1171.mv.qlogic.com (localhost [127.0.0.1])\n by dut1171.mv.qlogic.com (8.14.7/8.14.7) with ESMTP id 06DFEIQS017596;\n Mon, 13 Jul 2020 08:14:18 -0700", "(from root@localhost)\n by dut1171.mv.qlogic.com (8.14.7/8.14.7/Submit) id 06DFEIjQ017595;\n Mon, 13 Jul 2020 08:14:18 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0818; bh=XuzxdlrSCusSe0KiGJzg0I3sHK0L6QnCvEpuuygTjzg=;\n b=hdQzWE9v8BRj70NgmxM0W2OIGWsoifutnMsrUxgo9mSxwKt2Pl6nfdDMXt9JmRfhr5SI\n 6uARwB5qUCJn1g4wknCT/ocuWSgiagWHL7E2SCBvbvT5sHK9hvELYHzynvCIdxa3fDaq\n tmCaD/Mv8kn/KHoC78BZ66fhbSQOj9o3nAH5PwbeSx0V69qugA1EKWNy3Hoone7FPrDt\n QpuOpSmds175Ai5oC3YRr8q8FwUGlkRnHvGvtfPzkq8x1xwh0znTBugiTqu1W8bpsugK\n u9NpoYg7ZT65m/QG/BFCq8cwFuG99DyshAXfYDZ8Bb3SbNRQFPVHKRCRSdf3Lt7asIBY cw==", "From": "Manish Chopra <manishc@marvell.com>", "To": "<jerinjacobk@gmail.com>, <jerinj@marvell.com>, <ferruh.yigit@intel.com>,\n <grive@u256.net>", "CC": "<dev@dpdk.org>, <irusskikh@marvell.com>, <rmody@marvell.com>,\n <GR-Everest-DPDK-Dev@marvell.com>, <anatoly.burakov@intel.com>,\n <xavier.huwei@huawei.com>, <humin29@huawei.com>,\n <yisen.zhuang@huawei.com>, <xiao.w.wang@intel.com>,\n <qiming.yang@intel.com>, <qi.z.zhang@intel.com>,\n <heinrich.kuhn@netronome.com>", "Date": "Mon, 13 Jul 2020 08:13:13 -0700", "Message-ID": "<20200713151319.17547-2-manishc@marvell.com>", "X-Mailer": "git-send-email 2.12.0", "In-Reply-To": "<20200713151319.17547-1-manishc@marvell.com>", "References": "<20200713151319.17547-1-manishc@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687\n definitions=2020-07-13_14:2020-07-13,\n 2020-07-13 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 1/7] lib/librte_pci: add rte_pci_regs.h", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This is merely copy of latest linux/pci_regs.h in\norder to avoid dependency of dpdk on user headers.\n\nSigned-off-by: Manish Chopra <manishc@marvell.com>\nSigned-off-by: Igor Russkikh <irusskikh@marvell.com>\n---\n drivers/bus/pci/linux/pci_uio.c | 2 +-\n drivers/bus/pci/linux/pci_vfio.c | 2 +-\n drivers/net/bnx2x/bnx2x.h | 2 +-\n drivers/net/hns3/hns3_ethdev_vf.c | 2 +-\n drivers/vdpa/ifc/base/ifcvf_osdep.h | 2 +-\n lib/librte_pci/Makefile | 1 +\n lib/librte_pci/meson.build | 2 +-\n lib/librte_pci/rte_pci_regs.h | 1075 +++++++++++++++++++++++++++\n 8 files changed, 1082 insertions(+), 6 deletions(-)\n create mode 100644 lib/librte_pci/rte_pci_regs.h", "diff": "diff --git a/drivers/bus/pci/linux/pci_uio.c b/drivers/bus/pci/linux/pci_uio.c\nindex b62200153..698eace00 100644\n--- a/drivers/bus/pci/linux/pci_uio.c\n+++ b/drivers/bus/pci/linux/pci_uio.c\n@@ -10,12 +10,12 @@\n #include <sys/stat.h>\n #include <sys/mman.h>\n #include <sys/sysmacros.h>\n-#include <linux/pci_regs.h>\n \n #if defined(RTE_ARCH_X86)\n #include <sys/io.h>\n #endif\n \n+#include <rte_pci_regs.h>\n #include <rte_string_fns.h>\n #include <rte_log.h>\n #include <rte_pci.h>\ndiff --git a/drivers/bus/pci/linux/pci_vfio.c b/drivers/bus/pci/linux/pci_vfio.c\nindex fdeb9a8ca..96494fcfd 100644\n--- a/drivers/bus/pci/linux/pci_vfio.c\n+++ b/drivers/bus/pci/linux/pci_vfio.c\n@@ -4,13 +4,13 @@\n \n #include <string.h>\n #include <fcntl.h>\n-#include <linux/pci_regs.h>\n #include <sys/eventfd.h>\n #include <sys/socket.h>\n #include <sys/ioctl.h>\n #include <sys/mman.h>\n #include <stdbool.h>\n \n+#include <rte_pci_regs.h>\n #include <rte_log.h>\n #include <rte_pci.h>\n #include <rte_bus_pci.h>\ndiff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h\nindex 69cc1430a..4ec269dc6 100644\n--- a/drivers/net/bnx2x/bnx2x.h\n+++ b/drivers/net/bnx2x/bnx2x.h\n@@ -18,6 +18,7 @@\n #include <rte_spinlock.h>\n #include <rte_bus_pci.h>\n #include <rte_io.h>\n+#include <rte_pci_regs.h>\n \n #include \"bnx2x_osal.h\"\n #include \"bnx2x_ethdev.h\"\n@@ -31,7 +32,6 @@\n #include \"elink.h\"\n \n #ifndef RTE_EXEC_ENV_FREEBSD\n-#include <linux/pci_regs.h>\n \n #define PCIY_PMG PCI_CAP_ID_PM\n #define PCIY_MSI PCI_CAP_ID_MSI\ndiff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c\nindex 54e5dac52..81f9e7edc 100644\n--- a/drivers/net/hns3/hns3_ethdev_vf.c\n+++ b/drivers/net/hns3/hns3_ethdev_vf.c\n@@ -9,8 +9,8 @@\n #include <inttypes.h>\n #include <unistd.h>\n #include <arpa/inet.h>\n-#include <linux/pci_regs.h>\n \n+#include <rte_pci_regs.h>\n #include <rte_alarm.h>\n #include <rte_atomic.h>\n #include <rte_bus_pci.h>\ndiff --git a/drivers/vdpa/ifc/base/ifcvf_osdep.h b/drivers/vdpa/ifc/base/ifcvf_osdep.h\nindex 6aef25ea4..0a759703d 100644\n--- a/drivers/vdpa/ifc/base/ifcvf_osdep.h\n+++ b/drivers/vdpa/ifc/base/ifcvf_osdep.h\n@@ -6,8 +6,8 @@\n #define _IFCVF_OSDEP_H_\n \n #include <stdint.h>\n-#include <linux/pci_regs.h>\n \n+#include <rte_pci_regs.h>\n #include <rte_cycles.h>\n #include <rte_pci.h>\n #include <rte_bus_pci.h>\ndiff --git a/lib/librte_pci/Makefile b/lib/librte_pci/Makefile\nindex 7943f30ca..4d153b9ac 100644\n--- a/lib/librte_pci/Makefile\n+++ b/lib/librte_pci/Makefile\n@@ -15,5 +15,6 @@ EXPORT_MAP := rte_pci_version.map\n SRCS-$(CONFIG_RTE_LIBRTE_PCI) += rte_pci.c\n \n SYMLINK-$(CONFIG_RTE_LIBRTE_PCI)-include += rte_pci.h\n+SYMLINK-y-include += rte_pci_regs.h\n \n include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/lib/librte_pci/meson.build b/lib/librte_pci/meson.build\nindex dd41cd506..5c7afbbfb 100644\n--- a/lib/librte_pci/meson.build\n+++ b/lib/librte_pci/meson.build\n@@ -2,4 +2,4 @@\n # Copyright(c) 2017 Intel Corporation\n \n sources = files('rte_pci.c')\n-headers = files('rte_pci.h')\n+headers = files('rte_pci.h', 'rte_pci_regs.h')\ndiff --git a/lib/librte_pci/rte_pci_regs.h b/lib/librte_pci/rte_pci_regs.h\nnew file mode 100644\nindex 000000000..1d11f4de5\n--- /dev/null\n+++ b/lib/librte_pci/rte_pci_regs.h\n@@ -0,0 +1,1075 @@\n+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */\n+/*\n+ *\tPCI standard defines\n+ *\tCopyright 1994, Drew Eckhardt\n+ *\tCopyright 1997--1999 Martin Mares <mj@ucw.cz>\n+ *\n+ *\tFor more information, please consult the following manuals (look at\n+ *\thttp://www.pcisig.com/ for how to get them):\n+ *\n+ *\tPCI BIOS Specification\n+ *\tPCI Local Bus Specification\n+ *\tPCI to PCI Bridge Specification\n+ *\tPCI System Design Guide\n+ *\n+ *\tFor HyperTransport information, please consult the following manuals\n+ *\tfrom http://www.hypertransport.org :\n+ *\n+ *\tThe HyperTransport I/O Link Specification\n+ */\n+\n+#ifndef _RTE_PCI_REGS_H_\n+#define _RTE_PCI_REGS_H_\n+\n+/*\n+ * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of\n+ * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of\n+ * configuration space.\n+ */\n+#define PCI_CFG_SPACE_SIZE\t256\n+#define PCI_CFG_SPACE_EXP_SIZE\t4096\n+\n+/*\n+ * Under PCI, each device has 256 bytes of configuration address space,\n+ * of which the first 64 bytes are standardized as follows:\n+ */\n+#define PCI_STD_HEADER_SIZEOF\t64\n+#define PCI_STD_NUM_BARS\t6\t/* Number of standard BARs */\n+#define PCI_VENDOR_ID\t\t0x00\t/* 16 bits */\n+#define PCI_DEVICE_ID\t\t0x02\t/* 16 bits */\n+#define PCI_COMMAND\t\t0x04\t/* 16 bits */\n+#define PCI_COMMAND_IO\t\t0x1\t/* Enable response in I/O space */\n+#define PCI_COMMAND_MEMORY\t0x2\t/* Enable response in Memory space */\n+#define PCI_COMMAND_MASTER\t0x4\t/* Enable bus mastering */\n+#define PCI_COMMAND_SPECIAL\t0x8\t/* Enable response to special cycles */\n+#define PCI_COMMAND_INVALIDATE\t0x10\t/* Use memory write and invalidate */\n+#define PCI_COMMAND_VGA_PALETTE 0x20\t/* Enable palette snooping */\n+#define PCI_COMMAND_PARITY\t0x40\t/* Enable parity checking */\n+#define PCI_COMMAND_WAIT\t0x80\t/* Enable address/data stepping */\n+#define PCI_COMMAND_SERR\t0x100\t/* Enable SERR */\n+#define PCI_COMMAND_FAST_BACK\t0x200\t/* Enable back-to-back writes */\n+#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */\n+\n+#define PCI_STATUS\t\t0x06\t/* 16 bits */\n+#define PCI_STATUS_IMM_READY\t0x01\t/* Immediate Readiness */\n+#define PCI_STATUS_INTERRUPT\t0x08\t/* Interrupt status */\n+#define PCI_STATUS_CAP_LIST\t0x10\t/* Support Capability List */\n+#define PCI_STATUS_66MHZ\t0x20\t/* Support 66 MHz PCI 2.1 bus */\n+#define PCI_STATUS_UDF\t\t0x40\t/* Support User Definable Features [obsolete] */\n+#define PCI_STATUS_FAST_BACK\t0x80\t/* Accept fast-back to back */\n+#define PCI_STATUS_PARITY\t0x100\t/* Detected parity error */\n+#define PCI_STATUS_DEVSEL_MASK\t0x600\t/* DEVSEL timing */\n+#define PCI_STATUS_DEVSEL_FAST\t\t0x000\n+#define PCI_STATUS_DEVSEL_MEDIUM\t0x200\n+#define PCI_STATUS_DEVSEL_SLOW\t\t0x400\n+#define PCI_STATUS_SIG_TARGET_ABORT\t0x800 /* Set on target abort */\n+#define PCI_STATUS_REC_TARGET_ABORT\t0x1000 /* Master ack of \" */\n+#define PCI_STATUS_REC_MASTER_ABORT\t0x2000 /* Set on master abort */\n+#define PCI_STATUS_SIG_SYSTEM_ERROR\t0x4000 /* Set when we drive SERR */\n+#define PCI_STATUS_DETECTED_PARITY\t0x8000 /* Set on parity error */\n+\n+#define PCI_CLASS_REVISION\t0x08\t/* High 24 bits are class, low 8 revision */\n+#define PCI_REVISION_ID\t\t0x08\t/* Revision ID */\n+#define PCI_CLASS_PROG\t\t0x09\t/* Reg. Level Programming Interface */\n+#define PCI_CLASS_DEVICE\t0x0a\t/* Device class */\n+\n+#define PCI_CACHE_LINE_SIZE\t0x0c\t/* 8 bits */\n+#define PCI_LATENCY_TIMER\t0x0d\t/* 8 bits */\n+#define PCI_HEADER_TYPE\t\t0x0e\t/* 8 bits */\n+#define PCI_HEADER_TYPE_NORMAL\t\t0\n+#define PCI_HEADER_TYPE_BRIDGE\t\t1\n+#define PCI_HEADER_TYPE_CARDBUS\t2\n+\n+#define PCI_BIST\t\t0x0f\t/* 8 bits */\n+#define PCI_BIST_CODE_MASK\t0x0f\t/* Return result */\n+#define PCI_BIST_START\t\t0x40\t/* 1 to start BIST, 2 secs or less */\n+#define PCI_BIST_CAPABLE\t0x80\t/* 1 if BIST capable */\n+\n+/*\n+ * Base addresses specify locations in memory or I/O space.\n+ * Decoded size can be determined by writing a value of\n+ * 0xffffffff to the register, and reading it back. Only\n+ * 1 bits are decoded.\n+ */\n+#define PCI_BASE_ADDRESS_0\t0x10\t/* 32 bits */\n+#define PCI_BASE_ADDRESS_1\t0x14\t/* 32 bits [htype 0,1 only] */\n+#define PCI_BASE_ADDRESS_2\t0x18\t/* 32 bits [htype 0 only] */\n+#define PCI_BASE_ADDRESS_3\t0x1c\t/* 32 bits */\n+#define PCI_BASE_ADDRESS_4\t0x20\t/* 32 bits */\n+#define PCI_BASE_ADDRESS_5\t0x24\t/* 32 bits */\n+#define PCI_BASE_ADDRESS_SPACE\t\t0x01\t/* 0 = memory, 1 = I/O */\n+#define PCI_BASE_ADDRESS_SPACE_IO\t0x01\n+#define PCI_BASE_ADDRESS_SPACE_MEMORY\t0x00\n+#define PCI_BASE_ADDRESS_MEM_TYPE_MASK\t0x06\n+#define PCI_BASE_ADDRESS_MEM_TYPE_32\t0x00\t/* 32 bit address */\n+#define PCI_BASE_ADDRESS_MEM_TYPE_1M\t0x02\t/* Below 1M [obsolete] */\n+#define PCI_BASE_ADDRESS_MEM_TYPE_64\t0x04\t/* 64 bit address */\n+#define PCI_BASE_ADDRESS_MEM_PREFETCH\t0x08\t/* prefetchable? */\n+#define PCI_BASE_ADDRESS_MEM_MASK\t(~0x0fUL)\n+#define PCI_BASE_ADDRESS_IO_MASK\t(~0x03UL)\n+/* bit 1 is reserved if address_space = 1 */\n+\n+/* Header type 0 (normal devices) */\n+#define PCI_CARDBUS_CIS\t\t0x28\n+#define PCI_SUBSYSTEM_VENDOR_ID\t0x2c\n+#define PCI_SUBSYSTEM_ID\t0x2e\n+#define PCI_ROM_ADDRESS\t\t0x30\t/* Bits 31..11 are address, 10..1 reserved */\n+#define PCI_ROM_ADDRESS_ENABLE\t0x01\n+#define PCI_ROM_ADDRESS_MASK\t(~0x7ffU)\n+\n+#define PCI_CAPABILITY_LIST\t0x34\t/* Offset of first capability list entry */\n+\n+/* 0x35-0x3b are reserved */\n+#define PCI_INTERRUPT_LINE\t0x3c\t/* 8 bits */\n+#define PCI_INTERRUPT_PIN\t0x3d\t/* 8 bits */\n+#define PCI_MIN_GNT\t\t0x3e\t/* 8 bits */\n+#define PCI_MAX_LAT\t\t0x3f\t/* 8 bits */\n+\n+/* Header type 1 (PCI-to-PCI bridges) */\n+#define PCI_PRIMARY_BUS\t\t0x18\t/* Primary bus number */\n+#define PCI_SECONDARY_BUS\t0x19\t/* Secondary bus number */\n+#define PCI_SUBORDINATE_BUS\t0x1a\t/* Highest bus number behind the bridge */\n+#define PCI_SEC_LATENCY_TIMER\t0x1b\t/* Latency timer for secondary interface */\n+#define PCI_IO_BASE\t\t0x1c\t/* I/O range behind the bridge */\n+#define PCI_IO_LIMIT\t\t0x1d\n+#define PCI_IO_RANGE_TYPE_MASK\t0x0fUL\t/* I/O bridging type */\n+#define PCI_IO_RANGE_TYPE_16\t0x00\n+#define PCI_IO_RANGE_TYPE_32\t0x01\n+#define PCI_IO_RANGE_MASK\t(~0x0fUL) /* Standard 4K I/O windows */\n+#define PCI_IO_1K_RANGE_MASK\t(~0x03UL) /* Intel 1K I/O windows */\n+#define PCI_SEC_STATUS\t\t0x1e\t/* Secondary status register, only bit 14 used */\n+#define PCI_MEMORY_BASE\t\t0x20\t/* Memory range behind */\n+#define PCI_MEMORY_LIMIT\t0x22\n+#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL\n+#define PCI_MEMORY_RANGE_MASK\t(~0x0fUL)\n+#define PCI_PREF_MEMORY_BASE\t0x24\t/* Prefetchable memory range behind */\n+#define PCI_PREF_MEMORY_LIMIT\t0x26\n+#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL\n+#define PCI_PREF_RANGE_TYPE_32\t0x00\n+#define PCI_PREF_RANGE_TYPE_64\t0x01\n+#define PCI_PREF_RANGE_MASK\t(~0x0fUL)\n+#define PCI_PREF_BASE_UPPER32\t0x28\t/* Upper half of prefetchable memory range */\n+#define PCI_PREF_LIMIT_UPPER32\t0x2c\n+#define PCI_IO_BASE_UPPER16\t0x30\t/* Upper half of I/O addresses */\n+#define PCI_IO_LIMIT_UPPER16\t0x32\n+/* 0x34 same as for htype 0 */\n+/* 0x35-0x3b is reserved */\n+#define PCI_ROM_ADDRESS1\t0x38\t/* Same as PCI_ROM_ADDRESS, but for htype 1 */\n+/* 0x3c-0x3d are same as for htype 0 */\n+#define PCI_BRIDGE_CONTROL\t0x3e\n+#define PCI_BRIDGE_CTL_PARITY\t0x01\t/* Enable parity detection on secondary interface */\n+#define PCI_BRIDGE_CTL_SERR\t0x02\t/* The same for SERR forwarding */\n+#define PCI_BRIDGE_CTL_ISA\t0x04\t/* Enable ISA mode */\n+#define PCI_BRIDGE_CTL_VGA\t0x08\t/* Forward VGA addresses */\n+#define PCI_BRIDGE_CTL_MASTER_ABORT\t0x20 /* Report master aborts */\n+#define PCI_BRIDGE_CTL_BUS_RESET\t0x40\t/* Secondary bus reset */\n+#define PCI_BRIDGE_CTL_FAST_BACK\t0x80\t/* Fast Back2Back enabled on secondary interface */\n+\n+/* Header type 2 (CardBus bridges) */\n+#define PCI_CB_CAPABILITY_LIST\t0x14\n+/* 0x15 reserved */\n+#define PCI_CB_SEC_STATUS\t0x16\t/* Secondary status */\n+#define PCI_CB_PRIMARY_BUS\t0x18\t/* PCI bus number */\n+#define PCI_CB_CARD_BUS\t\t0x19\t/* CardBus bus number */\n+#define PCI_CB_SUBORDINATE_BUS\t0x1a\t/* Subordinate bus number */\n+#define PCI_CB_LATENCY_TIMER\t0x1b\t/* CardBus latency timer */\n+#define PCI_CB_MEMORY_BASE_0\t0x1c\n+#define PCI_CB_MEMORY_LIMIT_0\t0x20\n+#define PCI_CB_MEMORY_BASE_1\t0x24\n+#define PCI_CB_MEMORY_LIMIT_1\t0x28\n+#define PCI_CB_IO_BASE_0\t0x2c\n+#define PCI_CB_IO_BASE_0_HI\t0x2e\n+#define PCI_CB_IO_LIMIT_0\t0x30\n+#define PCI_CB_IO_LIMIT_0_HI\t0x32\n+#define PCI_CB_IO_BASE_1\t0x34\n+#define PCI_CB_IO_BASE_1_HI\t0x36\n+#define PCI_CB_IO_LIMIT_1\t0x38\n+#define PCI_CB_IO_LIMIT_1_HI\t0x3a\n+#define PCI_CB_IO_RANGE_MASK\t(~0x03UL)\n+/* 0x3c-0x3d are same as for htype 0 */\n+#define PCI_CB_BRIDGE_CONTROL\t0x3e\n+#define PCI_CB_BRIDGE_CTL_PARITY\t0x01\t/* Similar to standard bridge control register */\n+#define PCI_CB_BRIDGE_CTL_SERR\t\t0x02\n+#define PCI_CB_BRIDGE_CTL_ISA\t\t0x04\n+#define PCI_CB_BRIDGE_CTL_VGA\t\t0x08\n+#define PCI_CB_BRIDGE_CTL_MASTER_ABORT\t0x20\n+#define PCI_CB_BRIDGE_CTL_CB_RESET\t0x40\t/* CardBus reset */\n+#define PCI_CB_BRIDGE_CTL_16BIT_INT\t0x80\t/* Enable interrupt for 16-bit cards */\n+#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100\t/* Prefetch enable for both memory regions */\n+#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200\n+#define PCI_CB_BRIDGE_CTL_POST_WRITES\t0x400\n+#define PCI_CB_SUBSYSTEM_VENDOR_ID\t0x40\n+#define PCI_CB_SUBSYSTEM_ID\t\t0x42\n+#define PCI_CB_LEGACY_MODE_BASE\t\t0x44\t/* 16-bit PC Card legacy mode base address (ExCa) */\n+/* 0x48-0x7f reserved */\n+\n+/* Capability lists */\n+\n+#define PCI_CAP_LIST_ID\t\t0\t/* Capability ID */\n+#define PCI_CAP_ID_PM\t\t0x01\t/* Power Management */\n+#define PCI_CAP_ID_AGP\t\t0x02\t/* Accelerated Graphics Port */\n+#define PCI_CAP_ID_VPD\t\t0x03\t/* Vital Product Data */\n+#define PCI_CAP_ID_SLOTID\t0x04\t/* Slot Identification */\n+#define PCI_CAP_ID_MSI\t\t0x05\t/* Message Signalled Interrupts */\n+#define PCI_CAP_ID_CHSWP\t0x06\t/* CompactPCI HotSwap */\n+#define PCI_CAP_ID_PCIX\t0x07\t/* PCI-X */\n+#define PCI_CAP_ID_HT\t\t0x08\t/* HyperTransport */\n+#define PCI_CAP_ID_VNDR\t0x09\t/* Vendor-Specific */\n+#define PCI_CAP_ID_DBG\t\t0x0A\t/* Debug port */\n+#define PCI_CAP_ID_CCRC\t0x0B\t/* CompactPCI Central Resource Control */\n+#define PCI_CAP_ID_SHPC\t0x0C\t/* PCI Standard Hot-Plug Controller */\n+#define PCI_CAP_ID_SSVID\t0x0D\t/* Bridge subsystem vendor/device ID */\n+#define PCI_CAP_ID_AGP3\t0x0E\t/* AGP Target PCI-PCI bridge */\n+#define PCI_CAP_ID_SECDEV\t0x0F\t/* Secure Device */\n+#define PCI_CAP_ID_EXP\t\t0x10\t/* PCI Express */\n+#define PCI_CAP_ID_MSIX\t0x11\t/* MSI-X */\n+#define PCI_CAP_ID_SATA\t0x12\t/* SATA Data/Index Conf. */\n+#define PCI_CAP_ID_AF\t\t0x13\t/* PCI Advanced Features */\n+#define PCI_CAP_ID_EA\t\t0x14\t/* PCI Enhanced Allocation */\n+#define PCI_CAP_ID_MAX\t\tPCI_CAP_ID_EA\n+#define PCI_CAP_LIST_NEXT\t1\t/* Next capability in the list */\n+#define PCI_CAP_FLAGS\t\t2\t/* Capability defined flags (16 bits) */\n+#define PCI_CAP_SIZEOF\t\t4\n+\n+/* Power Management Registers */\n+\n+#define PCI_PM_PMC\t\t2\t/* PM Capabilities Register */\n+#define PCI_PM_CAP_VER_MASK\t0x0007\t/* Version */\n+#define PCI_PM_CAP_PME_CLOCK\t0x0008\t/* PME clock required */\n+#define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */\n+#define PCI_PM_CAP_DSI\t\t0x0020\t/* Device specific initialization */\n+#define PCI_PM_CAP_AUX_POWER\t0x01C0\t/* Auxiliary power support mask */\n+#define PCI_PM_CAP_D1\t\t0x0200\t/* D1 power state support */\n+#define PCI_PM_CAP_D2\t\t0x0400\t/* D2 power state support */\n+#define PCI_PM_CAP_PME\t\t0x0800\t/* PME pin supported */\n+#define PCI_PM_CAP_PME_MASK\t0xF800\t/* PME Mask of all supported states */\n+#define PCI_PM_CAP_PME_D0\t0x0800\t/* PME# from D0 */\n+#define PCI_PM_CAP_PME_D1\t0x1000\t/* PME# from D1 */\n+#define PCI_PM_CAP_PME_D2\t0x2000\t/* PME# from D2 */\n+#define PCI_PM_CAP_PME_D3\t0x4000\t/* PME# from D3 (hot) */\n+#define PCI_PM_CAP_PME_D3cold\t0x8000\t/* PME# from D3 (cold) */\n+#define PCI_PM_CAP_PME_SHIFT\t11\t/* Start of the PME Mask in PMC */\n+#define PCI_PM_CTRL\t\t4\t/* PM control and status register */\n+#define PCI_PM_CTRL_STATE_MASK\t0x0003\t/* Current power state (D0 to D3) */\n+#define PCI_PM_CTRL_NO_SOFT_RESET\t0x0008\t/* No reset for D3hot->D0 */\n+#define PCI_PM_CTRL_PME_ENABLE\t0x0100\t/* PME pin enable */\n+#define PCI_PM_CTRL_DATA_SEL_MASK\t0x1e00\t/* Data select (??) */\n+#define PCI_PM_CTRL_DATA_SCALE_MASK\t0x6000\t/* Data scale (??) */\n+#define PCI_PM_CTRL_PME_STATUS\t0x8000\t/* PME pin status */\n+#define PCI_PM_PPB_EXTENSIONS\t6\t/* PPB support extensions (??) */\n+#define PCI_PM_PPB_B2_B3\t0x40\t/* Stop clock when in D3hot (??) */\n+#define PCI_PM_BPCC_ENABLE\t0x80\t/* Bus power/clock control enable (??) */\n+#define PCI_PM_DATA_REGISTER\t7\t/* (??) */\n+#define PCI_PM_SIZEOF\t\t8\n+\n+/* AGP registers */\n+\n+#define PCI_AGP_VERSION\t\t2\t/* BCD version number */\n+#define PCI_AGP_RFU\t\t3\t/* Rest of capability flags */\n+#define PCI_AGP_STATUS\t\t4\t/* Status register */\n+#define PCI_AGP_STATUS_RQ_MASK\t0xff000000\t/* Maximum number of requests - 1 */\n+#define PCI_AGP_STATUS_SBA\t0x0200\t/* Sideband addressing supported */\n+#define PCI_AGP_STATUS_64BIT\t0x0020\t/* 64-bit addressing supported */\n+#define PCI_AGP_STATUS_FW\t0x0010\t/* FW transfers supported */\n+#define PCI_AGP_STATUS_RATE4\t0x0004\t/* 4x transfer rate supported */\n+#define PCI_AGP_STATUS_RATE2\t0x0002\t/* 2x transfer rate supported */\n+#define PCI_AGP_STATUS_RATE1\t0x0001\t/* 1x transfer rate supported */\n+#define PCI_AGP_COMMAND\t\t8\t/* Control register */\n+#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */\n+#define PCI_AGP_COMMAND_SBA\t0x0200\t/* Sideband addressing enabled */\n+#define PCI_AGP_COMMAND_AGP\t0x0100\t/* Allow processing of AGP transactions */\n+#define PCI_AGP_COMMAND_64BIT\t0x0020\t/* Allow processing of 64-bit addresses */\n+#define PCI_AGP_COMMAND_FW\t0x0010\t/* Force FW transfers */\n+#define PCI_AGP_COMMAND_RATE4\t0x0004\t/* Use 4x rate */\n+#define PCI_AGP_COMMAND_RATE2\t0x0002\t/* Use 2x rate */\n+#define PCI_AGP_COMMAND_RATE1\t0x0001\t/* Use 1x rate */\n+#define PCI_AGP_SIZEOF\t\t12\n+\n+/* Vital Product Data */\n+\n+#define PCI_VPD_ADDR\t\t2\t/* Address to access (15 bits!) */\n+#define PCI_VPD_ADDR_MASK\t0x7fff\t/* Address mask */\n+#define PCI_VPD_ADDR_F\t\t0x8000\t/* Write 0, 1 indicates completion */\n+#define PCI_VPD_DATA\t\t4\t/* 32-bits of data returned here */\n+#define PCI_CAP_VPD_SIZEOF\t8\n+\n+/* Slot Identification */\n+\n+#define PCI_SID_ESR\t\t2\t/* Expansion Slot Register */\n+#define PCI_SID_ESR_NSLOTS\t0x1f\t/* Number of expansion slots available */\n+#define PCI_SID_ESR_FIC\t0x20\t/* First In Chassis Flag */\n+#define PCI_SID_CHASSIS_NR\t3\t/* Chassis Number */\n+\n+/* Message Signalled Interrupt registers */\n+\n+#define PCI_MSI_FLAGS\t\t2\t/* Message Control */\n+#define PCI_MSI_FLAGS_ENABLE\t0x0001\t/* MSI feature enabled */\n+#define PCI_MSI_FLAGS_QMASK\t0x000e\t/* Maximum queue size available */\n+#define PCI_MSI_FLAGS_QSIZE\t0x0070\t/* Message queue size configured */\n+#define PCI_MSI_FLAGS_64BIT\t0x0080\t/* 64-bit addresses allowed */\n+#define PCI_MSI_FLAGS_MASKBIT\t0x0100\t/* Per-vector masking capable */\n+#define PCI_MSI_RFU\t\t3\t/* Rest of capability flags */\n+#define PCI_MSI_ADDRESS_LO\t4\t/* Lower 32 bits */\n+#define PCI_MSI_ADDRESS_HI\t8\t/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */\n+#define PCI_MSI_DATA_32\t\t8\t/* 16 bits of data for 32-bit devices */\n+#define PCI_MSI_MASK_32\t\t12\t/* Mask bits register for 32-bit devices */\n+#define PCI_MSI_PENDING_32\t16\t/* Pending intrs for 32-bit devices */\n+#define PCI_MSI_DATA_64\t\t12\t/* 16 bits of data for 64-bit devices */\n+#define PCI_MSI_MASK_64\t\t16\t/* Mask bits register for 64-bit devices */\n+#define PCI_MSI_PENDING_64\t20\t/* Pending intrs for 64-bit devices */\n+\n+/* MSI-X registers (in MSI-X capability) */\n+#define PCI_MSIX_FLAGS\t\t2\t/* Message Control */\n+#define PCI_MSIX_FLAGS_QSIZE\t0x07FF\t/* Table size */\n+#define PCI_MSIX_FLAGS_MASKALL\t0x4000\t/* Mask all vectors for this function */\n+#define PCI_MSIX_FLAGS_ENABLE\t0x8000\t/* MSI-X enable */\n+#define PCI_MSIX_TABLE\t\t4\t/* Table offset */\n+#define PCI_MSIX_TABLE_BIR\t0x00000007 /* BAR index */\n+#define PCI_MSIX_TABLE_OFFSET\t0xfffffff8 /* Offset into specified BAR */\n+#define PCI_MSIX_PBA\t\t8\t/* Pending Bit Array offset */\n+#define PCI_MSIX_PBA_BIR\t0x00000007 /* BAR index */\n+#define PCI_MSIX_PBA_OFFSET\t0xfffffff8 /* Offset into specified BAR */\n+#define PCI_MSIX_FLAGS_BIRMASK\tPCI_MSIX_PBA_BIR /* deprecated */\n+#define PCI_CAP_MSIX_SIZEOF\t12\t/* size of MSIX registers */\n+\n+/* MSI-X Table entry format (in memory mapped by a BAR) */\n+#define PCI_MSIX_ENTRY_SIZE\t\t16\n+#define PCI_MSIX_ENTRY_LOWER_ADDR\t0 /* Message Address */\n+#define PCI_MSIX_ENTRY_UPPER_ADDR\t4 /* Message Upper Address */\n+#define PCI_MSIX_ENTRY_DATA\t\t8 /* Message Data */\n+#define PCI_MSIX_ENTRY_VECTOR_CTRL\t12 /* Vector Control */\n+#define PCI_MSIX_ENTRY_CTRL_MASKBIT\t0x00000001\n+\n+/* CompactPCI Hotswap Register */\n+\n+#define PCI_CHSWP_CSR\t\t2\t/* Control and Status Register */\n+#define PCI_CHSWP_DHA\t\t0x01\t/* Device Hiding Arm */\n+#define PCI_CHSWP_EIM\t\t0x02\t/* ENUM# Signal Mask */\n+#define PCI_CHSWP_PIE\t\t0x04\t/* Pending Insert or Extract */\n+#define PCI_CHSWP_LOO\t\t0x08\t/* LED On / Off */\n+#define PCI_CHSWP_PI\t\t0x30\t/* Programming Interface */\n+#define PCI_CHSWP_EXT\t\t0x40\t/* ENUM# status - extraction */\n+#define PCI_CHSWP_INS\t\t0x80\t/* ENUM# status - insertion */\n+\n+/* PCI Advanced Feature registers */\n+\n+#define PCI_AF_LENGTH\t\t2\n+#define PCI_AF_CAP\t\t3\n+#define PCI_AF_CAP_TP\t\t0x01\n+#define PCI_AF_CAP_FLR\t\t0x02\n+#define PCI_AF_CTRL\t\t4\n+#define PCI_AF_CTRL_FLR\t0x01\n+#define PCI_AF_STATUS\t\t5\n+#define PCI_AF_STATUS_TP\t0x01\n+#define PCI_CAP_AF_SIZEOF\t6\t/* size of AF registers */\n+\n+/* PCI Enhanced Allocation registers */\n+\n+#define PCI_EA_NUM_ENT\t\t2\t/* Number of Capability Entries */\n+#define PCI_EA_NUM_ENT_MASK\t0x3f\t/* Num Entries Mask */\n+#define PCI_EA_FIRST_ENT\t4\t/* First EA Entry in List */\n+#define PCI_EA_FIRST_ENT_BRIDGE\t8\t/* First EA Entry for Bridges */\n+#define PCI_EA_ES\t\t0x00000007 /* Entry Size */\n+#define PCI_EA_BEI\t\t0x000000f0 /* BAR Equivalent Indicator */\n+\n+/* EA fixed Secondary and Subordinate bus numbers for Bridge */\n+#define PCI_EA_SEC_BUS_MASK\t0xff\n+#define PCI_EA_SUB_BUS_MASK\t0xff00\n+#define PCI_EA_SUB_BUS_SHIFT\t8\n+\n+/* 0-5 map to BARs 0-5 respectively */\n+#define PCI_EA_BEI_BAR0\t\t0\n+#define PCI_EA_BEI_BAR5\t\t5\n+#define PCI_EA_BEI_BRIDGE\t\t6\t/* Resource behind bridge */\n+#define PCI_EA_BEI_ENI\t\t7\t/* Equivalent Not Indicated */\n+#define PCI_EA_BEI_ROM\t\t8\t/* Expansion ROM */\n+/* 9-14 map to VF BARs 0-5 respectively */\n+#define PCI_EA_BEI_VF_BAR0\t\t9\n+#define PCI_EA_BEI_VF_BAR5\t\t14\n+#define PCI_EA_BEI_RESERVED\t\t15\t/* Reserved - Treat like ENI */\n+#define PCI_EA_PP\t\t0x0000ff00\t/* Primary Properties */\n+#define PCI_EA_SP\t\t0x00ff0000\t/* Secondary Properties */\n+#define PCI_EA_P_MEM\t\t\t0x00\t/* Non-Prefetch Memory */\n+#define PCI_EA_P_MEM_PREFETCH\t\t0x01\t/* Prefetchable Memory */\n+#define PCI_EA_P_IO\t\t\t0x02\t/* I/O Space */\n+#define PCI_EA_P_VF_MEM_PREFETCH\t0x03\t/* VF Prefetchable Memory */\n+#define PCI_EA_P_VF_MEM\t\t0x04\t/* VF Non-Prefetch Memory */\n+#define PCI_EA_P_BRIDGE_MEM\t\t0x05\t/* Bridge Non-Prefetch Memory */\n+#define PCI_EA_P_BRIDGE_MEM_PREFETCH\t0x06\t/* Bridge Prefetchable Memory */\n+#define PCI_EA_P_BRIDGE_IO\t\t0x07\t/* Bridge I/O Space */\n+/* 0x08-0xfc reserved */\n+#define PCI_EA_P_MEM_RESERVED\t\t0xfd\t/* Reserved Memory */\n+#define PCI_EA_P_IO_RESERVED\t\t0xfe\t/* Reserved I/O Space */\n+#define PCI_EA_P_UNAVAILABLE\t\t0xff\t/* Entry Unavailable */\n+#define PCI_EA_WRITABLE\t0x40000000\t/* Writable: 1 = RW, 0 = HwInit */\n+#define PCI_EA_ENABLE\t\t0x80000000\t/* Enable for this entry */\n+#define PCI_EA_BASE\t\t4\t\t/* Base Address Offset */\n+#define PCI_EA_MAX_OFFSET\t8\t\t/* MaxOffset (resource length) */\n+/* bit 0 is reserved */\n+#define PCI_EA_IS_64\t\t0x00000002\t/* 64-bit field flag */\n+#define PCI_EA_FIELD_MASK\t0xfffffffc\t/* For Base & Max Offset */\n+\n+/* PCI-X registers (Type 0 (non-bridge) devices) */\n+\n+#define PCI_X_CMD\t\t2\t/* Modes & Features */\n+#define PCI_X_CMD_DPERR_E\t0x0001\t/* Data Parity Error Recovery Enable */\n+#define PCI_X_CMD_ERO\t\t0x0002\t/* Enable Relaxed Ordering */\n+#define PCI_X_CMD_READ_512\t0x0000\t/* 512 byte maximum read byte count */\n+#define PCI_X_CMD_READ_1K\t0x0004\t/* 1Kbyte maximum read byte count */\n+#define PCI_X_CMD_READ_2K\t0x0008\t/* 2Kbyte maximum read byte count */\n+#define PCI_X_CMD_READ_4K\t0x000c\t/* 4Kbyte maximum read byte count */\n+#define PCI_X_CMD_MAX_READ\t0x000c\t/* Max Memory Read Byte Count */\n+\t\t\t\t/* Max # of outstanding split transactions */\n+#define PCI_X_CMD_SPLIT_1\t0x0000\t/* Max 1 */\n+#define PCI_X_CMD_SPLIT_2\t0x0010\t/* Max 2 */\n+#define PCI_X_CMD_SPLIT_3\t0x0020\t/* Max 3 */\n+#define PCI_X_CMD_SPLIT_4\t0x0030\t/* Max 4 */\n+#define PCI_X_CMD_SPLIT_8\t0x0040\t/* Max 8 */\n+#define PCI_X_CMD_SPLIT_12\t0x0050\t/* Max 12 */\n+#define PCI_X_CMD_SPLIT_16\t0x0060\t/* Max 16 */\n+#define PCI_X_CMD_SPLIT_32\t0x0070\t/* Max 32 */\n+#define PCI_X_CMD_MAX_SPLIT\t0x0070\t/* Max Outstanding Split Transactions */\n+#define PCI_X_CMD_VERSION(x)\t(((x) >> 12) & 3) /* Version */\n+#define PCI_X_STATUS\t\t4\t/* PCI-X capabilities */\n+#define PCI_X_STATUS_DEVFN\t0x000000ff\t/* A copy of devfn */\n+#define PCI_X_STATUS_BUS\t0x0000ff00\t/* A copy of bus nr */\n+#define PCI_X_STATUS_64BIT\t0x00010000\t/* 64-bit device */\n+#define PCI_X_STATUS_133MHZ\t0x00020000\t/* 133 MHz capable */\n+#define PCI_X_STATUS_SPL_DISC\t0x00040000\t/* Split Completion Discarded */\n+#define PCI_X_STATUS_UNX_SPL\t0x00080000\t/* Unexpected Split Completion */\n+#define PCI_X_STATUS_COMPLEX\t0x00100000\t/* Device Complexity */\n+#define PCI_X_STATUS_MAX_READ\t0x00600000\t/* Designed Max Memory Read Count */\n+#define PCI_X_STATUS_MAX_SPLIT\t0x03800000\t/* Designed Max Outstanding Split Transactions */\n+#define PCI_X_STATUS_MAX_CUM\t0x1c000000\t/* Designed Max Cumulative Read Size */\n+#define PCI_X_STATUS_SPL_ERR\t0x20000000\t/* Rcvd Split Completion Error Msg */\n+#define PCI_X_STATUS_266MHZ\t0x40000000\t/* 266 MHz capable */\n+#define PCI_X_STATUS_533MHZ\t0x80000000\t/* 533 MHz capable */\n+#define PCI_X_ECC_CSR\t\t8\t/* ECC control and status */\n+#define PCI_CAP_PCIX_SIZEOF_V0\t8\t/* size of registers for Version 0 */\n+#define PCI_CAP_PCIX_SIZEOF_V1\t24\t/* size for Version 1 */\n+#define PCI_CAP_PCIX_SIZEOF_V2\tPCI_CAP_PCIX_SIZEOF_V1\t/* Same for v2 */\n+\n+/* PCI-X registers (Type 1 (bridge) devices) */\n+\n+#define PCI_X_BRIDGE_SSTATUS\t2\t/* Secondary Status */\n+#define PCI_X_SSTATUS_64BIT\t0x0001\t/* Secondary AD interface is 64 bits */\n+#define PCI_X_SSTATUS_133MHZ\t0x0002\t/* 133 MHz capable */\n+#define PCI_X_SSTATUS_FREQ\t0x03c0\t/* Secondary Bus Mode and Frequency */\n+#define PCI_X_SSTATUS_VERS\t0x3000\t/* PCI-X Capability Version */\n+#define PCI_X_SSTATUS_V1\t0x1000\t/* Mode 2, not Mode 1 */\n+#define PCI_X_SSTATUS_V2\t0x2000\t/* Mode 1 or Modes 1 and 2 */\n+#define PCI_X_SSTATUS_266MHZ\t0x4000\t/* 266 MHz capable */\n+#define PCI_X_SSTATUS_533MHZ\t0x8000\t/* 533 MHz capable */\n+#define PCI_X_BRIDGE_STATUS\t4\t/* Bridge Status */\n+\n+/* PCI Bridge Subsystem ID registers */\n+\n+#define PCI_SSVID_VENDOR_ID 4\t/* PCI Bridge subsystem vendor ID */\n+#define PCI_SSVID_DEVICE_ID 6\t/* PCI Bridge subsystem device ID */\n+\n+/* PCI Express capability registers */\n+\n+#define PCI_EXP_FLAGS\t\t2\t/* Capabilities register */\n+#define PCI_EXP_FLAGS_VERS\t0x000f\t/* Capability version */\n+#define PCI_EXP_FLAGS_TYPE\t0x00f0\t/* Device/Port type */\n+#define PCI_EXP_TYPE_ENDPOINT\t 0x0\t/* Express Endpoint */\n+#define PCI_EXP_TYPE_LEG_END\t 0x1\t/* Legacy Endpoint */\n+#define PCI_EXP_TYPE_ROOT_PORT 0x4\t/* Root Port */\n+#define PCI_EXP_TYPE_UPSTREAM\t 0x5\t/* Upstream Port */\n+#define PCI_EXP_TYPE_DOWNSTREAM 0x6\t/* Downstream Port */\n+#define PCI_EXP_TYPE_PCI_BRIDGE 0x7\t/* PCIe to PCI/PCI-X Bridge */\n+#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8\t/* PCI/PCI-X to PCIe Bridge */\n+#define PCI_EXP_TYPE_RC_END\t 0x9\t/* Root Complex Integrated Endpoint */\n+#define PCI_EXP_TYPE_RC_EC\t 0xa\t/* Root Complex Event Collector */\n+#define PCI_EXP_FLAGS_SLOT\t0x0100\t/* Slot implemented */\n+#define PCI_EXP_FLAGS_IRQ\t0x3e00\t/* Interrupt message number */\n+#define PCI_EXP_DEVCAP\t\t4\t/* Device capabilities */\n+#define PCI_EXP_DEVCAP_PAYLOAD\t0x00000007 /* Max_Payload_Size */\n+#define PCI_EXP_DEVCAP_PHANTOM\t0x00000018 /* Phantom functions */\n+#define PCI_EXP_DEVCAP_EXT_TAG\t0x00000020 /* Extended tags */\n+#define PCI_EXP_DEVCAP_L0S\t0x000001c0 /* L0s Acceptable Latency */\n+#define PCI_EXP_DEVCAP_L1\t0x00000e00 /* L1 Acceptable Latency */\n+#define PCI_EXP_DEVCAP_ATN_BUT\t0x00001000 /* Attention Button Present */\n+#define PCI_EXP_DEVCAP_ATN_IND\t0x00002000 /* Attention Indicator Present */\n+#define PCI_EXP_DEVCAP_PWR_IND\t0x00004000 /* Power Indicator Present */\n+#define PCI_EXP_DEVCAP_RBER\t0x00008000 /* Role-Based Error Reporting */\n+#define PCI_EXP_DEVCAP_PWR_VAL\t0x03fc0000 /* Slot Power Limit Value */\n+#define PCI_EXP_DEVCAP_PWR_SCL\t0x0c000000 /* Slot Power Limit Scale */\n+#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */\n+#define PCI_EXP_DEVCTL\t\t8\t/* Device Control */\n+#define PCI_EXP_DEVCTL_CERE\t0x0001\t/* Correctable Error Reporting En. */\n+#define PCI_EXP_DEVCTL_NFERE\t0x0002\t/* Non-Fatal Error Reporting Enable */\n+#define PCI_EXP_DEVCTL_FERE\t0x0004\t/* Fatal Error Reporting Enable */\n+#define PCI_EXP_DEVCTL_URRE\t0x0008\t/* Unsupported Request Reporting En. */\n+#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */\n+#define PCI_EXP_DEVCTL_PAYLOAD\t0x00e0\t/* Max_Payload_Size */\n+#define PCI_EXP_DEVCTL_EXT_TAG\t0x0100\t/* Extended Tag Field Enable */\n+#define PCI_EXP_DEVCTL_PHANTOM\t0x0200\t/* Phantom Functions Enable */\n+#define PCI_EXP_DEVCTL_AUX_PME\t0x0400\t/* Auxiliary Power PM Enable */\n+#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */\n+#define PCI_EXP_DEVCTL_READRQ\t0x7000\t/* Max_Read_Request_Size */\n+#define PCI_EXP_DEVCTL_READRQ_128B 0x0000 /* 128 Bytes */\n+#define PCI_EXP_DEVCTL_READRQ_256B 0x1000 /* 256 Bytes */\n+#define PCI_EXP_DEVCTL_READRQ_512B 0x2000 /* 512 Bytes */\n+#define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */\n+#define PCI_EXP_DEVCTL_READRQ_2048B 0x4000 /* 2048 Bytes */\n+#define PCI_EXP_DEVCTL_READRQ_4096B 0x5000 /* 4096 Bytes */\n+#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */\n+#define PCI_EXP_DEVSTA\t\t10\t/* Device Status */\n+#define PCI_EXP_DEVSTA_CED\t0x0001\t/* Correctable Error Detected */\n+#define PCI_EXP_DEVSTA_NFED\t0x0002\t/* Non-Fatal Error Detected */\n+#define PCI_EXP_DEVSTA_FED\t0x0004\t/* Fatal Error Detected */\n+#define PCI_EXP_DEVSTA_URD\t0x0008\t/* Unsupported Request Detected */\n+#define PCI_EXP_DEVSTA_AUXPD\t0x0010\t/* AUX Power Detected */\n+#define PCI_EXP_DEVSTA_TRPND\t0x0020\t/* Transactions Pending */\n+#define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1\t12\t/* v1 endpoints without link end here */\n+#define PCI_EXP_LNKCAP\t\t12\t/* Link Capabilities */\n+#define PCI_EXP_LNKCAP_SLS\t0x0000000f /* Supported Link Speeds */\n+#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */\n+#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */\n+#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */\n+#define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */\n+#define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */\n+#define PCI_EXP_LNKCAP_MLW\t0x000003f0 /* Maximum Link Width */\n+#define PCI_EXP_LNKCAP_ASPMS\t0x00000c00 /* ASPM Support */\n+#define PCI_EXP_LNKCAP_L0SEL\t0x00007000 /* L0s Exit Latency */\n+#define PCI_EXP_LNKCAP_L1EL\t0x00038000 /* L1 Exit Latency */\n+#define PCI_EXP_LNKCAP_CLKPM\t0x00040000 /* Clock Power Management */\n+#define PCI_EXP_LNKCAP_SDERC\t0x00080000 /* Surprise Down Error Reporting Capable */\n+#define PCI_EXP_LNKCAP_DLLLARC\t0x00100000 /* Data Link Layer Link Active Reporting Capable */\n+#define PCI_EXP_LNKCAP_LBNC\t0x00200000 /* Link Bandwidth Notification Capability */\n+#define PCI_EXP_LNKCAP_PN\t0xff000000 /* Port Number */\n+#define PCI_EXP_LNKCTL\t\t16\t/* Link Control */\n+#define PCI_EXP_LNKCTL_ASPMC\t0x0003\t/* ASPM Control */\n+#define PCI_EXP_LNKCTL_ASPM_L0S 0x0001\t/* L0s Enable */\n+#define PCI_EXP_LNKCTL_ASPM_L1 0x0002\t/* L1 Enable */\n+#define PCI_EXP_LNKCTL_RCB\t0x0008\t/* Read Completion Boundary */\n+#define PCI_EXP_LNKCTL_LD\t0x0010\t/* Link Disable */\n+#define PCI_EXP_LNKCTL_RL\t0x0020\t/* Retrain Link */\n+#define PCI_EXP_LNKCTL_CCC\t0x0040\t/* Common Clock Configuration */\n+#define PCI_EXP_LNKCTL_ES\t0x0080\t/* Extended Synch */\n+#define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */\n+#define PCI_EXP_LNKCTL_HAWD\t0x0200\t/* Hardware Autonomous Width Disable */\n+#define PCI_EXP_LNKCTL_LBMIE\t0x0400\t/* Link Bandwidth Management Interrupt Enable */\n+#define PCI_EXP_LNKCTL_LABIE\t0x0800\t/* Link Autonomous Bandwidth Interrupt Enable */\n+#define PCI_EXP_LNKSTA\t\t18\t/* Link Status */\n+#define PCI_EXP_LNKSTA_CLS\t0x000f\t/* Current Link Speed */\n+#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */\n+#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */\n+#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */\n+#define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */\n+#define PCI_EXP_LNKSTA_CLS_32_0GB 0x0005 /* Current Link Speed 32.0GT/s */\n+#define PCI_EXP_LNKSTA_NLW\t0x03f0\t/* Negotiated Link Width */\n+#define PCI_EXP_LNKSTA_NLW_X1\t0x0010\t/* Current Link Width x1 */\n+#define PCI_EXP_LNKSTA_NLW_X2\t0x0020\t/* Current Link Width x2 */\n+#define PCI_EXP_LNKSTA_NLW_X4\t0x0040\t/* Current Link Width x4 */\n+#define PCI_EXP_LNKSTA_NLW_X8\t0x0080\t/* Current Link Width x8 */\n+#define PCI_EXP_LNKSTA_NLW_SHIFT 4\t/* start of NLW mask in link status */\n+#define PCI_EXP_LNKSTA_LT\t0x0800\t/* Link Training */\n+#define PCI_EXP_LNKSTA_SLC\t0x1000\t/* Slot Clock Configuration */\n+#define PCI_EXP_LNKSTA_DLLLA\t0x2000\t/* Data Link Layer Link Active */\n+#define PCI_EXP_LNKSTA_LBMS\t0x4000\t/* Link Bandwidth Management Status */\n+#define PCI_EXP_LNKSTA_LABS\t0x8000\t/* Link Autonomous Bandwidth Status */\n+#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1\t20\t/* v1 endpoints with link end here */\n+#define PCI_EXP_SLTCAP\t\t20\t/* Slot Capabilities */\n+#define PCI_EXP_SLTCAP_ABP\t0x00000001 /* Attention Button Present */\n+#define PCI_EXP_SLTCAP_PCP\t0x00000002 /* Power Controller Present */\n+#define PCI_EXP_SLTCAP_MRLSP\t0x00000004 /* MRL Sensor Present */\n+#define PCI_EXP_SLTCAP_AIP\t0x00000008 /* Attention Indicator Present */\n+#define PCI_EXP_SLTCAP_PIP\t0x00000010 /* Power Indicator Present */\n+#define PCI_EXP_SLTCAP_HPS\t0x00000020 /* Hot-Plug Surprise */\n+#define PCI_EXP_SLTCAP_HPC\t0x00000040 /* Hot-Plug Capable */\n+#define PCI_EXP_SLTCAP_SPLV\t0x00007f80 /* Slot Power Limit Value */\n+#define PCI_EXP_SLTCAP_SPLS\t0x00018000 /* Slot Power Limit Scale */\n+#define PCI_EXP_SLTCAP_EIP\t0x00020000 /* Electromechanical Interlock Present */\n+#define PCI_EXP_SLTCAP_NCCS\t0x00040000 /* No Command Completed Support */\n+#define PCI_EXP_SLTCAP_PSN\t0xfff80000 /* Physical Slot Number */\n+#define PCI_EXP_SLTCTL\t\t24\t/* Slot Control */\n+#define PCI_EXP_SLTCTL_ABPE\t0x0001\t/* Attention Button Pressed Enable */\n+#define PCI_EXP_SLTCTL_PFDE\t0x0002\t/* Power Fault Detected Enable */\n+#define PCI_EXP_SLTCTL_MRLSCE\t0x0004\t/* MRL Sensor Changed Enable */\n+#define PCI_EXP_SLTCTL_PDCE\t0x0008\t/* Presence Detect Changed Enable */\n+#define PCI_EXP_SLTCTL_CCIE\t0x0010\t/* Command Completed Interrupt Enable */\n+#define PCI_EXP_SLTCTL_HPIE\t0x0020\t/* Hot-Plug Interrupt Enable */\n+#define PCI_EXP_SLTCTL_AIC\t0x00c0\t/* Attention Indicator Control */\n+#define PCI_EXP_SLTCTL_ATTN_IND_SHIFT 6 /* Attention Indicator shift */\n+#define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040 /* Attention Indicator on */\n+#define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 /* Attention Indicator blinking */\n+#define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0 /* Attention Indicator off */\n+#define PCI_EXP_SLTCTL_PIC\t0x0300\t/* Power Indicator Control */\n+#define PCI_EXP_SLTCTL_PWR_IND_ON 0x0100 /* Power Indicator on */\n+#define PCI_EXP_SLTCTL_PWR_IND_BLINK 0x0200 /* Power Indicator blinking */\n+#define PCI_EXP_SLTCTL_PWR_IND_OFF 0x0300 /* Power Indicator off */\n+#define PCI_EXP_SLTCTL_PCC\t0x0400\t/* Power Controller Control */\n+#define PCI_EXP_SLTCTL_PWR_ON 0x0000 /* Power On */\n+#define PCI_EXP_SLTCTL_PWR_OFF 0x0400 /* Power Off */\n+#define PCI_EXP_SLTCTL_EIC\t0x0800\t/* Electromechanical Interlock Control */\n+#define PCI_EXP_SLTCTL_DLLSCE\t0x1000\t/* Data Link Layer State Changed Enable */\n+#define PCI_EXP_SLTCTL_IBPD_DISABLE\t0x4000 /* In-band PD disable */\n+#define PCI_EXP_SLTSTA\t\t26\t/* Slot Status */\n+#define PCI_EXP_SLTSTA_ABP\t0x0001\t/* Attention Button Pressed */\n+#define PCI_EXP_SLTSTA_PFD\t0x0002\t/* Power Fault Detected */\n+#define PCI_EXP_SLTSTA_MRLSC\t0x0004\t/* MRL Sensor Changed */\n+#define PCI_EXP_SLTSTA_PDC\t0x0008\t/* Presence Detect Changed */\n+#define PCI_EXP_SLTSTA_CC\t0x0010\t/* Command Completed */\n+#define PCI_EXP_SLTSTA_MRLSS\t0x0020\t/* MRL Sensor State */\n+#define PCI_EXP_SLTSTA_PDS\t0x0040\t/* Presence Detect State */\n+#define PCI_EXP_SLTSTA_EIS\t0x0080\t/* Electromechanical Interlock Status */\n+#define PCI_EXP_SLTSTA_DLLSC\t0x0100\t/* Data Link Layer State Changed */\n+#define PCI_EXP_RTCTL\t\t28\t/* Root Control */\n+#define PCI_EXP_RTCTL_SECEE\t0x0001\t/* System Error on Correctable Error */\n+#define PCI_EXP_RTCTL_SENFEE\t0x0002\t/* System Error on Non-Fatal Error */\n+#define PCI_EXP_RTCTL_SEFEE\t0x0004\t/* System Error on Fatal Error */\n+#define PCI_EXP_RTCTL_PMEIE\t0x0008\t/* PME Interrupt Enable */\n+#define PCI_EXP_RTCTL_CRSSVE\t0x0010\t/* CRS Software Visibility Enable */\n+#define PCI_EXP_RTCAP\t\t30\t/* Root Capabilities */\n+#define PCI_EXP_RTCAP_CRSVIS\t0x0001\t/* CRS Software Visibility capability */\n+#define PCI_EXP_RTSTA\t\t32\t/* Root Status */\n+#define PCI_EXP_RTSTA_PME\t0x00010000 /* PME status */\n+#define PCI_EXP_RTSTA_PENDING\t0x00020000 /* PME pending */\n+/*\n+ * The Device Capabilities 2, Device Status 2, Device Control 2,\n+ * Link Capabilities 2, Link Status 2, Link Control 2,\n+ * Slot Capabilities 2, Slot Status 2, and Slot Control 2 registers\n+ * are only present on devices with PCIe Capability version 2.\n+ * Use pcie_capability_read_word() and similar interfaces to use them\n+ * safely.\n+ */\n+#define PCI_EXP_DEVCAP2\t\t36\t/* Device Capabilities 2 */\n+#define PCI_EXP_DEVCAP2_COMP_TMOUT_DIS\t0x00000010 /* Completion Timeout Disable supported */\n+#define PCI_EXP_DEVCAP2_ARI\t\t0x00000020 /* Alternative Routing-ID */\n+#define PCI_EXP_DEVCAP2_ATOMIC_ROUTE\t0x00000040 /* Atomic Op routing */\n+#define PCI_EXP_DEVCAP2_ATOMIC_COMP32\t0x00000080 /* 32b AtomicOp completion */\n+#define PCI_EXP_DEVCAP2_ATOMIC_COMP64\t0x00000100 /* 64b AtomicOp completion */\n+#define PCI_EXP_DEVCAP2_ATOMIC_COMP128\t0x00000200 /* 128b AtomicOp completion */\n+#define PCI_EXP_DEVCAP2_LTR\t\t0x00000800 /* Latency tolerance reporting */\n+#define PCI_EXP_DEVCAP2_OBFF_MASK\t0x000c0000 /* OBFF support mechanism */\n+#define PCI_EXP_DEVCAP2_OBFF_MSG\t0x00040000 /* New message signaling */\n+#define PCI_EXP_DEVCAP2_OBFF_WAKE\t0x00080000 /* Re-use WAKE# for OBFF */\n+#define PCI_EXP_DEVCAP2_EE_PREFIX\t0x00200000 /* End-End TLP Prefix */\n+#define PCI_EXP_DEVCTL2\t\t40\t/* Device Control 2 */\n+#define PCI_EXP_DEVCTL2_COMP_TIMEOUT\t0x000f\t/* Completion Timeout Value */\n+#define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS\t0x0010\t/* Completion Timeout Disable */\n+#define PCI_EXP_DEVCTL2_ARI\t\t0x0020\t/* Alternative Routing-ID */\n+#define PCI_EXP_DEVCTL2_ATOMIC_REQ\t0x0040\t/* Set Atomic requests */\n+#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */\n+#define PCI_EXP_DEVCTL2_IDO_REQ_EN\t0x0100\t/* Allow IDO for requests */\n+#define PCI_EXP_DEVCTL2_IDO_CMP_EN\t0x0200\t/* Allow IDO for completions */\n+#define PCI_EXP_DEVCTL2_LTR_EN\t\t0x0400\t/* Enable LTR mechanism */\n+#define PCI_EXP_DEVCTL2_OBFF_MSGA_EN\t0x2000\t/* Enable OBFF Message type A */\n+#define PCI_EXP_DEVCTL2_OBFF_MSGB_EN\t0x4000\t/* Enable OBFF Message type B */\n+#define PCI_EXP_DEVCTL2_OBFF_WAKE_EN\t0x6000\t/* OBFF using WAKE# signaling */\n+#define PCI_EXP_DEVSTA2\t\t42\t/* Device Status 2 */\n+#define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2\t44\t/* v2 endpoints without link end here */\n+#define PCI_EXP_LNKCAP2\t\t44\t/* Link Capabilities 2 */\n+#define PCI_EXP_LNKCAP2_SLS_2_5GB\t0x00000002 /* Supported Speed 2.5GT/s */\n+#define PCI_EXP_LNKCAP2_SLS_5_0GB\t0x00000004 /* Supported Speed 5GT/s */\n+#define PCI_EXP_LNKCAP2_SLS_8_0GB\t0x00000008 /* Supported Speed 8GT/s */\n+#define PCI_EXP_LNKCAP2_SLS_16_0GB\t0x00000010 /* Supported Speed 16GT/s */\n+#define PCI_EXP_LNKCAP2_SLS_32_0GB\t0x00000020 /* Supported Speed 32GT/s */\n+#define PCI_EXP_LNKCAP2_CROSSLINK\t0x00000100 /* Crosslink supported */\n+#define PCI_EXP_LNKCTL2\t\t48\t/* Link Control 2 */\n+#define PCI_EXP_LNKCTL2_TLS\t\t0x000f\n+#define PCI_EXP_LNKCTL2_TLS_2_5GT\t0x0001 /* Supported Speed 2.5GT/s */\n+#define PCI_EXP_LNKCTL2_TLS_5_0GT\t0x0002 /* Supported Speed 5GT/s */\n+#define PCI_EXP_LNKCTL2_TLS_8_0GT\t0x0003 /* Supported Speed 8GT/s */\n+#define PCI_EXP_LNKCTL2_TLS_16_0GT\t0x0004 /* Supported Speed 16GT/s */\n+#define PCI_EXP_LNKCTL2_TLS_32_0GT\t0x0005 /* Supported Speed 32GT/s */\n+#define PCI_EXP_LNKCTL2_ENTER_COMP\t0x0010 /* Enter Compliance */\n+#define PCI_EXP_LNKCTL2_TX_MARGIN\t0x0380 /* Transmit Margin */\n+#define PCI_EXP_LNKCTL2_HASD\t\t0x0020 /* HW Autonomous Speed Disable */\n+#define PCI_EXP_LNKSTA2\t\t50\t/* Link Status 2 */\n+#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2\t52\t/* v2 endpoints with link end here */\n+#define PCI_EXP_SLTCAP2\t\t52\t/* Slot Capabilities 2 */\n+#define PCI_EXP_SLTCAP2_IBPD\t0x00000001 /* In-band PD Disable Supported */\n+#define PCI_EXP_SLTCTL2\t\t56\t/* Slot Control 2 */\n+#define PCI_EXP_SLTSTA2\t\t58\t/* Slot Status 2 */\n+\n+/* Extended Capabilities (PCI-X 2.0 and Express) */\n+#define PCI_EXT_CAP_ID(header)\t\t(header & 0x0000ffff)\n+#define PCI_EXT_CAP_VER(header)\t\t((header >> 16) & 0xf)\n+#define PCI_EXT_CAP_NEXT(header)\t((header >> 20) & 0xffc)\n+\n+#define PCI_EXT_CAP_ID_ERR\t0x01\t/* Advanced Error Reporting */\n+#define PCI_EXT_CAP_ID_VC\t0x02\t/* Virtual Channel Capability */\n+#define PCI_EXT_CAP_ID_DSN\t0x03\t/* Device Serial Number */\n+#define PCI_EXT_CAP_ID_PWR\t0x04\t/* Power Budgeting */\n+#define PCI_EXT_CAP_ID_RCLD\t0x05\t/* Root Complex Link Declaration */\n+#define PCI_EXT_CAP_ID_RCILC\t0x06\t/* Root Complex Internal Link Control */\n+#define PCI_EXT_CAP_ID_RCEC\t0x07\t/* Root Complex Event Collector */\n+#define PCI_EXT_CAP_ID_MFVC\t0x08\t/* Multi-Function VC Capability */\n+#define PCI_EXT_CAP_ID_VC9\t0x09\t/* same as _VC */\n+#define PCI_EXT_CAP_ID_RCRB\t0x0A\t/* Root Complex RB? */\n+#define PCI_EXT_CAP_ID_VNDR\t0x0B\t/* Vendor-Specific */\n+#define PCI_EXT_CAP_ID_CAC\t0x0C\t/* Config Access - obsolete */\n+#define PCI_EXT_CAP_ID_ACS\t0x0D\t/* Access Control Services */\n+#define PCI_EXT_CAP_ID_ARI\t0x0E\t/* Alternate Routing ID */\n+#define PCI_EXT_CAP_ID_ATS\t0x0F\t/* Address Translation Services */\n+#define PCI_EXT_CAP_ID_SRIOV\t0x10\t/* Single Root I/O Virtualization */\n+#define PCI_EXT_CAP_ID_MRIOV\t0x11\t/* Multi Root I/O Virtualization */\n+#define PCI_EXT_CAP_ID_MCAST\t0x12\t/* Multicast */\n+#define PCI_EXT_CAP_ID_PRI\t0x13\t/* Page Request Interface */\n+#define PCI_EXT_CAP_ID_AMD_XXX\t0x14\t/* Reserved for AMD */\n+#define PCI_EXT_CAP_ID_REBAR\t0x15\t/* Resizable BAR */\n+#define PCI_EXT_CAP_ID_DPA\t0x16\t/* Dynamic Power Allocation */\n+#define PCI_EXT_CAP_ID_TPH\t0x17\t/* TPH Requester */\n+#define PCI_EXT_CAP_ID_LTR\t0x18\t/* Latency Tolerance Reporting */\n+#define PCI_EXT_CAP_ID_SECPCI\t0x19\t/* Secondary PCIe Capability */\n+#define PCI_EXT_CAP_ID_PMUX\t0x1A\t/* Protocol Multiplexing */\n+#define PCI_EXT_CAP_ID_PASID\t0x1B\t/* Process Address Space ID */\n+#define PCI_EXT_CAP_ID_DPC\t0x1D\t/* Downstream Port Containment */\n+#define PCI_EXT_CAP_ID_L1SS\t0x1E\t/* L1 PM Substates */\n+#define PCI_EXT_CAP_ID_PTM\t0x1F\t/* Precision Time Measurement */\n+#define PCI_EXT_CAP_ID_DLF\t0x25\t/* Data Link Feature */\n+#define PCI_EXT_CAP_ID_PL_16GT\t0x26\t/* Physical Layer 16.0 GT/s */\n+#define PCI_EXT_CAP_ID_MAX\tPCI_EXT_CAP_ID_PL_16GT\n+\n+#define PCI_EXT_CAP_DSN_SIZEOF\t12\n+#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40\n+\n+/* Advanced Error Reporting */\n+#define PCI_ERR_UNCOR_STATUS\t4\t/* Uncorrectable Error Status */\n+#define PCI_ERR_UNC_UND\t0x00000001\t/* Undefined */\n+#define PCI_ERR_UNC_DLP\t0x00000010\t/* Data Link Protocol */\n+#define PCI_ERR_UNC_SURPDN\t0x00000020\t/* Surprise Down */\n+#define PCI_ERR_UNC_POISON_TLP\t0x00001000\t/* Poisoned TLP */\n+#define PCI_ERR_UNC_FCP\t0x00002000\t/* Flow Control Protocol */\n+#define PCI_ERR_UNC_COMP_TIME\t0x00004000\t/* Completion Timeout */\n+#define PCI_ERR_UNC_COMP_ABORT\t0x00008000\t/* Completer Abort */\n+#define PCI_ERR_UNC_UNX_COMP\t0x00010000\t/* Unexpected Completion */\n+#define PCI_ERR_UNC_RX_OVER\t0x00020000\t/* Receiver Overflow */\n+#define PCI_ERR_UNC_MALF_TLP\t0x00040000\t/* Malformed TLP */\n+#define PCI_ERR_UNC_ECRC\t0x00080000\t/* ECRC Error Status */\n+#define PCI_ERR_UNC_UNSUP\t0x00100000\t/* Unsupported Request */\n+#define PCI_ERR_UNC_ACSV\t0x00200000\t/* ACS Violation */\n+#define PCI_ERR_UNC_INTN\t0x00400000\t/* internal error */\n+#define PCI_ERR_UNC_MCBTLP\t0x00800000\t/* MC blocked TLP */\n+#define PCI_ERR_UNC_ATOMEG\t0x01000000\t/* Atomic egress blocked */\n+#define PCI_ERR_UNC_TLPPRE\t0x02000000\t/* TLP prefix blocked */\n+#define PCI_ERR_UNCOR_MASK\t8\t/* Uncorrectable Error Mask */\n+\t/* Same bits as above */\n+#define PCI_ERR_UNCOR_SEVER\t12\t/* Uncorrectable Error Severity */\n+\t/* Same bits as above */\n+#define PCI_ERR_COR_STATUS\t16\t/* Correctable Error Status */\n+#define PCI_ERR_COR_RCVR\t0x00000001\t/* Receiver Error Status */\n+#define PCI_ERR_COR_BAD_TLP\t0x00000040\t/* Bad TLP Status */\n+#define PCI_ERR_COR_BAD_DLLP\t0x00000080\t/* Bad DLLP Status */\n+#define PCI_ERR_COR_REP_ROLL\t0x00000100\t/* REPLAY_NUM Rollover */\n+#define PCI_ERR_COR_REP_TIMER\t0x00001000\t/* Replay Timer Timeout */\n+#define PCI_ERR_COR_ADV_NFAT\t0x00002000\t/* Advisory Non-Fatal */\n+#define PCI_ERR_COR_INTERNAL\t0x00004000\t/* Corrected Internal */\n+#define PCI_ERR_COR_LOG_OVER\t0x00008000\t/* Header Log Overflow */\n+#define PCI_ERR_COR_MASK\t20\t/* Correctable Error Mask */\n+\t/* Same bits as above */\n+#define PCI_ERR_CAP\t\t24\t/* Advanced Error Capabilities */\n+#define PCI_ERR_CAP_FEP(x)\t((x) & 31)\t/* First Error Pointer */\n+#define PCI_ERR_CAP_ECRC_GENC\t0x00000020\t/* ECRC Generation Capable */\n+#define PCI_ERR_CAP_ECRC_GENE\t0x00000040\t/* ECRC Generation Enable */\n+#define PCI_ERR_CAP_ECRC_CHKC\t0x00000080\t/* ECRC Check Capable */\n+#define PCI_ERR_CAP_ECRC_CHKE\t0x00000100\t/* ECRC Check Enable */\n+#define PCI_ERR_HEADER_LOG\t28\t/* Header Log Register (16 bytes) */\n+#define PCI_ERR_ROOT_COMMAND\t44\t/* Root Error Command */\n+#define PCI_ERR_ROOT_CMD_COR_EN\t0x00000001 /* Correctable Err Reporting Enable */\n+#define PCI_ERR_ROOT_CMD_NONFATAL_EN\t0x00000002 /* Non-Fatal Err Reporting Enable */\n+#define PCI_ERR_ROOT_CMD_FATAL_EN\t0x00000004 /* Fatal Err Reporting Enable */\n+#define PCI_ERR_ROOT_STATUS\t48\n+#define PCI_ERR_ROOT_COR_RCV\t\t0x00000001 /* ERR_COR Received */\n+#define PCI_ERR_ROOT_MULTI_COR_RCV\t0x00000002 /* Multiple ERR_COR */\n+#define PCI_ERR_ROOT_UNCOR_RCV\t\t0x00000004 /* ERR_FATAL/NONFATAL */\n+#define PCI_ERR_ROOT_MULTI_UNCOR_RCV\t0x00000008 /* Multiple FATAL/NONFATAL */\n+#define PCI_ERR_ROOT_FIRST_FATAL\t0x00000010 /* First UNC is Fatal */\n+#define PCI_ERR_ROOT_NONFATAL_RCV\t0x00000020 /* Non-Fatal Received */\n+#define PCI_ERR_ROOT_FATAL_RCV\t\t0x00000040 /* Fatal Received */\n+#define PCI_ERR_ROOT_AER_IRQ\t\t0xf8000000 /* Advanced Error Interrupt Message Number */\n+#define PCI_ERR_ROOT_ERR_SRC\t52\t/* Error Source Identification */\n+\n+/* Virtual Channel */\n+#define PCI_VC_PORT_CAP1\t4\n+#define PCI_VC_CAP1_EVCC\t0x00000007\t/* extended VC count */\n+#define PCI_VC_CAP1_LPEVCC\t0x00000070\t/* low prio extended VC count */\n+#define PCI_VC_CAP1_ARB_SIZE\t0x00000c00\n+#define PCI_VC_PORT_CAP2\t8\n+#define PCI_VC_CAP2_32_PHASE\t\t0x00000002\n+#define PCI_VC_CAP2_64_PHASE\t\t0x00000004\n+#define PCI_VC_CAP2_128_PHASE\t\t0x00000008\n+#define PCI_VC_CAP2_ARB_OFF\t\t0xff000000\n+#define PCI_VC_PORT_CTRL\t12\n+#define PCI_VC_PORT_CTRL_LOAD_TABLE\t0x00000001\n+#define PCI_VC_PORT_STATUS\t14\n+#define PCI_VC_PORT_STATUS_TABLE\t0x00000001\n+#define PCI_VC_RES_CAP\t\t16\n+#define PCI_VC_RES_CAP_32_PHASE\t0x00000002\n+#define PCI_VC_RES_CAP_64_PHASE\t0x00000004\n+#define PCI_VC_RES_CAP_128_PHASE\t0x00000008\n+#define PCI_VC_RES_CAP_128_PHASE_TB\t0x00000010\n+#define PCI_VC_RES_CAP_256_PHASE\t0x00000020\n+#define PCI_VC_RES_CAP_ARB_OFF\t\t0xff000000\n+#define PCI_VC_RES_CTRL\t\t20\n+#define PCI_VC_RES_CTRL_LOAD_TABLE\t0x00010000\n+#define PCI_VC_RES_CTRL_ARB_SELECT\t0x000e0000\n+#define PCI_VC_RES_CTRL_ID\t\t0x07000000\n+#define PCI_VC_RES_CTRL_ENABLE\t\t0x80000000\n+#define PCI_VC_RES_STATUS\t26\n+#define PCI_VC_RES_STATUS_TABLE\t0x00000001\n+#define PCI_VC_RES_STATUS_NEGO\t\t0x00000002\n+#define PCI_CAP_VC_BASE_SIZEOF\t\t0x10\n+#define PCI_CAP_VC_PER_VC_SIZEOF\t0x0C\n+\n+/* Power Budgeting */\n+#define PCI_PWR_DSR\t\t4\t/* Data Select Register */\n+#define PCI_PWR_DATA\t\t8\t/* Data Register */\n+#define PCI_PWR_DATA_BASE(x)\t((x) & 0xff)\t /* Base Power */\n+#define PCI_PWR_DATA_SCALE(x)\t(((x) >> 8) & 3) /* Data Scale */\n+#define PCI_PWR_DATA_PM_SUB(x)\t(((x) >> 10) & 7) /* PM Sub State */\n+#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */\n+#define PCI_PWR_DATA_TYPE(x)\t(((x) >> 15) & 7) /* Type */\n+#define PCI_PWR_DATA_RAIL(x)\t(((x) >> 18) & 7) /* Power Rail */\n+#define PCI_PWR_CAP\t\t12\t/* Capability */\n+#define PCI_PWR_CAP_BUDGET(x)\t((x) & 1)\t/* Included in system budget */\n+#define PCI_EXT_CAP_PWR_SIZEOF\t16\n+\n+/* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */\n+#define PCI_VNDR_HEADER\t\t4\t/* Vendor-Specific Header */\n+#define PCI_VNDR_HEADER_ID(x)\t((x) & 0xffff)\n+#define PCI_VNDR_HEADER_REV(x)\t(((x) >> 16) & 0xf)\n+#define PCI_VNDR_HEADER_LEN(x)\t(((x) >> 20) & 0xfff)\n+\n+/*\n+ * HyperTransport sub capability types\n+ *\n+ * Unfortunately there are both 3 bit and 5 bit capability types defined\n+ * in the HT spec, catering for that is a little messy. You probably don't\n+ * want to use these directly, just use pci_find_ht_capability() and it\n+ * will do the right thing for you.\n+ */\n+#define HT_3BIT_CAP_MASK\t0xE0\n+#define HT_CAPTYPE_SLAVE\t0x00\t/* Slave/Primary link configuration */\n+#define HT_CAPTYPE_HOST\t\t0x20\t/* Host/Secondary link configuration */\n+\n+#define HT_5BIT_CAP_MASK\t0xF8\n+#define HT_CAPTYPE_IRQ\t\t0x80\t/* IRQ Configuration */\n+#define HT_CAPTYPE_REMAPPING_40\t0xA0\t/* 40 bit address remapping */\n+#define HT_CAPTYPE_REMAPPING_64 0xA2\t/* 64 bit address remapping */\n+#define HT_CAPTYPE_UNITID_CLUMP\t0x90\t/* Unit ID clumping */\n+#define HT_CAPTYPE_EXTCONF\t0x98\t/* Extended Configuration Space Access */\n+#define HT_CAPTYPE_MSI_MAPPING\t0xA8\t/* MSI Mapping Capability */\n+#define HT_MSI_FLAGS\t\t0x02\t\t/* Offset to flags */\n+#define HT_MSI_FLAGS_ENABLE\t0x1\t\t/* Mapping enable */\n+#define HT_MSI_FLAGS_FIXED\t0x2\t\t/* Fixed mapping only */\n+#define HT_MSI_FIXED_ADDR\t0x00000000FEE00000ULL\t/* Fixed addr */\n+#define HT_MSI_ADDR_LO\t\t0x04\t\t/* Offset to low addr bits */\n+#define HT_MSI_ADDR_LO_MASK\t0xFFF00000\t/* Low address bit mask */\n+#define HT_MSI_ADDR_HI\t\t0x08\t\t/* Offset to high addr bits */\n+#define HT_CAPTYPE_DIRECT_ROUTE\t0xB0\t/* Direct routing configuration */\n+#define HT_CAPTYPE_VCSET\t0xB8\t/* Virtual Channel configuration */\n+#define HT_CAPTYPE_ERROR_RETRY\t0xC0\t/* Retry on error configuration */\n+#define HT_CAPTYPE_GEN3\t\t0xD0\t/* Generation 3 HyperTransport configuration */\n+#define HT_CAPTYPE_PM\t\t0xE0\t/* HyperTransport power management configuration */\n+#define HT_CAP_SIZEOF_LONG\t28\t/* slave & primary */\n+#define HT_CAP_SIZEOF_SHORT\t24\t/* host & secondary */\n+\n+/* Alternative Routing-ID Interpretation */\n+#define PCI_ARI_CAP\t\t0x04\t/* ARI Capability Register */\n+#define PCI_ARI_CAP_MFVC\t0x0001\t/* MFVC Function Groups Capability */\n+#define PCI_ARI_CAP_ACS\t0x0002\t/* ACS Function Groups Capability */\n+#define PCI_ARI_CAP_NFN(x)\t(((x) >> 8) & 0xff) /* Next Function Number */\n+#define PCI_ARI_CTRL\t\t0x06\t/* ARI Control Register */\n+#define PCI_ARI_CTRL_MFVC\t0x0001\t/* MFVC Function Groups Enable */\n+#define PCI_ARI_CTRL_ACS\t0x0002\t/* ACS Function Groups Enable */\n+#define PCI_ARI_CTRL_FG(x)\t(((x) >> 4) & 7) /* Function Group */\n+#define PCI_EXT_CAP_ARI_SIZEOF\t8\n+\n+/* Address Translation Service */\n+#define PCI_ATS_CAP\t\t0x04\t/* ATS Capability Register */\n+#define PCI_ATS_CAP_QDEP(x)\t((x) & 0x1f)\t/* Invalidate Queue Depth */\n+#define PCI_ATS_MAX_QDEP\t32\t/* Max Invalidate Queue Depth */\n+#define PCI_ATS_CAP_PAGE_ALIGNED\t0x0020 /* Page Aligned Request */\n+#define PCI_ATS_CTRL\t\t0x06\t/* ATS Control Register */\n+#define PCI_ATS_CTRL_ENABLE\t0x8000\t/* ATS Enable */\n+#define PCI_ATS_CTRL_STU(x)\t((x) & 0x1f)\t/* Smallest Translation Unit */\n+#define PCI_ATS_MIN_STU\t12\t/* shift of minimum STU block */\n+#define PCI_EXT_CAP_ATS_SIZEOF\t8\n+\n+/* Page Request Interface */\n+#define PCI_PRI_CTRL\t\t0x04\t/* PRI control register */\n+#define PCI_PRI_CTRL_ENABLE\t0x0001\t/* Enable */\n+#define PCI_PRI_CTRL_RESET\t0x0002\t/* Reset */\n+#define PCI_PRI_STATUS\t\t0x06\t/* PRI status register */\n+#define PCI_PRI_STATUS_RF\t0x0001\t/* Response Failure */\n+#define PCI_PRI_STATUS_UPRGI\t0x0002\t/* Unexpected PRG index */\n+#define PCI_PRI_STATUS_STOPPED\t0x0100\t/* PRI Stopped */\n+#define PCI_PRI_STATUS_PASID\t0x8000\t/* PRG Response PASID Required */\n+#define PCI_PRI_MAX_REQ\t\t0x08\t/* PRI max reqs supported */\n+#define PCI_PRI_ALLOC_REQ\t0x0c\t/* PRI max reqs allowed */\n+#define PCI_EXT_CAP_PRI_SIZEOF\t16\n+\n+/* Process Address Space ID */\n+#define PCI_PASID_CAP\t\t0x04 /* PASID feature register */\n+#define PCI_PASID_CAP_EXEC\t0x02\t/* Exec permissions Supported */\n+#define PCI_PASID_CAP_PRIV\t0x04\t/* Privilege Mode Supported */\n+#define PCI_PASID_CTRL\t\t0x06 /* PASID control register */\n+#define PCI_PASID_CTRL_ENABLE\t0x01\t/* Enable bit */\n+#define PCI_PASID_CTRL_EXEC\t0x02\t/* Exec permissions Enable */\n+#define PCI_PASID_CTRL_PRIV\t0x04\t/* Privilege Mode Enable */\n+#define PCI_EXT_CAP_PASID_SIZEOF\t8\n+\n+/* Single Root I/O Virtualization */\n+#define PCI_SRIOV_CAP\t\t0x04\t/* SR-IOV Capabilities */\n+#define PCI_SRIOV_CAP_VFM\t0x00000001 /* VF Migration Capable */\n+#define PCI_SRIOV_CAP_INTR(x)\t((x) >> 21) /* Interrupt Message Number */\n+#define PCI_SRIOV_CTRL\t\t0x08\t/* SR-IOV Control */\n+#define PCI_SRIOV_CTRL_VFE\t0x0001\t/* VF Enable */\n+#define PCI_SRIOV_CTRL_VFM\t0x0002\t/* VF Migration Enable */\n+#define PCI_SRIOV_CTRL_INTR\t0x0004\t/* VF Migration Interrupt Enable */\n+#define PCI_SRIOV_CTRL_MSE\t0x0008\t/* VF Memory Space Enable */\n+#define PCI_SRIOV_CTRL_ARI\t0x0010\t/* ARI Capable Hierarchy */\n+#define PCI_SRIOV_STATUS\t0x0a\t/* SR-IOV Status */\n+#define PCI_SRIOV_STATUS_VFM\t0x0001\t/* VF Migration Status */\n+#define PCI_SRIOV_INITIAL_VF\t0x0c\t/* Initial VFs */\n+#define PCI_SRIOV_TOTAL_VF\t0x0e\t/* Total VFs */\n+#define PCI_SRIOV_NUM_VF\t0x10\t/* Number of VFs */\n+#define PCI_SRIOV_FUNC_LINK\t0x12\t/* Function Dependency Link */\n+#define PCI_SRIOV_VF_OFFSET\t0x14\t/* First VF Offset */\n+#define PCI_SRIOV_VF_STRIDE\t0x16\t/* Following VF Stride */\n+#define PCI_SRIOV_VF_DID\t0x1a\t/* VF Device ID */\n+#define PCI_SRIOV_SUP_PGSIZE\t0x1c\t/* Supported Page Sizes */\n+#define PCI_SRIOV_SYS_PGSIZE\t0x20\t/* System Page Size */\n+#define PCI_SRIOV_BAR\t\t0x24\t/* VF BAR0 */\n+#define PCI_SRIOV_NUM_BARS\t6\t/* Number of VF BARs */\n+#define PCI_SRIOV_VFM\t\t0x3c\t/* VF Migration State Array Offset*/\n+#define PCI_SRIOV_VFM_BIR(x)\t((x) & 7)\t/* State BIR */\n+#define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7)\t/* State Offset */\n+#define PCI_SRIOV_VFM_UA\t0x0\t/* Inactive.Unavailable */\n+#define PCI_SRIOV_VFM_MI\t0x1\t/* Dormant.MigrateIn */\n+#define PCI_SRIOV_VFM_MO\t0x2\t/* Active.MigrateOut */\n+#define PCI_SRIOV_VFM_AV\t0x3\t/* Active.Available */\n+#define PCI_EXT_CAP_SRIOV_SIZEOF 64\n+\n+#define PCI_LTR_MAX_SNOOP_LAT\t0x4\n+#define PCI_LTR_MAX_NOSNOOP_LAT\t0x6\n+#define PCI_LTR_VALUE_MASK\t0x000003ff\n+#define PCI_LTR_SCALE_MASK\t0x00001c00\n+#define PCI_LTR_SCALE_SHIFT\t10\n+#define PCI_EXT_CAP_LTR_SIZEOF\t8\n+\n+/* Access Control Service */\n+#define PCI_ACS_CAP\t\t0x04\t/* ACS Capability Register */\n+#define PCI_ACS_SV\t\t0x0001\t/* Source Validation */\n+#define PCI_ACS_TB\t\t0x0002\t/* Translation Blocking */\n+#define PCI_ACS_RR\t\t0x0004\t/* P2P Request Redirect */\n+#define PCI_ACS_CR\t\t0x0008\t/* P2P Completion Redirect */\n+#define PCI_ACS_UF\t\t0x0010\t/* Upstream Forwarding */\n+#define PCI_ACS_EC\t\t0x0020\t/* P2P Egress Control */\n+#define PCI_ACS_DT\t\t0x0040\t/* Direct Translated P2P */\n+#define PCI_ACS_EGRESS_BITS\t0x05\t/* ACS Egress Control Vector Size */\n+#define PCI_ACS_CTRL\t\t0x06\t/* ACS Control Register */\n+#define PCI_ACS_EGRESS_CTL_V\t0x08\t/* ACS Egress Control Vector */\n+\n+#define PCI_VSEC_HDR\t\t4\t/* extended cap - vendor-specific */\n+#define PCI_VSEC_HDR_LEN_SHIFT\t20\t/* shift for length field */\n+\n+/* SATA capability */\n+#define PCI_SATA_REGS\t\t4\t/* SATA REGs specifier */\n+#define PCI_SATA_REGS_MASK\t0xF\t/* location - BAR#/inline */\n+#define PCI_SATA_REGS_INLINE\t0xF\t/* REGS in config space */\n+#define PCI_SATA_SIZEOF_SHORT\t8\n+#define PCI_SATA_SIZEOF_LONG\t16\n+\n+/* Resizable BARs */\n+#define PCI_REBAR_CAP\t\t4\t/* capability register */\n+#define PCI_REBAR_CAP_SIZES\t\t0x00FFFFF0 /* supported BAR sizes */\n+#define PCI_REBAR_CTRL\t\t8\t/* control register */\n+#define PCI_REBAR_CTRL_BAR_IDX\t\t0x00000007 /* BAR index */\n+#define PCI_REBAR_CTRL_NBAR_MASK\t0x000000E0 /* # of resizable BARs */\n+#define PCI_REBAR_CTRL_NBAR_SHIFT\t5\t /* shift for # of BARs */\n+#define PCI_REBAR_CTRL_BAR_SIZE\t0x00001F00 /* BAR size */\n+#define PCI_REBAR_CTRL_BAR_SHIFT\t8\t /* shift for BAR size */\n+\n+/* Dynamic Power Allocation */\n+#define PCI_DPA_CAP\t\t4\t/* capability register */\n+#define PCI_DPA_CAP_SUBSTATE_MASK\t0x1F\t/* # substates - 1 */\n+#define PCI_DPA_BASE_SIZEOF\t16\t/* size with 0 substates */\n+\n+/* TPH Requester */\n+#define PCI_TPH_CAP\t\t4\t/* capability register */\n+#define PCI_TPH_CAP_LOC_MASK\t0x600\t/* location mask */\n+#define PCI_TPH_LOC_NONE\t0x000\t/* no location */\n+#define PCI_TPH_LOC_CAP\t0x200\t/* in capability */\n+#define PCI_TPH_LOC_MSIX\t0x400\t/* in MSI-X */\n+#define PCI_TPH_CAP_ST_MASK\t0x07FF0000\t/* st table mask */\n+#define PCI_TPH_CAP_ST_SHIFT\t16\t/* st table shift */\n+#define PCI_TPH_BASE_SIZEOF\t12\t/* size with no st table */\n+\n+/* Downstream Port Containment */\n+#define PCI_EXP_DPC_CAP\t\t\t4\t/* DPC Capability */\n+#define PCI_EXP_DPC_IRQ\t\t\t0x001F\t/* Interrupt Message Number */\n+#define PCI_EXP_DPC_CAP_RP_EXT\t\t0x0020\t/* Root Port Extensions */\n+#define PCI_EXP_DPC_CAP_POISONED_TLP\t0x0040\t/* Poisoned TLP Egress Blocking Supported */\n+#define PCI_EXP_DPC_CAP_SW_TRIGGER\t0x0080\t/* Software Triggering Supported */\n+#define PCI_EXP_DPC_RP_PIO_LOG_SIZE\t0x0F00\t/* RP PIO Log Size */\n+#define PCI_EXP_DPC_CAP_DL_ACTIVE\t0x1000\t/* ERR_COR signal on DL_Active supported */\n+\n+#define PCI_EXP_DPC_CTL\t\t\t6\t/* DPC control */\n+#define PCI_EXP_DPC_CTL_EN_FATAL\t0x0001\t/* Enable trigger on ERR_FATAL message */\n+#define PCI_EXP_DPC_CTL_EN_NONFATAL\t0x0002\t/* Enable trigger on ERR_NONFATAL message */\n+#define PCI_EXP_DPC_CTL_INT_EN\t\t0x0008\t/* DPC Interrupt Enable */\n+\n+#define PCI_EXP_DPC_STATUS\t\t8\t/* DPC Status */\n+#define PCI_EXP_DPC_STATUS_TRIGGER\t 0x0001 /* Trigger Status */\n+#define PCI_EXP_DPC_STATUS_TRIGGER_RSN\t 0x0006 /* Trigger Reason */\n+#define PCI_EXP_DPC_STATUS_INTERRUPT\t 0x0008 /* Interrupt Status */\n+#define PCI_EXP_DPC_RP_BUSY\t\t 0x0010 /* Root Port Busy */\n+#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */\n+\n+#define PCI_EXP_DPC_SOURCE_ID\t\t10\t/* DPC Source Identifier */\n+\n+#define PCI_EXP_DPC_RP_PIO_STATUS\t 0x0C\t/* RP PIO Status */\n+#define PCI_EXP_DPC_RP_PIO_MASK\t\t 0x10\t/* RP PIO Mask */\n+#define PCI_EXP_DPC_RP_PIO_SEVERITY\t 0x14\t/* RP PIO Severity */\n+#define PCI_EXP_DPC_RP_PIO_SYSERROR\t 0x18\t/* RP PIO SysError */\n+#define PCI_EXP_DPC_RP_PIO_EXCEPTION\t 0x1C\t/* RP PIO Exception */\n+#define PCI_EXP_DPC_RP_PIO_HEADER_LOG\t 0x20\t/* RP PIO Header Log */\n+#define PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG\t 0x30\t/* RP PIO ImpSpec Log */\n+#define PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG 0x34\t/* RP PIO TLP Prefix Log */\n+\n+/* Precision Time Measurement */\n+#define PCI_PTM_CAP\t\t\t0x04\t /* PTM Capability */\n+#define PCI_PTM_CAP_REQ\t\t0x00000001 /* Requester capable */\n+#define PCI_PTM_CAP_ROOT\t\t0x00000004 /* Root capable */\n+#define PCI_PTM_GRANULARITY_MASK\t0x0000FF00 /* Clock granularity */\n+#define PCI_PTM_CTRL\t\t\t0x08\t /* PTM Control */\n+#define PCI_PTM_CTRL_ENABLE\t\t0x00000001 /* PTM enable */\n+#define PCI_PTM_CTRL_ROOT\t\t0x00000002 /* Root select */\n+\n+/* ASPM L1 PM Substates */\n+#define PCI_L1SS_CAP\t\t0x04\t/* Capabilities Register */\n+#define PCI_L1SS_CAP_PCIPM_L1_2\t0x00000001 /* PCI-PM L1.2 Supported */\n+#define PCI_L1SS_CAP_PCIPM_L1_1\t0x00000002 /* PCI-PM L1.1 Supported */\n+#define PCI_L1SS_CAP_ASPM_L1_2\t\t0x00000004 /* ASPM L1.2 Supported */\n+#define PCI_L1SS_CAP_ASPM_L1_1\t\t0x00000008 /* ASPM L1.1 Supported */\n+#define PCI_L1SS_CAP_L1_PM_SS\t\t0x00000010 /* L1 PM Substates Supported */\n+#define PCI_L1SS_CAP_CM_RESTORE_TIME\t0x0000ff00 /* Port Common_Mode_Restore_Time */\n+#define PCI_L1SS_CAP_P_PWR_ON_SCALE\t0x00030000 /* Port T_POWER_ON scale */\n+#define PCI_L1SS_CAP_P_PWR_ON_VALUE\t0x00f80000 /* Port T_POWER_ON value */\n+#define PCI_L1SS_CTL1\t\t0x08\t/* Control 1 Register */\n+#define PCI_L1SS_CTL1_PCIPM_L1_2\t0x00000001 /* PCI-PM L1.2 Enable */\n+#define PCI_L1SS_CTL1_PCIPM_L1_1\t0x00000002 /* PCI-PM L1.1 Enable */\n+#define PCI_L1SS_CTL1_ASPM_L1_2\t0x00000004 /* ASPM L1.2 Enable */\n+#define PCI_L1SS_CTL1_ASPM_L1_1\t0x00000008 /* ASPM L1.1 Enable */\n+#define PCI_L1SS_CTL1_L1SS_MASK\t0x0000000f\n+#define PCI_L1SS_CTL1_CM_RESTORE_TIME\t0x0000ff00 /* Common_Mode_Restore_Time */\n+#define PCI_L1SS_CTL1_LTR_L12_TH_VALUE\t0x03ff0000 /* LTR_L1.2_THRESHOLD_Value */\n+#define PCI_L1SS_CTL1_LTR_L12_TH_SCALE\t0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */\n+#define PCI_L1SS_CTL2\t\t0x0c\t/* Control 2 Register */\n+\n+/* Data Link Feature */\n+#define PCI_DLF_CAP\t\t0x04\t/* Capabilities Register */\n+#define PCI_DLF_EXCHANGE_ENABLE\t0x80000000 /* Data Link Feature Exchange Enable */\n+\n+/* Physical Layer 16.0 GT/s */\n+#define PCI_PL_16GT_LE_CTRL\t0x20\t/* Lane Equalization Control Register */\n+#define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK\t\t0x0000000F\n+#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK\t\t0x000000F0\n+#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT\t4\n+\n+#endif /* _RTE_PCI_REGS_H_ */\n", "prefixes": [ "v2", "1/7" ] }