Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/73205/?format=api
{ "id": 73205, "url": "http://patches.dpdk.org/api/patches/73205/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200706082502.26935-7-somnath.kotur@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200706082502.26935-7-somnath.kotur@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200706082502.26935-7-somnath.kotur@broadcom.com", "date": "2020-07-06T08:24:48", "name": "[06/20] net/bnxt: updated hsi_struct_def_dpdk.h", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "2dce38d83f1a221d218383f187fb2d352fda233c", "submitter": { "id": 908, "url": "http://patches.dpdk.org/api/people/908/?format=api", "name": "Somnath Kotur", "email": "somnath.kotur@broadcom.com" }, "delegate": { "id": 1766, "url": "http://patches.dpdk.org/api/users/1766/?format=api", "username": "ajitkhaparde", "first_name": "Ajit", "last_name": "Khaparde", "email": "ajit.khaparde@broadcom.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200706082502.26935-7-somnath.kotur@broadcom.com/mbox/", "series": [ { "id": 10805, "url": "http://patches.dpdk.org/api/series/10805/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=10805", "date": "2020-07-06T08:24:42", "name": "bnxt patches", "version": 1, "mbox": "http://patches.dpdk.org/series/10805/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/73205/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/73205/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3C83BA00C5;\n\tMon, 6 Jul 2020 10:31:32 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id CEC501DA9B;\n\tMon, 6 Jul 2020 10:30:16 +0200 (CEST)", "from relay.smtp.broadcom.com (unknown [192.19.211.62])\n by dpdk.org (Postfix) with ESMTP id C87D71D594\n for <dev@dpdk.org>; Mon, 6 Jul 2020 10:30:04 +0200 (CEST)", "from dhcp-10-123-153-55.dhcp.broadcom.net\n (dhcp-10-123-153-55.dhcp.broadcom.net [10.123.153.55])\n by relay.smtp.broadcom.com (Postfix) with ESMTP id DE77C2982B3;\n Mon, 6 Jul 2020 01:30:03 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com DE77C2982B3", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com;\n s=dkimrelay; t=1594024204;\n bh=At8STEQtqROUZ7DG23zDh0AMzyq1Ek9gQ7iDojMUTCA=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=ZkLlOJ2a8o7M7wkAzWluauymQHOzzdeM9UqVJ+II5rjkJPz51bphJFPm1QfrVH4ac\n xhIINL1jfnRnOoMFcx50K9zoERfIfeGUNGGFAveGchKXJ4JNb0vVTa6LhFvxiXyMeK\n fhwzE3AJc5mYkAzM+67XWWal5aTv4BIOylZlY+Cc=", "From": "Somnath Kotur <somnath.kotur@broadcom.com>", "To": "dev@dpdk.org", "Cc": "ferruh.yigit@intel.com", "Date": "Mon, 6 Jul 2020 13:54:48 +0530", "Message-Id": "<20200706082502.26935-7-somnath.kotur@broadcom.com>", "X-Mailer": "git-send-email 2.10.1.613.g2cc2e70", "In-Reply-To": "<20200706082502.26935-1-somnath.kotur@broadcom.com>", "References": "<20200706082502.26935-1-somnath.kotur@broadcom.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 06/20] net/bnxt: updated hsi_struct_def_dpdk.h", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jay Ding <jay.ding@broadcom.com>\n\nBrought in the latest hsi_struct_def_dpdk.h in order to get\nthe TF global cfg set/get HWRM cmds.\n\nSigned-off-by: Jay Ding <jay.ding@broadcom.com>\nReviewed-by: Randy Schacher <stuart.schacher@broadcom.com>\nSigned-off-by: Somnath Kotur <somnath.kotur@broadcom.com>\nSigned-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>\n---\n drivers/net/bnxt/hsi_struct_def_dpdk.h | 1486 +++++++++++++++++++++++++++++++-\n 1 file changed, 1468 insertions(+), 18 deletions(-)", "diff": "diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex 30516eb..b76aee2 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -341,9 +341,14 @@ struct cmd_nums {\n \t#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)\n \t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)\n \t#define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)\n+\t#define HWRM_RING_SQ_ALLOC UINT32_C(0x55)\n+\t#define HWRM_RING_SQ_CFG UINT32_C(0x56)\n+\t#define HWRM_RING_SQ_FREE UINT32_C(0x57)\n \t#define HWRM_RING_RESET UINT32_C(0x5e)\n \t#define HWRM_RING_GRP_ALLOC UINT32_C(0x60)\n \t#define HWRM_RING_GRP_FREE UINT32_C(0x61)\n+\t#define HWRM_RING_CFG UINT32_C(0x62)\n+\t#define HWRM_RING_QCFG UINT32_C(0x63)\n \t/* Reserved for future use. */\n \t#define HWRM_RESERVED5 UINT32_C(0x64)\n \t/* Reserved for future use. */\n@@ -695,6 +700,10 @@ struct cmd_nums {\n \t/* Experimental */\n \t#define HWRM_TF_TCAM_FREE UINT32_C(0x2fb)\n \t/* Experimental */\n+\t#define HWRM_TF_GLOBAL_CFG_SET UINT32_C(0x2fc)\n+\t/* Experimental */\n+\t#define HWRM_TF_GLOBAL_CFG_GET UINT32_C(0x2fd)\n+\t/* Experimental */\n \t#define HWRM_SV UINT32_C(0x400)\n \t/* Experimental */\n \t#define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)\n@@ -933,8 +942,8 @@ struct hwrm_err_output {\n #define HWRM_VERSION_MINOR 10\n #define HWRM_VERSION_UPDATE 1\n /* non-zero means beta version */\n-#define HWRM_VERSION_RSVD 45\n-#define HWRM_VERSION_STR \"1.10.1.45\"\n+#define HWRM_VERSION_RSVD 48\n+#define HWRM_VERSION_STR \"1.10.1.48\"\n \n /****************\n * hwrm_ver_get *\n@@ -8889,6 +8898,16 @@ struct hwrm_func_vf_cfg_input {\n \t */\n \t#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \\\n \t\tUINT32_C(0x80)\n+\t/*\n+\t * If this bit is set to 1, the VF driver is requesting FW to enable\n+\t * PPP TX PUSH feature on all the TX rings specified in the\n+\t * num_tx_rings field. By default, the PPP TX push feature is\n+\t * disabled for all the TX rings of the VF. This flag is ignored if\n+\t * the num_tx_rings field is not specified or the VF doesn't support\n+\t * PPP tx push feature.\n+\t */\n+\t#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \\\n+\t\tUINT32_C(0x100)\n \t/* The number of RSS/COS contexts requested for the VF. */\n \tuint16_t\tnum_rsscos_ctxs;\n \t/* The number of completion rings requested for the VF. */\n@@ -9367,7 +9386,30 @@ struct hwrm_func_qcaps_output {\n \t */\n \t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT \\\n \t\tUINT32_C(0x8)\n-\tuint8_t\tunused_1[3];\n+\t/* If 1, the proxy mode is supported on this function */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PROXY_MODE_SUPPORT \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * If 1, the tx rings source interface override feature is supported\n+\t * on this function.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * If 1, the device supports scheduler queues. SQs can be managed\n+\t * using RING_SQ_ALLOC/CFG/FREE commands.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SQ_SUPPORTED \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * If set to 1, then this function supports the TX push mode that\n+\t * uses ping-pong buffers from the push pages.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED \\\n+\t\tUINT32_C(0x80)\n+\t/* The maximum number of SQs supported by this device. */\n+\tuint8_t\tmax_sqs;\n+\tuint8_t\tunused_1[2];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -9538,6 +9580,13 @@ struct hwrm_func_qcfg_output {\n \t#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_HOT_RESET_ALLOWED \\\n \t\tUINT32_C(0x200)\n \t/*\n+\t * If set to 1, then the PPP tx push mode is enabled for all the\n+\t * reserved TX rings of this function. If set to 0, then PPP tx push\n+\t * mode is disabled for all the reserved TX rings of this function.\n+\t */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PPP_PUSH_MODE_ENABLED \\\n+\t\tUINT32_C(0x400)\n+\t/*\n \t * This value is current MAC address configured for this\n \t * function. A value of 00-00-00-00-00-00 indicates no\n \t * MAC address is currently configured.\n@@ -9869,7 +9918,7 @@ struct hwrm_func_qcfg_output {\n *****************/\n \n \n-/* hwrm_func_cfg_input (size:704b/88B) */\n+/* hwrm_func_cfg_input (size:768b/96B) */\n struct hwrm_func_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n@@ -10100,6 +10149,16 @@ struct hwrm_func_cfg_input {\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_FLAGS_HOT_RESET_IF_EN_DIS \\\n \t\tUINT32_C(0x4000000)\n+\t/*\n+\t * If this bit is set to 1, the PF driver is requesting FW\n+\t * to enable PPP TX PUSH feature on all the TX rings specified in\n+\t * the num_tx_rings field. By default, the PPP TX push feature is\n+\t * disabled for all the TX rings of the function. This flag is\n+\t * ignored if num_tx_rings field is not specified or the function\n+\t * doesn't support PPP tx push feature.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \\\n+\t\tUINT32_C(0x8000000)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the mtu field to be\n@@ -10246,6 +10305,12 @@ struct hwrm_func_cfg_input {\n \t#define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT \\\n \t\tUINT32_C(0x800000)\n \t/*\n+\t * This bit must be '1' for the sq_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES_SQ_ID \\\n+\t\tUINT32_C(0x1000000)\n+\t/*\n \t * The maximum transmission unit of the function.\n \t * The HWRM should make sure that the mtu of\n \t * the function does not exceed the mtu of the physical\n@@ -10509,6 +10574,9 @@ struct hwrm_func_cfg_input {\n \t * be reserved for this function on the RX side.\n \t */\n \tuint16_t\tnum_mcast_filters;\n+\t/* Used by a PF driver to associate a SQ with a VF. */\n+\tuint16_t\tsq_id;\n+\tuint8_t\tunused_0[6];\n } __rte_packed;\n \n /* hwrm_func_cfg_output (size:128b/16B) */\n@@ -10682,7 +10750,7 @@ struct hwrm_func_qstats_output {\n ************************/\n \n \n-/* hwrm_func_qstats_ext_input (size:192b/24B) */\n+/* hwrm_func_qstats_ext_input (size:256b/32B) */\n struct hwrm_func_qstats_ext_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n@@ -10737,7 +10805,22 @@ struct hwrm_func_qstats_ext_input {\n \t#define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)\n \t#define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \\\n \t\tHWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK\n-\tuint8_t\tunused_0[5];\n+\tuint8_t\tunused_0[1];\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the sq_id and traffic_class fields to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SQ_ID UINT32_C(0x1)\n+\t/* Specifies the SQ for which to gather statistics */\n+\tuint16_t\tsq_id;\n+\t/*\n+\t * Specifies the traffic class for which to gather statistics. Valid\n+\t * values are 0 through (max_configurable_queues - 1), where\n+\t * max_configurable_queues is in the response of HWRM_QUEUE_QPORTCFG\n+\t */\n+\tuint16_t\ttraffic_class;\n+\tuint8_t\tunused_1[4];\n } __rte_packed;\n \n /* hwrm_func_qstats_ext_output (size:1472b/184B) */\n@@ -15128,8 +15211,13 @@ struct hwrm_port_phy_cfg_input {\n \t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * When this bit is set to '1', the link shall be forced to\n-\t * the force_link_speed value.\n+\t * When this bit is set to '1', and the force_pam4_link_speed\n+\t * bit in the 'enables' field is '0', the link shall be forced\n+\t * to the force_link_speed value.\n+\t *\n+\t * When this bit is set to '1', and the force_pam4_link_speed\n+\t * bit in the 'enables' field is '1', the link shall be forced\n+\t * to the force_pam4_link_speed value.\n \t *\n \t * When this bit is set to '1', the HWRM client should\n \t * not enable any of the auto negotiation related\n@@ -15602,7 +15690,23 @@ struct hwrm_port_phy_cfg_input {\n \t/* 10Gb link speed */\n \t#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \\\n \t\tUINT32_C(0x40)\n-\tuint8_t\tunused_2[2];\n+\t/*\n+\t * This is the speed that will be used if the force and force_pam4\n+\t * bits are '1'. If unsupported speed is selected, an error\n+\t * will be generated.\n+\t */\n+\tuint16_t\tforce_pam4_link_speed;\n+\t/* 50Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB \\\n+\t\tUINT32_C(0x1f4)\n+\t/* 100Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB \\\n+\t\tUINT32_C(0x3e8)\n+\t/* 200Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB \\\n+\t\tUINT32_C(0x7d0)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_LAST \\\n+\t\tHWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB\n \t/*\n \t * Requested setting of TX LPI timer in microseconds.\n \t * This field is valid only when EEE is enabled and TX LPI is\n@@ -25307,6 +25411,9 @@ struct hwrm_vnic_cfg_input {\n \t/* This bit must be '1' for the queue_id field to be configured. */\n \t#define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \\\n \t\tUINT32_C(0x80)\n+\t/* This bit must be '1' for the rx_csum_v2_mode field to be configured. */\n+\t#define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE \\\n+\t\tUINT32_C(0x100)\n \t/* Logical vnic ID */\n \tuint16_t\tvnic_id;\n \t/*\n@@ -25364,7 +25471,41 @@ struct hwrm_vnic_cfg_input {\n \t * filter rules with destination VNIC specified.\n \t */\n \tuint16_t\tqueue_id;\n-\tuint8_t\tunused0[6];\n+\t/*\n+\t * If the device supports the RX V2 and RX TPA start V2 completion\n+\t * records as indicated by the HWRM_VNIC_QCAPS command, this field is\n+\t * used to specify the two RX checksum modes supported by these\n+\t * completion records.\n+\t */\n+\tuint8_t\trx_csum_v2_mode;\n+\t/*\n+\t * When configured with this checksum mode, the number of header\n+\t * groups in the delivered packet with a valid IP checksum and\n+\t * the number of header groups in the delivered packet with a valid\n+\t * L4 checksum are reported. Valid checksums are counted from the\n+\t * outermost header group to the innermost header group, stopping at\n+\t * the first error. This is the default checksum mode supported if\n+\t * the driver doesn't explicitly configure the RX checksum mode.\n+\t */\n+\t#define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)\n+\t/*\n+\t * When configured with this checksum mode, the checksum status is\n+\t * reported using 'all ok' mode. In the RX completion record, one\n+\t * bit indicates if the IP checksum is valid for all the parsed\n+\t * header groups with an IP checksum. Another bit indicates if the\n+\t * L4 checksum is valid for all the parsed header groups with an L4\n+\t * checksum. The number of header groups that were parsed by the\n+\t * chip and passed in the delivered packet is also reported.\n+\t */\n+\t#define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)\n+\t/*\n+\t * Any rx_csum_v2_mode value larger than or equal to this is not\n+\t * valid\n+\t */\n+\t#define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)\n+\t#define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_LAST \\\n+\t\tHWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX\n+\tuint8_t\tunused0[5];\n } __rte_packed;\n \n /* hwrm_vnic_cfg_output (size:128b/16B) */\n@@ -25539,7 +25680,33 @@ struct hwrm_vnic_qcfg_output {\n \t * queue association.\n \t */\n \tuint16_t\tqueue_id;\n-\tuint8_t\tunused_1[5];\n+\t/*\n+\t * If the device supports the RX V2 and RX TPA start V2 completion\n+\t * records as indicated by the HWRM_VNIC_QCAPS command, this field is\n+\t * used to specify the current RX checksum mode configured for all the\n+\t * RX rings of a VNIC.\n+\t */\n+\tuint8_t\trx_csum_v2_mode;\n+\t/*\n+\t * This value indicates that the VNIC is configured to use the\n+\t * default RX checksum mode for all the rings associated with this\n+\t * VNIC.\n+\t */\n+\t#define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)\n+\t/*\n+\t * This value indicates that the VNIC is configured to use the RX\n+\t * checksum ‘all_ok’ mode for all the rings associated with this\n+\t * VNIC.\n+\t */\n+\t#define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)\n+\t/*\n+\t * Any rx_csum_v2_mode value larger than or equal to this is not\n+\t * valid\n+\t */\n+\t#define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)\n+\t#define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_LAST \\\n+\t\tHWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX\n+\tuint8_t\tunused_1[4];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -25677,6 +25844,17 @@ struct hwrm_vnic_qcaps_output {\n \t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \\\n \t\tUINT32_C(0x100)\n \t/*\n+\t * When this bit is '1', it indicates that HW and firmware supports\n+\t * the use of RX V2 and RX TPA start V2 completion records for all\n+\t * the RX rings of a VNIC. Once set, this feature is mandatory to\n+\t * be used for the RX rings of the VNIC. Additionally, two new RX\n+\t * checksum features supported by these ompletion records can be\n+\t * configured using the HWRM_VNIC_CFG on a VNIC. If set to '0', the\n+\t * HW and the firmware does not support this feature.\n+\t */\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP \\\n+\t\tUINT32_C(0x200)\n+\t/*\n \t * This field advertises the maximum concurrent TPA aggregations\n \t * supported by the VNIC on new devices that support TPA v2.\n \t * '0' means that TPA v2 is not supported.\n@@ -26308,6 +26486,13 @@ struct hwrm_vnic_plcmodes_cfg_input {\n \t */\n \t#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \\\n \t\tUINT32_C(0x20)\n+\t/*\n+\t * When this bit is '1', the VNIC shall be configured use the virtio\n+\t * placement algorithm. This feature can only be configured when\n+\t * proxy mode is supported on the function.\n+\t */\n+\t#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_VIRTIO_PLACEMENT \\\n+\t\tUINT32_C(0x40)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the jumbo_thresh_valid field to be\n@@ -26327,6 +26512,12 @@ struct hwrm_vnic_plcmodes_cfg_input {\n \t */\n \t#define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \\\n \t\tUINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for the max_bds_valid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_MAX_BDS_VALID \\\n+\t\tUINT32_C(0x8)\n \t/* Logical vnic ID */\n \tuint32_t\tvnic_id;\n \t/*\n@@ -26354,7 +26545,21 @@ struct hwrm_vnic_plcmodes_cfg_input {\n \t * This value shall be in multiple of 4 bytes.\n \t */\n \tuint16_t\thds_threshold;\n-\tuint8_t\tunused_0[6];\n+\t/*\n+\t * When virtio placement algorithm is enabled, this\n+\t * value is used to determine the the maximum number of BDs\n+\t * that can be used to place an Rx Packet.\n+\t * If an incoming packet does not fit in the buffers described\n+\t * by the max BDs, the packet will be dropped and an error\n+\t * will be reported in the completion. Valid values for this\n+\t * field are between 1 and 8. If the VNIC uses header-data-\n+\t * separation and/or TPA with buffer spanning enabled, valid\n+\t * values for this field are between 2 and 8.\n+\t * This feature can only be configured when proxy mode is\n+\t * supported on the function.\n+\t */\n+\tuint16_t\tmax_bds;\n+\tuint8_t\tunused_0[4];\n } __rte_packed;\n \n /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */\n@@ -26372,8 +26577,9 @@ struct hwrm_vnic_plcmodes_cfg_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -26472,6 +26678,13 @@ struct hwrm_vnic_plcmodes_qcfg_output {\n \t#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \\\n \t\tUINT32_C(0x40)\n \t/*\n+\t * When this bit is '1', the VNIC is configured to use the virtio\n+\t * placement algorithm. This feature can only be configured when\n+\t * proxy mode is supported on the function.\n+\t */\n+\t#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_VIRTIO_PLACEMENT \\\n+\t\tUINT32_C(0x80)\n+\t/*\n \t * When jumbo placement algorithm is enabled, this value\n \t * is used to determine the threshold for jumbo placement.\n \t * Packets with length larger than this value will be\n@@ -26496,13 +26709,28 @@ struct hwrm_vnic_plcmodes_qcfg_output {\n \t * This value shall be in multiple of 4 bytes.\n \t */\n \tuint16_t\thds_threshold;\n-\tuint8_t\tunused_0[5];\n+\t/*\n+\t * When virtio placement algorithm is enabled, this\n+\t * value is used to determine the the maximum number of BDs\n+\t * that can be used to place an Rx Packet.\n+\t * If an incoming packet does not fit in the buffers described\n+\t * by the max BDs, the packet will be dropped and an error\n+\t * will be reported in the completion. Valid values for this\n+\t * field are between 1 and 8. If the VNIC uses header-data-\n+\t * separation and/or TPA with buffer spanning enabled, valid\n+\t * values for this field are between 2 and 8.\n+\t * This feature can only be configured when proxy mode is supported\n+\t * on the function\n+\t */\n+\tuint16_t\tmax_bds;\n+\tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -26700,6 +26928,12 @@ struct hwrm_ring_alloc_input {\n \t */\n \t#define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \\\n \t\tUINT32_C(0x100)\n+\t/*\n+\t * This bit must be '1' for the sq_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_ALLOC_INPUT_ENABLES_SQ_ID \\\n+\t\tUINT32_C(0x200)\n \t/* Ring Type. */\n \tuint8_t\tring_type;\n \t/* L2 Completion Ring (CR) */\n@@ -26765,7 +26999,8 @@ struct hwrm_ring_alloc_input {\n \t * element of the ring.\n \t */\n \tuint8_t\tpage_tbl_depth;\n-\tuint8_t\tunused_1[2];\n+\t/* Used by a PF driver to associate a SQ with one of its TX rings. */\n+\tuint16_t\tsq_id;\n \t/*\n \t * Number of 16B units in the ring. Minimum size for\n \t * a ring is 16 16B entries.\n@@ -27132,6 +27367,290 @@ struct hwrm_ring_reset_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n+/*****************\n+ * hwrm_ring_cfg *\n+ *****************/\n+\n+\n+/* hwrm_ring_cfg_input (size:256b/32B) */\n+struct hwrm_ring_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Ring Type. */\n+\tuint8_t\tring_type;\n+\t/* TX Ring (TR) */\n+\t#define HWRM_RING_CFG_INPUT_RING_TYPE_TX UINT32_C(0x1)\n+\t/* RX Ring (RR) */\n+\t#define HWRM_RING_CFG_INPUT_RING_TYPE_RX UINT32_C(0x2)\n+\t#define HWRM_RING_CFG_INPUT_RING_TYPE_LAST \\\n+\t\tHWRM_RING_CFG_INPUT_RING_TYPE_RX\n+\tuint8_t\tunused_0;\n+\t/* Physical number of the ring. */\n+\tuint16_t\tring_id;\n+\t/* Ring config enable bits. */\n+\tuint16_t\tenables;\n+\t/*\n+\t * For Rx rings, the incoming packet data can be placed at either\n+\t * a 0B, 2B, 10B or 12B offset from the start of the Rx packet\n+\t * buffer.\n+\t * When '1', the received packet will be padded with 2B, 10B or 12B\n+\t * of zeros at the front of the packet. The exact offset is specified\n+\t * by rx_sop_pad_bytes parameter.\n+\t * When '0', the received packet will not be padded.\n+\t * Note that this flag is only used for Rx rings and is ignored\n+\t * for all other rings included Rx Aggregation rings.\n+\t */\n+\t#define HWRM_RING_CFG_INPUT_ENABLES_RX_SOP_PAD_ENABLE \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.\n+\t * When rings are allocated, the PCI function on which driver issues\n+\t * HWRM_RING_CFG command is assumed to own the rings. Hardware takes\n+\t * the buffer descriptors (BDs) from those rings is assumed to issue\n+\t * packet payload DMA using same PCI function. When proxy mode is\n+\t * enabled, hardware can perform payload DMA using another PCI\n+\t * function on same or different host.\n+\t * When set to '0', the PCI function on which driver issues\n+\t * HWRM_RING_CFG command is used for host payload DMA operation.\n+\t * When set to '1', the host PCI function specified by proxy_fid is\n+\t * used for host payload DMA operation.\n+\t */\n+\t#define HWRM_RING_CFG_INPUT_ENABLES_PROXY_MODE_ENABLE \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * Tx ring packet source interface override, for Tx rings only.\n+\t * When TX rings are allocated, the PCI function on which driver\n+\t * issues HWRM_RING_CFG is assumed to be source interface of\n+\t * packets sent from TX ring.\n+\t * When set to '1', the host PCI function specified by proxy_fid\n+\t * is used as source interface of the transmitted packets.\n+\t */\n+\t#define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \\\n+\t\tUINT32_C(0x4)\n+\t/* The sq_id field is valid */\n+\t#define HWRM_RING_CFG_INPUT_ENABLES_SQ_ID \\\n+\t\tUINT32_C(0x8)\n+\t/* Update completion ring ID associated with Tx or Rx ring. */\n+\t#define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * Proxy function FID value.\n+\t * This value is only used when either proxy_mode_enable flag or\n+\t * tx_proxy_svif_override is set to '1'.\n+\t * When proxy_mode_enable is set to '1', it identifies a host PCI\n+\t * function used for host payload DMA operations.\n+\t * When tx_proxy_src_intf is set to '1', it identifies a host PCI\n+\t * function as source interface for all transmitted packets from\n+\t * the TX ring.\n+\t */\n+\tuint16_t\tproxy_fid;\n+\t/*\n+\t * Identifies the new scheduler queue (SQ) to associate with the ring.\n+\t * Only valid for Tx rings.\n+\t * A value of zero indicates that the Tx ring should be associated\n+\t * with the default scheduler queue (SQ).\n+\t */\n+\tuint16_t\tsq_id;\n+\t/*\n+\t * This field is valid for TX or Rx rings. This value identifies the\n+\t * new completion ring ID to associate with the TX or Rx ring.\n+\t */\n+\tuint16_t\tcmpl_ring_id;\n+\t/*\n+\t * Rx SOP padding amount in bytes.\n+\t * This value is only used when rx_sop_pad_enable flag is set to '1'.\n+\t */\n+\tuint8_t\trx_sop_pad_bytes;\n+\tuint8_t\tunused_1[3];\n+} __rte_packed;\n+\n+/* hwrm_ring_cfg_output (size:128b/16B) */\n+struct hwrm_ring_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/******************\n+ * hwrm_ring_qcfg *\n+ ******************/\n+\n+\n+/* hwrm_ring_qcfg_input (size:192b/24B) */\n+struct hwrm_ring_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Ring Type. */\n+\tuint8_t\tring_type;\n+\t/* TX Ring (TR) */\n+\t#define HWRM_RING_QCFG_INPUT_RING_TYPE_TX UINT32_C(0x1)\n+\t/* RX Ring (RR) */\n+\t#define HWRM_RING_QCFG_INPUT_RING_TYPE_RX UINT32_C(0x2)\n+\t#define HWRM_RING_QCFG_INPUT_RING_TYPE_LAST \\\n+\t\tHWRM_RING_QCFG_INPUT_RING_TYPE_RX\n+\tuint8_t\tunused_0[5];\n+\t/* Physical number of the ring. */\n+\tuint16_t\tring_id;\n+} __rte_packed;\n+\n+/* hwrm_ring_qcfg_output (size:192b/24B) */\n+struct hwrm_ring_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Ring config enable bits. */\n+\tuint16_t\tenables;\n+\t/*\n+\t * For Rx rings, the incoming packet data can be placed at either\n+\t * a 0B, 2B, 10B or 12B offset from the start of the Rx packet\n+\t * buffer.\n+\t * When '1', the received packet will be padded with 2B, 10B or 12B\n+\t * of zeros at the front of the packet. The exact offset is specified\n+\t * by rx_sop_pad_bytes parameter.\n+\t * When '0', the received packet will not be padded.\n+\t * Note that this flag is only used for Rx rings and is ignored\n+\t * for all other rings included Rx Aggregation rings.\n+\t */\n+\t#define HWRM_RING_QCFG_OUTPUT_ENABLES_RX_SOP_PAD_ENABLE \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.\n+\t * When rings are allocated, the PCI function on which driver issues\n+\t * HWRM_RING_CFG command is assumed to own the rings. Hardware takes\n+\t * the buffer descriptors (BDs) from those rings is assumed to issue\n+\t * packet payload DMA using same PCI function. When proxy mode is\n+\t * enabled, hardware can perform payload DMA using another PCI\n+\t * function on same or different host.\n+\t * When set to '0', the PCI function on which driver issues\n+\t * HWRM_RING_CFG command is used for host payload DMA operation.\n+\t * When set to '1', the host PCI function specified by proxy_fid is\n+\t * used for host payload DMA operation.\n+\t */\n+\t#define HWRM_RING_QCFG_OUTPUT_ENABLES_PROXY_MODE_ENABLE \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * Tx ring packet source interface override, for Tx rings only.\n+\t * When TX rings are allocated, the PCI function on which driver\n+\t * issues HWRM_RING_CFG is assumed to be source interface of\n+\t * packets sent from TX ring.\n+\t * When set to '1', the host PCI function specified by proxy_fid is\n+\t * used as source interface of the transmitted packets.\n+\t */\n+\t#define HWRM_RING_QCFG_OUTPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * Proxy function FID value.\n+\t * This value is only used when either proxy_mode_enable flag or\n+\t * tx_proxy_svif_override is set to '1'.\n+\t * When proxy_mode_enable is set to '1', it identifies a host PCI\n+\t * function used for host payload DMA operations.\n+\t * When tx_proxy_src_intf is set to '1', it identifies a host PCI\n+\t * function as source interface for all transmitted packets from the TX\n+\t * ring.\n+\t */\n+\tuint16_t\tproxy_fid;\n+\t/*\n+\t * Identifies the new scheduler queue (SQ) to associate with the ring.\n+\t * Only valid for Tx rings.\n+\t * A value of zero indicates that the Tx ring should be associated with\n+\t * the default scheduler queue (SQ).\n+\t */\n+\tuint16_t\tsq_id;\n+\t/*\n+\t * This field is used when ring_type is a TX or Rx ring.\n+\t * This value indicates what completion ring the TX or Rx ring\n+\t * is associated with.\n+\t */\n+\tuint16_t\tcmpl_ring_id;\n+\t/*\n+\t * Rx SOP padding amount in bytes.\n+\t * This value is only used when rx_sop_pad_enable flag is set to '1'.\n+\t */\n+\tuint8_t\trx_sop_pad_bytes;\n+\tuint8_t\tunused_0[6];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n /**************************\n * hwrm_ring_aggint_qcaps *\n **************************/\n@@ -27702,6 +28221,780 @@ struct hwrm_ring_grp_free_output {\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n+\n+/**********************\n+ * hwrm_ring_sq_alloc *\n+ **********************/\n+\n+\n+/* hwrm_ring_sq_alloc_input (size:1088b/136B) */\n+struct hwrm_ring_sq_alloc_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the tqm_ring0 fields to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the tqm_ring1 fields to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the tqm_ring2 fields to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for the tqm_ring3 fields to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8)\n+\t/*\n+\t * This bit must be '1' for the tqm_ring4 fields to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10)\n+\t/*\n+\t * This bit must be '1' for the tqm_ring5 fields to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20)\n+\t/*\n+\t * This bit must be '1' for the tqm_ring6 fields to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40)\n+\t/*\n+\t * This bit must be '1' for the tqm_ring7 fields to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80)\n+\t/* Reserved for future use. */\n+\tuint32_t\treserved;\n+\t/* TQM ring 0 page size and level. */\n+\tuint8_t\ttqm_ring0_pg_size_tqm_ring0_lvl;\n+\t/* TQM ring 0 PBL indirect levels. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_MASK UINT32_C(0xf)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_SFT 0\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 \\\n+\t\tUINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * PBL pointer points to PDE table with each entry pointing to PTE\n+\t * tables.\n+\t */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LAST \\\n+\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2\n+\t/* TQM ring 0 page size. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK UINT32_C(0xf0)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT 4\n+\t/* 4KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K \\\n+\t\t(UINT32_C(0x0) << 4)\n+\t/* 8KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K \\\n+\t\t(UINT32_C(0x1) << 4)\n+\t/* 64KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t/* 2MB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M \\\n+\t\t(UINT32_C(0x3) << 4)\n+\t/* 8MB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M \\\n+\t\t(UINT32_C(0x4) << 4)\n+\t/* 1GB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G \\\n+\t\t(UINT32_C(0x5) << 4)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST \\\n+\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G\n+\t/* TQM ring 1 page size and level. */\n+\tuint8_t\ttqm_ring1_pg_size_tqm_ring1_lvl;\n+\t/* TQM ring 1 PBL indirect levels. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_MASK UINT32_C(0xf)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_SFT 0\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 \\\n+\t\tUINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * PBL pointer points to PDE table with each entry pointing to PTE\n+\t * tables.\n+\t */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LAST \\\n+\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2\n+\t/* TQM ring 1 page size. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK UINT32_C(0xf0)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT 4\n+\t/* 4KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K \\\n+\t\t(UINT32_C(0x0) << 4)\n+\t/* 8KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K \\\n+\t\t(UINT32_C(0x1) << 4)\n+\t/* 64KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t/* 2MB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M \\\n+\t\t(UINT32_C(0x3) << 4)\n+\t/* 8MB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M \\\n+\t\t(UINT32_C(0x4) << 4)\n+\t/* 1GB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G \\\n+\t\t(UINT32_C(0x5) << 4)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST \\\n+\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G\n+\t/* TQM ring 2 page size and level. */\n+\tuint8_t\ttqm_ring2_pg_size_tqm_ring2_lvl;\n+\t/* TQM ring 2 PBL indirect levels. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_MASK UINT32_C(0xf)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_SFT 0\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 \\\n+\t\tUINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * PBL pointer points to PDE table with each entry pointing to PTE\n+\t * tables.\n+\t */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LAST \\\n+\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2\n+\t/* TQM ring 2 page size. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK UINT32_C(0xf0)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT 4\n+\t/* 4KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K \\\n+\t\t(UINT32_C(0x0) << 4)\n+\t/* 8KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K \\\n+\t\t(UINT32_C(0x1) << 4)\n+\t/* 64KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t/* 2MB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M \\\n+\t\t(UINT32_C(0x3) << 4)\n+\t/* 8MB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M \\\n+\t\t(UINT32_C(0x4) << 4)\n+\t/* 1GB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G \\\n+\t\t(UINT32_C(0x5) << 4)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST \\\n+\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G\n+\t/* TQM ring 3 page size and level. */\n+\tuint8_t\ttqm_ring3_pg_size_tqm_ring3_lvl;\n+\t/* TQM ring 3 PBL indirect levels. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_MASK UINT32_C(0xf)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_SFT 0\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 \\\n+\t\tUINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * PBL pointer points to PDE table with each entry pointing to PTE\n+\t * tables.\n+\t */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LAST \\\n+\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2\n+\t/* TQM ring 3 page size. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK UINT32_C(0xf0)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT 4\n+\t/* 4KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K \\\n+\t\t(UINT32_C(0x0) << 4)\n+\t/* 8KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K \\\n+\t\t(UINT32_C(0x1) << 4)\n+\t/* 64KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t/* 2MB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M \\\n+\t\t(UINT32_C(0x3) << 4)\n+\t/* 8MB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M \\\n+\t\t(UINT32_C(0x4) << 4)\n+\t/* 1GB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G \\\n+\t\t(UINT32_C(0x5) << 4)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST \\\n+\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G\n+\t/* TQM ring 4 page size and level. */\n+\tuint8_t\ttqm_ring4_pg_size_tqm_ring4_lvl;\n+\t/* TQM ring 4 PBL indirect levels. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_MASK UINT32_C(0xf)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_SFT 0\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 \\\n+\t\tUINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * PBL pointer points to PDE table with each entry pointing to PTE\n+\t * tables.\n+\t */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LAST \\\n+\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2\n+\t/* TQM ring 4 page size. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK UINT32_C(0xf0)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT 4\n+\t/* 4KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K \\\n+\t\t(UINT32_C(0x0) << 4)\n+\t/* 8KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K \\\n+\t\t(UINT32_C(0x1) << 4)\n+\t/* 64KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t/* 2MB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M \\\n+\t\t(UINT32_C(0x3) << 4)\n+\t/* 8MB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M \\\n+\t\t(UINT32_C(0x4) << 4)\n+\t/* 1GB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G \\\n+\t\t(UINT32_C(0x5) << 4)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST \\\n+\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G\n+\t/* TQM ring 5 page size and level. */\n+\tuint8_t\ttqm_ring5_pg_size_tqm_ring5_lvl;\n+\t/* TQM ring 5 PBL indirect levels. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_MASK UINT32_C(0xf)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_SFT 0\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 \\\n+\t\tUINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * PBL pointer points to PDE table with each entry pointing to PTE\n+\t * tables.\n+\t */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LAST \\\n+\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2\n+\t/* TQM ring 5 page size. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK UINT32_C(0xf0)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT 4\n+\t/* 4KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K \\\n+\t\t(UINT32_C(0x0) << 4)\n+\t/* 8KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K \\\n+\t\t(UINT32_C(0x1) << 4)\n+\t/* 64KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t/* 2MB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M \\\n+\t\t(UINT32_C(0x3) << 4)\n+\t/* 8MB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M \\\n+\t\t(UINT32_C(0x4) << 4)\n+\t/* 1GB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G \\\n+\t\t(UINT32_C(0x5) << 4)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST \\\n+\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G\n+\t/* TQM ring 6 page size and level. */\n+\tuint8_t\ttqm_ring6_pg_size_tqm_ring6_lvl;\n+\t/* TQM ring 6 PBL indirect levels. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_MASK UINT32_C(0xf)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_SFT 0\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 \\\n+\t\tUINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * PBL pointer points to PDE table with each entry pointing to PTE\n+\t * tables.\n+\t */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LAST \\\n+\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2\n+\t/* TQM ring 6 page size. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK UINT32_C(0xf0)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT 4\n+\t/* 4KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K \\\n+\t\t(UINT32_C(0x0) << 4)\n+\t/* 8KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K \\\n+\t\t(UINT32_C(0x1) << 4)\n+\t/* 64KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t/* 2MB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M \\\n+\t\t(UINT32_C(0x3) << 4)\n+\t/* 8MB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M \\\n+\t\t(UINT32_C(0x4) << 4)\n+\t/* 1GB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G \\\n+\t\t(UINT32_C(0x5) << 4)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST \\\n+\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G\n+\t/* TQM ring 7 page size and level. */\n+\tuint8_t\ttqm_ring7_pg_size_tqm_ring7_lvl;\n+\t/* TQM ring 7 PBL indirect levels. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_MASK UINT32_C(0xf)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_SFT 0\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 \\\n+\t\tUINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * PBL pointer points to PDE table with each entry pointing to PTE\n+\t * tables.\n+\t */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LAST \\\n+\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2\n+\t/* TQM ring 7 page size. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK UINT32_C(0xf0)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT 4\n+\t/* 4KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K \\\n+\t\t(UINT32_C(0x0) << 4)\n+\t/* 8KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K \\\n+\t\t(UINT32_C(0x1) << 4)\n+\t/* 64KB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t/* 2MB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M \\\n+\t\t(UINT32_C(0x3) << 4)\n+\t/* 8MB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M \\\n+\t\t(UINT32_C(0x4) << 4)\n+\t/* 1GB. */\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G \\\n+\t\t(UINT32_C(0x5) << 4)\n+\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST \\\n+\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G\n+\t/* TQM ring 0 page directory. */\n+\tuint64_t\ttqm_ring0_page_dir;\n+\t/* TQM ring 1 page directory. */\n+\tuint64_t\ttqm_ring1_page_dir;\n+\t/* TQM ring 2 page directory. */\n+\tuint64_t\ttqm_ring2_page_dir;\n+\t/* TQM ring 3 page directory. */\n+\tuint64_t\ttqm_ring3_page_dir;\n+\t/* TQM ring 4 page directory. */\n+\tuint64_t\ttqm_ring4_page_dir;\n+\t/* TQM ring 5 page directory. */\n+\tuint64_t\ttqm_ring5_page_dir;\n+\t/* TQM ring 6 page directory. */\n+\tuint64_t\ttqm_ring6_page_dir;\n+\t/* TQM ring 7 page directory. */\n+\tuint64_t\ttqm_ring7_page_dir;\n+\t/*\n+\t * Number of TQM ring 0 entries.\n+\t *\n+\t * TQM fastpath rings should be sized large enough to accommodate the\n+\t * maximum number of QPs (either L2 or RoCE, or both if shared)\n+\t * that can be enqueued to the TQM ring.\n+\t *\n+\t * Note that TQM ring sizes cannot be extended while the system is\n+\t * operational. If a PF driver needs to extend a TQM ring, it needs\n+\t * to delete the SQ and then reallocate it.\n+\t */\n+\tuint32_t\ttqm_ring0_num_entries;\n+\t/*\n+\t * Number of TQM ring 1 entries.\n+\t *\n+\t * TQM fastpath rings should be sized large enough to accommodate the\n+\t * maximum number of QPs (either L2 or RoCE, or both if shared)\n+\t * that can be enqueued to the TQM ring.\n+\t *\n+\t * Note that TQM ring sizes cannot be extended while the system is\n+\t * operational. If a PF driver needs to extend a TQM ring, it needs\n+\t * to delete the SQ and then reallocate it.\n+\t */\n+\tuint32_t\ttqm_ring1_num_entries;\n+\t/*\n+\t * Number of TQM ring 2 entries.\n+\t *\n+\t * TQM fastpath rings should be sized large enough to accommodate the\n+\t * maximum number of QPs (either L2 or RoCE, or both if shared)\n+\t * that can be enqueued to the TQM ring.\n+\t *\n+\t * Note that TQM ring sizes cannot be extended while the system is\n+\t * operational. If a PF driver needs to extend a TQM ring, it needs\n+\t * to delete the SQ and then reallocate it.\n+\t */\n+\tuint32_t\ttqm_ring2_num_entries;\n+\t/*\n+\t * Number of TQM ring 3 entries.\n+\t *\n+\t * TQM fastpath rings should be sized large enough to accommodate the\n+\t * maximum number of QPs (either L2 or RoCE, or both if shared)\n+\t * that can be enqueued to the TQM ring.\n+\t *\n+\t * Note that TQM ring sizes cannot be extended while the system is\n+\t * operational. If a PF driver needs to extend a TQM ring, it needs\n+\t * to delete the SQ and then reallocate it.\n+\t */\n+\tuint32_t\ttqm_ring3_num_entries;\n+\t/*\n+\t * Number of TQM ring 4 entries.\n+\t *\n+\t * TQM fastpath rings should be sized large enough to accommodate the\n+\t * maximum number of QPs (either L2 or RoCE, or both if shared)\n+\t * that can be enqueued to the TQM ring.\n+\t *\n+\t * Note that TQM ring sizes cannot be extended while the system is\n+\t * operational. If a PF driver needs to extend a TQM ring, it needs\n+\t * to delete the SQ and then reallocate it.\n+\t */\n+\tuint32_t\ttqm_ring4_num_entries;\n+\t/*\n+\t * Number of TQM ring 5 entries.\n+\t *\n+\t * TQM fastpath rings should be sized large enough to accommodate the\n+\t * maximum number of QPs (either L2 or RoCE, or both if shared)\n+\t * that can be enqueued to the TQM ring.\n+\t *\n+\t * Note that TQM ring sizes cannot be extended while the system is\n+\t * operational. If a PF driver needs to extend a TQM ring, it needs\n+\t * to delete the SQ and then reallocate it.\n+\t */\n+\tuint32_t\ttqm_ring5_num_entries;\n+\t/*\n+\t * Number of TQM ring 6 entries.\n+\t *\n+\t * TQM fastpath rings should be sized large enough to accommodate the\n+\t * maximum number of QPs (either L2 or RoCE, or both if shared)\n+\t * that can be enqueued to the TQM ring.\n+\t *\n+\t * Note that TQM ring sizes cannot be extended while the system is\n+\t * operational. If a PF driver needs to extend a TQM ring, it needs\n+\t * to delete the SQ and then reallocate it.\n+\t */\n+\tuint32_t\ttqm_ring6_num_entries;\n+\t/*\n+\t * Number of TQM ring 7 entries.\n+\t *\n+\t * TQM fastpath rings should be sized large enough to accommodate the\n+\t * maximum number of QPs (either L2 or RoCE, or both if shared)\n+\t * that can be enqueued to the TQM ring.\n+\t *\n+\t * Note that TQM ring sizes cannot be extended while the system is\n+\t * operational. If a PF driver needs to extend a TQM ring, it needs\n+\t * to delete the SQ and then reallocate it.\n+\t */\n+\tuint32_t\ttqm_ring7_num_entries;\n+\t/* Number of bytes that have been allocated for each context entry. */\n+\tuint16_t\ttqm_entry_size;\n+\tuint8_t\tunused_0[6];\n+} __rte_packed;\n+\n+/* hwrm_ring_sq_alloc_output (size:128b/16B) */\n+struct hwrm_ring_sq_alloc_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * This is an identifier for the SQ to be used in other HWRM commands\n+\t * that need to reference this SQ. This value is greater than zero\n+\t * (i.e. a sq_id of zero references the default SQ).\n+\t */\n+\tuint16_t\tsq_id;\n+\tuint8_t\tunused_0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/********************\n+ * hwrm_ring_sq_cfg *\n+ ********************/\n+\n+\n+/* hwrm_ring_sq_cfg_input (size:768b/96B) */\n+struct hwrm_ring_sq_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Identifies the SQ being configured. A sq_id of zero refers to the\n+\t * default SQ.\n+\t */\n+\tuint16_t\tsq_id;\n+\t/*\n+\t * This field is an 8 bit bitmap that indicates which TCs are enabled\n+\t * in this SQ. Bit 0 represents traffic class 0 and bit 7 represents\n+\t * traffic class 7.\n+\t */\n+\tuint8_t\ttc_enabled;\n+\tuint8_t\tunused_0;\n+\tuint32_t\tflags;\n+\t/* The tc_max_bw array and the max_bw parameters are valid */\n+\t#define HWRM_RING_SQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED \\\n+\t\tUINT32_C(0x1)\n+\t/* The tc_min_bw array is valid */\n+\t#define HWRM_RING_SQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED \\\n+\t\tUINT32_C(0x2)\n+\t/* Maximum bandwidth of the traffic class, specified in Mbps. */\n+\tuint32_t\tmax_bw_tc0;\n+\t/* Maximum bandwidth of the traffic class, specified in Mbps. */\n+\tuint32_t\tmax_bw_tc1;\n+\t/* Maximum bandwidth of the traffic class, specified in Mbps. */\n+\tuint32_t\tmax_bw_tc2;\n+\t/* Maximum bandwidth of the traffic class, specified in Mbps. */\n+\tuint32_t\tmax_bw_tc3;\n+\t/* Maximum bandwidth of the traffic class, specified in Mbps. */\n+\tuint32_t\tmax_bw_tc4;\n+\t/* Maximum bandwidth of the traffic class, specified in Mbps. */\n+\tuint32_t\tmax_bw_tc5;\n+\t/* Maximum bandwidth of the traffic class, specified in Mbps. */\n+\tuint32_t\tmax_bw_tc6;\n+\t/* Maximum bandwidth of the traffic class, specified in Mbps. */\n+\tuint32_t\tmax_bw_tc7;\n+\t/*\n+\t * Bandwidth reservation for the traffic class, specified in Mbps.\n+\t * A value of zero signifies that traffic belonging to this class\n+\t * shares the bandwidth reservation for the same traffic class of\n+\t * the default SQ.\n+\t */\n+\tuint32_t\tmin_bw_tc0;\n+\t/*\n+\t * Bandwidth reservation for the traffic class, specified in Mbps.\n+\t * A value of zero signifies that traffic belonging to this class\n+\t * shares the bandwidth reservation for the same traffic class of\n+\t * the default SQ.\n+\t */\n+\tuint32_t\tmin_bw_tc1;\n+\t/*\n+\t * Bandwidth reservation for the traffic class, specified in Mbps.\n+\t * A value of zero signifies that traffic belonging to this class\n+\t * shares the bandwidth reservation for the same traffic class of\n+\t * the default SQ.\n+\t */\n+\tuint32_t\tmin_bw_tc2;\n+\t/*\n+\t * Bandwidth reservation for the traffic class, specified in Mbps.\n+\t * A value of zero signifies that traffic belonging to this class\n+\t * shares the bandwidth reservation for the same traffic class of\n+\t * the default SQ.\n+\t */\n+\tuint32_t\tmin_bw_tc3;\n+\t/*\n+\t * Bandwidth reservation for the traffic class, specified in Mbps.\n+\t * A value of zero signifies that traffic belonging to this class\n+\t * shares the bandwidth reservation for the same traffic class of\n+\t * the default SQ.\n+\t */\n+\tuint32_t\tmin_bw_tc4;\n+\t/*\n+\t * Bandwidth reservation for the traffic class, specified in Mbps.\n+\t * A value of zero signifies that traffic belonging to this class\n+\t * shares the bandwidth reservation for the same traffic class of\n+\t * the default SQ.\n+\t */\n+\tuint32_t\tmin_bw_tc5;\n+\t/*\n+\t * Bandwidth reservation for the traffic class, specified in Mbps.\n+\t * A value of zero signifies that traffic belonging to this class\n+\t * shares the bandwidth reservation for the same traffic class of\n+\t * the default SQ.\n+\t */\n+\tuint32_t\tmin_bw_tc6;\n+\t/*\n+\t * Bandwidth reservation for the traffic class, specified in Mbps.\n+\t * A value of zero signifies that traffic belonging to this class\n+\t * shares the bandwidth reservation for the same traffic class of\n+\t * the default SQ.\n+\t */\n+\tuint32_t\tmin_bw_tc7;\n+\t/*\n+\t * Indicates the max bandwidth for all enabled traffic classes in\n+\t * this SQ, specified in Mbps.\n+\t */\n+\tuint32_t\tmax_bw;\n+\tuint8_t\tunused_1[4];\n+} __rte_packed;\n+\n+/* hwrm_ring_sq_cfg_output (size:128b/16B) */\n+struct hwrm_ring_sq_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/*********************\n+ * hwrm_ring_sq_free *\n+ *********************/\n+\n+\n+/* hwrm_ring_sq_free_input (size:192b/24B) */\n+struct hwrm_ring_sq_free_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Identifies the SQ being freed. */\n+\tuint16_t\tsq_id;\n+\tuint8_t\tunused_0[6];\n+} __rte_packed;\n+\n+/* hwrm_ring_sq_free_output (size:128b/16B) */\n+struct hwrm_ring_sq_free_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n /*\n * special reserved flow ID to identify per function default\n * flows for vSwitch offload\n@@ -37315,6 +38608,163 @@ struct hwrm_tf_tcam_free_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n+/**************************\n+ * hwrm_tf_global_cfg_set *\n+ **************************/\n+\n+\n+/* hwrm_tf_global_cfg_set_input (size:448b/56B) */\n+struct hwrm_tf_global_cfg_set_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint32_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX\n+\t/* Global Cfg type */\n+\tuint32_t\ttype;\n+\t/* Offset of the type */\n+\tuint32_t\toffset;\n+\t/* Size of the data to set in bytes */\n+\tuint16_t\tsize;\n+\t/* unused. */\n+\tuint8_t\tunused0[6];\n+\t/* Data to set */\n+\tuint8_t\tdata[16];\n+} __rte_packed;\n+\n+/* hwrm_tf_global_cfg_set_output (size:128b/16B) */\n+struct hwrm_tf_global_cfg_set_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written. When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/**************************\n+ * hwrm_tf_global_cfg_get *\n+ **************************/\n+\n+\n+/* hwrm_tf_global_cfg_get_input (size:320b/40B) */\n+struct hwrm_tf_global_cfg_get_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint32_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX\n+\t/* Global Cfg type */\n+\tuint32_t\ttype;\n+\t/* Offset of the type */\n+\tuint32_t\toffset;\n+\t/* Size of the data to set in bytes */\n+\tuint16_t\tsize;\n+\t/* unused. */\n+\tuint8_t\tunused0[6];\n+} __rte_packed;\n+\n+/* hwrm_tf_global_cfg_get_output (size:256b/32B) */\n+struct hwrm_tf_global_cfg_get_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Size of the data read in bytes */\n+\tuint16_t\tsize;\n+\t/* unused. */\n+\tuint8_t\tunused0[6];\n+\t/* Data to set */\n+\tuint8_t\tdata[16];\n+} __rte_packed;\n+\n /******************************\n * hwrm_tunnel_dst_port_query *\n ******************************/\n", "prefixes": [ "06/20" ] }