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GET /api/patches/72175/?format=api
{ "id": 72175, "url": "http://patches.dpdk.org/api/patches/72175/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1593091838-51869-3-git-send-email-matan@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1593091838-51869-3-git-send-email-matan@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1593091838-51869-3-git-send-email-matan@mellanox.com", "date": "2020-06-25T13:30:37", "name": "[v2,2/3] vdpa/mlx5: optimize completion queue poll", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d1d678d1bde9acf07a9c47d736583d8083d6058e", "submitter": { "id": 796, "url": "http://patches.dpdk.org/api/people/796/?format=api", "name": "Matan Azrad", "email": "matan@mellanox.com" }, "delegate": { "id": 2642, "url": "http://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1593091838-51869-3-git-send-email-matan@mellanox.com/mbox/", "series": [ { "id": 10616, "url": "http://patches.dpdk.org/api/series/10616/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=10616", "date": "2020-06-25T13:30:35", "name": "vdpa/mlx5: optimize cpu utilization", "version": 2, "mbox": "http://patches.dpdk.org/series/10616/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/72175/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/72175/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 13BB1A0350;\n\tThu, 25 Jun 2020 15:31:05 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 369C11B6B4;\n\tThu, 25 Jun 2020 15:30:56 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id D3BAAFEB\n for <dev@dpdk.org>; Thu, 25 Jun 2020 15:30:54 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n matan@mellanox.com) with SMTP; 25 Jun 2020 16:30:49 +0300", "from pegasus25.mtr.labs.mlnx. (pegasus25.mtr.labs.mlnx\n [10.210.16.10])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 05PDUeEB021446;\n Thu, 25 Jun 2020 16:30:49 +0300" ], "From": "Matan Azrad <matan@mellanox.com>", "To": "Maxime Coquelin <maxime.coquelin@redhat.com>", "Cc": "dev@dpdk.org, Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "Date": "Thu, 25 Jun 2020 13:30:37 +0000", "Message-Id": "<1593091838-51869-3-git-send-email-matan@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1593091838-51869-1-git-send-email-matan@mellanox.com>", "References": "<1592507476-442112-1-git-send-email-matan@mellanox.com>\n <1593091838-51869-1-git-send-email-matan@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v2 2/3] vdpa/mlx5: optimize completion queue poll", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The vDPA driver uses a CQ in order to know when traffic works were\ncompleted by the HW.\n\nEach traffic burst completion adds a CQE to the CQ.\n\nWhen the vDPA driver detects CQEs in the CQ, it triggers the guest\nnotification for the corresponding queue and consumes all of them.\n\nThere is collapse feature in the HW that configures the HW to write all the\nCQEs in the first entry of the CQ.\n\nUsing this feature, the vDPA driver can read only the first CQE,\nvalidate that the completion counter inside the CQE was changed and if\nso, to notify the guest.\n\nUse CQ collapse feature in order to improve the poll utilization.\n\nSigned-off-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/vdpa/mlx5/mlx5_vdpa_event.c | 73 ++++++++++++++++++++-----------------\n 1 file changed, 40 insertions(+), 33 deletions(-)", "diff": "diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c\nindex 69c8bf6..25f11fd 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c\n@@ -127,12 +127,12 @@\n \tstruct mlx5_devx_cq_attr attr;\n \tsize_t pgsize = sysconf(_SC_PAGESIZE);\n \tuint32_t umem_size;\n-\tint ret;\n \tuint16_t event_nums[1] = {0};\n+\tuint16_t cq_size = 1 << log_desc_n;\n+\tint ret;\n \n \tcq->log_desc_n = log_desc_n;\n-\tumem_size = sizeof(struct mlx5_cqe) * (1 << log_desc_n) +\n-\t\t\t\t\t\t\tsizeof(*cq->db_rec) * 2;\n+\tumem_size = sizeof(struct mlx5_cqe) * cq_size + sizeof(*cq->db_rec) * 2;\n \tcq->umem_buf = rte_zmalloc(__func__, umem_size, 4096);\n \tif (!cq->umem_buf) {\n \t\tDRV_LOG(ERR, \"Failed to allocate memory for CQ.\");\n@@ -149,13 +149,13 @@\n \t}\n \tattr.q_umem_valid = 1;\n \tattr.db_umem_valid = 1;\n-\tattr.use_first_only = 0;\n+\tattr.use_first_only = 1;\n \tattr.overrun_ignore = 0;\n \tattr.uar_page_id = priv->uar->page_id;\n \tattr.q_umem_id = cq->umem_obj->umem_id;\n \tattr.q_umem_offset = 0;\n \tattr.db_umem_id = cq->umem_obj->umem_id;\n-\tattr.db_umem_offset = sizeof(struct mlx5_cqe) * (1 << log_desc_n);\n+\tattr.db_umem_offset = sizeof(struct mlx5_cqe) * cq_size;\n \tattr.eqn = priv->eqn;\n \tattr.log_cq_size = log_desc_n;\n \tattr.log_page_size = rte_log2_u32(pgsize);\n@@ -187,7 +187,8 @@\n \t}\n \tcq->callfd = callfd;\n \t/* Init CQ to ones to be in HW owner in the start. */\n-\tmemset((void *)(uintptr_t)cq->umem_buf, 0xFF, attr.db_umem_offset);\n+\tcq->cqes[0].op_own = MLX5_CQE_OWNER_MASK;\n+\tcq->cqes[0].wqe_counter = rte_cpu_to_be_16(cq_size - 1);\n \t/* First arming. */\n \tmlx5_vdpa_cq_arm(priv, cq);\n \treturn 0;\n@@ -203,34 +204,40 @@\n \t\t\t\tcontainer_of(cq, struct mlx5_vdpa_event_qp, cq);\n \tconst unsigned int cq_size = 1 << cq->log_desc_n;\n \tconst unsigned int cq_mask = cq_size - 1;\n-\tuint32_t total = 0;\n-\tint ret;\n-\n-\tdo {\n-\t\tvolatile struct mlx5_cqe *cqe = cq->cqes + ((cq->cq_ci + total)\n-\t\t\t\t\t\t\t & cq_mask);\n-\n-\t\tret = check_cqe(cqe, cq_size, cq->cq_ci + total);\n-\t\tswitch (ret) {\n-\t\tcase MLX5_CQE_STATUS_ERR:\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint16_t wqe_counter;\n+\t\t\tuint8_t rsvd5;\n+\t\t\tuint8_t op_own;\n+\t\t};\n+\t\tuint32_t word;\n+\t} last_word;\n+\tuint16_t next_wqe_counter = cq->cq_ci & cq_mask;\n+\tuint16_t cur_wqe_counter;\n+\tuint16_t comp;\n+\n+\tlast_word.word = rte_read32(&cq->cqes[0].wqe_counter);\n+\tcur_wqe_counter = rte_be_to_cpu_16(last_word.wqe_counter);\n+\tcomp = (cur_wqe_counter + 1u - next_wqe_counter) & cq_mask;\n+\tif (comp) {\n+\t\tcq->cq_ci += comp;\n+\t\tMLX5_ASSERT(!!(cq->cq_ci & cq_size) ==\n+\t\t\t MLX5_CQE_OWNER(last_word.op_own));\n+\t\tMLX5_ASSERT(MLX5_CQE_OPCODE(last_word.op_own) !=\n+\t\t\t MLX5_CQE_INVALID);\n+\t\tif (unlikely(!(MLX5_CQE_OPCODE(last_word.op_own) ==\n+\t\t\t MLX5_CQE_RESP_ERR ||\n+\t\t\t MLX5_CQE_OPCODE(last_word.op_own) ==\n+\t\t\t MLX5_CQE_REQ_ERR)))\n \t\t\tcq->errors++;\n-\t\t\t/*fall-through*/\n-\t\tcase MLX5_CQE_STATUS_SW_OWN:\n-\t\t\ttotal++;\n-\t\t\tbreak;\n-\t\tcase MLX5_CQE_STATUS_HW_OWN:\n-\t\tdefault:\n-\t\t\tbreak;\n-\t\t}\n-\t} while (ret != MLX5_CQE_STATUS_HW_OWN);\n-\trte_io_wmb();\n-\tcq->cq_ci += total;\n-\t/* Ring CQ doorbell record. */\n-\tcq->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);\n-\trte_io_wmb();\n-\t/* Ring SW QP doorbell record. */\n-\teqp->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci + cq_size);\n-\treturn total;\n+\t\trte_io_wmb();\n+\t\t/* Ring CQ doorbell record. */\n+\t\tcq->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);\n+\t\trte_io_wmb();\n+\t\t/* Ring SW QP doorbell record. */\n+\t\teqp->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci + cq_size);\n+\t}\n+\treturn comp;\n }\n \n static void\n", "prefixes": [ "v2", "2/3" ] }