Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/71890/?format=api
{ "id": 71890, "url": "http://patches.dpdk.org/api/patches/71890/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200622064634.70941-24-guinanx.sun@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200622064634.70941-24-guinanx.sun@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200622064634.70941-24-guinanx.sun@intel.com", "date": "2020-06-22T06:45:47", "name": "[23/70] net/e1000/base: remove duplicated codes from 82575", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b898d0959ebbd29923eed62bfbbda3d6bf144aef", "submitter": { "id": 1476, "url": "http://patches.dpdk.org/api/people/1476/?format=api", "name": "Guinan Sun", "email": "guinanx.sun@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200622064634.70941-24-guinanx.sun@intel.com/mbox/", "series": [ { "id": 10543, "url": "http://patches.dpdk.org/api/series/10543/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=10543", "date": "2020-06-22T06:45:24", "name": "update e1000 base code", "version": 1, "mbox": "http://patches.dpdk.org/series/10543/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/71890/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/71890/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 593FAA0350;\n\tMon, 22 Jun 2020 09:09:32 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 544241D426;\n\tMon, 22 Jun 2020 09:06:01 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by dpdk.org (Postfix) with ESMTP id 753881D42B\n for <dev@dpdk.org>; Mon, 22 Jun 2020 09:05:59 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 22 Jun 2020 00:05:59 -0700", "from dpdk.sh.intel.com ([10.239.255.83])\n by fmsmga001.fm.intel.com with ESMTP; 22 Jun 2020 00:05:56 -0700" ], "IronPort-SDR": [ "\n 7YzFGQVecBCBhMOcNfgjsJK7MBg592EpvKxcybtCj/S+m/24dpLvYwjnyLvMgngybbDVJ3r7TN\n Qcm+2t0Aaofw==", "\n ewkoYZtAYyR13Z8EmGl9hNwfSK35SU5vt8qLKa1EaTc7/+kO5eP8vaRg2DL03oUtBSeddq6/fu\n V1B5OZoC4BTQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9659\"; a=\"141944803\"", "E=Sophos;i=\"5.75,266,1589266800\"; d=\"scan'208\";a=\"141944803\"", "E=Sophos;i=\"5.75,266,1589266800\"; d=\"scan'208\";a=\"384408915\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Guinan Sun <guinanx.sun@intel.com>", "To": "dev@dpdk.org", "Cc": "Jeff Guo <jia.guo@intel.com>, Zhao1 Wei <wei.zhao1@intel.com>,\n Guinan Sun <guinanx.sun@intel.com>,\n Jeff Kirsher <jeffrey.t.kirsher@intel.com>,\n Sasha Neftin <sasha.neftin@intel.com>", "Date": "Mon, 22 Jun 2020 06:45:47 +0000", "Message-Id": "<20200622064634.70941-24-guinanx.sun@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200622064634.70941-1-guinanx.sun@intel.com>", "References": "<20200622064634.70941-1-guinanx.sun@intel.com>", "Subject": "[dpdk-dev] [PATCH 23/70] net/e1000/base: remove duplicated codes\n\tfrom 82575", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "These files will improve e1000_82575 codes.\nRemove the code duplication from e1000_82575 files.\nRemove the licenses.\nClean family specific functions from base.\n\nSigned-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>\nSigned-off-by: Sasha Neftin <sasha.neftin@intel.com>\nSigned-off-by: Guinan Sun <guinanx.sun@intel.com>\n---\n drivers/net/e1000/Makefile | 1 +\n drivers/net/e1000/base/e1000_82575.c | 493 +++++++++------------------\n drivers/net/e1000/base/e1000_82575.h | 107 +-----\n drivers/net/e1000/base/e1000_base.c | 191 +++++++++++\n drivers/net/e1000/base/e1000_base.h | 127 +++++++\n drivers/net/e1000/base/e1000_hw.h | 1 +\n drivers/net/e1000/base/e1000_i210.c | 2 +-\n drivers/net/e1000/base/e1000_i225.c | 2 +-\n drivers/net/e1000/base/meson.build | 1 +\n drivers/net/e1000/igb_rxtx.c | 2 +-\n 10 files changed, 489 insertions(+), 438 deletions(-)\n create mode 100644 drivers/net/e1000/base/e1000_base.c\n create mode 100644 drivers/net/e1000/base/e1000_base.h", "diff": "diff --git a/drivers/net/e1000/Makefile b/drivers/net/e1000/Makefile\nindex 82e156ecb..b7f749454 100644\n--- a/drivers/net/e1000/Makefile\n+++ b/drivers/net/e1000/Makefile\n@@ -60,6 +60,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_82575.c\n SRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_i210.c\n SRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_i225.c\n SRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_api.c\n+SRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_base.c\n SRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_ich8lan.c\n SRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_logs.c\n SRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_mac.c\ndiff --git a/drivers/net/e1000/base/e1000_82575.c b/drivers/net/e1000/base/e1000_82575.c\nindex 49c065014..b392d1f2a 100644\n--- a/drivers/net/e1000/base/e1000_82575.c\n+++ b/drivers/net/e1000/base/e1000_82575.c\n@@ -18,8 +18,6 @@\n \n STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw);\n STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw);\n-STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw);\n-STATIC void e1000_release_phy_82575(struct e1000_hw *hw);\n STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);\n STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);\n STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw);\n@@ -31,6 +29,7 @@ STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);\n STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,\n \t\t\t\t\t u16 *data);\n STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw);\n+STATIC s32 e1000_init_hw_82575(struct e1000_hw *hw);\n STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw);\n STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,\n \t\t\t\t u32 offset, u16 *data);\n@@ -56,10 +55,8 @@ STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,\n STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw);\n STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);\n STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw);\n-STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw);\n STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);\n STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);\n-STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);\n STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);\n STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);\n STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);\n@@ -128,8 +125,8 @@ STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)\n }\n \n /**\n- * e1000_init_phy_params_82575 - Init PHY func ptrs.\n- * @hw: pointer to the HW structure\n+ * e1000_init_phy_params_82575 - Initialize PHY function ptrs\n+ * @hw: pointer to the HW structure\n **/\n STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)\n {\n@@ -147,17 +144,17 @@ STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)\n \t\tgoto out;\n \t}\n \n-\tphy->ops.power_up = e1000_power_up_phy_copper;\n-\tphy->ops.power_down = e1000_power_down_phy_copper_82575;\n+\tphy->ops.power_up\t= e1000_power_up_phy_copper;\n+\tphy->ops.power_down\t= e1000_power_down_phy_copper_base;\n \n \tphy->autoneg_mask\t= AUTONEG_ADVERTISE_SPEED_DEFAULT;\n \tphy->reset_delay_us\t= 100;\n \n-\tphy->ops.acquire\t= e1000_acquire_phy_82575;\n+\tphy->ops.acquire\t= e1000_acquire_phy_base;\n \tphy->ops.check_reset_block = e1000_check_reset_block_generic;\n \tphy->ops.commit\t\t= e1000_phy_sw_reset_generic;\n \tphy->ops.get_cfg_done\t= e1000_get_cfg_done_82575;\n-\tphy->ops.release\t= e1000_release_phy_82575;\n+\tphy->ops.release\t= e1000_release_phy_base;\n \n \tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n \n@@ -204,76 +201,38 @@ STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)\n \tcase I347AT4_E_PHY_ID:\n \tcase M88E1112_E_PHY_ID:\n \tcase M88E1340M_E_PHY_ID:\n+\t\tphy->type\t\t= e1000_phy_m88;\n+\t\tphy->ops.check_polarity\t= e1000_check_polarity_m88;\n+\t\tphy->ops.get_info\t= e1000_get_phy_info_m88;\n+\t\tphy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;\n+\t\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;\n+\t\tbreak;\n \tcase M88E1111_I_PHY_ID:\n \t\tphy->type\t\t= e1000_phy_m88;\n \t\tphy->ops.check_polarity\t= e1000_check_polarity_m88;\n \t\tphy->ops.get_info\t= e1000_get_phy_info_m88;\n-\t\tif (phy->id == I347AT4_E_PHY_ID ||\n-\t\t phy->id == M88E1112_E_PHY_ID ||\n-\t\t phy->id == M88E1340M_E_PHY_ID)\n-\t\t\tphy->ops.get_cable_length =\n-\t\t\t\t\t e1000_get_cable_length_m88_gen2;\n-\t\telse if (phy->id == M88E1543_E_PHY_ID ||\n-\t\t\t phy->id == M88E1512_E_PHY_ID)\n-\t\t\tphy->ops.get_cable_length =\n-\t\t\t\t\t e1000_get_cable_length_m88_gen2;\n-\t\telse\n-\t\t\tphy->ops.get_cable_length = e1000_get_cable_length_m88;\n+\t\tphy->ops.get_cable_length = e1000_get_cable_length_m88;\n \t\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;\n-\t\t/* Check if this PHY is confgured for media swap. */\n-\t\tif (phy->id == M88E1112_E_PHY_ID) {\n-\t\t\tu16 data;\n-\n-\t\t\tret_val = phy->ops.write_reg(hw,\n-\t\t\t\t\t\t E1000_M88E1112_PAGE_ADDR,\n-\t\t\t\t\t\t 2);\n-\t\t\tif (ret_val)\n-\t\t\t\tgoto out;\n-\n-\t\t\tret_val = phy->ops.read_reg(hw,\n-\t\t\t\t\t\t E1000_M88E1112_MAC_CTRL_1,\n-\t\t\t\t\t\t &data);\n-\t\t\tif (ret_val)\n-\t\t\t\tgoto out;\n-\n-\t\t\tdata = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>\n-\t\t\t E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;\n-\t\t\tif (data == E1000_M88E1112_AUTO_COPPER_SGMII ||\n-\t\t\t data == E1000_M88E1112_AUTO_COPPER_BASEX)\n-\t\t\t\thw->mac.ops.check_for_link =\n-\t\t\t\t\t\te1000_check_for_link_media_swap;\n-\t\t}\n-\t\tif (phy->id == M88E1512_E_PHY_ID) {\n-\t\t\tret_val = e1000_initialize_M88E1512_phy(hw);\n-\t\t\tif (ret_val)\n-\t\t\t\tgoto out;\n-\t\t}\n-\t\tif (phy->id == M88E1543_E_PHY_ID) {\n-\t\t\tret_val = e1000_initialize_M88E1543_phy(hw);\n-\t\t\tif (ret_val)\n-\t\t\t\tgoto out;\n-\t\t}\n \t\tbreak;\n \tcase IGP03E1000_E_PHY_ID:\n \tcase IGP04E1000_E_PHY_ID:\n-\t\tphy->type = e1000_phy_igp_3;\n-\t\tphy->ops.check_polarity = e1000_check_polarity_igp;\n-\t\tphy->ops.get_info = e1000_get_phy_info_igp;\n+\t\tphy->type\t\t= e1000_phy_igp_3;\n+\t\tphy->ops.check_polarity\t= e1000_check_polarity_igp;\n+\t\tphy->ops.get_info\t= e1000_get_phy_info_igp;\n \t\tphy->ops.get_cable_length = e1000_get_cable_length_igp_2;\n-\t\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;\n \t\tphy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;\n \t\tphy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;\n+\t\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;\n \t\tbreak;\n \tcase I82580_I_PHY_ID:\n \tcase I350_I_PHY_ID:\n-\t\tphy->type = e1000_phy_82580;\n-\t\tphy->ops.check_polarity = e1000_check_polarity_82577;\n-\t\tphy->ops.force_speed_duplex =\n-\t\t\t\t\t e1000_phy_force_speed_duplex_82577;\n+\t\tphy->type\t\t= e1000_phy_82580;\n+\t\tphy->ops.check_polarity\t= e1000_check_polarity_82577;\n+\t\tphy->ops.get_info\t= e1000_get_phy_info_82577;\n \t\tphy->ops.get_cable_length = e1000_get_cable_length_82577;\n-\t\tphy->ops.get_info = e1000_get_phy_info_82577;\n \t\tphy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;\n \t\tphy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;\n+\t\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82577;\n \t\tbreak;\n \tcase I210_I_PHY_ID:\n \t\tphy->type\t\t= e1000_phy_i210;\n@@ -292,98 +251,50 @@ STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)\n \t\tgoto out;\n \t}\n \n-out:\n-\treturn ret_val;\n-}\n-\n-/**\n- * e1000_init_nvm_params_82575 - Init NVM func ptrs.\n- * @hw: pointer to the HW structure\n- **/\n-s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)\n-{\n-\tstruct e1000_nvm_info *nvm = &hw->nvm;\n-\tu32 eecd = E1000_READ_REG(hw, E1000_EECD);\n-\tu16 size;\n-\n-\tDEBUGFUNC(\"e1000_init_nvm_params_82575\");\n-\n-\tsize = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>\n-\t\t E1000_EECD_SIZE_EX_SHIFT);\n-\t/*\n-\t * Added to a constant, \"size\" becomes the left-shift value\n-\t * for setting word_size.\n-\t */\n-\tsize += NVM_WORD_SIZE_BASE_SHIFT;\n-\n-\t/* Just in case size is out of range, cap it to the largest\n-\t * EEPROM size supported\n-\t */\n-\tif (size > 15)\n-\t\tsize = 15;\n-\n-\tnvm->word_size = 1 << size;\n-\tif (hw->mac.type < e1000_i210) {\n-\t\tnvm->opcode_bits = 8;\n-\t\tnvm->delay_usec = 1;\n+\t/* Check if this PHY is configured for media swap. */\n+\tswitch (phy->id) {\n+\tcase M88E1112_E_PHY_ID:\n+\t{\n+\t\tu16 data;\n \n-\t\tswitch (nvm->override) {\n-\t\tcase e1000_nvm_override_spi_large:\n-\t\t\tnvm->page_size = 32;\n-\t\t\tnvm->address_bits = 16;\n-\t\t\tbreak;\n-\t\tcase e1000_nvm_override_spi_small:\n-\t\t\tnvm->page_size = 8;\n-\t\t\tnvm->address_bits = 8;\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tnvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;\n-\t\t\tnvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?\n-\t\t\t\t\t 16 : 8;\n-\t\t\tbreak;\n-\t\t}\n-\t\tif (nvm->word_size == (1 << 15))\n-\t\t\tnvm->page_size = 128;\n+\t\tret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 2);\n+\t\tif (ret_val)\n+\t\t\tgoto out;\n+\t\tret_val = phy->ops.read_reg(hw, E1000_M88E1112_MAC_CTRL_1,\n+\t\t\t\t\t &data);\n+\t\tif (ret_val)\n+\t\t\tgoto out;\n \n-\t\tnvm->type = e1000_nvm_eeprom_spi;\n-\t} else {\n-\t\tnvm->type = e1000_nvm_flash_hw;\n+\t\tdata = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>\n+\t\t\tE1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;\n+\t\tif (data == E1000_M88E1112_AUTO_COPPER_SGMII ||\n+\t\t data == E1000_M88E1112_AUTO_COPPER_BASEX)\n+\t\t\thw->mac.ops.check_for_link =\n+\t\t\t\t\t\te1000_check_for_link_media_swap;\n+\t\tbreak;\n \t}\n-\n-\t/* Function Pointers */\n-\tnvm->ops.acquire = e1000_acquire_nvm_82575;\n-\tnvm->ops.release = e1000_release_nvm_82575;\n-\tif (nvm->word_size < (1 << 15))\n-\t\tnvm->ops.read = e1000_read_nvm_eerd;\n-\telse\n-\t\tnvm->ops.read = e1000_read_nvm_spi;\n-\n-\tnvm->ops.write = e1000_write_nvm_spi;\n-\tnvm->ops.validate = e1000_validate_nvm_checksum_generic;\n-\tnvm->ops.update = e1000_update_nvm_checksum_generic;\n-\tnvm->ops.valid_led_default = e1000_valid_led_default_82575;\n-\n-\t/* override generic family function pointers for specific descendants */\n-\tswitch (hw->mac.type) {\n-\tcase e1000_82580:\n-\t\tnvm->ops.validate = e1000_validate_nvm_checksum_82580;\n-\t\tnvm->ops.update = e1000_update_nvm_checksum_82580;\n+\tcase M88E1512_E_PHY_ID:\n+\t{\n+\t\tret_val = e1000_initialize_M88E1512_phy(hw);\n \t\tbreak;\n-\tcase e1000_i350:\n-\tcase e1000_i354:\n-\t\tnvm->ops.validate = e1000_validate_nvm_checksum_i350;\n-\t\tnvm->ops.update = e1000_update_nvm_checksum_i350;\n+\t}\n+\tcase M88E1543_E_PHY_ID:\n+\t{\n+\t\tret_val = e1000_initialize_M88E1543_phy(hw);\n \t\tbreak;\n+\t}\n \tdefault:\n-\t\tbreak;\n+\t\tgoto out;\n \t}\n \n-\treturn E1000_SUCCESS;\n+out:\n+\treturn ret_val;\n }\n \n+\n /**\n- * e1000_init_mac_params_82575 - Init MAC func ptrs.\n- * @hw: pointer to the HW structure\n+ * e1000_init_mac_params_82575 - Initialize MAC function ptrs\n+ * @hw: pointer to the HW structure\n **/\n STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)\n {\n@@ -392,13 +303,16 @@ STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)\n \n \tDEBUGFUNC(\"e1000_init_mac_params_82575\");\n \n+\t/* Initialize function pointer */\n+\te1000_init_mac_ops_generic(hw);\n+\n \t/* Derives media type */\n \te1000_get_media_type_82575(hw);\n-\t/* Set mta register count */\n+\t/* Set MTA register count */\n \tmac->mta_reg_count = 128;\n-\t/* Set uta register count */\n+\t/* Set UTA register count */\n \tmac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;\n-\t/* Set rar entry count */\n+\t/* Set RAR entry count */\n \tmac->rar_entry_count = E1000_RAR_ENTRIES_82575;\n \tif (mac->type == e1000_82576)\n \t\tmac->rar_entry_count = E1000_RAR_ENTRIES_82576;\n@@ -432,16 +346,11 @@ STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)\n \t\tmac->ops.reset_hw = e1000_reset_hw_82580;\n \telse\n \t\tmac->ops.reset_hw = e1000_reset_hw_82575;\n-\t/* hw initialization */\n+\t/* HW initialization */\n \tif (mac->type == e1000_i210 || mac->type == e1000_i211)\n \t\tmac->ops.init_hw = e1000_init_hw_i210;\n \telse\n-#ifndef NO_I225_SUPPORT\n-\tif (mac->type == e1000_i225)\n-\t\tmac->ops.init_hw = e1000_init_hw_i225;\n-\telse\n-#endif /* NO_I225_SUPPORT */\n-\tmac->ops.init_hw = e1000_init_hw_82575;\n+\t\tmac->ops.init_hw = e1000_init_hw_82575;\n \t/* link setup */\n \tmac->ops.setup_link = e1000_setup_link_generic;\n \t/* physical interface link setup */\n@@ -473,7 +382,7 @@ STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)\n \t}\n \tif (hw->mac.type >= e1000_82580)\n \t\tmac->ops.validate_mdi_setting =\n-\t\t\t\te1000_validate_mdi_setting_crossover_generic;\n+\t\t\te1000_validate_mdi_setting_crossover_generic;\n \t/* ID LED init */\n \tmac->ops.id_led_init = e1000_id_led_init_generic;\n \t/* blink LED */\n@@ -491,18 +400,13 @@ STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)\n \tmac->ops.get_link_up_info = e1000_get_link_up_info_82575;\n \t/* acquire SW_FW sync */\n \tmac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;\n+\t/* release SW_FW sync */\n \tmac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;\n \tif (mac->type == e1000_i210 || mac->type == e1000_i211) {\n \t\tmac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;\n \t\tmac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;\n \t}\n-#ifndef NO_I225_SUPPORT\n-\tif (mac->type >= e1000_i225) {\n-\t\tmac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i225;\n-\t\tmac->ops.release_swfw_sync = e1000_release_swfw_sync_i225;\n-\t}\n \n-#endif /* NO_I225_SUPPORT */\n \t/* set lan id for port to determine which phy lock to use */\n \thw->mac.ops.set_lan_id(hw);\n \n@@ -510,63 +414,102 @@ STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)\n }\n \n /**\n- * e1000_init_function_pointers_82575 - Init func ptrs.\n- * @hw: pointer to the HW structure\n- *\n- * Called to initialize all function pointers and parameters.\n+ * e1000_init_nvm_params_82575 - Initialize NVM function ptrs\n+ * @hw: pointer to the HW structure\n **/\n-void e1000_init_function_pointers_82575(struct e1000_hw *hw)\n+s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)\n {\n-\tDEBUGFUNC(\"e1000_init_function_pointers_82575\");\n+\tstruct e1000_nvm_info *nvm = &hw->nvm;\n+\tu32 eecd = E1000_READ_REG(hw, E1000_EECD);\n+\tu16 size;\n \n-\thw->mac.ops.init_params = e1000_init_mac_params_82575;\n-\thw->nvm.ops.init_params = e1000_init_nvm_params_82575;\n-\thw->phy.ops.init_params = e1000_init_phy_params_82575;\n-\thw->mbx.ops.init_params = e1000_init_mbx_params_pf;\n-}\n+\tDEBUGFUNC(\"e1000_init_nvm_params_82575\");\n \n-/**\n- * e1000_acquire_phy_82575 - Acquire rights to access PHY\n- * @hw: pointer to the HW structure\n- *\n- * Acquire access rights to the correct PHY.\n- **/\n-STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)\n-{\n-\tu16 mask = E1000_SWFW_PHY0_SM;\n+\tsize = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>\n+\t\t E1000_EECD_SIZE_EX_SHIFT);\n+\t/* Added to a constant, \"size\" becomes the left-shift value\n+\t * for setting word_size.\n+\t */\n+\tsize += NVM_WORD_SIZE_BASE_SHIFT;\n+\n+\t/* Just in case size is out of range, cap it to the largest\n+\t * EEPROM size supported\n+\t */\n+\tif (size > 15)\n+\t\tsize = 15;\n \n-\tDEBUGFUNC(\"e1000_acquire_phy_82575\");\n+\tnvm->word_size = 1 << size;\n+\tif (hw->mac.type < e1000_i210) {\n+\t\tnvm->opcode_bits = 8;\n+\t\tnvm->delay_usec = 1;\n \n-\tif (hw->bus.func == E1000_FUNC_1)\n-\t\tmask = E1000_SWFW_PHY1_SM;\n-\telse if (hw->bus.func == E1000_FUNC_2)\n-\t\tmask = E1000_SWFW_PHY2_SM;\n-\telse if (hw->bus.func == E1000_FUNC_3)\n-\t\tmask = E1000_SWFW_PHY3_SM;\n+\t\tswitch (nvm->override) {\n+\t\tcase e1000_nvm_override_spi_large:\n+\t\t\tnvm->page_size = 32;\n+\t\t\tnvm->address_bits = 16;\n+\t\t\tbreak;\n+\t\tcase e1000_nvm_override_spi_small:\n+\t\t\tnvm->page_size = 8;\n+\t\t\tnvm->address_bits = 8;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tnvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;\n+\t\t\tnvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?\n+\t\t\t\t\t 16 : 8;\n+\t\t\tbreak;\n+\t\t}\n+\t\tif (nvm->word_size == (1 << 15))\n+\t\t\tnvm->page_size = 128;\n+\n+\t\tnvm->type = e1000_nvm_eeprom_spi;\n+\t} else {\n+\t\tnvm->type = e1000_nvm_flash_hw;\n+\t}\n+\n+\t/* Function Pointers */\n+\tnvm->ops.acquire = e1000_acquire_nvm_82575;\n+\tnvm->ops.release = e1000_release_nvm_82575;\n+\tif (nvm->word_size < (1 << 15))\n+\t\tnvm->ops.read = e1000_read_nvm_eerd;\n+\telse\n+\t\tnvm->ops.read = e1000_read_nvm_spi;\n+\n+\tnvm->ops.write = e1000_write_nvm_spi;\n+\tnvm->ops.validate = e1000_validate_nvm_checksum_generic;\n+\tnvm->ops.update = e1000_update_nvm_checksum_generic;\n+\tnvm->ops.valid_led_default = e1000_valid_led_default_82575;\n+\n+\t/* override generic family function pointers for specific descendants */\n+\tswitch (hw->mac.type) {\n+\tcase e1000_82580:\n+\t\tnvm->ops.validate = e1000_validate_nvm_checksum_82580;\n+\t\tnvm->ops.update = e1000_update_nvm_checksum_82580;\n+\t\tbreak;\n+\tcase e1000_i350:\n+\t\tnvm->ops.validate = e1000_validate_nvm_checksum_i350;\n+\t\tnvm->ops.update = e1000_update_nvm_checksum_i350;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n \n-\treturn hw->mac.ops.acquire_swfw_sync(hw, mask);\n+\treturn E1000_SUCCESS;\n }\n \n /**\n- * e1000_release_phy_82575 - Release rights to access PHY\n+ * e1000_init_function_pointers_82575 - Init func ptrs.\n * @hw: pointer to the HW structure\n *\n- * A wrapper to release access rights to the correct PHY.\n+ * Called to initialize all function pointers and parameters.\n **/\n-STATIC void e1000_release_phy_82575(struct e1000_hw *hw)\n+void e1000_init_function_pointers_82575(struct e1000_hw *hw)\n {\n-\tu16 mask = E1000_SWFW_PHY0_SM;\n-\n-\tDEBUGFUNC(\"e1000_release_phy_82575\");\n-\n-\tif (hw->bus.func == E1000_FUNC_1)\n-\t\tmask = E1000_SWFW_PHY1_SM;\n-\telse if (hw->bus.func == E1000_FUNC_2)\n-\t\tmask = E1000_SWFW_PHY2_SM;\n-\telse if (hw->bus.func == E1000_FUNC_3)\n-\t\tmask = E1000_SWFW_PHY3_SM;\n+\tDEBUGFUNC(\"e1000_init_function_pointers_82575\");\n \n-\thw->mac.ops.release_swfw_sync(hw, mask);\n+\thw->mac.ops.init_params = e1000_init_mac_params_82575;\n+\thw->nvm.ops.init_params = e1000_init_nvm_params_82575;\n+\thw->phy.ops.init_params = e1000_init_phy_params_82575;\n+\thw->mbx.ops.init_params = e1000_init_mbx_params_pf;\n }\n \n /**\n@@ -1467,16 +1410,15 @@ STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)\n }\n \n /**\n- * e1000_init_hw_82575 - Initialize hardware\n- * @hw: pointer to the HW structure\n+ * e1000_init_hw_82575 - Initialize hardware\n+ * @hw: pointer to the HW structure\n *\n- * This inits the hardware readying it for operation.\n+ * This inits the hardware readying it for operation.\n **/\n-s32 e1000_init_hw_82575(struct e1000_hw *hw)\n+STATIC s32 e1000_init_hw_82575(struct e1000_hw *hw)\n {\n \tstruct e1000_mac_info *mac = &hw->mac;\n \ts32 ret_val;\n-\tu16 i, rar_count = mac->rar_entry_count;\n \n \tDEBUGFUNC(\"e1000_init_hw_82575\");\n \n@@ -1491,27 +1433,12 @@ s32 e1000_init_hw_82575(struct e1000_hw *hw)\n \tDEBUGOUT(\"Initializing the IEEE VLAN\\n\");\n \tmac->ops.clear_vfta(hw);\n \n-\t/* Setup the receive address */\n-\te1000_init_rx_addrs_generic(hw, rar_count);\n-\n-\t/* Zero out the Multicast HASH table */\n-\tDEBUGOUT(\"Zeroing the MTA\\n\");\n-\tfor (i = 0; i < mac->mta_reg_count; i++)\n-\t\tE1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);\n-\n-\t/* Zero out the Unicast HASH table */\n-\tDEBUGOUT(\"Zeroing the UTA\\n\");\n-\tfor (i = 0; i < mac->uta_reg_count; i++)\n-\t\tE1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);\n-\n-\t/* Setup link and flow control */\n-\tret_val = mac->ops.setup_link(hw);\n+\tret_val = e1000_init_hw_base(hw);\n \n \t/* Set the default MTU size */\n \thw->dev_spec._82575.mtu = 1500;\n \n-\t/*\n-\t * Clear all of the statistics registers (clear on read). It is\n+\t/* Clear all of the statistics registers (clear on read). It is\n \t * important that we do this after we have tried to establish link\n \t * because the symbol error count will increment wildly if there\n \t * is no link.\n@@ -1520,7 +1447,6 @@ s32 e1000_init_hw_82575(struct e1000_hw *hw)\n \n \treturn ret_val;\n }\n-\n /**\n * e1000_setup_copper_link_82575 - Configure copper link settings\n * @hw: pointer to the HW structure\n@@ -1531,9 +1457,9 @@ s32 e1000_init_hw_82575(struct e1000_hw *hw)\n **/\n STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)\n {\n-\tu32 ctrl;\n-\ts32 ret_val;\n \tu32 phpm_reg;\n+\ts32 ret_val;\n+\tu32 ctrl;\n \n \tDEBUGFUNC(\"e1000_setup_copper_link_82575\");\n \n@@ -1572,14 +1498,21 @@ STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)\n \t}\n \tswitch (hw->phy.type) {\n \tcase e1000_phy_i210:\n+\t/* fall through */\n \tcase e1000_phy_m88:\n \t\tswitch (hw->phy.id) {\n \t\tcase I347AT4_E_PHY_ID:\n+\t\t/* fall through */\n \t\tcase M88E1112_E_PHY_ID:\n+\t\t/* fall through */\n \t\tcase M88E1340M_E_PHY_ID:\n+\t\t/* fall through */\n \t\tcase M88E1543_E_PHY_ID:\n+\t\t/* fall through */\n \t\tcase M88E1512_E_PHY_ID:\n+\t\t/* fall through */\n \t\tcase I210_I_PHY_ID:\n+\t\t/* fall through */\n \t\t\tret_val = e1000_copper_link_setup_m88_gen2(hw);\n \t\t\tbreak;\n \t\tdefault:\n@@ -1593,8 +1526,6 @@ STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)\n \tcase e1000_phy_82580:\n \t\tret_val = e1000_copper_link_setup_82577(hw);\n \t\tbreak;\n-\tcase e1000_phy_none:\n-\t\tbreak;\n \tdefault:\n \t\tret_val = -E1000_ERR_PHY;\n \t\tbreak;\n@@ -1956,7 +1887,7 @@ STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw)\n * Inits recommended HW defaults after a reset when there is no EEPROM\n * detected. This is only for the 82575.\n **/\n-STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw)\n+s32 e1000_reset_init_script_82575(struct e1000_hw *hw)\n {\n \tDEBUGFUNC(\"e1000_reset_init_script_82575\");\n \n@@ -2034,27 +1965,6 @@ STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)\n \tE1000_WRITE_FLUSH(hw);\n }\n \n-/**\n- * e1000_power_down_phy_copper_82575 - Remove link during PHY power down\n- * @hw: pointer to the HW structure\n- *\n- * In the case of a PHY power down to save power, or to turn off link during a\n- * driver unload, or wake on lan is not enabled, remove the link.\n- **/\n-STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)\n-{\n-\tstruct e1000_phy_info *phy = &hw->phy;\n-\n-\tif (!(phy->ops.check_reset_block))\n-\t\treturn;\n-\n-\t/* If the management interface is not enabled, then power down */\n-\tif (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))\n-\t\te1000_power_down_phy_copper(hw);\n-\n-\treturn;\n-}\n-\n /**\n * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters\n * @hw: pointer to the HW structure\n@@ -2120,85 +2030,6 @@ STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)\n \t\tE1000_READ_REG(hw, E1000_SCVPC);\n }\n \n-/**\n- * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable\n- * @hw: pointer to the HW structure\n- *\n- * After Rx enable, if manageability is enabled then there is likely some\n- * bad data at the start of the fifo and possibly in the DMA fifo. This\n- * function clears the fifos and flushes any packets that came in as rx was\n- * being enabled.\n- **/\n-void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)\n-{\n-\tu32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;\n-\tint i, ms_wait;\n-\n-\tDEBUGFUNC(\"e1000_rx_fifo_flush_82575\");\n-\n-\t/* disable IPv6 options as per hardware errata */\n-\trfctl = E1000_READ_REG(hw, E1000_RFCTL);\n-\trfctl |= E1000_RFCTL_IPV6_EX_DIS;\n-\tE1000_WRITE_REG(hw, E1000_RFCTL, rfctl);\n-\n-\tif (hw->mac.type != e1000_82575 ||\n-\t !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))\n-\t\treturn;\n-\n-\t/* Disable all Rx queues */\n-\tfor (i = 0; i < 4; i++) {\n-\t\trxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));\n-\t\tE1000_WRITE_REG(hw, E1000_RXDCTL(i),\n-\t\t\t\trxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);\n-\t}\n-\t/* Poll all queues to verify they have shut down */\n-\tfor (ms_wait = 0; ms_wait < 10; ms_wait++) {\n-\t\tmsec_delay(1);\n-\t\trx_enabled = 0;\n-\t\tfor (i = 0; i < 4; i++)\n-\t\t\trx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));\n-\t\tif (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))\n-\t\t\tbreak;\n-\t}\n-\n-\tif (ms_wait == 10)\n-\t\tDEBUGOUT(\"Queue disable timed out after 10ms\\n\");\n-\n-\t/* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all\n-\t * incoming packets are rejected. Set enable and wait 2ms so that\n-\t * any packet that was coming in as RCTL.EN was set is flushed\n-\t */\n-\tE1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);\n-\n-\trlpml = E1000_READ_REG(hw, E1000_RLPML);\n-\tE1000_WRITE_REG(hw, E1000_RLPML, 0);\n-\n-\trctl = E1000_READ_REG(hw, E1000_RCTL);\n-\ttemp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);\n-\ttemp_rctl |= E1000_RCTL_LPE;\n-\n-\tE1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);\n-\tE1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);\n-\tE1000_WRITE_FLUSH(hw);\n-\tmsec_delay(2);\n-\n-\t/* Enable Rx queues that were previously enabled and restore our\n-\t * previous state\n-\t */\n-\tfor (i = 0; i < 4; i++)\n-\t\tE1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);\n-\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n-\tE1000_WRITE_FLUSH(hw);\n-\n-\tE1000_WRITE_REG(hw, E1000_RLPML, rlpml);\n-\tE1000_WRITE_REG(hw, E1000_RFCTL, rfctl);\n-\n-\t/* Flush receive errors generated by workaround */\n-\tE1000_READ_REG(hw, E1000_ROC);\n-\tE1000_READ_REG(hw, E1000_RNBC);\n-\tE1000_READ_REG(hw, E1000_MPC);\n-}\n-\n /**\n * e1000_set_pcie_completion_timeout - set pci-e completion timeout\n * @hw: pointer to the HW structure\ndiff --git a/drivers/net/e1000/base/e1000_82575.h b/drivers/net/e1000/base/e1000_82575.h\nindex 52dd7a9a1..25fc20ba8 100644\n--- a/drivers/net/e1000/base/e1000_82575.h\n+++ b/drivers/net/e1000/base/e1000_82575.h\n@@ -93,11 +93,8 @@ struct e1000_adv_context_desc {\n #endif\n \n /* SRRCTL bit definitions */\n-#define E1000_SRRCTL_BSIZEPKT_SHIFT\t\t10 /* Shift _right_ */\n #define E1000_SRRCTL_BSIZEHDRSIZE_MASK\t\t0x00000F00\n-#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT\t\t2 /* Shift _left_ */\n #define E1000_SRRCTL_DESCTYPE_LEGACY\t\t0x00000000\n-#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF\t0x02000000\n #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT\t\t0x04000000\n #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS\t0x0A000000\n #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION\t0x06000000\n@@ -160,38 +157,6 @@ struct e1000_adv_context_desc {\n #define E1000_IMIREXT_CTRL_FIN\t0x00040000 /* Check FIN bit in header */\n #define E1000_IMIREXT_CTRL_BP\t0x00080000 /* Bypass check of ctrl bits */\n \n-/* Receive Descriptor - Advanced */\n-union e1000_adv_rx_desc {\n-\tstruct {\n-\t\t__le64 pkt_addr; /* Packet buffer address */\n-\t\t__le64 hdr_addr; /* Header buffer address */\n-\t} read;\n-\tstruct {\n-\t\tstruct {\n-\t\t\tunion {\n-\t\t\t\t__le32 data;\n-\t\t\t\tstruct {\n-\t\t\t\t\t__le16 pkt_info; /*RSS type, Pkt type*/\n-\t\t\t\t\t/* Split Header, header buffer len */\n-\t\t\t\t\t__le16 hdr_info;\n-\t\t\t\t} hs_rss;\n-\t\t\t} lo_dword;\n-\t\t\tunion {\n-\t\t\t\t__le32 rss; /* RSS Hash */\n-\t\t\t\tstruct {\n-\t\t\t\t\t__le16 ip_id; /* IP id */\n-\t\t\t\t\t__le16 csum; /* Packet Checksum */\n-\t\t\t\t} csum_ip;\n-\t\t\t} hi_dword;\n-\t\t} lower;\n-\t\tstruct {\n-\t\t\t__le32 status_error; /* ext status/error */\n-\t\t\t__le16 length; /* Packet length */\n-\t\t\t__le16 vlan; /* VLAN tag */\n-\t\t} upper;\n-\t} wb; /* writeback */\n-};\n-\n #define E1000_RXDADV_RSSTYPE_MASK\t0x0000000F\n #define E1000_RXDADV_RSSTYPE_SHIFT\t12\n #define E1000_RXDADV_HDRBUFLEN_MASK\t0x7FE0\n@@ -248,77 +213,10 @@ union e1000_adv_rx_desc {\n #define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH\t\t0x10000000\n #define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED\t0x18000000\n \n-/* Transmit Descriptor - Advanced */\n-union e1000_adv_tx_desc {\n-\tstruct {\n-\t\t__le64 buffer_addr; /* Address of descriptor's data buf */\n-\t\t__le32 cmd_type_len;\n-\t\t__le32 olinfo_status;\n-\t} read;\n-\tstruct {\n-\t\t__le64 rsvd; /* Reserved */\n-\t\t__le32 nxtseq_seed;\n-\t\t__le32 status;\n-\t} wb;\n-};\n-\n-/* Adv Transmit Descriptor Config Masks */\n-#define E1000_ADVTXD_DTYP_CTXT\t0x00200000 /* Advanced Context Descriptor */\n-#define E1000_ADVTXD_DTYP_DATA\t0x00300000 /* Advanced Data Descriptor */\n-#define E1000_ADVTXD_DCMD_EOP\t0x01000000 /* End of Packet */\n-#define E1000_ADVTXD_DCMD_IFCS\t0x02000000 /* Insert FCS (Ethernet CRC) */\n-#define E1000_ADVTXD_DCMD_RS\t0x08000000 /* Report Status */\n-#define E1000_ADVTXD_DCMD_DDTYP_ISCSI\t0x10000000 /* DDP hdr type or iSCSI */\n-#define E1000_ADVTXD_DCMD_DEXT\t0x20000000 /* Descriptor extension (1=Adv) */\n-#define E1000_ADVTXD_DCMD_VLE\t0x40000000 /* VLAN pkt enable */\n-#define E1000_ADVTXD_DCMD_TSE\t0x80000000 /* TCP Seg enable */\n-#define E1000_ADVTXD_MAC_LINKSEC\t0x00040000 /* Apply LinkSec on pkt */\n-#define E1000_ADVTXD_MAC_TSTAMP\t\t0x00080000 /* IEEE1588 Timestamp pkt */\n-#define E1000_ADVTXD_STAT_SN_CRC\t0x00000002 /* NXTSEQ/SEED prsnt in WB */\n-#define E1000_ADVTXD_IDX_SHIFT\t\t4 /* Adv desc Index shift */\n-#define E1000_ADVTXD_POPTS_ISCO_1ST\t0x00000000 /* 1st TSO of iSCSI PDU */\n-#define E1000_ADVTXD_POPTS_ISCO_MDL\t0x00000800 /* Middle TSO of iSCSI PDU */\n-#define E1000_ADVTXD_POPTS_ISCO_LAST\t0x00001000 /* Last TSO of iSCSI PDU */\n-/* 1st & Last TSO-full iSCSI PDU*/\n-#define E1000_ADVTXD_POPTS_ISCO_FULL\t0x00001800\n-#define E1000_ADVTXD_POPTS_IPSEC\t0x00000400 /* IPSec offload request */\n-#define E1000_ADVTXD_PAYLEN_SHIFT\t14 /* Adv desc PAYLEN shift */\n-\n-/* Context descriptors */\n-struct e1000_adv_tx_context_desc {\n-\t__le32 vlan_macip_lens;\n-\t__le32 seqnum_seed;\n-\t__le32 type_tucmd_mlhl;\n-\t__le32 mss_l4len_idx;\n-};\n-\n-#define E1000_ADVTXD_MACLEN_SHIFT\t9 /* Adv ctxt desc mac len shift */\n-#define E1000_ADVTXD_VLAN_SHIFT\t\t16 /* Adv ctxt vlan tag shift */\n-#define E1000_ADVTXD_TUCMD_IPV4\t\t0x00000400 /* IP Packet Type: 1=IPv4 */\n-#define E1000_ADVTXD_TUCMD_IPV6\t\t0x00000000 /* IP Packet Type: 0=IPv6 */\n-#define E1000_ADVTXD_TUCMD_L4T_UDP\t0x00000000 /* L4 Packet TYPE of UDP */\n-#define E1000_ADVTXD_TUCMD_L4T_TCP\t0x00000800 /* L4 Packet TYPE of TCP */\n-#define E1000_ADVTXD_TUCMD_L4T_SCTP\t0x00001000 /* L4 Packet TYPE of SCTP */\n-#define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP\t0x00002000 /* IPSec Type ESP */\n-/* IPSec Encrypt Enable for ESP */\n-#define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN\t0x00004000\n-/* Req requires Markers and CRC */\n-#define E1000_ADVTXD_TUCMD_MKRREQ\t0x00002000\n-#define E1000_ADVTXD_L4LEN_SHIFT\t8 /* Adv ctxt L4LEN shift */\n-#define E1000_ADVTXD_MSS_SHIFT\t\t16 /* Adv ctxt MSS shift */\n-/* Adv ctxt IPSec SA IDX mask */\n-#define E1000_ADVTXD_IPSEC_SA_INDEX_MASK\t0x000000FF\n-/* Adv ctxt IPSec ESP len mask */\n-#define E1000_ADVTXD_IPSEC_ESP_LEN_MASK\t\t0x000000FF\n-\n-/* Additional Transmit Descriptor Control definitions */\n-#define E1000_TXDCTL_QUEUE_ENABLE\t0x02000000 /* Ena specific Tx Queue */\n #define E1000_TXDCTL_SWFLSH\t\t0x04000000 /* Tx Desc. wbk flushing */\n /* Tx Queue Arbitration Priority 0=low, 1=high */\n #define E1000_TXDCTL_PRIORITY\t\t0x08000000\n \n-/* Additional Receive Descriptor Control definitions */\n-#define E1000_RXDCTL_QUEUE_ENABLE\t0x02000000 /* Ena specific Rx Queue */\n #define E1000_RXDCTL_SWFLSH\t\t0x04000000 /* Rx Desc. wbk flushing */\n \n /* Direct Cache Access (DCA) definitions */\n@@ -444,13 +342,14 @@ struct e1000_adv_tx_context_desc {\n \n #define ALL_QUEUES\t\t0xFFFF\n \n+s32 e1000_reset_init_script_82575(struct e1000_hw *hw);\n+s32 e1000_init_nvm_params_82575(struct e1000_hw *hw);\n+\n /* Rx packet buffer size defines */\n #define E1000_RXPBS_SIZE_MASK_82576\t0x0000007F\n void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable);\n void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf);\n void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable);\n-s32 e1000_init_nvm_params_82575(struct e1000_hw *hw);\n-s32 e1000_init_hw_82575(struct e1000_hw *hw);\n \n enum e1000_promisc_type {\n \te1000_promisc_disabled = 0, /* all promisc modes disabled */\ndiff --git a/drivers/net/e1000/base/e1000_base.c b/drivers/net/e1000/base/e1000_base.c\nnew file mode 100644\nindex 000000000..342735693\n--- /dev/null\n+++ b/drivers/net/e1000/base/e1000_base.c\n@@ -0,0 +1,191 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2020 Intel Corporation\n+ */\n+\n+#include \"e1000_hw.h\"\n+#include \"e1000_82575.h\"\n+#include \"e1000_i225.h\"\n+#include \"e1000_mac.h\"\n+#include \"e1000_base.h\"\n+#include \"e1000_manage.h\"\n+\n+/**\n+ * e1000_acquire_phy_base - Acquire rights to access PHY\n+ * @hw: pointer to the HW structure\n+ *\n+ * Acquire access rights to the correct PHY.\n+ **/\n+s32 e1000_acquire_phy_base(struct e1000_hw *hw)\n+{\n+\tu16 mask = E1000_SWFW_PHY0_SM;\n+\n+\tDEBUGFUNC(\"e1000_acquire_phy_base\");\n+\n+\tif (hw->bus.func == E1000_FUNC_1)\n+\t\tmask = E1000_SWFW_PHY1_SM;\n+\telse if (hw->bus.func == E1000_FUNC_2)\n+\t\tmask = E1000_SWFW_PHY2_SM;\n+\telse if (hw->bus.func == E1000_FUNC_3)\n+\t\tmask = E1000_SWFW_PHY3_SM;\n+\n+\treturn hw->mac.ops.acquire_swfw_sync(hw, mask);\n+}\n+\n+/**\n+ * e1000_release_phy_base - Release rights to access PHY\n+ * @hw: pointer to the HW structure\n+ *\n+ * A wrapper to release access rights to the correct PHY.\n+ **/\n+void e1000_release_phy_base(struct e1000_hw *hw)\n+{\n+\tu16 mask = E1000_SWFW_PHY0_SM;\n+\n+\tDEBUGFUNC(\"e1000_release_phy_base\");\n+\n+\tif (hw->bus.func == E1000_FUNC_1)\n+\t\tmask = E1000_SWFW_PHY1_SM;\n+\telse if (hw->bus.func == E1000_FUNC_2)\n+\t\tmask = E1000_SWFW_PHY2_SM;\n+\telse if (hw->bus.func == E1000_FUNC_3)\n+\t\tmask = E1000_SWFW_PHY3_SM;\n+\n+\thw->mac.ops.release_swfw_sync(hw, mask);\n+}\n+\n+/**\n+ * e1000_init_hw_base - Initialize hardware\n+ * @hw: pointer to the HW structure\n+ *\n+ * This inits the hardware readying it for operation.\n+ **/\n+s32 e1000_init_hw_base(struct e1000_hw *hw)\n+{\n+\tstruct e1000_mac_info *mac = &hw->mac;\n+\ts32 ret_val;\n+\tu16 i, rar_count = mac->rar_entry_count;\n+\n+\tDEBUGFUNC(\"e1000_init_hw_base\");\n+\n+\t/* Setup the receive address */\n+\te1000_init_rx_addrs_generic(hw, rar_count);\n+\n+\t/* Zero out the Multicast HASH table */\n+\tDEBUGOUT(\"Zeroing the MTA\\n\");\n+\tfor (i = 0; i < mac->mta_reg_count; i++)\n+\t\tE1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);\n+\n+\t/* Zero out the Unicast HASH table */\n+\tDEBUGOUT(\"Zeroing the UTA\\n\");\n+\tfor (i = 0; i < mac->uta_reg_count; i++)\n+\t\tE1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);\n+\n+\t/* Setup link and flow control */\n+\tret_val = mac->ops.setup_link(hw);\n+\t/*\n+\t * Clear all of the statistics registers (clear on read). It is\n+\t * important that we do this after we have tried to establish link\n+\t * because the symbol error count will increment wildly if there\n+\t * is no link.\n+\t */\n+\te1000_clear_hw_cntrs_base_generic(hw);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ * e1000_power_down_phy_copper_base - Remove link during PHY power down\n+ * @hw: pointer to the HW structure\n+ *\n+ * In the case of a PHY power down to save power, or to turn off link during a\n+ * driver unload, or wake on lan is not enabled, remove the link.\n+ **/\n+void e1000_power_down_phy_copper_base(struct e1000_hw *hw)\n+{\n+\tstruct e1000_phy_info *phy = &hw->phy;\n+\n+\tif (!(phy->ops.check_reset_block))\n+\t\treturn;\n+\n+\t/* If the management interface is not enabled, then power down */\n+\tif (phy->ops.check_reset_block(hw))\n+\t\te1000_power_down_phy_copper(hw);\n+}\n+\n+/**\n+ * e1000_rx_fifo_flush_base - Clean Rx FIFO after Rx enable\n+ * @hw: pointer to the HW structure\n+ *\n+ * After Rx enable, if manageability is enabled then there is likely some\n+ * bad data at the start of the FIFO and possibly in the DMA FIFO. This\n+ * function clears the FIFOs and flushes any packets that came in as Rx was\n+ * being enabled.\n+ **/\n+void e1000_rx_fifo_flush_base(struct e1000_hw *hw)\n+{\n+\tu32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;\n+\tint i, ms_wait;\n+\n+\tDEBUGFUNC(\"e1000_rx_fifo_flush_base\");\n+\n+\t/* disable IPv6 options as per hardware errata */\n+\trfctl = E1000_READ_REG(hw, E1000_RFCTL);\n+\trfctl |= E1000_RFCTL_IPV6_EX_DIS;\n+\tE1000_WRITE_REG(hw, E1000_RFCTL, rfctl);\n+\n+\tif (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))\n+\t\treturn;\n+\n+\t/* Disable all Rx queues */\n+\tfor (i = 0; i < 4; i++) {\n+\t\trxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));\n+\t\tE1000_WRITE_REG(hw, E1000_RXDCTL(i),\n+\t\t\t\trxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);\n+\t}\n+\t/* Poll all queues to verify they have shut down */\n+\tfor (ms_wait = 0; ms_wait < 10; ms_wait++) {\n+\t\tmsec_delay(1);\n+\t\trx_enabled = 0;\n+\t\tfor (i = 0; i < 4; i++)\n+\t\t\trx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));\n+\t\tif (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))\n+\t\t\tbreak;\n+\t}\n+\n+\tif (ms_wait == 10)\n+\t\tDEBUGOUT(\"Queue disable timed out after 10ms\\n\");\n+\n+\t/* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all\n+\t * incoming packets are rejected. Set enable and wait 2ms so that\n+\t * any packet that was coming in as RCTL.EN was set is flushed\n+\t */\n+\tE1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);\n+\n+\trlpml = E1000_READ_REG(hw, E1000_RLPML);\n+\tE1000_WRITE_REG(hw, E1000_RLPML, 0);\n+\n+\trctl = E1000_READ_REG(hw, E1000_RCTL);\n+\ttemp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);\n+\ttemp_rctl |= E1000_RCTL_LPE;\n+\n+\tE1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);\n+\tE1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);\n+\tE1000_WRITE_FLUSH(hw);\n+\tmsec_delay(2);\n+\n+\t/* Enable Rx queues that were previously enabled and restore our\n+\t * previous state\n+\t */\n+\tfor (i = 0; i < 4; i++)\n+\t\tE1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);\n+\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n+\tE1000_WRITE_FLUSH(hw);\n+\n+\tE1000_WRITE_REG(hw, E1000_RLPML, rlpml);\n+\tE1000_WRITE_REG(hw, E1000_RFCTL, rfctl);\n+\n+\t/* Flush receive errors generated by workaround */\n+\tE1000_READ_REG(hw, E1000_ROC);\n+\tE1000_READ_REG(hw, E1000_RNBC);\n+\tE1000_READ_REG(hw, E1000_MPC);\n+}\ndiff --git a/drivers/net/e1000/base/e1000_base.h b/drivers/net/e1000/base/e1000_base.h\nnew file mode 100644\nindex 000000000..0d6172b6d\n--- /dev/null\n+++ b/drivers/net/e1000/base/e1000_base.h\n@@ -0,0 +1,127 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2020 Intel Corporation\n+ */\n+\n+#ifndef _E1000_BASE_H_\n+#define _E1000_BASE_H_\n+\n+/* forward declaration */\n+s32 e1000_init_hw_base(struct e1000_hw *hw);\n+void e1000_power_down_phy_copper_base(struct e1000_hw *hw);\n+extern void e1000_rx_fifo_flush_base(struct e1000_hw *hw);\n+s32 e1000_acquire_phy_base(struct e1000_hw *hw);\n+void e1000_release_phy_base(struct e1000_hw *hw);\n+\n+/* Transmit Descriptor - Advanced */\n+union e1000_adv_tx_desc {\n+\tstruct {\n+\t\t__le64 buffer_addr; /* Address of descriptor's data buf */\n+\t\t__le32 cmd_type_len;\n+\t\t__le32 olinfo_status;\n+\t} read;\n+\tstruct {\n+\t\t__le64 rsvd; /* Reserved */\n+\t\t__le32 nxtseq_seed;\n+\t\t__le32 status;\n+\t} wb;\n+};\n+\n+/* Context descriptors */\n+struct e1000_adv_tx_context_desc {\n+\t__le32 vlan_macip_lens;\n+\tunion {\n+\t\t__le32 launch_time;\n+\t\t__le32 seqnum_seed;\n+\t} u;\n+\t__le32 type_tucmd_mlhl;\n+\t__le32 mss_l4len_idx;\n+};\n+\n+/* Adv Transmit Descriptor Config Masks */\n+#define E1000_ADVTXD_DTYP_CTXT\t0x00200000 /* Advanced Context Descriptor */\n+#define E1000_ADVTXD_DTYP_DATA\t0x00300000 /* Advanced Data Descriptor */\n+#define E1000_ADVTXD_DCMD_EOP\t0x01000000 /* End of Packet */\n+#define E1000_ADVTXD_DCMD_IFCS\t0x02000000 /* Insert FCS (Ethernet CRC) */\n+#define E1000_ADVTXD_DCMD_RS\t0x08000000 /* Report Status */\n+#define E1000_ADVTXD_DCMD_DDTYP_ISCSI\t0x10000000 /* DDP hdr type or iSCSI */\n+#define E1000_ADVTXD_DCMD_DEXT\t0x20000000 /* Descriptor extension (1=Adv) */\n+#define E1000_ADVTXD_DCMD_VLE\t0x40000000 /* VLAN pkt enable */\n+#define E1000_ADVTXD_DCMD_TSE\t0x80000000 /* TCP Seg enable */\n+#define E1000_ADVTXD_MAC_LINKSEC\t0x00040000 /* Apply LinkSec on pkt */\n+#define E1000_ADVTXD_MAC_TSTAMP\t\t0x00080000 /* IEEE1588 Timestamp pkt */\n+#define E1000_ADVTXD_STAT_SN_CRC\t0x00000002 /* NXTSEQ/SEED prsnt in WB */\n+#define E1000_ADVTXD_IDX_SHIFT\t\t4 /* Adv desc Index shift */\n+#define E1000_ADVTXD_POPTS_ISCO_1ST\t0x00000000 /* 1st TSO of iSCSI PDU */\n+#define E1000_ADVTXD_POPTS_ISCO_MDL\t0x00000800 /* Middle TSO of iSCSI PDU */\n+#define E1000_ADVTXD_POPTS_ISCO_LAST\t0x00001000 /* Last TSO of iSCSI PDU */\n+/* 1st & Last TSO-full iSCSI PDU*/\n+#define E1000_ADVTXD_POPTS_ISCO_FULL\t0x00001800\n+#define E1000_ADVTXD_POPTS_IPSEC\t0x00000400 /* IPSec offload request */\n+#define E1000_ADVTXD_PAYLEN_SHIFT\t14 /* Adv desc PAYLEN shift */\n+\n+/* Advanced Transmit Context Descriptor Config */\n+#define E1000_ADVTXD_MACLEN_SHIFT\t9 /* Adv ctxt desc mac len shift */\n+#define E1000_ADVTXD_VLAN_SHIFT\t\t16 /* Adv ctxt vlan tag shift */\n+#define E1000_ADVTXD_TUCMD_IPV4\t\t0x00000400 /* IP Packet Type: 1=IPv4 */\n+#define E1000_ADVTXD_TUCMD_IPV6\t\t0x00000000 /* IP Packet Type: 0=IPv6 */\n+#define E1000_ADVTXD_TUCMD_L4T_UDP\t0x00000000 /* L4 Packet TYPE of UDP */\n+#define E1000_ADVTXD_TUCMD_L4T_TCP\t0x00000800 /* L4 Packet TYPE of TCP */\n+#define E1000_ADVTXD_TUCMD_L4T_SCTP\t0x00001000 /* L4 Packet TYPE of SCTP */\n+#define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP\t0x00002000 /* IPSec Type ESP */\n+/* IPSec Encrypt Enable for ESP */\n+#define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN\t0x00004000\n+/* Req requires Markers and CRC */\n+#define E1000_ADVTXD_TUCMD_MKRREQ\t0x00002000\n+#define E1000_ADVTXD_L4LEN_SHIFT\t8 /* Adv ctxt L4LEN shift */\n+#define E1000_ADVTXD_MSS_SHIFT\t\t16 /* Adv ctxt MSS shift */\n+/* Adv ctxt IPSec SA IDX mask */\n+#define E1000_ADVTXD_IPSEC_SA_INDEX_MASK\t0x000000FF\n+/* Adv ctxt IPSec ESP len mask */\n+#define E1000_ADVTXD_IPSEC_ESP_LEN_MASK\t\t0x000000FF\n+\n+#define E1000_RAR_ENTRIES_BASE\t\t16\n+\n+/* Receive Descriptor - Advanced */\n+union e1000_adv_rx_desc {\n+\tstruct {\n+\t\t__le64 pkt_addr; /* Packet buffer address */\n+\t\t__le64 hdr_addr; /* Header buffer address */\n+\t} read;\n+\tstruct {\n+\t\tstruct {\n+\t\t\tunion {\n+\t\t\t\t__le32 data;\n+\t\t\t\tstruct {\n+\t\t\t\t\t__le16 pkt_info; /*RSS type, Pkt type*/\n+\t\t\t\t\t/* Split Header, header buffer len */\n+\t\t\t\t\t__le16 hdr_info;\n+\t\t\t\t} hs_rss;\n+\t\t\t} lo_dword;\n+\t\t\tunion {\n+\t\t\t\t__le32 rss; /* RSS Hash */\n+\t\t\t\tstruct {\n+\t\t\t\t\t__le16 ip_id; /* IP id */\n+\t\t\t\t\t__le16 csum; /* Packet Checksum */\n+\t\t\t\t} csum_ip;\n+\t\t\t} hi_dword;\n+\t\t} lower;\n+\t\tstruct {\n+\t\t\t__le32 status_error; /* ext status/error */\n+\t\t\t__le16 length; /* Packet length */\n+\t\t\t__le16 vlan; /* VLAN tag */\n+\t\t} upper;\n+\t} wb; /* writeback */\n+};\n+\n+/* Additional Transmit Descriptor Control definitions */\n+#define E1000_TXDCTL_QUEUE_ENABLE\t0x02000000 /* Ena specific Tx Queue */\n+\n+/* Additional Receive Descriptor Control definitions */\n+#define E1000_RXDCTL_QUEUE_ENABLE\t0x02000000 /* Ena specific Rx Queue */\n+\n+/* SRRCTL bit definitions */\n+#define E1000_SRRCTL_BSIZEPKT_SHIFT\t\t10 /* Shift _right_ */\n+#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT\t\t2 /* Shift _left_ */\n+#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF\t0x02000000\n+\n+#endif /* _E1000_BASE_H_ */\ndiff --git a/drivers/net/e1000/base/e1000_hw.h b/drivers/net/e1000/base/e1000_hw.h\nindex 76b4dd5c1..848d21645 100644\n--- a/drivers/net/e1000/base/e1000_hw.h\n+++ b/drivers/net/e1000/base/e1000_hw.h\n@@ -1032,6 +1032,7 @@ struct e1000_hw {\n #include \"e1000_82575.h\"\n #include \"e1000_i210.h\"\n #include \"e1000_i225.h\"\n+#include \"e1000_base.h\"\n \n /* These functions must be implemented by drivers */\n void e1000_pci_clear_mwi(struct e1000_hw *hw);\ndiff --git a/drivers/net/e1000/base/e1000_i210.c b/drivers/net/e1000/base/e1000_i210.c\nindex c00161456..d4e4b527a 100644\n--- a/drivers/net/e1000/base/e1000_i210.c\n+++ b/drivers/net/e1000/base/e1000_i210.c\n@@ -936,6 +936,6 @@ s32 e1000_init_hw_i210(struct e1000_hw *hw)\n \t\t\treturn ret_val;\n \t}\n \thw->phy.ops.get_cfg_done = e1000_get_cfg_done_i210;\n-\tret_val = e1000_init_hw_82575(hw);\n+\tret_val = e1000_init_hw_base(hw);\n \treturn ret_val;\n }\ndiff --git a/drivers/net/e1000/base/e1000_i225.c b/drivers/net/e1000/base/e1000_i225.c\nindex 87ccf6d9c..505eff8f9 100644\n--- a/drivers/net/e1000/base/e1000_i225.c\n+++ b/drivers/net/e1000/base/e1000_i225.c\n@@ -1144,7 +1144,7 @@ s32 e1000_init_hw_i225(struct e1000_hw *hw)\n \t\t\treturn ret_val;\n \t}\n \thw->phy.ops.get_cfg_done = e1000_get_cfg_done_i225;\n-\tret_val = e1000_init_hw_82575(hw);\n+\tret_val = e1000_init_hw_base(hw);\n \treturn ret_val;\n }\n \ndiff --git a/drivers/net/e1000/base/meson.build b/drivers/net/e1000/base/meson.build\nindex d13c32033..f1ff51a04 100644\n--- a/drivers/net/e1000/base/meson.build\n+++ b/drivers/net/e1000/base/meson.build\n@@ -10,6 +10,7 @@ sources = [\n \t'e1000_82571.c',\n \t'e1000_82575.c',\n \t'e1000_api.c',\n+\t'e1000_base.c',\n \t'e1000_i210.c',\n \t'e1000_i225.c',\n \t'e1000_ich8lan.c',\ndiff --git a/drivers/net/e1000/igb_rxtx.c b/drivers/net/e1000/igb_rxtx.c\nindex 684fa4ad8..688320284 100644\n--- a/drivers/net/e1000/igb_rxtx.c\n+++ b/drivers/net/e1000/igb_rxtx.c\n@@ -320,7 +320,7 @@ igbe_set_xmit_ctx(struct igb_tx_queue* txq,\n \tvlan_macip_lens = (uint32_t)tx_offload.data;\n \tctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);\n \tctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);\n-\tctx_txd->seqnum_seed = 0;\n+\tctx_txd->u.seqnum_seed = 0;\n }\n \n /*\n", "prefixes": [ "23/70" ] }