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{
    "id": 71639,
    "url": "http://patches.dpdk.org/api/patches/71639/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1592312536-14106-1-git-send-email-anoobj@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1592312536-14106-1-git-send-email-anoobj@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1592312536-14106-1-git-send-email-anoobj@marvell.com",
    "date": "2020-06-16T13:02:15",
    "name": "[1/2] crypto/octeontx2: discover capabilities",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "e518996393ac331048514fa409f5f3dd08176b74",
    "submitter": {
        "id": 1205,
        "url": "http://patches.dpdk.org/api/people/1205/?format=api",
        "name": "Anoob Joseph",
        "email": "anoobj@marvell.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patches.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1592312536-14106-1-git-send-email-anoobj@marvell.com/mbox/",
    "series": [
        {
            "id": 10470,
            "url": "http://patches.dpdk.org/api/series/10470/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=10470",
            "date": "2020-06-16T13:02:16",
            "name": "[1/2] crypto/octeontx2: discover capabilities",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/10470/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/71639/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/71639/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
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        ],
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        "From": "Anoob Joseph <anoobj@marvell.com>",
        "To": "Akhil Goyal <akhil.goyal@nxp.com>, Radu Nicolau <radu.nicolau@intel.com>",
        "CC": "Tejasree Kondoj <ktejasree@marvell.com>, Narayana Prasad\n <pathreya@marvell.com>, Anoob Joseph <anoobj@marvell.com>, <dev@dpdk.org>",
        "Date": "Tue, 16 Jun 2020 18:32:15 +0530",
        "Message-ID": "<1592312536-14106-1-git-send-email-anoobj@marvell.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
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        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.216, 18.0.687\n definitions=2020-06-16_04:2020-06-16,\n 2020-06-16 signatures=0",
        "Subject": "[dpdk-dev] [PATCH 1/2] crypto/octeontx2: discover capabilities",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Tejasree Kondoj <ktejasree@marvell.com>\n\nPopulate capabilities based on device features.\n\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n drivers/common/octeontx2/otx2_mbox.h          |  33 +\n drivers/crypto/octeontx2/otx2_cryptodev.c     |   7 +\n drivers/crypto/octeontx2/otx2_cryptodev.h     |   2 +\n .../octeontx2/otx2_cryptodev_capabilities.c   | 562 ++++++++++--------\n .../octeontx2/otx2_cryptodev_capabilities.h   |  12 +-\n .../crypto/octeontx2/otx2_cryptodev_mbox.c    |  21 +\n .../crypto/octeontx2/otx2_cryptodev_mbox.h    |   3 +\n drivers/crypto/octeontx2/otx2_cryptodev_ops.c |   2 +-\n drivers/crypto/octeontx2/otx2_cryptodev_ops.h |   6 -\n 9 files changed, 390 insertions(+), 258 deletions(-)",
    "diff": "diff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h\nindex 7fa4276e9e..34b1d06632 100644\n--- a/drivers/common/octeontx2/otx2_mbox.h\n+++ b/drivers/common/octeontx2/otx2_mbox.h\n@@ -198,6 +198,7 @@ M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg,\t\t\t\\\n \t\t\t       cpt_inline_ipsec_cfg_msg, msg_rsp)\t\\\n M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg,\t\t\t\\\n \t\t\t       cpt_rx_inline_lf_cfg_msg, msg_rsp)\t\\\n+M(CPT_GET_CAPS,\t\t0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg)\t\\\n /* NPC mbox IDs (range 0x6000 - 0x7FFF) */\t\t\t\t\\\n M(NPC_MCAM_ALLOC_ENTRY,\t0x6000, npc_mcam_alloc_entry,\t\t\t\\\n \t\t\t\tnpc_mcam_alloc_entry_req,\t\t\\\n@@ -1258,6 +1259,38 @@ struct cpt_rx_inline_lf_cfg_msg {\n \tuint16_t __otx2_io sso_pf_func;\n };\n \n+enum cpt_eng_type {\n+\tCPT_ENG_TYPE_AE = 1,\n+\tCPT_ENG_TYPE_SE = 2,\n+\tCPT_ENG_TYPE_IE = 3,\n+\tCPT_MAX_ENG_TYPES,\n+};\n+\n+/* CPT HW capabilities */\n+union cpt_eng_caps {\n+\tuint64_t __otx2_io u;\n+\tstruct {\n+\t\tuint64_t __otx2_io reserved_0_4:5;\n+\t\tuint64_t __otx2_io mul:1;\n+\t\tuint64_t __otx2_io sha1_sha2:1;\n+\t\tuint64_t __otx2_io chacha20:1;\n+\t\tuint64_t __otx2_io zuc_snow3g:1;\n+\t\tuint64_t __otx2_io sha3:1;\n+\t\tuint64_t __otx2_io aes:1;\n+\t\tuint64_t __otx2_io kasumi:1;\n+\t\tuint64_t __otx2_io des:1;\n+\t\tuint64_t __otx2_io crc:1;\n+\t\tuint64_t __otx2_io reserved_14_63:50;\n+\t};\n+};\n+\n+struct cpt_caps_rsp_msg {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __otx2_io cpt_pf_drv_version;\n+\tuint8_t __otx2_io cpt_revision;\n+\tunion cpt_eng_caps eng_caps[CPT_MAX_ENG_TYPES];\n+};\n+\n /* NPC mbox message structs */\n \n #define NPC_MCAM_ENTRY_INVALID\t0xFFFF\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c\nindex 6ffbc2eb7c..77aa315dc0 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev.c\n@@ -14,6 +14,7 @@\n \n #include \"otx2_common.h\"\n #include \"otx2_cryptodev.h\"\n+#include \"otx2_cryptodev_capabilities.h\"\n #include \"otx2_cryptodev_mbox.h\"\n #include \"otx2_cryptodev_ops.h\"\n #include \"otx2_dev.h\"\n@@ -96,6 +97,12 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \n \tCPT_LOG_INFO(\"Max queues supported by device: %d\", vf->max_queues);\n \n+\tret = otx2_cpt_hardware_caps_get(dev, vf->hw_caps);\n+\tif (ret) {\n+\t\tCPT_LOG_ERR(\"Could not determine hardware capabilities\");\n+\t\tgoto otx2_dev_fini;\n+\t}\n+\n \tdev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |\n \t\t\t     RTE_CRYPTODEV_FF_HW_ACCELERATED |\n \t\t\t     RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h\nindex c0aa661b3b..e7a1730b22 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev.h\n@@ -29,6 +29,8 @@ struct otx2_cpt_vf {\n \t/**< MSI-X offsets */\n \tuint8_t err_intr_registered:1;\n \t/**< Are error interrupts registered? */\n+\tunion cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES];\n+\t/**< CPT device capabilities */\n };\n \n #define CPT_LOGTYPE otx2_cpt_logtype\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c\nindex 3eb3d8532c..9e18c4eee0 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c\n@@ -5,115 +5,87 @@\n #include <rte_cryptodev.h>\n \n #include \"otx2_cryptodev_capabilities.h\"\n+#include \"otx2_mbox.h\"\n \n-static const struct\n-rte_cryptodev_capabilities otx2_cpt_capabilities[] = {\n-\t/* Symmetric capabilities */\n-\t{\t/* NULL (AUTH) */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_NULL,\n-\t\t\t\t.block_size = 1,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 0,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 0,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t}, },\n-\t\t}, },\n-\t},\n-\t{\t/* AES GMAC (AUTH) */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_AES_GMAC,\n-\t\t\t\t.block_size = 16,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 32,\n-\t\t\t\t\t.increment = 8\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 8,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 4\n-\t\t\t\t},\n-\t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 12,\n-\t\t\t\t\t.max = 12,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t}\n-\t\t\t}, }\n+#define CPT_EGRP_GET(hw_caps, name, egrp) do {\t\\\n+\tif ((hw_caps[CPT_ENG_TYPE_SE].name) &&\t\\\n+\t    (hw_caps[CPT_ENG_TYPE_IE].name))\t\\\n+\t\t*egrp = OTX2_CPT_EGRP_SE_IE;\t\\\n+\telse if (hw_caps[CPT_ENG_TYPE_SE].name)\t\\\n+\t\t*egrp = OTX2_CPT_EGRP_SE;\t\\\n+\telse if (hw_caps[CPT_ENG_TYPE_AE].name)\t\\\n+\t\t*egrp = OTX2_CPT_EGRP_AE;\t\\\n+\telse\t\t\t\t\t\\\n+\t\t*egrp = OTX2_CPT_EGRP_MAX;\t\\\n+} while (0)\n+\n+#define CPT_CAPS_ADD(hw_caps, name) do {\t\t\t\t\\\n+\tenum otx2_cpt_egrp egrp;\t\t\t\t\t\\\n+\tCPT_EGRP_GET(hw_caps, name, &egrp);\t\t\t\t\\\n+\tif (egrp < OTX2_CPT_EGRP_MAX)\t\t\t\t\t\\\n+\t\tcpt_caps_add(caps_##name, RTE_DIM(caps_##name));\t\\\n+} while (0)\n+\n+#define OTX2_CPT_MAX_CAPS 34\n+\n+static struct rte_cryptodev_capabilities otx2_cpt_caps[OTX2_CPT_MAX_CAPS];\n+\n+static const struct rte_cryptodev_capabilities caps_mul[] = {\n+\t{\t/* RSA */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,\n+\t\t{.asym = {\n+\t\t\t.xform_capa = {\n+\t\t\t\t.xform_type = RTE_CRYPTO_ASYM_XFORM_RSA,\n+\t\t\t\t.op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |\n+\t\t\t\t\t(1 << RTE_CRYPTO_ASYM_OP_VERIFY) |\n+\t\t\t\t\t(1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) |\n+\t\t\t\t\t(1 << RTE_CRYPTO_ASYM_OP_DECRYPT)),\n+\t\t\t\t{.modlen = {\n+\t\t\t\t\t.min = 17,\n+\t\t\t\t\t.max = 1024,\n+\t\t\t\t\t.increment = 1\n+\t\t\t\t}, }\n+\t\t\t}\n \t\t}, }\n \t},\n-\t{\t/* KASUMI (F9) */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_KASUMI_F9,\n-\t\t\t\t.block_size = 8,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 4,\n-\t\t\t\t\t.max = 4,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t}, }\n+\t{\t/* MOD_EXP */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,\n+\t\t{.asym = {\n+\t\t\t.xform_capa = {\n+\t\t\t\t.xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX,\n+\t\t\t\t.op_types = 0,\n+\t\t\t\t{.modlen = {\n+\t\t\t\t\t.min = 17,\n+\t\t\t\t\t.max = 1024,\n+\t\t\t\t\t.increment = 1\n+\t\t\t\t}, }\n+\t\t\t}\n \t\t}, }\n \t},\n-\t{\t/* MD5 */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_MD5,\n-\t\t\t\t.block_size = 64,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 0,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t}, }\n-\t\t}, }\n+\t{\t/* ECDSA */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,\n+\t\t{.asym = {\n+\t\t\t.xform_capa = {\n+\t\t\t\t.xform_type = RTE_CRYPTO_ASYM_XFORM_ECDSA,\n+\t\t\t\t.op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |\n+\t\t\t\t\t(1 << RTE_CRYPTO_ASYM_OP_VERIFY)),\n+\t\t\t\t}\n+\t\t\t},\n+\t\t}\n \t},\n-\t{\t/* MD5 HMAC */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_MD5_HMAC,\n-\t\t\t\t.block_size = 64,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 8,\n-\t\t\t\t\t.max = 64,\n-\t\t\t\t\t.increment = 8\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t}, }\n-\t\t}, }\n+\t{\t/* ECPM */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,\n+\t\t{.asym = {\n+\t\t\t.xform_capa = {\n+\t\t\t\t.xform_type = RTE_CRYPTO_ASYM_XFORM_ECPM,\n+\t\t\t\t.op_types = 0\n+\t\t\t\t}\n+\t\t\t},\n+\t\t}\n \t},\n+};\n+\n+static const struct rte_cryptodev_capabilities caps_sha1_sha2[] = {\n \t{\t/* SHA1 */\n \t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n \t\t{.sym = {\n@@ -147,9 +119,9 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {\n \t\t\t\t\t.increment = 1\n \t\t\t\t},\n \t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 20,\n+\t\t\t\t\t.min = 12,\n \t\t\t\t\t.max = 20,\n-\t\t\t\t\t.increment = 0\n+\t\t\t\t\t.increment = 8\n \t\t\t\t},\n \t\t\t}, }\n \t\t}, }\n@@ -227,9 +199,9 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {\n \t\t\t\t\t.increment = 1\n \t\t\t\t},\n \t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 32,\n+\t\t\t\t\t.min = 16,\n \t\t\t\t\t.max = 32,\n-\t\t\t\t\t.increment = 0\n+\t\t\t\t\t.increment = 16\n \t\t\t\t},\n \t\t\t}, }\n \t\t}, }\n@@ -267,9 +239,9 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {\n \t\t\t\t\t.increment = 1\n \t\t\t\t},\n \t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 48,\n+\t\t\t\t\t.min = 24,\n \t\t\t\t\t.max = 48,\n-\t\t\t\t\t.increment = 0\n+\t\t\t\t\t.increment = 24\n \t\t\t\t\t},\n \t\t\t}, }\n \t\t}, }\n@@ -307,28 +279,66 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {\n \t\t\t\t\t.increment = 1\n \t\t\t\t},\n \t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 64,\n+\t\t\t\t\t.min = 32,\n \t\t\t\t\t.max = 64,\n-\t\t\t\t\t.increment = 0\n+\t\t\t\t\t.increment = 32\n \t\t\t\t},\n \t\t\t}, }\n \t\t}, }\n \t},\n-\t{\t/* SNOW 3G (UIA2) */\n+\t{\t/* MD5 */\n \t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n \t\t{.sym = {\n \t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n \t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,\n-\t\t\t\t.block_size = 16,\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_MD5,\n+\t\t\t\t.block_size = 64,\n \t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 0,\n+\t\t\t\t\t.max = 0,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.digest_size = {\n \t\t\t\t\t.min = 16,\n \t\t\t\t\t.max = 16,\n \t\t\t\t\t.increment = 0\n \t\t\t\t},\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{\t/* MD5 HMAC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_MD5_HMAC,\n+\t\t\t\t.block_size = 64,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 8,\n+\t\t\t\t\t.max = 64,\n+\t\t\t\t\t.increment = 8\n+\t\t\t\t},\n \t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 4,\n-\t\t\t\t\t.max = 4,\n+\t\t\t\t\t.min = 12,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 4\n+\t\t\t\t},\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+};\n+\n+static const struct rte_cryptodev_capabilities caps_zuc_snow3g[] = {\n+\t{\t/* SNOW 3G (UEA2) */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n \t\t\t\t\t.increment = 0\n \t\t\t\t},\n \t\t\t\t.iv_size = {\n@@ -339,23 +349,18 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {\n \t\t\t}, }\n \t\t}, }\n \t},\n-\t{\t/* ZUC (EIA3) */\n+\t{\t/* ZUC (EEA3) */\n \t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n \t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_ZUC_EIA3,\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_ZUC_EEA3,\n \t\t\t\t.block_size = 16,\n \t\t\t\t.key_size = {\n \t\t\t\t\t.min = 16,\n \t\t\t\t\t.max = 16,\n \t\t\t\t\t.increment = 0\n \t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 4,\n-\t\t\t\t\t.max = 4,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n \t\t\t\t.iv_size = {\n \t\t\t\t\t.min = 16,\n \t\t\t\t\t.max = 16,\n@@ -364,61 +369,79 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {\n \t\t\t}, }\n \t\t}, }\n \t},\n-\t{\t/* NULL (CIPHER) */\n+\t{\t/* SNOW 3G (UIA2) */\n \t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n \t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n-\t\t\t{.cipher = {\n-\t\t\t\t.algo = RTE_CRYPTO_CIPHER_NULL,\n-\t\t\t\t.block_size = 1,\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,\n+\t\t\t\t.block_size = 16,\n \t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 0,\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.digest_size = {\n+\t\t\t\t\t.min = 4,\n+\t\t\t\t\t.max = 4,\n \t\t\t\t\t.increment = 0\n \t\t\t\t},\n \t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 0,\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n \t\t\t\t\t.increment = 0\n \t\t\t\t}\n-\t\t\t}, },\n+\t\t\t}, }\n \t\t}, }\n \t},\n-\t{\t/* 3DES CBC */\n+\t{\t/* ZUC (EIA3) */\n \t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n \t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n-\t\t\t{.cipher = {\n-\t\t\t\t.algo = RTE_CRYPTO_CIPHER_3DES_CBC,\n-\t\t\t\t.block_size = 8,\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_ZUC_EIA3,\n+\t\t\t\t.block_size = 16,\n \t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 24,\n-\t\t\t\t\t.max = 24,\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.digest_size = {\n+\t\t\t\t\t.min = 4,\n+\t\t\t\t\t.max = 4,\n \t\t\t\t\t.increment = 0\n \t\t\t\t},\n \t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 8,\n+\t\t\t\t\t.min = 16,\n \t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 8\n+\t\t\t\t\t.increment = 0\n \t\t\t\t}\n \t\t\t}, }\n \t\t}, }\n \t},\n-\t{\t/* 3DES ECB */\n+};\n+\n+static const struct rte_cryptodev_capabilities caps_aes[] = {\n+\t{\t/* AES GMAC (AUTH) */\n \t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n \t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n-\t\t\t{.cipher = {\n-\t\t\t\t.algo = RTE_CRYPTO_CIPHER_3DES_ECB,\n-\t\t\t\t.block_size = 8,\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_AES_GMAC,\n+\t\t\t\t.block_size = 16,\n \t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 24,\n-\t\t\t\t\t.max = 24,\n-\t\t\t\t\t.increment = 0\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 32,\n+\t\t\t\t\t.increment = 8\n+\t\t\t\t},\n+\t\t\t\t.digest_size = {\n+\t\t\t\t\t.min = 8,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 4\n \t\t\t\t},\n \t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 0,\n+\t\t\t\t\t.min = 12,\n+\t\t\t\t\t.max = 12,\n \t\t\t\t\t.increment = 0\n \t\t\t\t}\n \t\t\t}, }\n@@ -484,26 +507,39 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {\n \t\t\t}, }\n \t\t}, }\n \t},\n-\t{\t/* DES CBC */\n+\t{\t/* AES GCM */\n \t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n \t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n-\t\t\t{.cipher = {\n-\t\t\t\t.algo = RTE_CRYPTO_CIPHER_DES_CBC,\n-\t\t\t\t.block_size = 8,\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,\n+\t\t\t{.aead = {\n+\t\t\t\t.algo = RTE_CRYPTO_AEAD_AES_GCM,\n+\t\t\t\t.block_size = 16,\n \t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 8,\n-\t\t\t\t\t.max = 8,\n-\t\t\t\t\t.increment = 0\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 32,\n+\t\t\t\t\t.increment = 8\n+\t\t\t\t},\n+\t\t\t\t.digest_size = {\n+\t\t\t\t\t.min = 4,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 1\n+\t\t\t\t},\n+\t\t\t\t.aad_size = {\n+\t\t\t\t\t.min = 0,\n+\t\t\t\t\t.max = 1024,\n+\t\t\t\t\t.increment = 1\n \t\t\t\t},\n \t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 8,\n-\t\t\t\t\t.max = 8,\n+\t\t\t\t\t.min = 12,\n+\t\t\t\t\t.max = 12,\n \t\t\t\t\t.increment = 0\n \t\t\t\t}\n \t\t\t}, }\n \t\t}, }\n \t},\n+};\n+\n+static const struct rte_cryptodev_capabilities caps_kasumi[] = {\n \t{\t/* KASUMI (F8) */\n \t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n \t\t{.sym = {\n@@ -524,137 +560,163 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {\n \t\t\t}, }\n \t\t}, }\n \t},\n-\t{\t/* SNOW 3G (UEA2) */\n+\t{\t/* KASUMI (F9) */\n \t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n \t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n-\t\t\t{.cipher = {\n-\t\t\t\t.algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,\n-\t\t\t\t.block_size = 16,\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_KASUMI_F9,\n+\t\t\t\t.block_size = 8,\n \t\t\t\t.key_size = {\n \t\t\t\t\t.min = 16,\n \t\t\t\t\t.max = 16,\n \t\t\t\t\t.increment = 0\n \t\t\t\t},\n+\t\t\t\t.digest_size = {\n+\t\t\t\t\t.min = 4,\n+\t\t\t\t\t.max = 4,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+};\n+\n+static const struct rte_cryptodev_capabilities caps_des[] = {\n+\t{\t/* 3DES CBC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_3DES_CBC,\n+\t\t\t\t.block_size = 8,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 24,\n+\t\t\t\t\t.max = 24,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n \t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.min = 8,\n \t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 8\n+\t\t\t\t}\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{\t/* 3DES ECB */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_3DES_ECB,\n+\t\t\t\t.block_size = 8,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 24,\n+\t\t\t\t\t.max = 24,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 0,\n+\t\t\t\t\t.max = 0,\n \t\t\t\t\t.increment = 0\n \t\t\t\t}\n \t\t\t}, }\n \t\t}, }\n \t},\n-\t{\t/* ZUC (EEA3) */\n+\t{\t/* DES CBC */\n \t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n \t\t{.sym = {\n \t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n \t\t\t{.cipher = {\n-\t\t\t\t.algo = RTE_CRYPTO_CIPHER_ZUC_EEA3,\n-\t\t\t\t.block_size = 16,\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_DES_CBC,\n+\t\t\t\t.block_size = 8,\n \t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.min = 8,\n+\t\t\t\t\t.max = 8,\n \t\t\t\t\t.increment = 0\n \t\t\t\t},\n \t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.min = 8,\n+\t\t\t\t\t.max = 8,\n \t\t\t\t\t.increment = 0\n \t\t\t\t}\n \t\t\t}, }\n \t\t}, }\n \t},\n-\t{\t/* AES GCM */\n+};\n+\n+static const struct rte_cryptodev_capabilities caps_null[] = {\n+\t{\t/* NULL (AUTH) */\n \t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n \t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,\n-\t\t\t{.aead = {\n-\t\t\t\t.algo = RTE_CRYPTO_AEAD_AES_GCM,\n-\t\t\t\t.block_size = 16,\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_NULL,\n+\t\t\t\t.block_size = 1,\n \t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 32,\n-\t\t\t\t\t.increment = 8\n+\t\t\t\t\t.min = 0,\n+\t\t\t\t\t.max = 0,\n+\t\t\t\t\t.increment = 0\n \t\t\t\t},\n \t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 4,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 1\n+\t\t\t\t\t.min = 0,\n+\t\t\t\t\t.max = 0,\n+\t\t\t\t\t.increment = 0\n \t\t\t\t},\n-\t\t\t\t.aad_size = {\n+\t\t\t}, },\n+\t\t}, },\n+\t},\n+\t{\t/* NULL (CIPHER) */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_NULL,\n+\t\t\t\t.block_size = 1,\n+\t\t\t\t.key_size = {\n \t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 1024,\n-\t\t\t\t\t.increment = 1\n+\t\t\t\t\t.max = 0,\n+\t\t\t\t\t.increment = 0\n \t\t\t\t},\n \t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 12,\n-\t\t\t\t\t.max = 12,\n+\t\t\t\t\t.min = 0,\n+\t\t\t\t\t.max = 0,\n \t\t\t\t\t.increment = 0\n \t\t\t\t}\n-\t\t\t}, }\n+\t\t\t}, },\n \t\t}, }\n \t},\n-\t/* End of symmetric capabilities */\n+};\n \n-\t/* Asymmetric capabilities */\n-\t{\t/* RSA */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,\n-\t\t{.asym = {\n-\t\t\t.xform_capa = {\n-\t\t\t\t.xform_type = RTE_CRYPTO_ASYM_XFORM_RSA,\n-\t\t\t\t.op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |\n-\t\t\t\t\t(1 << RTE_CRYPTO_ASYM_OP_VERIFY) |\n-\t\t\t\t\t(1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) |\n-\t\t\t\t\t(1 << RTE_CRYPTO_ASYM_OP_DECRYPT)),\n-\t\t\t\t{.modlen = {\n-\t\t\t\t\t.min = 17,\n-\t\t\t\t\t.max = 1024,\n-\t\t\t\t\t.increment = 1\n-\t\t\t\t}, }\n-\t\t\t}\n-\t\t}, }\n-\t},\n-\t{\t/* MOD_EXP */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,\n-\t\t{.asym = {\n-\t\t\t.xform_capa = {\n-\t\t\t\t.xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX,\n-\t\t\t\t.op_types = 0,\n-\t\t\t\t{.modlen = {\n-\t\t\t\t\t.min = 17,\n-\t\t\t\t\t.max = 1024,\n-\t\t\t\t\t.increment = 1\n-\t\t\t\t}, }\n-\t\t\t}\n-\t\t}, }\n-\t},\n-\t{\t/* ECDSA */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,\n-\t\t{.asym = {\n-\t\t\t.xform_capa = {\n-\t\t\t\t.xform_type = RTE_CRYPTO_ASYM_XFORM_ECDSA,\n-\t\t\t\t.op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |\n-\t\t\t\t\t(1 << RTE_CRYPTO_ASYM_OP_VERIFY)),\n-\t\t\t\t}\n-\t\t\t},\n-\t\t}\n-\t},\n-\t{\t/* ECPM */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,\n-\t\t{.asym = {\n-\t\t\t.xform_capa = {\n-\t\t\t\t.xform_type = RTE_CRYPTO_ASYM_XFORM_ECPM,\n-\t\t\t\t.op_types = 0\n-\t\t\t\t}\n-\t\t\t},\n-\t\t}\n-\t},\n-\t/* End of asymmetric capabilities */\n+static const struct rte_cryptodev_capabilities caps_end[] = {\n \tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n };\n \n+static void\n+cpt_caps_add(const struct rte_cryptodev_capabilities *caps, int nb_caps)\n+{\n+\tstatic int cur_pos;\n+\n+\tif (cur_pos + nb_caps > OTX2_CPT_MAX_CAPS)\n+\t\treturn;\n+\n+\tmemcpy(&otx2_cpt_caps[cur_pos], caps, nb_caps * sizeof(caps[0]));\n+\tcur_pos += nb_caps;\n+}\n+\n const struct rte_cryptodev_capabilities *\n-otx2_cpt_capabilities_get(void)\n+otx2_cpt_capabilities_get(union cpt_eng_caps *hw_caps)\n {\n-\treturn otx2_cpt_capabilities;\n+\n+\tCPT_CAPS_ADD(hw_caps, mul);\n+\tCPT_CAPS_ADD(hw_caps, sha1_sha2);\n+\tCPT_CAPS_ADD(hw_caps, zuc_snow3g);\n+\tCPT_CAPS_ADD(hw_caps, aes);\n+\tCPT_CAPS_ADD(hw_caps, kasumi);\n+\tCPT_CAPS_ADD(hw_caps, des);\n+\n+\tcpt_caps_add(caps_null, RTE_DIM(caps_null));\n+\tcpt_caps_add(caps_end, RTE_DIM(caps_end));\n+\n+\treturn otx2_cpt_caps;\n }\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h\nindex f103c32eda..e07a2a8c92 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h\n@@ -7,10 +7,20 @@\n \n #include <rte_cryptodev.h>\n \n+#include \"otx2_mbox.h\"\n+\n+enum otx2_cpt_egrp {\n+\tOTX2_CPT_EGRP_SE = 0,\n+\tOTX2_CPT_EGRP_SE_IE = 1,\n+\tOTX2_CPT_EGRP_AE = 2,\n+\tOTX2_CPT_EGRP_MAX,\n+};\n+\n /*\n  * Get capabilities list for the device\n  *\n  */\n-const struct rte_cryptodev_capabilities *otx2_cpt_capabilities_get(void);\n+const struct rte_cryptodev_capabilities *\n+otx2_cpt_capabilities_get(union cpt_eng_caps *hw_caps);\n \n #endif /* _OTX2_CRYPTODEV_CAPABILITIES_H_ */\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c\nindex 6bb8316ec9..6028439de3 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c\n@@ -14,6 +14,27 @@\n \n #include \"cpt_pmd_logs.h\"\n \n+int\n+otx2_cpt_hardware_caps_get(const struct rte_cryptodev *dev,\n+\t\t\t      union cpt_eng_caps *hw_caps)\n+{\n+\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n+\tstruct otx2_dev *otx2_dev = &vf->otx2_dev;\n+\tstruct cpt_caps_rsp_msg *rsp;\n+\tint ret;\n+\n+\totx2_mbox_alloc_msg_cpt_caps_get(otx2_dev->mbox);\n+\n+\tret = otx2_mbox_process_msg(otx2_dev->mbox, (void *)&rsp);\n+\tif (ret)\n+\t\treturn -EIO;\n+\n+\tmemcpy(hw_caps, rsp->eng_caps,\n+\t\tsizeof(union cpt_eng_caps) * CPT_MAX_ENG_TYPES);\n+\n+\treturn 0;\n+}\n+\n int\n otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,\n \t\t\t      uint16_t *nb_queues)\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h\nindex ae66b08461..4bc057774f 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h\n@@ -9,6 +9,9 @@\n \n #include \"otx2_cryptodev_hw_access.h\"\n \n+int otx2_cpt_hardware_caps_get(const struct rte_cryptodev *dev,\n+\t\t\t      union cpt_eng_caps *hw_caps);\n+\n int otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,\n \t\t\t\t  uint16_t *nb_queues);\n \ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\nindex ad292a08f7..132f599efd 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n@@ -1067,7 +1067,7 @@ otx2_cpt_dev_info_get(struct rte_cryptodev *dev,\n \tif (info != NULL) {\n \t\tinfo->max_nb_queue_pairs = vf->max_queues;\n \t\tinfo->feature_flags = dev->feature_flags;\n-\t\tinfo->capabilities = otx2_cpt_capabilities_get();\n+\t\tinfo->capabilities = otx2_cpt_capabilities_get(vf->hw_caps);\n \t\tinfo->sym.max_nb_sessions = 0;\n \t\tinfo->driver_id = otx2_cryptodev_driver_id;\n \t\tinfo->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ;\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h\nindex f83e36b486..1970187f88 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h\n@@ -10,12 +10,6 @@\n #define OTX2_CPT_MIN_HEADROOM_REQ\t24\n #define OTX2_CPT_MIN_TAILROOM_REQ\t8\n \n-enum otx2_cpt_egrp {\n-\tOTX2_CPT_EGRP_SE = 0,\n-\tOTX2_CPT_EGRP_SE_IE = 1,\n-\tOTX2_CPT_EGRP_AE = 2\n-};\n-\n extern struct rte_cryptodev_ops otx2_cpt_ops;\n \n #endif /* _OTX2_CRYPTODEV_OPS_H_ */\n",
    "prefixes": [
        "1/2"
    ]
}