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GET /api/patches/71333/?format=api
{ "id": 71333, "url": "http://patches.dpdk.org/api/patches/71333/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200612032410.20864-10-guinanx.sun@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200612032410.20864-10-guinanx.sun@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200612032410.20864-10-guinanx.sun@intel.com", "date": "2020-06-12T03:23:58", "name": "[09/21] net/ixgbe/base: remove whitespace in function comments", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3385321f4d6fca379c33955521abbb3b4cfaa936", "submitter": { "id": 1476, "url": "http://patches.dpdk.org/api/people/1476/?format=api", "name": "Guinan Sun", "email": "guinanx.sun@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200612032410.20864-10-guinanx.sun@intel.com/mbox/", "series": [ { "id": 10428, "url": "http://patches.dpdk.org/api/series/10428/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=10428", "date": "2020-06-12T03:23:49", "name": "update ixgbe base code", "version": 1, "mbox": "http://patches.dpdk.org/series/10428/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/71333/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/71333/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id ABBBAA00BE;\n\tFri, 12 Jun 2020 05:47:27 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 31AE31BEB5;\n\tFri, 12 Jun 2020 05:46:27 +0200 (CEST)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n by dpdk.org (Postfix) with ESMTP id 975451BEB5\n for <dev@dpdk.org>; Fri, 12 Jun 2020 05:46:23 +0200 (CEST)", "from orsmga002.jf.intel.com ([10.7.209.21])\n by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 11 Jun 2020 20:46:23 -0700", "from intel.sh.intel.com ([10.239.255.18])\n by orsmga002.jf.intel.com with ESMTP; 11 Jun 2020 20:46:18 -0700" ], "IronPort-SDR": [ "\n ktlzRV8L1PzDIpnz22JENR6/93gAha+hFXO5zCv6+sNZoQPfnIMhk6aRZ8vJ9v5g43FCNNVUNr\n +++XUhI7Fyww==", "\n Fk/XuNBQCwZe+EQVf72oJNf+v0E3+G5sWUg23ChbcqwpPRfZy7lJluvEe7dVk1ZcPXvyEJORnz\n 5e8Wcj6VVVlQ==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.73,501,1583222400\"; d=\"scan'208\";a=\"289759534\"", "From": "Guinan Sun <guinanx.sun@intel.com>", "To": "dev@dpdk.org", "Cc": "Guinan Sun <guinanx.sun@intel.com>,\n Jacob Keller <jacob.e.keller@intel.com>", "Date": "Fri, 12 Jun 2020 03:23:58 +0000", "Message-Id": "<20200612032410.20864-10-guinanx.sun@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200612032410.20864-1-guinanx.sun@intel.com>", "References": "<20200612032410.20864-1-guinanx.sun@intel.com>", "Subject": "[dpdk-dev] [PATCH 09/21] net/ixgbe/base: remove whitespace in\n\tfunction comments", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Remove unnecessary extra whitespace on all function comments, replacing\n' * ' with ' * '.\n\nThis was done automatically via sed using the following transformation:\n\n sed 's/^ \\* / * /'\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\nSigned-off-by: Guinan Sun <guinanx.sun@intel.com>\n---\n drivers/net/ixgbe/base/ixgbe_82598.c | 238 +++---\n drivers/net/ixgbe/base/ixgbe_82599.c | 384 +++++-----\n drivers/net/ixgbe/base/ixgbe_api.c | 874 ++++++++++-----------\n drivers/net/ixgbe/base/ixgbe_common.c | 1024 ++++++++++++-------------\n drivers/net/ixgbe/base/ixgbe_dcb.c | 6 +-\n drivers/net/ixgbe/base/ixgbe_hv_vf.c | 20 +-\n drivers/net/ixgbe/base/ixgbe_mbx.c | 258 +++----\n drivers/net/ixgbe/base/ixgbe_phy.c | 394 +++++-----\n drivers/net/ixgbe/base/ixgbe_vf.c | 166 ++--\n drivers/net/ixgbe/base/ixgbe_x540.c | 188 ++---\n drivers/net/ixgbe/base/ixgbe_x550.c | 480 ++++++------\n 11 files changed, 2016 insertions(+), 2016 deletions(-)", "diff": "diff --git a/drivers/net/ixgbe/base/ixgbe_82598.c b/drivers/net/ixgbe/base/ixgbe_82598.c\nindex c83e1c6b3..6a7983f17 100644\n--- a/drivers/net/ixgbe/base/ixgbe_82598.c\n+++ b/drivers/net/ixgbe/base/ixgbe_82598.c\n@@ -38,14 +38,14 @@ STATIC void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,\n STATIC s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\t\t\tu8 *sff8472_data);\n /**\n- * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout\n- * @hw: pointer to the HW structure\n+ * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout\n+ * @hw: pointer to the HW structure\n *\n- * The defaults for 82598 should be in the range of 50us to 50ms,\n- * however the hardware default for these parts is 500us to 1ms which is less\n- * than the 10ms recommended by the pci-e spec. To address this we need to\n- * increase the value to either 10ms to 250ms for capability version 1 config,\n- * or 16ms to 55ms for version 2.\n+ * The defaults for 82598 should be in the range of 50us to 50ms,\n+ * however the hardware default for these parts is 500us to 1ms which is less\n+ * than the 10ms recommended by the pci-e spec. To address this we need to\n+ * increase the value to either 10ms to 250ms for capability version 1 config,\n+ * or 16ms to 55ms for version 2.\n **/\n void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)\n {\n@@ -80,11 +80,11 @@ void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_init_ops_82598 - Inits func ptrs and MAC type\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_ops_82598 - Inits func ptrs and MAC type\n+ * @hw: pointer to hardware structure\n *\n- * Initialize the function pointers and assign the MAC type for 82598.\n- * Does not touch the hardware.\n+ * Initialize the function pointers and assign the MAC type for 82598.\n+ * Does not touch the hardware.\n **/\n s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)\n {\n@@ -150,12 +150,12 @@ s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_init_phy_ops_82598 - PHY/SFP specific init\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_phy_ops_82598 - PHY/SFP specific init\n+ * @hw: pointer to hardware structure\n *\n- * Initialize any function pointers that were not able to be\n- * set during init_shared_code because the PHY/SFP type was\n- * not known. Perform the SFP init if necessary.\n+ * Initialize any function pointers that were not able to be\n+ * set during init_shared_code because the PHY/SFP type was\n+ * not known. Perform the SFP init if necessary.\n *\n **/\n s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)\n@@ -214,11 +214,11 @@ s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx\n- * @hw: pointer to hardware structure\n+ * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx\n+ * @hw: pointer to hardware structure\n *\n- * Starts the hardware using the generic start_hw function.\n- * Disables relaxed ordering Then set pcie completion timeout\n+ * Starts the hardware using the generic start_hw function.\n+ * Disables relaxed ordering Then set pcie completion timeout\n *\n **/\n s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)\n@@ -256,12 +256,12 @@ s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_get_link_capabilities_82598 - Determines link capabilities\n- * @hw: pointer to hardware structure\n- * @speed: pointer to link speed\n- * @autoneg: boolean auto-negotiation value\n+ * ixgbe_get_link_capabilities_82598 - Determines link capabilities\n+ * @hw: pointer to hardware structure\n+ * @speed: pointer to link speed\n+ * @autoneg: boolean auto-negotiation value\n *\n- * Determines the link capabilities by reading the AUTOC register.\n+ * Determines the link capabilities by reading the AUTOC register.\n **/\n STATIC s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,\n \t\t\t\t\t ixgbe_link_speed *speed,\n@@ -317,10 +317,10 @@ STATIC s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_get_media_type_82598 - Determines media type\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_media_type_82598 - Determines media type\n+ * @hw: pointer to hardware structure\n *\n- * Returns the media type (fiber, copper, backplane)\n+ * Returns the media type (fiber, copper, backplane)\n **/\n STATIC enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)\n {\n@@ -370,10 +370,10 @@ STATIC enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_fc_enable_82598 - Enable flow control\n- * @hw: pointer to hardware structure\n+ * ixgbe_fc_enable_82598 - Enable flow control\n+ * @hw: pointer to hardware structure\n *\n- * Enable flow control according to the current settings.\n+ * Enable flow control according to the current settings.\n **/\n s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)\n {\n@@ -517,12 +517,12 @@ s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_start_mac_link_82598 - Configures MAC link settings\n- * @hw: pointer to hardware structure\n- * @autoneg_wait_to_complete: true when waiting for completion is needed\n+ * ixgbe_start_mac_link_82598 - Configures MAC link settings\n+ * @hw: pointer to hardware structure\n+ * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n- * Configures link settings based on values in the ixgbe_hw struct.\n- * Restarts the link. Performs autonegotiation if needed.\n+ * Configures link settings based on values in the ixgbe_hw struct.\n+ * Restarts the link. Performs autonegotiation if needed.\n **/\n STATIC s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,\n \t\t\t\t bool autoneg_wait_to_complete)\n@@ -566,11 +566,11 @@ STATIC s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_validate_link_ready - Function looks for phy link\n- * @hw: pointer to hardware structure\n+ * ixgbe_validate_link_ready - Function looks for phy link\n+ * @hw: pointer to hardware structure\n *\n- * Function indicates success when phy link is available. If phy is not ready\n- * within 5 seconds of MAC indicating link, the function returns error.\n+ * Function indicates success when phy link is available. If phy is not ready\n+ * within 5 seconds of MAC indicating link, the function returns error.\n **/\n STATIC s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)\n {\n@@ -601,13 +601,13 @@ STATIC s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_check_mac_link_82598 - Get link/speed status\n- * @hw: pointer to hardware structure\n- * @speed: pointer to link speed\n- * @link_up: true is link is up, false otherwise\n- * @link_up_wait_to_complete: bool used to wait for link up or not\n+ * ixgbe_check_mac_link_82598 - Get link/speed status\n+ * @hw: pointer to hardware structure\n+ * @speed: pointer to link speed\n+ * @link_up: true is link is up, false otherwise\n+ * @link_up_wait_to_complete: bool used to wait for link up or not\n *\n- * Reads the links register to determine if link is up and the current speed\n+ * Reads the links register to determine if link is up and the current speed\n **/\n STATIC s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,\n \t\t\t\t ixgbe_link_speed *speed, bool *link_up,\n@@ -691,12 +691,12 @@ STATIC s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_setup_mac_link_82598 - Set MAC link speed\n- * @hw: pointer to hardware structure\n- * @speed: new link speed\n- * @autoneg_wait_to_complete: true when waiting for completion is needed\n+ * ixgbe_setup_mac_link_82598 - Set MAC link speed\n+ * @hw: pointer to hardware structure\n+ * @speed: new link speed\n+ * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n- * Set the link speed in the AUTOC register and restarts link.\n+ * Set the link speed in the AUTOC register and restarts link.\n **/\n STATIC s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,\n \t\t\t\t ixgbe_link_speed speed,\n@@ -745,12 +745,12 @@ STATIC s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,\n \n \n /**\n- * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field\n- * @hw: pointer to hardware structure\n- * @speed: new link speed\n- * @autoneg_wait_to_complete: true if waiting is needed to complete\n+ * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field\n+ * @hw: pointer to hardware structure\n+ * @speed: new link speed\n+ * @autoneg_wait_to_complete: true if waiting is needed to complete\n *\n- * Sets the link speed in the AUTOC register in the MAC and restarts link.\n+ * Sets the link speed in the AUTOC register in the MAC and restarts link.\n **/\n STATIC s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,\n \t\t\t\t\t ixgbe_link_speed speed,\n@@ -770,12 +770,12 @@ STATIC s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_reset_hw_82598 - Performs hardware reset\n- * @hw: pointer to hardware structure\n+ * ixgbe_reset_hw_82598 - Performs hardware reset\n+ * @hw: pointer to hardware structure\n *\n- * Resets the hardware by resetting the transmit and receive units, masks and\n- * clears all interrupts, performing a PHY reset, and performing a link (MAC)\n- * reset.\n+ * Resets the hardware by resetting the transmit and receive units, masks and\n+ * clears all interrupts, performing a PHY reset, and performing a link (MAC)\n+ * reset.\n **/\n STATIC s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)\n {\n@@ -908,10 +908,10 @@ STATIC s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address\n- * @hw: pointer to hardware struct\n- * @rar: receive address register index to associate with a VMDq index\n- * @vmdq: VMDq set index\n+ * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address\n+ * @hw: pointer to hardware struct\n+ * @rar: receive address register index to associate with a VMDq index\n+ * @vmdq: VMDq set index\n **/\n s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n {\n@@ -934,10 +934,10 @@ s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n }\n \n /**\n- * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address\n- * @hw: pointer to hardware struct\n- * @rar: receive address register index to associate with a VMDq index\n- * @vmdq: VMDq clear index (not used in 82598, but elsewhere)\n+ * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address\n+ * @hw: pointer to hardware struct\n+ * @rar: receive address register index to associate with a VMDq index\n+ * @vmdq: VMDq clear index (not used in 82598, but elsewhere)\n **/\n STATIC s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n {\n@@ -962,14 +962,14 @@ STATIC s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n }\n \n /**\n- * ixgbe_set_vfta_82598 - Set VLAN filter table\n- * @hw: pointer to hardware structure\n- * @vlan: VLAN id to write to VLAN filter\n- * @vind: VMDq output index that maps queue to VLAN id in VFTA\n- * @vlan_on: boolean flag to turn on/off VLAN in VFTA\n- * @vlvf_bypass: boolean flag - unused\n+ * ixgbe_set_vfta_82598 - Set VLAN filter table\n+ * @hw: pointer to hardware structure\n+ * @vlan: VLAN id to write to VLAN filter\n+ * @vind: VMDq output index that maps queue to VLAN id in VFTA\n+ * @vlan_on: boolean flag to turn on/off VLAN in VFTA\n+ * @vlvf_bypass: boolean flag - unused\n *\n- * Turn on/off specified VLAN in the VLAN filter table.\n+ * Turn on/off specified VLAN in the VLAN filter table.\n **/\n s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,\n \t\t\t bool vlan_on, bool vlvf_bypass)\n@@ -1015,10 +1015,10 @@ s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,\n }\n \n /**\n- * ixgbe_clear_vfta_82598 - Clear VLAN filter table\n- * @hw: pointer to hardware structure\n+ * ixgbe_clear_vfta_82598 - Clear VLAN filter table\n+ * @hw: pointer to hardware structure\n *\n- * Clears the VLAN filer table, and the VMDq index associated with the filter\n+ * Clears the VLAN filer table, and the VMDq index associated with the filter\n **/\n STATIC s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)\n {\n@@ -1039,12 +1039,12 @@ STATIC s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register\n- * @hw: pointer to hardware structure\n- * @reg: analog register to read\n- * @val: read value\n+ * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register\n+ * @hw: pointer to hardware structure\n+ * @reg: analog register to read\n+ * @val: read value\n *\n- * Performs read operation to Atlas analog register specified.\n+ * Performs read operation to Atlas analog register specified.\n **/\n s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)\n {\n@@ -1063,12 +1063,12 @@ s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)\n }\n \n /**\n- * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register\n- * @hw: pointer to hardware structure\n- * @reg: atlas register to write\n- * @val: value to write\n+ * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register\n+ * @hw: pointer to hardware structure\n+ * @reg: atlas register to write\n+ * @val: value to write\n *\n- * Performs write operation to Atlas analog register specified.\n+ * Performs write operation to Atlas analog register specified.\n **/\n s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)\n {\n@@ -1085,13 +1085,13 @@ s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)\n }\n \n /**\n- * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface.\n- * @hw: pointer to hardware structure\n- * @dev_addr: address to read from\n- * @byte_offset: byte offset to read from dev_addr\n- * @eeprom_data: value read\n+ * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface.\n+ * @hw: pointer to hardware structure\n+ * @dev_addr: address to read from\n+ * @byte_offset: byte offset to read from dev_addr\n+ * @eeprom_data: value read\n *\n- * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.\n+ * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.\n **/\n STATIC s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,\n \t\t\t\t u8 byte_offset, u8 *eeprom_data)\n@@ -1159,12 +1159,12 @@ STATIC s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,\n }\n \n /**\n- * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.\n- * @hw: pointer to hardware structure\n- * @byte_offset: EEPROM byte offset to read\n- * @eeprom_data: value read\n+ * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: EEPROM byte offset to read\n+ * @eeprom_data: value read\n *\n- * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.\n+ * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.\n **/\n s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\t\tu8 *eeprom_data)\n@@ -1174,12 +1174,12 @@ s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,\n }\n \n /**\n- * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface.\n- * @hw: pointer to hardware structure\n- * @byte_offset: byte offset at address 0xA2\n- * @sff8472_data: value read\n+ * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface.\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: byte offset at address 0xA2\n+ * @sff8472_data: value read\n *\n- * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C\n+ * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C\n **/\n STATIC s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\t\t\tu8 *sff8472_data)\n@@ -1189,10 +1189,10 @@ STATIC s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,\n }\n \n /**\n- * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type\n+ * @hw: pointer to hardware structure\n *\n- * Determines physical layer capabilities of the current configuration.\n+ * Determines physical layer capabilities of the current configuration.\n **/\n u64 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)\n {\n@@ -1291,12 +1291,12 @@ u64 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple\n- * port devices.\n- * @hw: pointer to the HW structure\n+ * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple\n+ * port devices.\n+ * @hw: pointer to the HW structure\n *\n- * Calls common function and corrects issue with some single port devices\n- * that enable LAN1 but not LAN0.\n+ * Calls common function and corrects issue with some single port devices\n+ * that enable LAN1 but not LAN0.\n **/\n void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)\n {\n@@ -1325,8 +1325,8 @@ void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_enable_relaxed_ordering_82598 - enable relaxed ordering\n- * @hw: pointer to hardware structure\n+ * ixgbe_enable_relaxed_ordering_82598 - enable relaxed ordering\n+ * @hw: pointer to hardware structure\n *\n **/\n void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw)\n@@ -1395,11 +1395,11 @@ STATIC void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,\n }\n \n /**\n- * ixgbe_enable_rx_dma_82598 - Enable the Rx DMA unit\n- * @hw: pointer to hardware structure\n- * @regval: register value to write to RXCTRL\n+ * ixgbe_enable_rx_dma_82598 - Enable the Rx DMA unit\n+ * @hw: pointer to hardware structure\n+ * @regval: register value to write to RXCTRL\n *\n- * Enables the Rx DMA unit\n+ * Enables the Rx DMA unit\n **/\n s32 ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, u32 regval)\n {\ndiff --git a/drivers/net/ixgbe/base/ixgbe_82599.c b/drivers/net/ixgbe/base/ixgbe_82599.c\nindex 9cd0b1428..193233746 100644\n--- a/drivers/net/ixgbe/base/ixgbe_82599.c\n+++ b/drivers/net/ixgbe/base/ixgbe_82599.c\n@@ -71,12 +71,12 @@ void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_init_phy_ops_82599 - PHY/SFP specific init\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_phy_ops_82599 - PHY/SFP specific init\n+ * @hw: pointer to hardware structure\n *\n- * Initialize any function pointers that were not able to be\n- * set during init_shared_code because the PHY/SFP type was\n- * not known. Perform the SFP init if necessary.\n+ * Initialize any function pointers that were not able to be\n+ * set during init_shared_code because the PHY/SFP type was\n+ * not known. Perform the SFP init if necessary.\n *\n **/\n s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)\n@@ -205,14 +205,14 @@ s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)\n }\n \n /**\n- * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read\n- * @hw: pointer to hardware structure\n- * @locked: Return the if we locked for this read.\n- * @reg_val: Value we read from AUTOC\n+ * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read\n+ * @hw: pointer to hardware structure\n+ * @locked: Return the if we locked for this read.\n+ * @reg_val: Value we read from AUTOC\n *\n- * For this part (82599) we need to wrap read-modify-writes with a possible\n- * FW/SW lock. It is assumed this lock will be freed with the next\n- * prot_autoc_write_82599().\n+ * For this part (82599) we need to wrap read-modify-writes with a possible\n+ * FW/SW lock. It is assumed this lock will be freed with the next\n+ * prot_autoc_write_82599().\n */\n s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)\n {\n@@ -238,7 +238,7 @@ s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)\n * @hw: pointer to hardware structure\n * @autoc: value to write to AUTOC\n * @locked: bool to indicate whether the SW/FW lock was already taken by\n- * previous proc_autoc_read_82599.\n+ * previous proc_autoc_read_82599.\n *\n * This part (82599) may need to hold the SW/FW lock around all writes to\n * AUTOC. Likewise after a write we need to do a pipeline reset.\n@@ -278,11 +278,11 @@ s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)\n }\n \n /**\n- * ixgbe_init_ops_82599 - Inits func ptrs and MAC type\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_ops_82599 - Inits func ptrs and MAC type\n+ * @hw: pointer to hardware structure\n *\n- * Initialize the function pointers and assign the MAC type for 82599.\n- * Does not touch the hardware.\n+ * Initialize the function pointers and assign the MAC type for 82599.\n+ * Does not touch the hardware.\n **/\n \n s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)\n@@ -372,12 +372,12 @@ s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_get_link_capabilities_82599 - Determines link capabilities\n- * @hw: pointer to hardware structure\n- * @speed: pointer to link speed\n- * @autoneg: true when autoneg or autotry is enabled\n+ * ixgbe_get_link_capabilities_82599 - Determines link capabilities\n+ * @hw: pointer to hardware structure\n+ * @speed: pointer to link speed\n+ * @autoneg: true when autoneg or autotry is enabled\n *\n- * Determines the link capabilities by reading the AUTOC register.\n+ * Determines the link capabilities by reading the AUTOC register.\n **/\n s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,\n \t\t\t\t ixgbe_link_speed *speed,\n@@ -486,10 +486,10 @@ s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_get_media_type_82599 - Get media type\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_media_type_82599 - Get media type\n+ * @hw: pointer to hardware structure\n *\n- * Returns the media type (fiber, copper, backplane)\n+ * Returns the media type (fiber, copper, backplane)\n **/\n enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)\n {\n@@ -543,10 +543,10 @@ enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3\n- * @hw: pointer to hardware structure\n+ * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3\n+ * @hw: pointer to hardware structure\n *\n- * Disables link during D3 power down sequence.\n+ * Disables link during D3 power down sequence.\n *\n **/\n void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)\n@@ -566,12 +566,12 @@ void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_start_mac_link_82599 - Setup MAC link settings\n- * @hw: pointer to hardware structure\n- * @autoneg_wait_to_complete: true when waiting for completion is needed\n+ * ixgbe_start_mac_link_82599 - Setup MAC link settings\n+ * @hw: pointer to hardware structure\n+ * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n- * Configures link settings based on values in the ixgbe_hw struct.\n- * Restarts the link. Performs autonegotiation if needed.\n+ * Configures link settings based on values in the ixgbe_hw struct.\n+ * Restarts the link. Performs autonegotiation if needed.\n **/\n s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,\n \t\t\t bool autoneg_wait_to_complete)\n@@ -634,12 +634,12 @@ s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser\n- * @hw: pointer to hardware structure\n+ * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser\n+ * @hw: pointer to hardware structure\n *\n- * The base drivers may require better control over SFP+ module\n- * PHY states. This includes selectively shutting down the Tx\n- * laser on the PHY, effectively halting physical link.\n+ * The base drivers may require better control over SFP+ module\n+ * PHY states. This includes selectively shutting down the Tx\n+ * laser on the PHY, effectively halting physical link.\n **/\n void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)\n {\n@@ -657,12 +657,12 @@ void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser\n- * @hw: pointer to hardware structure\n+ * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser\n+ * @hw: pointer to hardware structure\n *\n- * The base drivers may require better control over SFP+ module\n- * PHY states. This includes selectively turning on the Tx\n- * laser on the PHY, effectively starting physical link.\n+ * The base drivers may require better control over SFP+ module\n+ * PHY states. This includes selectively turning on the Tx\n+ * laser on the PHY, effectively starting physical link.\n **/\n void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)\n {\n@@ -676,16 +676,16 @@ void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser\n- * @hw: pointer to hardware structure\n+ * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser\n+ * @hw: pointer to hardware structure\n *\n- * When the driver changes the link speeds that it can support,\n- * it sets autotry_restart to true to indicate that we need to\n- * initiate a new autotry session with the link partner. To do\n- * so, we set the speed then disable and re-enable the Tx laser, to\n- * alert the link partner that it also needs to restart autotry on its\n- * end. This is consistent with true clause 37 autoneg, which also\n- * involves a loss of signal.\n+ * When the driver changes the link speeds that it can support,\n+ * it sets autotry_restart to true to indicate that we need to\n+ * initiate a new autotry session with the link partner. To do\n+ * so, we set the speed then disable and re-enable the Tx laser, to\n+ * alert the link partner that it also needs to restart autotry on its\n+ * end. This is consistent with true clause 37 autoneg, which also\n+ * involves a loss of signal.\n **/\n void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)\n {\n@@ -703,11 +703,11 @@ void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_set_hard_rate_select_speed - Set module link speed\n- * @hw: pointer to hardware structure\n- * @speed: link speed to set\n+ * ixgbe_set_hard_rate_select_speed - Set module link speed\n+ * @hw: pointer to hardware structure\n+ * @speed: link speed to set\n *\n- * Set module link speed via RS0/RS1 rate select pins.\n+ * Set module link speed via RS0/RS1 rate select pins.\n */\n void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw,\n \t\t\t\t\tixgbe_link_speed speed)\n@@ -732,12 +732,12 @@ void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed\n- * @hw: pointer to hardware structure\n- * @speed: new link speed\n- * @autoneg_wait_to_complete: true when waiting for completion is needed\n+ * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed\n+ * @hw: pointer to hardware structure\n+ * @speed: new link speed\n+ * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n- * Implements the Intel SmartSpeed algorithm.\n+ * Implements the Intel SmartSpeed algorithm.\n **/\n s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,\n \t\t\t\t ixgbe_link_speed speed,\n@@ -844,12 +844,12 @@ s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_setup_mac_link_82599 - Set MAC link speed\n- * @hw: pointer to hardware structure\n- * @speed: new link speed\n- * @autoneg_wait_to_complete: true when waiting for completion is needed\n+ * ixgbe_setup_mac_link_82599 - Set MAC link speed\n+ * @hw: pointer to hardware structure\n+ * @speed: new link speed\n+ * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n- * Set the link speed in the AUTOC register and restarts link.\n+ * Set the link speed in the AUTOC register and restarts link.\n **/\n s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,\n \t\t\t ixgbe_link_speed speed,\n@@ -962,12 +962,12 @@ s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field\n- * @hw: pointer to hardware structure\n- * @speed: new link speed\n- * @autoneg_wait_to_complete: true if waiting is needed to complete\n+ * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field\n+ * @hw: pointer to hardware structure\n+ * @speed: new link speed\n+ * @autoneg_wait_to_complete: true if waiting is needed to complete\n *\n- * Restarts link on PHY and MAC based on settings passed in.\n+ * Restarts link on PHY and MAC based on settings passed in.\n **/\n STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,\n \t\t\t\t\t ixgbe_link_speed speed,\n@@ -987,12 +987,12 @@ STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_reset_hw_82599 - Perform hardware reset\n- * @hw: pointer to hardware structure\n+ * ixgbe_reset_hw_82599 - Perform hardware reset\n+ * @hw: pointer to hardware structure\n *\n- * Resets the hardware by resetting the transmit and receive units, masks\n- * and clears all interrupts, perform a PHY reset, and perform a link (MAC)\n- * reset.\n+ * Resets the hardware by resetting the transmit and receive units, masks\n+ * and clears all interrupts, perform a PHY reset, and perform a link (MAC)\n+ * reset.\n **/\n s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)\n {\n@@ -1188,8 +1188,8 @@ STATIC s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd)\n }\n \n /**\n- * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.\n- * @hw: pointer to hardware structure\n+ * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.\n+ * @hw: pointer to hardware structure\n **/\n s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)\n {\n@@ -1261,9 +1261,9 @@ s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers\n- * @hw: pointer to hardware structure\n- * @fdirctrl: value to write to flow director control register\n+ * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers\n+ * @hw: pointer to hardware structure\n+ * @fdirctrl: value to write to flow director control register\n **/\n STATIC void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)\n {\n@@ -1302,9 +1302,9 @@ STATIC void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)\n }\n \n /**\n- * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters\n- * @hw: pointer to hardware structure\n- * @fdirctrl: value to write to flow director control register, initially\n+ * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters\n+ * @hw: pointer to hardware structure\n+ * @fdirctrl: value to write to flow director control register, initially\n *\t contains just the value of the Rx packet buffer allocation\n **/\n s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)\n@@ -1328,11 +1328,11 @@ s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)\n }\n \n /**\n- * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters\n- * @hw: pointer to hardware structure\n- * @fdirctrl: value to write to flow director control register, initially\n+ * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters\n+ * @hw: pointer to hardware structure\n+ * @fdirctrl: value to write to flow director control register, initially\n *\t contains just the value of the Rx packet buffer allocation\n- * @cloud_mode: true - cloud mode, false - other mode\n+ * @cloud_mode: true - cloud mode, false - other mode\n **/\n s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,\n \t\t\tbool cloud_mode)\n@@ -1367,9 +1367,9 @@ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,\n }\n \n /**\n- * ixgbe_set_fdir_drop_queue_82599 - Set Flow Director drop queue\n- * @hw: pointer to hardware structure\n- * @dropqueue: Rx queue index used for the dropped packets\n+ * ixgbe_set_fdir_drop_queue_82599 - Set Flow Director drop queue\n+ * @hw: pointer to hardware structure\n+ * @dropqueue: Rx queue index used for the dropped packets\n **/\n void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue)\n {\n@@ -1425,15 +1425,15 @@ do { \\\n } while (0)\n \n /**\n- * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash\n- * @input: input bitstream to compute the hash on\n- * @common: compressed common input dword\n+ * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash\n+ * @input: input bitstream to compute the hash on\n+ * @common: compressed common input dword\n *\n- * This function is almost identical to the function above but contains\n- * several optimizations such as unwinding all of the loops, letting the\n- * compiler work out all of the conditional ifs since the keys are static\n- * defines, and computing two keys at once since the hashed dword stream\n- * will be the same for both keys.\n+ * This function is almost identical to the function above but contains\n+ * several optimizations such as unwinding all of the loops, letting the\n+ * compiler work out all of the conditional ifs since the keys are static\n+ * defines, and computing two keys at once since the hashed dword stream\n+ * will be the same for both keys.\n **/\n u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,\n \t\t\t\t union ixgbe_atr_hash_dword common)\n@@ -1492,11 +1492,11 @@ u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,\n }\n \n /**\n- * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter\n- * @hw: pointer to hardware structure\n- * @input: unique input dword\n- * @common: compressed common input dword\n- * @queue: queue index to direct traffic to\n+ * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter\n+ * @hw: pointer to hardware structure\n+ * @input: unique input dword\n+ * @common: compressed common input dword\n+ * @queue: queue index to direct traffic to\n *\n * Note that the tunnel bit in input must not be set when the hardware\n * tunneling support does not exist.\n@@ -1565,15 +1565,15 @@ do { \\\n } while (0)\n \n /**\n- * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash\n- * @input: input bitstream to compute the hash on\n- * @input_mask: mask for the input bitstream\n+ * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash\n+ * @input: input bitstream to compute the hash on\n+ * @input_mask: mask for the input bitstream\n *\n- * This function serves two main purposes. First it applies the input_mask\n- * to the atr_input resulting in a cleaned up atr_input data stream.\n- * Secondly it computes the hash and stores it in the bkt_hash field at\n- * the end of the input byte stream. This way it will be available for\n- * future use without needing to recompute the hash.\n+ * This function serves two main purposes. First it applies the input_mask\n+ * to the atr_input resulting in a cleaned up atr_input data stream.\n+ * Secondly it computes the hash and stores it in the bkt_hash field at\n+ * the end of the input byte stream. This way it will be available for\n+ * future use without needing to recompute the hash.\n **/\n void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,\n \t\t\t\t\t union ixgbe_atr_input *input_mask)\n@@ -1624,13 +1624,13 @@ void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,\n }\n \n /**\n- * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks\n- * @input_mask: mask to be bit swapped\n+ * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks\n+ * @input_mask: mask to be bit swapped\n *\n- * The source and destination port masks for flow director are bit swapped\n- * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to\n- * generate a correctly swapped value we need to bit swap the mask and that\n- * is what is accomplished by this function.\n+ * The source and destination port masks for flow director are bit swapped\n+ * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to\n+ * generate a correctly swapped value we need to bit swap the mask and that\n+ * is what is accomplished by this function.\n **/\n STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)\n {\n@@ -1963,16 +1963,16 @@ s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter\n- * @hw: pointer to hardware structure\n- * @input: input bitstream\n- * @input_mask: mask for the input bitstream\n- * @soft_id: software index for the filters\n- * @queue: queue index to direct traffic to\n- * @cloud_mode: unused\n+ * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter\n+ * @hw: pointer to hardware structure\n+ * @input: input bitstream\n+ * @input_mask: mask for the input bitstream\n+ * @soft_id: software index for the filters\n+ * @queue: queue index to direct traffic to\n+ * @cloud_mode: unused\n *\n- * Note that the caller to this function must lock before calling, since the\n- * hardware writes must be protected from one another.\n+ * Note that the caller to this function must lock before calling, since the\n+ * hardware writes must be protected from one another.\n **/\n s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,\n \t\t\t\t\tunion ixgbe_atr_input *input,\n@@ -2030,12 +2030,12 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register\n- * @hw: pointer to hardware structure\n- * @reg: analog register to read\n- * @val: read value\n+ * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register\n+ * @hw: pointer to hardware structure\n+ * @reg: analog register to read\n+ * @val: read value\n *\n- * Performs read operation to Omer analog register specified.\n+ * Performs read operation to Omer analog register specified.\n **/\n s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)\n {\n@@ -2054,12 +2054,12 @@ s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)\n }\n \n /**\n- * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register\n- * @hw: pointer to hardware structure\n- * @reg: atlas register to write\n- * @val: value to write\n+ * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register\n+ * @hw: pointer to hardware structure\n+ * @reg: atlas register to write\n+ * @val: value to write\n *\n- * Performs write operation to Omer analog register specified.\n+ * Performs write operation to Omer analog register specified.\n **/\n s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)\n {\n@@ -2076,12 +2076,12 @@ s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)\n }\n \n /**\n- * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx\n- * @hw: pointer to hardware structure\n+ * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx\n+ * @hw: pointer to hardware structure\n *\n- * Starts the hardware using the generic start_hw function\n- * and the generation start_hw function.\n- * Then performs revision-specific operations, if any.\n+ * Starts the hardware using the generic start_hw function\n+ * and the generation start_hw function.\n+ * Then performs revision-specific operations, if any.\n **/\n s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)\n {\n@@ -2107,12 +2107,12 @@ s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_identify_phy_82599 - Get physical layer module\n- * @hw: pointer to hardware structure\n+ * ixgbe_identify_phy_82599 - Get physical layer module\n+ * @hw: pointer to hardware structure\n *\n- * Determines the physical layer module found on the current adapter.\n- * If PHY already detected, maintains current PHY type in hw struct,\n- * otherwise executes the PHY detection routine.\n+ * Determines the physical layer module found on the current adapter.\n+ * If PHY already detected, maintains current PHY type in hw struct,\n+ * otherwise executes the PHY detection routine.\n **/\n s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)\n {\n@@ -2144,10 +2144,10 @@ s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type\n+ * @hw: pointer to hardware structure\n *\n- * Determines physical layer capabilities of the current configuration.\n+ * Determines physical layer capabilities of the current configuration.\n **/\n u64 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)\n {\n@@ -2231,11 +2231,11 @@ u64 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599\n- * @hw: pointer to hardware structure\n- * @regval: register value to write to RXCTRL\n+ * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599\n+ * @hw: pointer to hardware structure\n+ * @regval: register value to write to RXCTRL\n *\n- * Enables the Rx DMA unit for 82599\n+ * Enables the Rx DMA unit for 82599\n **/\n s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)\n {\n@@ -2262,14 +2262,14 @@ s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)\n }\n \n /**\n- * ixgbe_verify_fw_version_82599 - verify FW version for 82599\n- * @hw: pointer to hardware structure\n+ * ixgbe_verify_fw_version_82599 - verify FW version for 82599\n+ * @hw: pointer to hardware structure\n *\n- * Verifies that installed the firmware version is 0.6 or higher\n- * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.\n+ * Verifies that installed the firmware version is 0.6 or higher\n+ * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.\n *\n- * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or\n- * if the FW version is not supported.\n+ * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or\n+ * if the FW version is not supported.\n **/\n STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)\n {\n@@ -2326,11 +2326,11 @@ STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.\n- * @hw: pointer to hardware structure\n+ * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.\n+ * @hw: pointer to hardware structure\n *\n- * Returns true if the LESM FW module is present and enabled. Otherwise\n- * returns false. Smart Speed must be disabled if LESM FW module is enabled.\n+ * Returns true if the LESM FW module is present and enabled. Otherwise\n+ * returns false. Smart Speed must be disabled if LESM FW module is enabled.\n **/\n bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)\n {\n@@ -2370,15 +2370,15 @@ bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using\n- * fastest available method\n+ * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using\n+ * fastest available method\n *\n- * @hw: pointer to hardware structure\n- * @offset: offset of word in EEPROM to read\n- * @words: number of words\n- * @data: word(s) read from the EEPROM\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in EEPROM to read\n+ * @words: number of words\n+ * @data: word(s) read from the EEPROM\n *\n- * Retrieves 16 bit word(s) read from EEPROM\n+ * Retrieves 16 bit word(s) read from EEPROM\n **/\n STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,\n \t\t\t\t\t u16 words, u16 *data)\n@@ -2405,14 +2405,14 @@ STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,\n }\n \n /**\n- * ixgbe_read_eeprom_82599 - Read EEPROM word using\n- * fastest available method\n+ * ixgbe_read_eeprom_82599 - Read EEPROM word using\n+ * fastest available method\n *\n- * @hw: pointer to hardware structure\n- * @offset: offset of word in the EEPROM to read\n- * @data: word read from the EEPROM\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to read\n+ * @data: word read from the EEPROM\n *\n- * Reads a 16 bit word from the EEPROM\n+ * Reads a 16 bit word from the EEPROM\n **/\n STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,\n \t\t\t\t u16 offset, u16 *data)\n@@ -2438,7 +2438,7 @@ STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,\n /**\n * ixgbe_reset_pipeline_82599 - perform pipeline reset\n *\n- * @hw: pointer to hardware structure\n+ * @hw: pointer to hardware structure\n *\n * Reset pipeline by asserting Restart_AN together with LMS change to ensure\n * full pipeline reset. This function assumes the SW/FW lock is held.\n@@ -2487,14 +2487,14 @@ s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C\n- * @hw: pointer to hardware structure\n- * @byte_offset: byte offset to read\n- * @dev_addr: address to read from\n- * @data: value read\n+ * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: byte offset to read\n+ * @dev_addr: address to read from\n+ * @data: value read\n *\n- * Performs byte read operation to SFP module's EEPROM over I2C interface at\n- * a specified device address.\n+ * Performs byte read operation to SFP module's EEPROM over I2C interface at\n+ * a specified device address.\n **/\n STATIC s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\t\tu8 dev_addr, u8 *data)\n@@ -2545,14 +2545,14 @@ STATIC s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,\n }\n \n /**\n- * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C\n- * @hw: pointer to hardware structure\n- * @byte_offset: byte offset to write\n- * @dev_addr: address to read from\n- * @data: value to write\n+ * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: byte offset to write\n+ * @dev_addr: address to read from\n+ * @data: value to write\n *\n- * Performs byte write operation to SFP module's EEPROM over I2C interface at\n- * a specified device address.\n+ * Performs byte write operation to SFP module's EEPROM over I2C interface at\n+ * a specified device address.\n **/\n STATIC s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\t\t u8 dev_addr, u8 data)\ndiff --git a/drivers/net/ixgbe/base/ixgbe_api.c b/drivers/net/ixgbe/base/ixgbe_api.c\nindex 4d61513ec..8ac54af12 100644\n--- a/drivers/net/ixgbe/base/ixgbe_api.c\n+++ b/drivers/net/ixgbe/base/ixgbe_api.c\n@@ -41,16 +41,16 @@ void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map)\n }\n \n /**\n- * ixgbe_init_shared_code - Initialize the shared code\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_shared_code - Initialize the shared code\n+ * @hw: pointer to hardware structure\n *\n- * This will assign function pointers and assign the MAC type and PHY code.\n- * Does not touch the hardware. This function must be called prior to any\n- * other function in the shared code. The ixgbe_hw structure should be\n- * memset to 0 prior to calling this function. The following fields in\n- * hw structure should be filled in prior to calling this function:\n- * hw_addr, back, device_id, vendor_id, subsystem_device_id,\n- * subsystem_vendor_id, and revision_id\n+ * This will assign function pointers and assign the MAC type and PHY code.\n+ * Does not touch the hardware. This function must be called prior to any\n+ * other function in the shared code. The ixgbe_hw structure should be\n+ * memset to 0 prior to calling this function. The following fields in\n+ * hw structure should be filled in prior to calling this function:\n+ * hw_addr, back, device_id, vendor_id, subsystem_device_id,\n+ * subsystem_vendor_id, and revision_id\n **/\n s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)\n {\n@@ -112,11 +112,11 @@ s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_set_mac_type - Sets MAC type\n- * @hw: pointer to the HW structure\n+ * ixgbe_set_mac_type - Sets MAC type\n+ * @hw: pointer to the HW structure\n *\n- * This function sets the mac type of the adapter based on the\n- * vendor ID and device ID stored in the hw structure.\n+ * This function sets the mac type of the adapter based on the\n+ * vendor ID and device ID stored in the hw structure.\n **/\n s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)\n {\n@@ -235,10 +235,10 @@ s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_init_hw - Initialize the hardware\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_hw - Initialize the hardware\n+ * @hw: pointer to hardware structure\n *\n- * Initialize the hardware by resetting and then starting the hardware\n+ * Initialize the hardware by resetting and then starting the hardware\n **/\n s32 ixgbe_init_hw(struct ixgbe_hw *hw)\n {\n@@ -247,11 +247,11 @@ s32 ixgbe_init_hw(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_reset_hw - Performs a hardware reset\n- * @hw: pointer to hardware structure\n+ * ixgbe_reset_hw - Performs a hardware reset\n+ * @hw: pointer to hardware structure\n *\n- * Resets the hardware by resetting the transmit and receive units, masks and\n- * clears all interrupts, performs a PHY reset, and performs a MAC reset\n+ * Resets the hardware by resetting the transmit and receive units, masks and\n+ * clears all interrupts, performs a PHY reset, and performs a MAC reset\n **/\n s32 ixgbe_reset_hw(struct ixgbe_hw *hw)\n {\n@@ -260,14 +260,14 @@ s32 ixgbe_reset_hw(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_start_hw - Prepares hardware for Rx/Tx\n- * @hw: pointer to hardware structure\n+ * ixgbe_start_hw - Prepares hardware for Rx/Tx\n+ * @hw: pointer to hardware structure\n *\n- * Starts the hardware by filling the bus info structure and media type,\n- * clears all on chip counters, initializes receive address registers,\n- * multicast table, VLAN filter table, calls routine to setup link and\n- * flow control settings, and leaves transmit and receive units disabled\n- * and uninitialized.\n+ * Starts the hardware by filling the bus info structure and media type,\n+ * clears all on chip counters, initializes receive address registers,\n+ * multicast table, VLAN filter table, calls routine to setup link and\n+ * flow control settings, and leaves transmit and receive units disabled\n+ * and uninitialized.\n **/\n s32 ixgbe_start_hw(struct ixgbe_hw *hw)\n {\n@@ -276,12 +276,12 @@ s32 ixgbe_start_hw(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering,\n- * which is disabled by default in ixgbe_start_hw();\n+ * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering,\n+ * which is disabled by default in ixgbe_start_hw();\n *\n- * @hw: pointer to hardware structure\n+ * @hw: pointer to hardware structure\n *\n- * Enable relaxed ordering;\n+ * Enable relaxed ordering;\n **/\n void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw)\n {\n@@ -290,11 +290,11 @@ void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_clear_hw_cntrs - Clear hardware counters\n- * @hw: pointer to hardware structure\n+ * ixgbe_clear_hw_cntrs - Clear hardware counters\n+ * @hw: pointer to hardware structure\n *\n- * Clears all hardware statistics counters by reading them from the hardware\n- * Statistics counters are clear on read.\n+ * Clears all hardware statistics counters by reading them from the hardware\n+ * Statistics counters are clear on read.\n **/\n s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)\n {\n@@ -303,10 +303,10 @@ s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_get_media_type - Get media type\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_media_type - Get media type\n+ * @hw: pointer to hardware structure\n *\n- * Returns the media type (fiber, copper, backplane)\n+ * Returns the media type (fiber, copper, backplane)\n **/\n enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw)\n {\n@@ -315,14 +315,14 @@ enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_get_mac_addr - Get MAC address\n- * @hw: pointer to hardware structure\n- * @mac_addr: Adapter MAC address\n+ * ixgbe_get_mac_addr - Get MAC address\n+ * @hw: pointer to hardware structure\n+ * @mac_addr: Adapter MAC address\n *\n- * Reads the adapter's MAC address from the first Receive Address Register\n- * (RAR0) A reset of the adapter must have been performed prior to calling\n- * this function in order for the MAC address to have been loaded from the\n- * EEPROM into RAR0\n+ * Reads the adapter's MAC address from the first Receive Address Register\n+ * (RAR0) A reset of the adapter must have been performed prior to calling\n+ * this function in order for the MAC address to have been loaded from the\n+ * EEPROM into RAR0\n **/\n s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)\n {\n@@ -331,12 +331,12 @@ s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)\n }\n \n /**\n- * ixgbe_get_san_mac_addr - Get SAN MAC address\n- * @hw: pointer to hardware structure\n- * @san_mac_addr: SAN MAC address\n+ * ixgbe_get_san_mac_addr - Get SAN MAC address\n+ * @hw: pointer to hardware structure\n+ * @san_mac_addr: SAN MAC address\n *\n- * Reads the SAN MAC address from the EEPROM, if it's available. This is\n- * per-port, so set_lan_id() must be called before reading the addresses.\n+ * Reads the SAN MAC address from the EEPROM, if it's available. This is\n+ * per-port, so set_lan_id() must be called before reading the addresses.\n **/\n s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)\n {\n@@ -345,11 +345,11 @@ s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)\n }\n \n /**\n- * ixgbe_set_san_mac_addr - Write a SAN MAC address\n- * @hw: pointer to hardware structure\n- * @san_mac_addr: SAN MAC address\n+ * ixgbe_set_san_mac_addr - Write a SAN MAC address\n+ * @hw: pointer to hardware structure\n+ * @san_mac_addr: SAN MAC address\n *\n- * Writes A SAN MAC address to the EEPROM.\n+ * Writes A SAN MAC address to the EEPROM.\n **/\n s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)\n {\n@@ -358,11 +358,11 @@ s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)\n }\n \n /**\n- * ixgbe_get_device_caps - Get additional device capabilities\n- * @hw: pointer to hardware structure\n- * @device_caps: the EEPROM word for device capabilities\n+ * ixgbe_get_device_caps - Get additional device capabilities\n+ * @hw: pointer to hardware structure\n+ * @device_caps: the EEPROM word for device capabilities\n *\n- * Reads the extra device capabilities from the EEPROM\n+ * Reads the extra device capabilities from the EEPROM\n **/\n s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps)\n {\n@@ -371,13 +371,13 @@ s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps)\n }\n \n /**\n- * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM\n- * @hw: pointer to hardware structure\n- * @wwnn_prefix: the alternative WWNN prefix\n- * @wwpn_prefix: the alternative WWPN prefix\n+ * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM\n+ * @hw: pointer to hardware structure\n+ * @wwnn_prefix: the alternative WWNN prefix\n+ * @wwpn_prefix: the alternative WWPN prefix\n *\n- * This function will read the EEPROM from the alternative SAN MAC address\n- * block to check the support for the alternative WWNN/WWPN prefix support.\n+ * This function will read the EEPROM from the alternative SAN MAC address\n+ * block to check the support for the alternative WWNN/WWPN prefix support.\n **/\n s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,\n \t\t\t u16 *wwpn_prefix)\n@@ -388,11 +388,11 @@ s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,\n }\n \n /**\n- * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM\n- * @hw: pointer to hardware structure\n- * @bs: the fcoe boot status\n+ * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM\n+ * @hw: pointer to hardware structure\n+ * @bs: the fcoe boot status\n *\n- * This function will read the FCOE boot status from the iSCSI FCOE block\n+ * This function will read the FCOE boot status from the iSCSI FCOE block\n **/\n s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs)\n {\n@@ -402,10 +402,10 @@ s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs)\n }\n \n /**\n- * ixgbe_get_bus_info - Set PCI bus info\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_bus_info - Set PCI bus info\n+ * @hw: pointer to hardware structure\n *\n- * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure\n+ * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure\n **/\n s32 ixgbe_get_bus_info(struct ixgbe_hw *hw)\n {\n@@ -414,10 +414,10 @@ s32 ixgbe_get_bus_info(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_get_num_of_tx_queues - Get Tx queues\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_num_of_tx_queues - Get Tx queues\n+ * @hw: pointer to hardware structure\n *\n- * Returns the number of transmit queues for the given adapter.\n+ * Returns the number of transmit queues for the given adapter.\n **/\n u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw)\n {\n@@ -425,10 +425,10 @@ u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_get_num_of_rx_queues - Get Rx queues\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_num_of_rx_queues - Get Rx queues\n+ * @hw: pointer to hardware structure\n *\n- * Returns the number of receive queues for the given adapter.\n+ * Returns the number of receive queues for the given adapter.\n **/\n u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw)\n {\n@@ -436,13 +436,13 @@ u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_stop_adapter - Disable Rx/Tx units\n- * @hw: pointer to hardware structure\n+ * ixgbe_stop_adapter - Disable Rx/Tx units\n+ * @hw: pointer to hardware structure\n *\n- * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,\n- * disables transmit and receive units. The adapter_stopped flag is used by\n- * the shared code and drivers to determine if the adapter is in a stopped\n- * state and should not touch the hardware.\n+ * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,\n+ * disables transmit and receive units. The adapter_stopped flag is used by\n+ * the shared code and drivers to determine if the adapter is in a stopped\n+ * state and should not touch the hardware.\n **/\n s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)\n {\n@@ -451,12 +451,12 @@ s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_read_pba_string - Reads part number string from EEPROM\n- * @hw: pointer to hardware structure\n- * @pba_num: stores the part number string from the EEPROM\n- * @pba_num_size: part number string buffer length\n+ * ixgbe_read_pba_string - Reads part number string from EEPROM\n+ * @hw: pointer to hardware structure\n+ * @pba_num: stores the part number string from the EEPROM\n+ * @pba_num_size: part number string buffer length\n *\n- * Reads the part number string from the EEPROM.\n+ * Reads the part number string from the EEPROM.\n **/\n s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size)\n {\n@@ -464,11 +464,11 @@ s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size)\n }\n \n /**\n- * ixgbe_read_pba_num - Reads part number from EEPROM\n- * @hw: pointer to hardware structure\n- * @pba_num: stores the part number from the EEPROM\n+ * ixgbe_read_pba_num - Reads part number from EEPROM\n+ * @hw: pointer to hardware structure\n+ * @pba_num: stores the part number from the EEPROM\n *\n- * Reads the part number from the EEPROM.\n+ * Reads the part number from the EEPROM.\n **/\n s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num)\n {\n@@ -476,10 +476,10 @@ s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num)\n }\n \n /**\n- * ixgbe_identify_phy - Get PHY type\n- * @hw: pointer to hardware structure\n+ * ixgbe_identify_phy - Get PHY type\n+ * @hw: pointer to hardware structure\n *\n- * Determines the physical layer module found on the current adapter.\n+ * Determines the physical layer module found on the current adapter.\n **/\n s32 ixgbe_identify_phy(struct ixgbe_hw *hw)\n {\n@@ -494,8 +494,8 @@ s32 ixgbe_identify_phy(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_reset_phy - Perform a PHY reset\n- * @hw: pointer to hardware structure\n+ * ixgbe_reset_phy - Perform a PHY reset\n+ * @hw: pointer to hardware structure\n **/\n s32 ixgbe_reset_phy(struct ixgbe_hw *hw)\n {\n@@ -514,9 +514,9 @@ s32 ixgbe_reset_phy(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_get_phy_firmware_version -\n- * @hw: pointer to hardware structure\n- * @firmware_version: pointer to firmware version\n+ * ixgbe_get_phy_firmware_version -\n+ * @hw: pointer to hardware structure\n+ * @firmware_version: pointer to firmware version\n **/\n s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version)\n {\n@@ -529,13 +529,13 @@ s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version)\n }\n \n /**\n- * ixgbe_read_phy_reg - Read PHY register\n- * @hw: pointer to hardware structure\n- * @reg_addr: 32 bit address of PHY register to read\n- * @device_type: type of device you want to communicate with\n- * @phy_data: Pointer to read data from PHY register\n+ * ixgbe_read_phy_reg - Read PHY register\n+ * @hw: pointer to hardware structure\n+ * @reg_addr: 32 bit address of PHY register to read\n+ * @device_type: type of device you want to communicate with\n+ * @phy_data: Pointer to read data from PHY register\n *\n- * Reads a value from a specified PHY register\n+ * Reads a value from a specified PHY register\n **/\n s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,\n \t\t u16 *phy_data)\n@@ -548,13 +548,13 @@ s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,\n }\n \n /**\n- * ixgbe_write_phy_reg - Write PHY register\n- * @hw: pointer to hardware structure\n- * @reg_addr: 32 bit PHY register to write\n- * @device_type: type of device you want to communicate with\n- * @phy_data: Data to write to the PHY register\n+ * ixgbe_write_phy_reg - Write PHY register\n+ * @hw: pointer to hardware structure\n+ * @reg_addr: 32 bit PHY register to write\n+ * @device_type: type of device you want to communicate with\n+ * @phy_data: Data to write to the PHY register\n *\n- * Writes a value to specified PHY register\n+ * Writes a value to specified PHY register\n **/\n s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,\n \t\t\tu16 phy_data)\n@@ -567,10 +567,10 @@ s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,\n }\n \n /**\n- * ixgbe_setup_phy_link - Restart PHY autoneg\n- * @hw: pointer to hardware structure\n+ * ixgbe_setup_phy_link - Restart PHY autoneg\n+ * @hw: pointer to hardware structure\n *\n- * Restart autonegotiation and PHY and waits for completion.\n+ * Restart autonegotiation and PHY and waits for completion.\n **/\n s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)\n {\n@@ -593,13 +593,13 @@ s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_check_phy_link - Determine link and speed status\n- * @hw: pointer to hardware structure\n- * @speed: link speed\n- * @link_up: true when link is up\n+ * ixgbe_check_phy_link - Determine link and speed status\n+ * @hw: pointer to hardware structure\n+ * @speed: link speed\n+ * @link_up: true when link is up\n *\n- * Reads a PHY register to determine if link is up and the current speed for\n- * the PHY.\n+ * Reads a PHY register to determine if link is up and the current speed for\n+ * the PHY.\n **/\n s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n \t\t\t bool *link_up)\n@@ -609,12 +609,12 @@ s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n }\n \n /**\n- * ixgbe_setup_phy_link_speed - Set auto advertise\n- * @hw: pointer to hardware structure\n- * @speed: new link speed\n- * @autoneg_wait_to_complete: true when waiting for completion is needed\n+ * ixgbe_setup_phy_link_speed - Set auto advertise\n+ * @hw: pointer to hardware structure\n+ * @speed: new link speed\n+ * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n- * Sets the auto advertised capabilities\n+ * Sets the auto advertised capabilities\n **/\n s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n \t\t\t bool autoneg_wait_to_complete)\n@@ -636,13 +636,13 @@ s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on)\n }\n \n /**\n- * ixgbe_check_link - Get link and speed status\n- * @hw: pointer to hardware structure\n- * @speed: pointer to link speed\n- * @link_up: true when link is up\n- * @link_up_wait_to_complete: bool used to wait for link up or not\n+ * ixgbe_check_link - Get link and speed status\n+ * @hw: pointer to hardware structure\n+ * @speed: pointer to link speed\n+ * @link_up: true when link is up\n+ * @link_up_wait_to_complete: bool used to wait for link up or not\n *\n- * Reads the links register to determine if link is up and the current speed\n+ * Reads the links register to determine if link is up and the current speed\n **/\n s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n \t\t bool *link_up, bool link_up_wait_to_complete)\n@@ -653,10 +653,10 @@ s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n }\n \n /**\n- * ixgbe_disable_tx_laser - Disable Tx laser\n- * @hw: pointer to hardware structure\n+ * ixgbe_disable_tx_laser - Disable Tx laser\n+ * @hw: pointer to hardware structure\n *\n- * If the driver needs to disable the laser on SFI optics.\n+ * If the driver needs to disable the laser on SFI optics.\n **/\n void ixgbe_disable_tx_laser(struct ixgbe_hw *hw)\n {\n@@ -665,10 +665,10 @@ void ixgbe_disable_tx_laser(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_enable_tx_laser - Enable Tx laser\n- * @hw: pointer to hardware structure\n+ * ixgbe_enable_tx_laser - Enable Tx laser\n+ * @hw: pointer to hardware structure\n *\n- * If the driver needs to enable the laser on SFI optics.\n+ * If the driver needs to enable the laser on SFI optics.\n **/\n void ixgbe_enable_tx_laser(struct ixgbe_hw *hw)\n {\n@@ -677,12 +677,12 @@ void ixgbe_enable_tx_laser(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_flap_tx_laser - flap Tx laser to start autotry process\n- * @hw: pointer to hardware structure\n+ * ixgbe_flap_tx_laser - flap Tx laser to start autotry process\n+ * @hw: pointer to hardware structure\n *\n- * When the driver changes the link speeds that it can support then\n- * flap the tx laser to alert the link partner to start autotry\n- * process on its end.\n+ * When the driver changes the link speeds that it can support then\n+ * flap the tx laser to alert the link partner to start autotry\n+ * process on its end.\n **/\n void ixgbe_flap_tx_laser(struct ixgbe_hw *hw)\n {\n@@ -691,13 +691,13 @@ void ixgbe_flap_tx_laser(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_setup_link - Set link speed\n- * @hw: pointer to hardware structure\n- * @speed: new link speed\n- * @autoneg_wait_to_complete: true when waiting for completion is needed\n+ * ixgbe_setup_link - Set link speed\n+ * @hw: pointer to hardware structure\n+ * @speed: new link speed\n+ * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n- * Configures link settings. Restarts the link.\n- * Performs autonegotiation if needed.\n+ * Configures link settings. Restarts the link.\n+ * Performs autonegotiation if needed.\n **/\n s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n \t\t bool autoneg_wait_to_complete)\n@@ -708,13 +708,13 @@ s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n }\n \n /**\n- * ixgbe_setup_mac_link - Set link speed\n- * @hw: pointer to hardware structure\n- * @speed: new link speed\n- * @autoneg_wait_to_complete: true when waiting for completion is needed\n+ * ixgbe_setup_mac_link - Set link speed\n+ * @hw: pointer to hardware structure\n+ * @speed: new link speed\n+ * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n- * Configures link settings. Restarts the link.\n- * Performs autonegotiation if needed.\n+ * Configures link settings. Restarts the link.\n+ * Performs autonegotiation if needed.\n **/\n s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n \t\t\t bool autoneg_wait_to_complete)\n@@ -725,12 +725,12 @@ s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n }\n \n /**\n- * ixgbe_get_link_capabilities - Returns link capabilities\n- * @hw: pointer to hardware structure\n- * @speed: link speed capabilities\n- * @autoneg: true when autoneg or autotry is enabled\n+ * ixgbe_get_link_capabilities - Returns link capabilities\n+ * @hw: pointer to hardware structure\n+ * @speed: link speed capabilities\n+ * @autoneg: true when autoneg or autotry is enabled\n *\n- * Determines the link capabilities of the current configuration.\n+ * Determines the link capabilities of the current configuration.\n **/\n s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n \t\t\t\tbool *autoneg)\n@@ -740,11 +740,11 @@ s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n }\n \n /**\n- * ixgbe_led_on - Turn on LEDs\n- * @hw: pointer to hardware structure\n- * @index: led number to turn on\n+ * ixgbe_led_on - Turn on LEDs\n+ * @hw: pointer to hardware structure\n+ * @index: led number to turn on\n *\n- * Turns on the software controllable LEDs.\n+ * Turns on the software controllable LEDs.\n **/\n s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)\n {\n@@ -753,11 +753,11 @@ s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)\n }\n \n /**\n- * ixgbe_led_off - Turn off LEDs\n- * @hw: pointer to hardware structure\n- * @index: led number to turn off\n+ * ixgbe_led_off - Turn off LEDs\n+ * @hw: pointer to hardware structure\n+ * @index: led number to turn off\n *\n- * Turns off the software controllable LEDs.\n+ * Turns off the software controllable LEDs.\n **/\n s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index)\n {\n@@ -766,11 +766,11 @@ s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index)\n }\n \n /**\n- * ixgbe_blink_led_start - Blink LEDs\n- * @hw: pointer to hardware structure\n- * @index: led number to blink\n+ * ixgbe_blink_led_start - Blink LEDs\n+ * @hw: pointer to hardware structure\n+ * @index: led number to blink\n *\n- * Blink LED based on index.\n+ * Blink LED based on index.\n **/\n s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index)\n {\n@@ -779,11 +779,11 @@ s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index)\n }\n \n /**\n- * ixgbe_blink_led_stop - Stop blinking LEDs\n- * @hw: pointer to hardware structure\n- * @index: led number to stop\n+ * ixgbe_blink_led_stop - Stop blinking LEDs\n+ * @hw: pointer to hardware structure\n+ * @index: led number to stop\n *\n- * Stop blinking LED based on index.\n+ * Stop blinking LED based on index.\n **/\n s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index)\n {\n@@ -792,11 +792,11 @@ s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index)\n }\n \n /**\n- * ixgbe_init_eeprom_params - Initialize EEPROM parameters\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_eeprom_params - Initialize EEPROM parameters\n+ * @hw: pointer to hardware structure\n *\n- * Initializes the EEPROM parameters ixgbe_eeprom_info within the\n- * ixgbe_hw struct in order to set up EEPROM access.\n+ * Initializes the EEPROM parameters ixgbe_eeprom_info within the\n+ * ixgbe_hw struct in order to set up EEPROM access.\n **/\n s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw)\n {\n@@ -806,14 +806,14 @@ s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw)\n \n \n /**\n- * ixgbe_write_eeprom - Write word to EEPROM\n- * @hw: pointer to hardware structure\n- * @offset: offset within the EEPROM to be written to\n- * @data: 16 bit word to be written to the EEPROM\n+ * ixgbe_write_eeprom - Write word to EEPROM\n+ * @hw: pointer to hardware structure\n+ * @offset: offset within the EEPROM to be written to\n+ * @data: 16 bit word to be written to the EEPROM\n *\n- * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not\n- * called after this function, the EEPROM will most likely contain an\n- * invalid checksum.\n+ * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not\n+ * called after this function, the EEPROM will most likely contain an\n+ * invalid checksum.\n **/\n s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data)\n {\n@@ -822,15 +822,15 @@ s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data)\n }\n \n /**\n- * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM\n- * @hw: pointer to hardware structure\n- * @offset: offset within the EEPROM to be written to\n- * @data: 16 bit word(s) to be written to the EEPROM\n- * @words: number of words\n+ * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM\n+ * @hw: pointer to hardware structure\n+ * @offset: offset within the EEPROM to be written to\n+ * @data: 16 bit word(s) to be written to the EEPROM\n+ * @words: number of words\n *\n- * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not\n- * called after this function, the EEPROM will most likely contain an\n- * invalid checksum.\n+ * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not\n+ * called after this function, the EEPROM will most likely contain an\n+ * invalid checksum.\n **/\n s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words,\n \t\t\t u16 *data)\n@@ -841,12 +841,12 @@ s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words,\n }\n \n /**\n- * ixgbe_read_eeprom - Read word from EEPROM\n- * @hw: pointer to hardware structure\n- * @offset: offset within the EEPROM to be read\n- * @data: read 16 bit value from EEPROM\n+ * ixgbe_read_eeprom - Read word from EEPROM\n+ * @hw: pointer to hardware structure\n+ * @offset: offset within the EEPROM to be read\n+ * @data: read 16 bit value from EEPROM\n *\n- * Reads 16 bit value from EEPROM\n+ * Reads 16 bit value from EEPROM\n **/\n s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)\n {\n@@ -855,13 +855,13 @@ s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)\n }\n \n /**\n- * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM\n- * @hw: pointer to hardware structure\n- * @offset: offset within the EEPROM to be read\n- * @data: read 16 bit word(s) from EEPROM\n- * @words: number of words\n+ * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM\n+ * @hw: pointer to hardware structure\n+ * @offset: offset within the EEPROM to be read\n+ * @data: read 16 bit word(s) from EEPROM\n+ * @words: number of words\n *\n- * Reads 16 bit word(s) from EEPROM\n+ * Reads 16 bit word(s) from EEPROM\n **/\n s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,\n \t\t\t u16 words, u16 *data)\n@@ -872,11 +872,11 @@ s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,\n }\n \n /**\n- * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum\n- * @hw: pointer to hardware structure\n- * @checksum_val: calculated checksum\n+ * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum\n+ * @hw: pointer to hardware structure\n+ * @checksum_val: calculated checksum\n *\n- * Performs checksum calculation and validates the EEPROM checksum\n+ * Performs checksum calculation and validates the EEPROM checksum\n **/\n s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)\n {\n@@ -885,8 +885,8 @@ s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)\n }\n \n /**\n- * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum\n- * @hw: pointer to hardware structure\n+ * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum\n+ * @hw: pointer to hardware structure\n **/\n s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw)\n {\n@@ -895,13 +895,13 @@ s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_insert_mac_addr - Find a RAR for this mac address\n- * @hw: pointer to hardware structure\n- * @addr: Address to put into receive address register\n- * @vmdq: VMDq pool to assign\n+ * ixgbe_insert_mac_addr - Find a RAR for this mac address\n+ * @hw: pointer to hardware structure\n+ * @addr: Address to put into receive address register\n+ * @vmdq: VMDq pool to assign\n *\n- * Puts an ethernet address into a receive address register, or\n- * finds the rar that it is aleady in; adds to the pool list\n+ * Puts an ethernet address into a receive address register, or\n+ * finds the rar that it is aleady in; adds to the pool list\n **/\n s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)\n {\n@@ -911,14 +911,14 @@ s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)\n }\n \n /**\n- * ixgbe_set_rar - Set Rx address register\n- * @hw: pointer to hardware structure\n- * @index: Receive address register to write\n- * @addr: Address to put into receive address register\n- * @vmdq: VMDq \"set\"\n- * @enable_addr: set flag that address is active\n+ * ixgbe_set_rar - Set Rx address register\n+ * @hw: pointer to hardware structure\n+ * @index: Receive address register to write\n+ * @addr: Address to put into receive address register\n+ * @vmdq: VMDq \"set\"\n+ * @enable_addr: set flag that address is active\n *\n- * Puts an ethernet address into a receive address register.\n+ * Puts an ethernet address into a receive address register.\n **/\n s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,\n \t\t u32 enable_addr)\n@@ -928,11 +928,11 @@ s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,\n }\n \n /**\n- * ixgbe_clear_rar - Clear Rx address register\n- * @hw: pointer to hardware structure\n- * @index: Receive address register to write\n+ * ixgbe_clear_rar - Clear Rx address register\n+ * @hw: pointer to hardware structure\n+ * @index: Receive address register to write\n *\n- * Puts an ethernet address into a receive address register.\n+ * Puts an ethernet address into a receive address register.\n **/\n s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index)\n {\n@@ -941,10 +941,10 @@ s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index)\n }\n \n /**\n- * ixgbe_set_vmdq - Associate a VMDq index with a receive address\n- * @hw: pointer to hardware structure\n- * @rar: receive address register index to associate with VMDq index\n- * @vmdq: VMDq set or pool index\n+ * ixgbe_set_vmdq - Associate a VMDq index with a receive address\n+ * @hw: pointer to hardware structure\n+ * @rar: receive address register index to associate with VMDq index\n+ * @vmdq: VMDq set or pool index\n **/\n s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n {\n@@ -954,9 +954,9 @@ s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n }\n \n /**\n- * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address\n- * @hw: pointer to hardware structure\n- * @vmdq: VMDq default pool index\n+ * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address\n+ * @hw: pointer to hardware structure\n+ * @vmdq: VMDq default pool index\n **/\n s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq)\n {\n@@ -965,10 +965,10 @@ s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq)\n }\n \n /**\n- * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address\n- * @hw: pointer to hardware structure\n- * @rar: receive address register index to disassociate with VMDq index\n- * @vmdq: VMDq set or pool index\n+ * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address\n+ * @hw: pointer to hardware structure\n+ * @rar: receive address register index to disassociate with VMDq index\n+ * @vmdq: VMDq set or pool index\n **/\n s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n {\n@@ -977,12 +977,12 @@ s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n }\n \n /**\n- * ixgbe_init_rx_addrs - Initializes receive address filters.\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_rx_addrs - Initializes receive address filters.\n+ * @hw: pointer to hardware structure\n *\n- * Places the MAC address in receive address register 0 and clears the rest\n- * of the receive address registers. Clears the multicast table. Assumes\n- * the receiver is in reset when the routine is called.\n+ * Places the MAC address in receive address register 0 and clears the rest\n+ * of the receive address registers. Clears the multicast table. Assumes\n+ * the receiver is in reset when the routine is called.\n **/\n s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)\n {\n@@ -991,8 +991,8 @@ s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_get_num_rx_addrs - Returns the number of RAR entries.\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_num_rx_addrs - Returns the number of RAR entries.\n+ * @hw: pointer to hardware structure\n **/\n u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw)\n {\n@@ -1000,15 +1000,15 @@ u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses\n- * @hw: pointer to hardware structure\n- * @addr_list: the list of new multicast addresses\n- * @addr_count: number of addresses\n- * @func: iterator function to walk the multicast address list\n+ * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses\n+ * @hw: pointer to hardware structure\n+ * @addr_list: the list of new multicast addresses\n+ * @addr_count: number of addresses\n+ * @func: iterator function to walk the multicast address list\n *\n- * The given list replaces any existing list. Clears the secondary addrs from\n- * receive address registers. Uses unused receive address registers for the\n- * first secondary addresses, and falls back to promiscuous mode as needed.\n+ * The given list replaces any existing list. Clears the secondary addrs from\n+ * receive address registers. Uses unused receive address registers for the\n+ * first secondary addresses, and falls back to promiscuous mode as needed.\n **/\n s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,\n \t\t\t u32 addr_count, ixgbe_mc_addr_itr func)\n@@ -1019,17 +1019,17 @@ s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,\n }\n \n /**\n- * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses\n- * @hw: pointer to hardware structure\n- * @mc_addr_list: the list of new multicast addresses\n- * @mc_addr_count: number of addresses\n- * @func: iterator function to walk the multicast address list\n- * @clear: flag, when set clears the table beforehand\n+ * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses\n+ * @hw: pointer to hardware structure\n+ * @mc_addr_list: the list of new multicast addresses\n+ * @mc_addr_count: number of addresses\n+ * @func: iterator function to walk the multicast address list\n+ * @clear: flag, when set clears the table beforehand\n *\n- * The given list replaces any existing list. Clears the MC addrs from receive\n- * address registers and the multicast table. Uses unused receive address\n- * registers for the first multicast addresses, and hashes the rest into the\n- * multicast table.\n+ * The given list replaces any existing list. Clears the MC addrs from receive\n+ * address registers and the multicast table. Uses unused receive address\n+ * registers for the first multicast addresses, and hashes the rest into the\n+ * multicast table.\n **/\n s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,\n \t\t\t u32 mc_addr_count, ixgbe_mc_addr_itr func,\n@@ -1041,10 +1041,10 @@ s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,\n }\n \n /**\n- * ixgbe_enable_mc - Enable multicast address in RAR\n- * @hw: pointer to hardware structure\n+ * ixgbe_enable_mc - Enable multicast address in RAR\n+ * @hw: pointer to hardware structure\n *\n- * Enables multicast address in RAR and the use of the multicast hash table.\n+ * Enables multicast address in RAR and the use of the multicast hash table.\n **/\n s32 ixgbe_enable_mc(struct ixgbe_hw *hw)\n {\n@@ -1053,10 +1053,10 @@ s32 ixgbe_enable_mc(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_disable_mc - Disable multicast address in RAR\n- * @hw: pointer to hardware structure\n+ * ixgbe_disable_mc - Disable multicast address in RAR\n+ * @hw: pointer to hardware structure\n *\n- * Disables multicast address in RAR and the use of the multicast hash table.\n+ * Disables multicast address in RAR and the use of the multicast hash table.\n **/\n s32 ixgbe_disable_mc(struct ixgbe_hw *hw)\n {\n@@ -1065,10 +1065,10 @@ s32 ixgbe_disable_mc(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_clear_vfta - Clear VLAN filter table\n- * @hw: pointer to hardware structure\n+ * ixgbe_clear_vfta - Clear VLAN filter table\n+ * @hw: pointer to hardware structure\n *\n- * Clears the VLAN filer table, and the VMDq index associated with the filter\n+ * Clears the VLAN filer table, and the VMDq index associated with the filter\n **/\n s32 ixgbe_clear_vfta(struct ixgbe_hw *hw)\n {\n@@ -1077,14 +1077,14 @@ s32 ixgbe_clear_vfta(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_set_vfta - Set VLAN filter table\n- * @hw: pointer to hardware structure\n- * @vlan: VLAN id to write to VLAN filter\n- * @vind: VMDq output index that maps queue to VLAN id in VLVFB\n- * @vlan_on: boolean flag to turn on/off VLAN\n- * @vlvf_bypass: boolean flag indicating updating the default pool is okay\n+ * ixgbe_set_vfta - Set VLAN filter table\n+ * @hw: pointer to hardware structure\n+ * @vlan: VLAN id to write to VLAN filter\n+ * @vind: VMDq output index that maps queue to VLAN id in VLVFB\n+ * @vlan_on: boolean flag to turn on/off VLAN\n+ * @vlvf_bypass: boolean flag indicating updating the default pool is okay\n *\n- * Turn on/off specified VLAN in the VLAN filter table.\n+ * Turn on/off specified VLAN in the VLAN filter table.\n **/\n s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,\n \t\t bool vlvf_bypass)\n@@ -1094,17 +1094,17 @@ s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,\n }\n \n /**\n- * ixgbe_set_vlvf - Set VLAN Pool Filter\n- * @hw: pointer to hardware structure\n- * @vlan: VLAN id to write to VLAN filter\n- * @vind: VMDq output index that maps queue to VLAN id in VLVFB\n- * @vlan_on: boolean flag to turn on/off VLAN in VLVF\n- * @vfta_delta: pointer to the difference between the current value of VFTA\n+ * ixgbe_set_vlvf - Set VLAN Pool Filter\n+ * @hw: pointer to hardware structure\n+ * @vlan: VLAN id to write to VLAN filter\n+ * @vind: VMDq output index that maps queue to VLAN id in VLVFB\n+ * @vlan_on: boolean flag to turn on/off VLAN in VLVF\n+ * @vfta_delta: pointer to the difference between the current value of VFTA\n *\t\t and the desired value\n- * @vfta: the desired value of the VFTA\n- * @vlvf_bypass: boolean flag indicating updating the default pool is okay\n+ * @vfta: the desired value of the VFTA\n+ * @vlvf_bypass: boolean flag indicating updating the default pool is okay\n *\n- * Turn on/off specified bit in VLVF table.\n+ * Turn on/off specified bit in VLVF table.\n **/\n s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,\n \t\t u32 *vfta_delta, u32 vfta, bool vlvf_bypass)\n@@ -1115,11 +1115,11 @@ s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,\n }\n \n /**\n- * ixgbe_toggle_txdctl - Toggle VF's queues\n- * @hw: pointer to hardware structure\n- * @vind: VMDq pool index\n+ * ixgbe_toggle_txdctl - Toggle VF's queues\n+ * @hw: pointer to hardware structure\n+ * @vind: VMDq pool index\n *\n- * Enable and disable each queue in VF.\n+ * Enable and disable each queue in VF.\n */\n s32 ixgbe_toggle_txdctl(struct ixgbe_hw *hw, u32 vind)\n {\n@@ -1128,10 +1128,10 @@ s32 ixgbe_toggle_txdctl(struct ixgbe_hw *hw, u32 vind)\n }\n \n /**\n- * ixgbe_fc_enable - Enable flow control\n- * @hw: pointer to hardware structure\n+ * ixgbe_fc_enable - Enable flow control\n+ * @hw: pointer to hardware structure\n *\n- * Configures the flow control settings based on SW configuration.\n+ * Configures the flow control settings based on SW configuration.\n **/\n s32 ixgbe_fc_enable(struct ixgbe_hw *hw)\n {\n@@ -1140,10 +1140,10 @@ s32 ixgbe_fc_enable(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_setup_fc - Set up flow control\n- * @hw: pointer to hardware structure\n+ * ixgbe_setup_fc - Set up flow control\n+ * @hw: pointer to hardware structure\n *\n- * Called at init time to set up flow control.\n+ * Called at init time to set up flow control.\n **/\n s32 ixgbe_setup_fc(struct ixgbe_hw *hw)\n {\n@@ -1171,10 +1171,10 @@ s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,\n \n \n /**\n- * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data\n+ * @hw: pointer to hardware structure\n *\n- * Updates the temperatures in mac.thermal_sensor_data\n+ * Updates the temperatures in mac.thermal_sensor_data\n **/\n s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw)\n {\n@@ -1183,10 +1183,10 @@ s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds\n+ * @hw: pointer to hardware structure\n *\n- * Inits the thermal sensor thresholds according to the NVM map\n+ * Inits the thermal sensor thresholds according to the NVM map\n **/\n s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw)\n {\n@@ -1195,11 +1195,11 @@ s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_dmac_config - Configure DMA Coalescing registers.\n- * @hw: pointer to hardware structure\n+ * ixgbe_dmac_config - Configure DMA Coalescing registers.\n+ * @hw: pointer to hardware structure\n *\n- * Configure DMA coalescing. If enabling dmac, dmac is activated.\n- * When disabling dmac, dmac enable dmac bit is cleared.\n+ * Configure DMA coalescing. If enabling dmac, dmac is activated.\n+ * When disabling dmac, dmac enable dmac bit is cleared.\n **/\n s32 ixgbe_dmac_config(struct ixgbe_hw *hw)\n {\n@@ -1208,10 +1208,10 @@ s32 ixgbe_dmac_config(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers.\n- * @hw: pointer to hardware structure\n+ * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers.\n+ * @hw: pointer to hardware structure\n *\n- * Disables dmac, updates per TC settings, and then enable dmac.\n+ * Disables dmac, updates per TC settings, and then enable dmac.\n **/\n s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw)\n {\n@@ -1220,11 +1220,11 @@ s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers.\n- * @hw: pointer to hardware structure\n+ * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers.\n+ * @hw: pointer to hardware structure\n *\n- * Configure DMA coalescing threshold per TC and set high priority bit for\n- * FCOE TC. The dmac enable bit must be cleared before configuring.\n+ * Configure DMA coalescing threshold per TC and set high priority bit for\n+ * FCOE TC. The dmac enable bit must be cleared before configuring.\n **/\n s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw)\n {\n@@ -1233,13 +1233,13 @@ s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_setup_eee - Enable/disable EEE support\n- * @hw: pointer to the HW structure\n- * @enable_eee: boolean flag to enable EEE\n+ * ixgbe_setup_eee - Enable/disable EEE support\n+ * @hw: pointer to the HW structure\n+ * @enable_eee: boolean flag to enable EEE\n *\n- * Enable/disable EEE based on enable_ee flag.\n- * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C\n- * are modified.\n+ * Enable/disable EEE based on enable_ee flag.\n+ * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C\n+ * are modified.\n *\n **/\n s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee)\n@@ -1262,10 +1262,10 @@ void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable,\n }\n \n /**\n- * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing\n- * @hw: pointer to hardware structure\n- * @enable: enable or disable switch for Ethertype anti-spoofing\n- * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing\n+ * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing\n+ * @hw: pointer to hardware structure\n+ * @enable: enable or disable switch for Ethertype anti-spoofing\n+ * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing\n *\n **/\n void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)\n@@ -1275,13 +1275,13 @@ void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)\n }\n \n /**\n- * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register\n- * @hw: pointer to hardware structure\n- * @reg_addr: 32 bit address of PHY register to read\n- * @device_type: type of device you want to communicate with\n- * @phy_data: Pointer to read data from PHY register\n+ * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register\n+ * @hw: pointer to hardware structure\n+ * @reg_addr: 32 bit address of PHY register to read\n+ * @device_type: type of device you want to communicate with\n+ * @phy_data: Pointer to read data from PHY register\n *\n- * Reads a value from a specified PHY register\n+ * Reads a value from a specified PHY register\n **/\n s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,\n \t\t\t u32 device_type, u32 *phy_data)\n@@ -1291,13 +1291,13 @@ s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,\n }\n \n /**\n- * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband\n- * @hw: pointer to hardware structure\n- * @reg_addr: 32 bit PHY register to write\n- * @device_type: type of device you want to communicate with\n- * @phy_data: Data to write to the PHY register\n+ * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband\n+ * @hw: pointer to hardware structure\n+ * @reg_addr: 32 bit PHY register to write\n+ * @device_type: type of device you want to communicate with\n+ * @phy_data: Data to write to the PHY register\n *\n- * Writes a value to specified PHY register\n+ * Writes a value to specified PHY register\n **/\n s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,\n \t\t\t u32 device_type, u32 phy_data)\n@@ -1307,8 +1307,8 @@ s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,\n }\n \n /**\n- * ixgbe_disable_mdd - Disable malicious driver detection\n- * @hw: pointer to hardware structure\n+ * ixgbe_disable_mdd - Disable malicious driver detection\n+ * @hw: pointer to hardware structure\n *\n **/\n void ixgbe_disable_mdd(struct ixgbe_hw *hw)\n@@ -1318,8 +1318,8 @@ void ixgbe_disable_mdd(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_enable_mdd - Enable malicious driver detection\n- * @hw: pointer to hardware structure\n+ * ixgbe_enable_mdd - Enable malicious driver detection\n+ * @hw: pointer to hardware structure\n *\n **/\n void ixgbe_enable_mdd(struct ixgbe_hw *hw)\n@@ -1329,9 +1329,9 @@ void ixgbe_enable_mdd(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_mdd_event - Handle malicious driver detection event\n- * @hw: pointer to hardware structure\n- * @vf_bitmap: vf bitmap of malicious vfs\n+ * ixgbe_mdd_event - Handle malicious driver detection event\n+ * @hw: pointer to hardware structure\n+ * @vf_bitmap: vf bitmap of malicious vfs\n *\n **/\n void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap)\n@@ -1341,10 +1341,10 @@ void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap)\n }\n \n /**\n- * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver\n- * detection event\n- * @hw: pointer to hardware structure\n- * @vf: vf index\n+ * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver\n+ * detection event\n+ * @hw: pointer to hardware structure\n+ * @vf: vf index\n *\n **/\n void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf)\n@@ -1354,8 +1354,8 @@ void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf)\n }\n \n /**\n- * ixgbe_fw_recovery_mode - Check if in FW NVM recovery mode\n- * @hw: pointer to hardware structure\n+ * ixgbe_fw_recovery_mode - Check if in FW NVM recovery mode\n+ * @hw: pointer to hardware structure\n *\n **/\n bool ixgbe_fw_recovery_mode(struct ixgbe_hw *hw)\n@@ -1366,8 +1366,8 @@ bool ixgbe_fw_recovery_mode(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_enter_lplu - Transition to low power states\n- * @hw: pointer to hardware structure\n+ * ixgbe_enter_lplu - Transition to low power states\n+ * @hw: pointer to hardware structure\n *\n * Configures Low Power Link Up on transition to low power states\n * (from D0 to non-D0).\n@@ -1396,12 +1396,12 @@ s32 ixgbe_handle_lasi(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_read_analog_reg8 - Reads 8 bit analog register\n- * @hw: pointer to hardware structure\n- * @reg: analog register to read\n- * @val: read value\n+ * ixgbe_read_analog_reg8 - Reads 8 bit analog register\n+ * @hw: pointer to hardware structure\n+ * @reg: analog register to read\n+ * @val: read value\n *\n- * Performs write operation to analog register specified.\n+ * Performs write operation to analog register specified.\n **/\n s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)\n {\n@@ -1410,12 +1410,12 @@ s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)\n }\n \n /**\n- * ixgbe_write_analog_reg8 - Writes 8 bit analog register\n- * @hw: pointer to hardware structure\n- * @reg: analog register to write\n- * @val: value to write\n+ * ixgbe_write_analog_reg8 - Writes 8 bit analog register\n+ * @hw: pointer to hardware structure\n+ * @reg: analog register to write\n+ * @val: value to write\n *\n- * Performs write operation to Atlas analog register specified.\n+ * Performs write operation to Atlas analog register specified.\n **/\n s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)\n {\n@@ -1424,11 +1424,11 @@ s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)\n }\n \n /**\n- * ixgbe_init_uta_tables - Initializes Unicast Table Arrays.\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_uta_tables - Initializes Unicast Table Arrays.\n+ * @hw: pointer to hardware structure\n *\n- * Initializes the Unicast Table Arrays to zero on device load. This\n- * is part of the Rx init addr execution path.\n+ * Initializes the Unicast Table Arrays to zero on device load. This\n+ * is part of the Rx init addr execution path.\n **/\n s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw)\n {\n@@ -1437,13 +1437,13 @@ s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address\n- * @hw: pointer to hardware structure\n- * @byte_offset: byte offset to read\n- * @dev_addr: I2C bus address to read from\n- * @data: value read\n+ * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: byte offset to read\n+ * @dev_addr: I2C bus address to read from\n+ * @data: value read\n *\n- * Performs byte read operation to SFP module's EEPROM over I2C interface.\n+ * Performs byte read operation to SFP module's EEPROM over I2C interface.\n **/\n s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,\n \t\t\tu8 *data)\n@@ -1453,13 +1453,13 @@ s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,\n }\n \n /**\n- * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address\n- * @hw: pointer to hardware structure\n- * @byte_offset: byte offset to read\n- * @dev_addr: I2C bus address to read from\n- * @data: value read\n+ * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: byte offset to read\n+ * @dev_addr: I2C bus address to read from\n+ * @data: value read\n *\n- * Performs byte read operation to SFP module's EEPROM over I2C interface.\n+ * Performs byte read operation to SFP module's EEPROM over I2C interface.\n **/\n s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\t\t u8 dev_addr, u8 *data)\n@@ -1500,14 +1500,14 @@ s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)\n }\n \n /**\n- * ixgbe_write_i2c_byte - Writes 8 bit word over I2C\n- * @hw: pointer to hardware structure\n- * @byte_offset: byte offset to write\n- * @dev_addr: I2C bus address to write to\n- * @data: value to write\n+ * ixgbe_write_i2c_byte - Writes 8 bit word over I2C\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: byte offset to write\n+ * @dev_addr: I2C bus address to write to\n+ * @data: value to write\n *\n- * Performs byte write operation to SFP module's EEPROM over I2C interface\n- * at a specified device address.\n+ * Performs byte write operation to SFP module's EEPROM over I2C interface\n+ * at a specified device address.\n **/\n s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,\n \t\t\t u8 data)\n@@ -1517,14 +1517,14 @@ s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,\n }\n \n /**\n- * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C\n- * @hw: pointer to hardware structure\n- * @byte_offset: byte offset to write\n- * @dev_addr: I2C bus address to write to\n- * @data: value to write\n+ * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: byte offset to write\n+ * @dev_addr: I2C bus address to write to\n+ * @data: value to write\n *\n- * Performs byte write operation to SFP module's EEPROM over I2C interface\n- * at a specified device address.\n+ * Performs byte write operation to SFP module's EEPROM over I2C interface\n+ * at a specified device address.\n **/\n s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\t\t u8 dev_addr, u8 data)\n@@ -1565,12 +1565,12 @@ s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)\n }\n \n /**\n- * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface\n- * @hw: pointer to hardware structure\n- * @byte_offset: EEPROM byte offset to write\n- * @eeprom_data: value to write\n+ * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: EEPROM byte offset to write\n+ * @eeprom_data: value to write\n *\n- * Performs byte write operation to SFP module's EEPROM over I2C interface.\n+ * Performs byte write operation to SFP module's EEPROM over I2C interface.\n **/\n s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw,\n \t\t\t u8 byte_offset, u8 eeprom_data)\n@@ -1581,12 +1581,12 @@ s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface\n- * @hw: pointer to hardware structure\n- * @byte_offset: EEPROM byte offset to read\n- * @eeprom_data: value read\n+ * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: EEPROM byte offset to read\n+ * @eeprom_data: value read\n *\n- * Performs byte read operation to SFP module's EEPROM over I2C interface.\n+ * Performs byte read operation to SFP module's EEPROM over I2C interface.\n **/\n s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)\n {\n@@ -1596,10 +1596,10 @@ s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)\n }\n \n /**\n- * ixgbe_get_supported_physical_layer - Returns physical layer type\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_supported_physical_layer - Returns physical layer type\n+ * @hw: pointer to hardware structure\n *\n- * Determines physical layer capabilities of the current configuration.\n+ * Determines physical layer capabilities of the current configuration.\n **/\n u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)\n {\n@@ -1608,11 +1608,11 @@ u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics\n- * @hw: pointer to hardware structure\n- * @regval: bitfield to write to the Rx DMA register\n+ * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics\n+ * @hw: pointer to hardware structure\n+ * @regval: bitfield to write to the Rx DMA register\n *\n- * Enables the Rx DMA unit of the device.\n+ * Enables the Rx DMA unit of the device.\n **/\n s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval)\n {\n@@ -1621,10 +1621,10 @@ s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval)\n }\n \n /**\n- * ixgbe_disable_sec_rx_path - Stops the receive data path\n- * @hw: pointer to hardware structure\n+ * ixgbe_disable_sec_rx_path - Stops the receive data path\n+ * @hw: pointer to hardware structure\n *\n- * Stops the receive data path.\n+ * Stops the receive data path.\n **/\n s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw)\n {\n@@ -1633,10 +1633,10 @@ s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_enable_sec_rx_path - Enables the receive data path\n- * @hw: pointer to hardware structure\n+ * ixgbe_enable_sec_rx_path - Enables the receive data path\n+ * @hw: pointer to hardware structure\n *\n- * Enables the receive data path.\n+ * Enables the receive data path.\n **/\n s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw)\n {\n@@ -1645,12 +1645,12 @@ s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore\n- * @hw: pointer to hardware structure\n- * @mask: Mask to specify which semaphore to acquire\n+ * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore\n+ * @hw: pointer to hardware structure\n+ * @mask: Mask to specify which semaphore to acquire\n *\n- * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified\n- * function (CSR, PHY0, PHY1, EEPROM, Flash)\n+ * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified\n+ * function (CSR, PHY0, PHY1, EEPROM, Flash)\n **/\n s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)\n {\n@@ -1659,12 +1659,12 @@ s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)\n }\n \n /**\n- * ixgbe_release_swfw_semaphore - Release SWFW semaphore\n- * @hw: pointer to hardware structure\n- * @mask: Mask to specify which semaphore to release\n+ * ixgbe_release_swfw_semaphore - Release SWFW semaphore\n+ * @hw: pointer to hardware structure\n+ * @mask: Mask to specify which semaphore to release\n *\n- * Releases the SWFW semaphore through SW_FW_SYNC register for the specified\n- * function (CSR, PHY0, PHY1, EEPROM, Flash)\n+ * Releases the SWFW semaphore through SW_FW_SYNC register for the specified\n+ * function (CSR, PHY0, PHY1, EEPROM, Flash)\n **/\n void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)\n {\n@@ -1673,13 +1673,13 @@ void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)\n }\n \n /**\n- * ixgbe_init_swfw_semaphore - Clean up SWFW semaphore\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_swfw_semaphore - Clean up SWFW semaphore\n+ * @hw: pointer to hardware structure\n *\n- * Attempts to acquire the SWFW semaphore through SW_FW_SYNC register.\n- * Regardless of whether is succeeds or not it then release the semaphore.\n- * This is function is called to recover from catastrophic failures that\n- * may have left the semaphore locked.\n+ * Attempts to acquire the SWFW semaphore through SW_FW_SYNC register.\n+ * Regardless of whether is succeeds or not it then release the semaphore.\n+ * This is function is called to recover from catastrophic failures that\n+ * may have left the semaphore locked.\n **/\n void ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw)\n {\n@@ -1701,11 +1701,11 @@ void ixgbe_enable_rx(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_set_rate_select_speed - Set module link speed\n- * @hw: pointer to hardware structure\n- * @speed: link speed to set\n+ * ixgbe_set_rate_select_speed - Set module link speed\n+ * @hw: pointer to hardware structure\n+ * @speed: link speed to set\n *\n- * Set module link speed via the rate select.\n+ * Set module link speed via the rate select.\n */\n void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed)\n {\ndiff --git a/drivers/net/ixgbe/base/ixgbe_common.c b/drivers/net/ixgbe/base/ixgbe_common.c\nindex 420ad977b..c24127b03 100644\n--- a/drivers/net/ixgbe/base/ixgbe_common.c\n+++ b/drivers/net/ixgbe/base/ixgbe_common.c\n@@ -31,10 +31,10 @@ STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,\n \t\t\t\t\t\t u16 offset);\n \n /**\n- * ixgbe_init_ops_generic - Inits function ptrs\n- * @hw: pointer to the hardware structure\n+ * ixgbe_init_ops_generic - Inits function ptrs\n+ * @hw: pointer to the hardware structure\n *\n- * Initialize the function pointers.\n+ * Initialize the function pointers.\n **/\n s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)\n {\n@@ -195,10 +195,10 @@ bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_setup_fc_generic - Set up flow control\n- * @hw: pointer to hardware structure\n+ * ixgbe_setup_fc_generic - Set up flow control\n+ * @hw: pointer to hardware structure\n *\n- * Called at init time to set up flow control.\n+ * Called at init time to set up flow control.\n **/\n s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)\n {\n@@ -350,13 +350,13 @@ s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx\n- * @hw: pointer to hardware structure\n+ * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx\n+ * @hw: pointer to hardware structure\n *\n- * Starts the hardware by filling the bus info structure and media type, clears\n- * all on chip counters, initializes receive address registers, multicast\n- * table, VLAN filter table, calls routine to set up link and flow control\n- * settings, and leaves transmit and receive units disabled and uninitialized\n+ * Starts the hardware by filling the bus info structure and media type, clears\n+ * all on chip counters, initializes receive address registers, multicast\n+ * table, VLAN filter table, calls routine to set up link and flow control\n+ * settings, and leaves transmit and receive units disabled and uninitialized\n **/\n s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)\n {\n@@ -413,14 +413,14 @@ s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_start_hw_gen2 - Init sequence for common device family\n- * @hw: pointer to hw structure\n+ * ixgbe_start_hw_gen2 - Init sequence for common device family\n+ * @hw: pointer to hw structure\n *\n * Performs the init sequence common to the second generation\n * of 10 GbE devices.\n * Devices in the second generation:\n- * 82599\n- * X540\n+ * 82599\n+ * X540\n **/\n s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)\n {\n@@ -452,14 +452,14 @@ s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_init_hw_generic - Generic hardware initialization\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_hw_generic - Generic hardware initialization\n+ * @hw: pointer to hardware structure\n *\n- * Initialize the hardware by resetting the hardware, filling the bus info\n- * structure and media type, clears all on chip counters, initializes receive\n- * address registers, multicast table, VLAN filter table, calls routine to set\n- * up link and flow control settings, and leaves transmit and receive units\n- * disabled and uninitialized\n+ * Initialize the hardware by resetting the hardware, filling the bus info\n+ * structure and media type, clears all on chip counters, initializes receive\n+ * address registers, multicast table, VLAN filter table, calls routine to set\n+ * up link and flow control settings, and leaves transmit and receive units\n+ * disabled and uninitialized\n **/\n s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)\n {\n@@ -486,11 +486,11 @@ s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters\n- * @hw: pointer to hardware structure\n+ * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters\n+ * @hw: pointer to hardware structure\n *\n- * Clears all hardware statistics counters by reading them from the hardware\n- * Statistics counters are clear on read.\n+ * Clears all hardware statistics counters by reading them from the hardware\n+ * Statistics counters are clear on read.\n **/\n s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)\n {\n@@ -600,12 +600,12 @@ s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_read_pba_string_generic - Reads part number string from EEPROM\n- * @hw: pointer to hardware structure\n- * @pba_num: stores the part number string from the EEPROM\n- * @pba_num_size: part number string buffer length\n+ * ixgbe_read_pba_string_generic - Reads part number string from EEPROM\n+ * @hw: pointer to hardware structure\n+ * @pba_num: stores the part number string from the EEPROM\n+ * @pba_num_size: part number string buffer length\n *\n- * Reads the part number string from the EEPROM.\n+ * Reads the part number string from the EEPROM.\n **/\n s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,\n \t\t\t\t u32 pba_num_size)\n@@ -711,11 +711,11 @@ s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,\n }\n \n /**\n- * ixgbe_read_pba_num_generic - Reads part number from EEPROM\n- * @hw: pointer to hardware structure\n- * @pba_num: stores the part number from the EEPROM\n+ * ixgbe_read_pba_num_generic - Reads part number from EEPROM\n+ * @hw: pointer to hardware structure\n+ * @pba_num: stores the part number from the EEPROM\n *\n- * Reads the part number from the EEPROM.\n+ * Reads the part number from the EEPROM.\n **/\n s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)\n {\n@@ -745,15 +745,15 @@ s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)\n }\n \n /**\n- * ixgbe_read_pba_raw\n- * @hw: pointer to the HW structure\n- * @eeprom_buf: optional pointer to EEPROM image\n- * @eeprom_buf_size: size of EEPROM image in words\n- * @max_pba_block_size: PBA block size limit\n- * @pba: pointer to output PBA structure\n+ * ixgbe_read_pba_raw\n+ * @hw: pointer to the HW structure\n+ * @eeprom_buf: optional pointer to EEPROM image\n+ * @eeprom_buf_size: size of EEPROM image in words\n+ * @max_pba_block_size: PBA block size limit\n+ * @pba: pointer to output PBA structure\n *\n- * Reads PBA from EEPROM image when eeprom_buf is not NULL.\n- * Reads PBA from physical EEPROM device when eeprom_buf is NULL.\n+ * Reads PBA from EEPROM image when eeprom_buf is not NULL.\n+ * Reads PBA from physical EEPROM device when eeprom_buf is NULL.\n *\n **/\n s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,\n@@ -815,14 +815,14 @@ s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,\n }\n \n /**\n- * ixgbe_write_pba_raw\n- * @hw: pointer to the HW structure\n- * @eeprom_buf: optional pointer to EEPROM image\n- * @eeprom_buf_size: size of EEPROM image in words\n- * @pba: pointer to PBA structure\n+ * ixgbe_write_pba_raw\n+ * @hw: pointer to the HW structure\n+ * @eeprom_buf: optional pointer to EEPROM image\n+ * @eeprom_buf_size: size of EEPROM image in words\n+ * @pba: pointer to PBA structure\n *\n- * Writes PBA to EEPROM image when eeprom_buf is not NULL.\n- * Writes PBA to physical EEPROM device when eeprom_buf is NULL.\n+ * Writes PBA to EEPROM image when eeprom_buf is not NULL.\n+ * Writes PBA to physical EEPROM device when eeprom_buf is NULL.\n *\n **/\n s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,\n@@ -873,15 +873,15 @@ s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,\n }\n \n /**\n- * ixgbe_get_pba_block_size\n- * @hw: pointer to the HW structure\n- * @eeprom_buf: optional pointer to EEPROM image\n- * @eeprom_buf_size: size of EEPROM image in words\n- * @pba_data_size: pointer to output variable\n+ * ixgbe_get_pba_block_size\n+ * @hw: pointer to the HW structure\n+ * @eeprom_buf: optional pointer to EEPROM image\n+ * @eeprom_buf_size: size of EEPROM image in words\n+ * @pba_data_size: pointer to output variable\n *\n- * Returns the size of the PBA block in words. Function operates on EEPROM\n- * image if the eeprom_buf pointer is not NULL otherwise it accesses physical\n- * EEPROM device.\n+ * Returns the size of the PBA block in words. Function operates on EEPROM\n+ * image if the eeprom_buf pointer is not NULL otherwise it accesses physical\n+ * EEPROM device.\n *\n **/\n s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,\n@@ -934,13 +934,13 @@ s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,\n }\n \n /**\n- * ixgbe_get_mac_addr_generic - Generic get MAC address\n- * @hw: pointer to hardware structure\n- * @mac_addr: Adapter MAC address\n+ * ixgbe_get_mac_addr_generic - Generic get MAC address\n+ * @hw: pointer to hardware structure\n+ * @mac_addr: Adapter MAC address\n *\n- * Reads the adapter's MAC address from first Receive Address Register (RAR0)\n- * A reset of the adapter must be performed prior to calling this function\n- * in order for the MAC address to have been loaded from the EEPROM into RAR0\n+ * Reads the adapter's MAC address from first Receive Address Register (RAR0)\n+ * A reset of the adapter must be performed prior to calling this function\n+ * in order for the MAC address to have been loaded from the EEPROM into RAR0\n **/\n s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)\n {\n@@ -963,11 +963,11 @@ s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)\n }\n \n /**\n- * ixgbe_set_pci_config_data_generic - Generic store PCI bus info\n- * @hw: pointer to hardware structure\n- * @link_status: the link status returned by the PCI config space\n+ * ixgbe_set_pci_config_data_generic - Generic store PCI bus info\n+ * @hw: pointer to hardware structure\n+ * @link_status: the link status returned by the PCI config space\n *\n- * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure\n+ * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure\n **/\n void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)\n {\n@@ -1013,11 +1013,11 @@ void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)\n }\n \n /**\n- * ixgbe_get_bus_info_generic - Generic set PCI bus info\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_bus_info_generic - Generic set PCI bus info\n+ * @hw: pointer to hardware structure\n *\n- * Gets the PCI bus info (speed, width, type) then calls helper function to\n- * store this data within the ixgbe_hw structure.\n+ * Gets the PCI bus info (speed, width, type) then calls helper function to\n+ * store this data within the ixgbe_hw structure.\n **/\n s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)\n {\n@@ -1034,12 +1034,12 @@ s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices\n- * @hw: pointer to the HW structure\n+ * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices\n+ * @hw: pointer to the HW structure\n *\n- * Determines the LAN function id by reading memory-mapped registers and swaps\n- * the port value if requested, and set MAC instance for devices that share\n- * CS4227.\n+ * Determines the LAN function id by reading memory-mapped registers and swaps\n+ * the port value if requested, and set MAC instance for devices that share\n+ * CS4227.\n **/\n void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)\n {\n@@ -1067,13 +1067,13 @@ void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units\n- * @hw: pointer to hardware structure\n+ * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units\n+ * @hw: pointer to hardware structure\n *\n- * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,\n- * disables transmit and receive units. The adapter_stopped flag is used by\n- * the shared code and drivers to determine if the adapter is in a stopped\n- * state and should not touch the hardware.\n+ * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,\n+ * disables transmit and receive units. The adapter_stopped flag is used by\n+ * the shared code and drivers to determine if the adapter is in a stopped\n+ * state and should not touch the hardware.\n **/\n s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)\n {\n@@ -1121,11 +1121,11 @@ s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_init_led_link_act_generic - Store the LED index link/activity.\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_led_link_act_generic - Store the LED index link/activity.\n+ * @hw: pointer to hardware structure\n *\n- * Store the index for the link active LED. This will be used to support\n- * blinking the LED.\n+ * Store the index for the link active LED. This will be used to support\n+ * blinking the LED.\n **/\n s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw)\n {\n@@ -1162,9 +1162,9 @@ s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_led_on_generic - Turns on the software controllable LEDs.\n- * @hw: pointer to hardware structure\n- * @index: led number to turn on\n+ * ixgbe_led_on_generic - Turns on the software controllable LEDs.\n+ * @hw: pointer to hardware structure\n+ * @index: led number to turn on\n **/\n s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)\n {\n@@ -1185,9 +1185,9 @@ s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)\n }\n \n /**\n- * ixgbe_led_off_generic - Turns off the software controllable LEDs.\n- * @hw: pointer to hardware structure\n- * @index: led number to turn off\n+ * ixgbe_led_off_generic - Turns off the software controllable LEDs.\n+ * @hw: pointer to hardware structure\n+ * @index: led number to turn off\n **/\n s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)\n {\n@@ -1208,11 +1208,11 @@ s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)\n }\n \n /**\n- * ixgbe_init_eeprom_params_generic - Initialize EEPROM params\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_eeprom_params_generic - Initialize EEPROM params\n+ * @hw: pointer to hardware structure\n *\n- * Initializes the EEPROM parameters ixgbe_eeprom_info within the\n- * ixgbe_hw struct in order to set up EEPROM access.\n+ * Initializes the EEPROM parameters ixgbe_eeprom_info within the\n+ * ixgbe_hw struct in order to set up EEPROM access.\n **/\n s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)\n {\n@@ -1261,13 +1261,13 @@ s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang\n- * @hw: pointer to hardware structure\n- * @offset: offset within the EEPROM to write\n- * @words: number of word(s)\n- * @data: 16 bit word(s) to write to EEPROM\n+ * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang\n+ * @hw: pointer to hardware structure\n+ * @offset: offset within the EEPROM to write\n+ * @words: number of word(s)\n+ * @data: 16 bit word(s) to write to EEPROM\n *\n- * Reads 16 bit word(s) from EEPROM through bit-bang method\n+ * Reads 16 bit word(s) from EEPROM through bit-bang method\n **/\n s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,\n \t\t\t\t\t u16 words, u16 *data)\n@@ -1317,14 +1317,14 @@ s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,\n }\n \n /**\n- * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM\n- * @hw: pointer to hardware structure\n- * @offset: offset within the EEPROM to be written to\n- * @words: number of word(s)\n- * @data: 16 bit word(s) to be written to the EEPROM\n+ * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM\n+ * @hw: pointer to hardware structure\n+ * @offset: offset within the EEPROM to be written to\n+ * @words: number of word(s)\n+ * @data: 16 bit word(s) to be written to the EEPROM\n *\n- * If ixgbe_eeprom_update_checksum is not called after this function, the\n- * EEPROM will most likely contain an invalid checksum.\n+ * If ixgbe_eeprom_update_checksum is not called after this function, the\n+ * EEPROM will most likely contain an invalid checksum.\n **/\n STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,\n \t\t\t\t\t u16 words, u16 *data)\n@@ -1400,13 +1400,13 @@ STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,\n }\n \n /**\n- * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM\n- * @hw: pointer to hardware structure\n- * @offset: offset within the EEPROM to be written to\n- * @data: 16 bit word to be written to the EEPROM\n+ * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM\n+ * @hw: pointer to hardware structure\n+ * @offset: offset within the EEPROM to be written to\n+ * @data: 16 bit word to be written to the EEPROM\n *\n- * If ixgbe_eeprom_update_checksum is not called after this function, the\n- * EEPROM will most likely contain an invalid checksum.\n+ * If ixgbe_eeprom_update_checksum is not called after this function, the\n+ * EEPROM will most likely contain an invalid checksum.\n **/\n s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)\n {\n@@ -1428,13 +1428,13 @@ s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)\n }\n \n /**\n- * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang\n- * @hw: pointer to hardware structure\n- * @offset: offset within the EEPROM to be read\n- * @data: read 16 bit words(s) from EEPROM\n- * @words: number of word(s)\n+ * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang\n+ * @hw: pointer to hardware structure\n+ * @offset: offset within the EEPROM to be read\n+ * @data: read 16 bit words(s) from EEPROM\n+ * @words: number of word(s)\n *\n- * Reads 16 bit word(s) from EEPROM through bit-bang method\n+ * Reads 16 bit word(s) from EEPROM through bit-bang method\n **/\n s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,\n \t\t\t\t\t u16 words, u16 *data)\n@@ -1477,13 +1477,13 @@ s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,\n }\n \n /**\n- * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang\n- * @hw: pointer to hardware structure\n- * @offset: offset within the EEPROM to be read\n- * @words: number of word(s)\n- * @data: read 16 bit word(s) from EEPROM\n+ * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang\n+ * @hw: pointer to hardware structure\n+ * @offset: offset within the EEPROM to be read\n+ * @words: number of word(s)\n+ * @data: read 16 bit word(s) from EEPROM\n *\n- * Reads 16 bit word(s) from EEPROM through bit-bang method\n+ * Reads 16 bit word(s) from EEPROM through bit-bang method\n **/\n STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,\n \t\t\t\t\t u16 words, u16 *data)\n@@ -1535,12 +1535,12 @@ STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,\n }\n \n /**\n- * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang\n- * @hw: pointer to hardware structure\n- * @offset: offset within the EEPROM to be read\n- * @data: read 16 bit value from EEPROM\n+ * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang\n+ * @hw: pointer to hardware structure\n+ * @offset: offset within the EEPROM to be read\n+ * @data: read 16 bit value from EEPROM\n *\n- * Reads 16 bit value from EEPROM through bit-bang method\n+ * Reads 16 bit value from EEPROM through bit-bang method\n **/\n s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,\n \t\t\t\t u16 *data)\n@@ -1563,13 +1563,13 @@ s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,\n }\n \n /**\n- * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD\n- * @hw: pointer to hardware structure\n- * @offset: offset of word in the EEPROM to read\n- * @words: number of word(s)\n- * @data: 16 bit word(s) from the EEPROM\n+ * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to read\n+ * @words: number of word(s)\n+ * @data: 16 bit word(s) from the EEPROM\n *\n- * Reads a 16 bit word(s) from the EEPROM using the EERD register.\n+ * Reads a 16 bit word(s) from the EEPROM using the EERD register.\n **/\n s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,\n \t\t\t\t u16 words, u16 *data)\n@@ -1614,13 +1614,13 @@ s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,\n }\n \n /**\n- * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size\n- * @hw: pointer to hardware structure\n- * @offset: offset within the EEPROM to be used as a scratch pad\n+ * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size\n+ * @hw: pointer to hardware structure\n+ * @offset: offset within the EEPROM to be used as a scratch pad\n *\n- * Discover EEPROM page size by writing marching data at given offset.\n- * This function is called only when we are writing a new large buffer\n- * at given offset so the data would be overwritten anyway.\n+ * Discover EEPROM page size by writing marching data at given offset.\n+ * This function is called only when we are writing a new large buffer\n+ * at given offset so the data would be overwritten anyway.\n **/\n STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,\n \t\t\t\t\t\t u16 offset)\n@@ -1658,12 +1658,12 @@ STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_read_eerd_generic - Read EEPROM word using EERD\n- * @hw: pointer to hardware structure\n- * @offset: offset of word in the EEPROM to read\n- * @data: word read from the EEPROM\n+ * ixgbe_read_eerd_generic - Read EEPROM word using EERD\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to read\n+ * @data: word read from the EEPROM\n *\n- * Reads a 16 bit word from the EEPROM using the EERD register.\n+ * Reads a 16 bit word from the EEPROM using the EERD register.\n **/\n s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)\n {\n@@ -1671,13 +1671,13 @@ s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)\n }\n \n /**\n- * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR\n- * @hw: pointer to hardware structure\n- * @offset: offset of word in the EEPROM to write\n- * @words: number of word(s)\n- * @data: word(s) write to the EEPROM\n+ * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to write\n+ * @words: number of word(s)\n+ * @data: word(s) write to the EEPROM\n *\n- * Write a 16 bit word(s) to the EEPROM using the EEWR register.\n+ * Write a 16 bit word(s) to the EEPROM using the EEWR register.\n **/\n s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,\n \t\t\t\t u16 words, u16 *data)\n@@ -1727,12 +1727,12 @@ s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,\n }\n \n /**\n- * ixgbe_write_eewr_generic - Write EEPROM word using EEWR\n- * @hw: pointer to hardware structure\n- * @offset: offset of word in the EEPROM to write\n- * @data: word write to the EEPROM\n+ * ixgbe_write_eewr_generic - Write EEPROM word using EEWR\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to write\n+ * @data: word write to the EEPROM\n *\n- * Write a 16 bit word to the EEPROM using the EEWR register.\n+ * Write a 16 bit word to the EEPROM using the EEWR register.\n **/\n s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)\n {\n@@ -1740,12 +1740,12 @@ s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)\n }\n \n /**\n- * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status\n- * @hw: pointer to hardware structure\n- * @ee_reg: EEPROM flag for polling\n+ * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status\n+ * @hw: pointer to hardware structure\n+ * @ee_reg: EEPROM flag for polling\n *\n- * Polls the status bit (bit 1) of the EERD or EEWR to determine when the\n- * read or write is done respectively.\n+ * Polls the status bit (bit 1) of the EERD or EEWR to determine when the\n+ * read or write is done respectively.\n **/\n s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)\n {\n@@ -1776,11 +1776,11 @@ s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)\n }\n \n /**\n- * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang\n- * @hw: pointer to hardware structure\n+ * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang\n+ * @hw: pointer to hardware structure\n *\n- * Prepares EEPROM for access using bit-bang method. This function should\n- * be called before issuing a command to the EEPROM.\n+ * Prepares EEPROM for access using bit-bang method. This function should\n+ * be called before issuing a command to the EEPROM.\n **/\n STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)\n {\n@@ -1831,10 +1831,10 @@ STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_get_eeprom_semaphore - Get hardware semaphore\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_eeprom_semaphore - Get hardware semaphore\n+ * @hw: pointer to hardware structure\n *\n- * Sets the hardware semaphores so EEPROM access can occur for bit-bang method\n+ * Sets the hardware semaphores so EEPROM access can occur for bit-bang method\n **/\n STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)\n {\n@@ -1922,10 +1922,10 @@ STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_release_eeprom_semaphore - Release hardware semaphore\n- * @hw: pointer to hardware structure\n+ * ixgbe_release_eeprom_semaphore - Release hardware semaphore\n+ * @hw: pointer to hardware structure\n *\n- * This function clears hardware semaphore bits.\n+ * This function clears hardware semaphore bits.\n **/\n STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)\n {\n@@ -1942,8 +1942,8 @@ STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_ready_eeprom - Polls for EEPROM ready\n- * @hw: pointer to hardware structure\n+ * ixgbe_ready_eeprom - Polls for EEPROM ready\n+ * @hw: pointer to hardware structure\n **/\n STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)\n {\n@@ -1983,8 +1983,8 @@ STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_standby_eeprom - Returns EEPROM to a \"standby\" state\n- * @hw: pointer to hardware structure\n+ * ixgbe_standby_eeprom - Returns EEPROM to a \"standby\" state\n+ * @hw: pointer to hardware structure\n **/\n STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)\n {\n@@ -2006,10 +2006,10 @@ STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.\n- * @hw: pointer to hardware structure\n- * @data: data to send to the EEPROM\n- * @count: number of bits to shift out\n+ * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.\n+ * @hw: pointer to hardware structure\n+ * @data: data to send to the EEPROM\n+ * @count: number of bits to shift out\n **/\n STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,\n \t\t\t\t\tu16 count)\n@@ -2063,9 +2063,9 @@ STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,\n }\n \n /**\n- * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM\n- * @hw: pointer to hardware structure\n- * @count: number of bits to shift\n+ * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM\n+ * @hw: pointer to hardware structure\n+ * @count: number of bits to shift\n **/\n STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)\n {\n@@ -2103,9 +2103,9 @@ STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)\n }\n \n /**\n- * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.\n- * @hw: pointer to hardware structure\n- * @eec: EEC register's current value\n+ * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.\n+ * @hw: pointer to hardware structure\n+ * @eec: EEC register's current value\n **/\n STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)\n {\n@@ -2122,9 +2122,9 @@ STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)\n }\n \n /**\n- * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.\n- * @hw: pointer to hardware structure\n- * @eec: EEC's current value\n+ * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.\n+ * @hw: pointer to hardware structure\n+ * @eec: EEC's current value\n **/\n STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)\n {\n@@ -2141,8 +2141,8 @@ STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)\n }\n \n /**\n- * ixgbe_release_eeprom - Release EEPROM, release semaphores\n- * @hw: pointer to hardware structure\n+ * ixgbe_release_eeprom - Release EEPROM, release semaphores\n+ * @hw: pointer to hardware structure\n **/\n STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)\n {\n@@ -2171,10 +2171,10 @@ STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum\n- * @hw: pointer to hardware structure\n+ * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum\n+ * @hw: pointer to hardware structure\n *\n- * Returns a negative error code on error, or the 16-bit checksum\n+ * Returns a negative error code on error, or the 16-bit checksum\n **/\n s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)\n {\n@@ -2230,12 +2230,12 @@ s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum\n- * @hw: pointer to hardware structure\n- * @checksum_val: calculated checksum\n+ * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum\n+ * @hw: pointer to hardware structure\n+ * @checksum_val: calculated checksum\n *\n- * Performs checksum calculation and validates the EEPROM checksum. If the\n- * caller does not need checksum_val, the value can be NULL.\n+ * Performs checksum calculation and validates the EEPROM checksum. If the\n+ * caller does not need checksum_val, the value can be NULL.\n **/\n s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,\n \t\t\t\t\t u16 *checksum_val)\n@@ -2282,8 +2282,8 @@ s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum\n- * @hw: pointer to hardware structure\n+ * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum\n+ * @hw: pointer to hardware structure\n **/\n s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)\n {\n@@ -2314,10 +2314,10 @@ s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_validate_mac_addr - Validate MAC address\n- * @mac_addr: pointer to MAC address.\n+ * ixgbe_validate_mac_addr - Validate MAC address\n+ * @mac_addr: pointer to MAC address.\n *\n- * Tests a MAC address to ensure it is a valid Individual Address.\n+ * Tests a MAC address to ensure it is a valid Individual Address.\n **/\n s32 ixgbe_validate_mac_addr(u8 *mac_addr)\n {\n@@ -2340,14 +2340,14 @@ s32 ixgbe_validate_mac_addr(u8 *mac_addr)\n }\n \n /**\n- * ixgbe_set_rar_generic - Set Rx address register\n- * @hw: pointer to hardware structure\n- * @index: Receive address register to write\n- * @addr: Address to put into receive address register\n- * @vmdq: VMDq \"set\" or \"pool\" index\n- * @enable_addr: set flag that address is active\n+ * ixgbe_set_rar_generic - Set Rx address register\n+ * @hw: pointer to hardware structure\n+ * @index: Receive address register to write\n+ * @addr: Address to put into receive address register\n+ * @vmdq: VMDq \"set\" or \"pool\" index\n+ * @enable_addr: set flag that address is active\n *\n- * Puts an ethernet address into a receive address register.\n+ * Puts an ethernet address into a receive address register.\n **/\n s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,\n \t\t\t u32 enable_addr)\n@@ -2394,11 +2394,11 @@ s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,\n }\n \n /**\n- * ixgbe_clear_rar_generic - Remove Rx address register\n- * @hw: pointer to hardware structure\n- * @index: Receive address register to write\n+ * ixgbe_clear_rar_generic - Remove Rx address register\n+ * @hw: pointer to hardware structure\n+ * @index: Receive address register to write\n *\n- * Clears an ethernet address from a receive address register.\n+ * Clears an ethernet address from a receive address register.\n **/\n s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)\n {\n@@ -2432,12 +2432,12 @@ s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)\n }\n \n /**\n- * ixgbe_init_rx_addrs_generic - Initializes receive address filters.\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_rx_addrs_generic - Initializes receive address filters.\n+ * @hw: pointer to hardware structure\n *\n- * Places the MAC address in receive address register 0 and clears the rest\n- * of the receive address registers. Clears the multicast table. Assumes\n- * the receiver is in reset when the routine is called.\n+ * Places the MAC address in receive address register 0 and clears the rest\n+ * of the receive address registers. Clears the multicast table. Assumes\n+ * the receiver is in reset when the routine is called.\n **/\n s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)\n {\n@@ -2501,12 +2501,12 @@ s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_add_uc_addr - Adds a secondary unicast address.\n- * @hw: pointer to hardware structure\n- * @addr: new address\n- * @vmdq: VMDq \"set\" or \"pool\" index\n+ * ixgbe_add_uc_addr - Adds a secondary unicast address.\n+ * @hw: pointer to hardware structure\n+ * @addr: new address\n+ * @vmdq: VMDq \"set\" or \"pool\" index\n *\n- * Adds it to unused receive address register or goes into promiscuous mode.\n+ * Adds it to unused receive address register or goes into promiscuous mode.\n **/\n void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)\n {\n@@ -2535,18 +2535,18 @@ void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)\n }\n \n /**\n- * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses\n- * @hw: pointer to hardware structure\n- * @addr_list: the list of new addresses\n- * @addr_count: number of addresses\n- * @next: iterator function to walk the address list\n+ * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses\n+ * @hw: pointer to hardware structure\n+ * @addr_list: the list of new addresses\n+ * @addr_count: number of addresses\n+ * @next: iterator function to walk the address list\n *\n- * The given list replaces any existing list. Clears the secondary addrs from\n- * receive address registers. Uses unused receive address registers for the\n- * first secondary addresses, and falls back to promiscuous mode as needed.\n+ * The given list replaces any existing list. Clears the secondary addrs from\n+ * receive address registers. Uses unused receive address registers for the\n+ * first secondary addresses, and falls back to promiscuous mode as needed.\n *\n- * Drivers using secondary unicast addresses must set user_set_promisc when\n- * manually putting the device into promiscuous mode.\n+ * Drivers using secondary unicast addresses must set user_set_promisc when\n+ * manually putting the device into promiscuous mode.\n **/\n s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,\n \t\t\t\t u32 addr_count, ixgbe_mc_addr_itr next)\n@@ -2605,16 +2605,16 @@ s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,\n }\n \n /**\n- * ixgbe_mta_vector - Determines bit-vector in multicast table to set\n- * @hw: pointer to hardware structure\n- * @mc_addr: the multicast address\n+ * ixgbe_mta_vector - Determines bit-vector in multicast table to set\n+ * @hw: pointer to hardware structure\n+ * @mc_addr: the multicast address\n *\n- * Extracts the 12 bits, from a multicast address, to determine which\n- * bit-vector to set in the multicast table. The hardware uses 12 bits, from\n- * incoming rx multicast addresses, to determine the bit-vector to check in\n- * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set\n- * by the MO field of the MCSTCTRL. The MO field is set during initialization\n- * to mc_filter_type.\n+ * Extracts the 12 bits, from a multicast address, to determine which\n+ * bit-vector to set in the multicast table. The hardware uses 12 bits, from\n+ * incoming rx multicast addresses, to determine the bit-vector to check in\n+ * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set\n+ * by the MO field of the MCSTCTRL. The MO field is set during initialization\n+ * to mc_filter_type.\n **/\n STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)\n {\n@@ -2647,11 +2647,11 @@ STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)\n }\n \n /**\n- * ixgbe_set_mta - Set bit-vector in multicast table\n- * @hw: pointer to hardware structure\n- * @mc_addr: Multicast address\n+ * ixgbe_set_mta - Set bit-vector in multicast table\n+ * @hw: pointer to hardware structure\n+ * @mc_addr: Multicast address\n *\n- * Sets the bit-vector in the multicast table.\n+ * Sets the bit-vector in the multicast table.\n **/\n void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)\n {\n@@ -2681,15 +2681,15 @@ void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)\n }\n \n /**\n- * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses\n- * @hw: pointer to hardware structure\n- * @mc_addr_list: the list of new multicast addresses\n- * @mc_addr_count: number of addresses\n- * @next: iterator function to walk the multicast address list\n- * @clear: flag, when set clears the table beforehand\n+ * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses\n+ * @hw: pointer to hardware structure\n+ * @mc_addr_list: the list of new multicast addresses\n+ * @mc_addr_count: number of addresses\n+ * @next: iterator function to walk the multicast address list\n+ * @clear: flag, when set clears the table beforehand\n *\n- * When the clear flag is set, the given list replaces any existing list.\n- * Hashes the given addresses into the multicast table.\n+ * When the clear flag is set, the given list replaces any existing list.\n+ * Hashes the given addresses into the multicast table.\n **/\n s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,\n \t\t\t\t u32 mc_addr_count, ixgbe_mc_addr_itr next,\n@@ -2733,10 +2733,10 @@ s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,\n }\n \n /**\n- * ixgbe_enable_mc_generic - Enable multicast address in RAR\n- * @hw: pointer to hardware structure\n+ * ixgbe_enable_mc_generic - Enable multicast address in RAR\n+ * @hw: pointer to hardware structure\n *\n- * Enables multicast address in RAR and the use of the multicast hash table.\n+ * Enables multicast address in RAR and the use of the multicast hash table.\n **/\n s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)\n {\n@@ -2752,10 +2752,10 @@ s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_disable_mc_generic - Disable multicast address in RAR\n- * @hw: pointer to hardware structure\n+ * ixgbe_disable_mc_generic - Disable multicast address in RAR\n+ * @hw: pointer to hardware structure\n *\n- * Disables multicast address in RAR and the use of the multicast hash table.\n+ * Disables multicast address in RAR and the use of the multicast hash table.\n **/\n s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)\n {\n@@ -2770,10 +2770,10 @@ s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_fc_enable_generic - Enable flow control\n- * @hw: pointer to hardware structure\n+ * ixgbe_fc_enable_generic - Enable flow control\n+ * @hw: pointer to hardware structure\n *\n- * Enable flow control according to the current settings.\n+ * Enable flow control according to the current settings.\n **/\n s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)\n {\n@@ -2903,17 +2903,17 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_negotiate_fc - Negotiate flow control\n- * @hw: pointer to hardware structure\n- * @adv_reg: flow control advertised settings\n- * @lp_reg: link partner's flow control settings\n- * @adv_sym: symmetric pause bit in advertisement\n- * @adv_asm: asymmetric pause bit in advertisement\n- * @lp_sym: symmetric pause bit in link partner advertisement\n- * @lp_asm: asymmetric pause bit in link partner advertisement\n+ * ixgbe_negotiate_fc - Negotiate flow control\n+ * @hw: pointer to hardware structure\n+ * @adv_reg: flow control advertised settings\n+ * @lp_reg: link partner's flow control settings\n+ * @adv_sym: symmetric pause bit in advertisement\n+ * @adv_asm: asymmetric pause bit in advertisement\n+ * @lp_sym: symmetric pause bit in link partner advertisement\n+ * @lp_asm: asymmetric pause bit in link partner advertisement\n *\n- * Find the intersection between advertised settings and link partner's\n- * advertised settings\n+ * Find the intersection between advertised settings and link partner's\n+ * advertised settings\n **/\n s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,\n \t\t u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)\n@@ -2957,10 +2957,10 @@ s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,\n }\n \n /**\n- * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber\n- * @hw: pointer to hardware structure\n+ * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber\n+ * @hw: pointer to hardware structure\n *\n- * Enable flow control according on 1 gig fiber.\n+ * Enable flow control according on 1 gig fiber.\n **/\n STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)\n {\n@@ -2994,10 +2994,10 @@ STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37\n- * @hw: pointer to hardware structure\n+ * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37\n+ * @hw: pointer to hardware structure\n *\n- * Enable flow control according to IEEE clause 37.\n+ * Enable flow control according to IEEE clause 37.\n **/\n STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)\n {\n@@ -3038,10 +3038,10 @@ STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37\n- * @hw: pointer to hardware structure\n+ * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37\n+ * @hw: pointer to hardware structure\n *\n- * Enable flow control according to IEEE clause 37.\n+ * Enable flow control according to IEEE clause 37.\n **/\n STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)\n {\n@@ -3062,11 +3062,11 @@ STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_fc_autoneg - Configure flow control\n- * @hw: pointer to hardware structure\n+ * ixgbe_fc_autoneg - Configure flow control\n+ * @hw: pointer to hardware structure\n *\n- * Compares our advertised flow control capabilities to those advertised by\n- * our link partner, and determines the proper flow control mode to use.\n+ * Compares our advertised flow control capabilities to those advertised by\n+ * our link partner, and determines the proper flow control mode to use.\n **/\n void ixgbe_fc_autoneg(struct ixgbe_hw *hw)\n {\n@@ -3174,13 +3174,13 @@ STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_disable_pcie_master - Disable PCI-express master access\n- * @hw: pointer to hardware structure\n+ * ixgbe_disable_pcie_master - Disable PCI-express master access\n+ * @hw: pointer to hardware structure\n *\n- * Disables PCI-Express master access and verifies there are no pending\n- * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable\n- * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS\n- * is returned signifying master requests disabled.\n+ * Disables PCI-Express master access and verifies there are no pending\n+ * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable\n+ * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS\n+ * is returned signifying master requests disabled.\n **/\n s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)\n {\n@@ -3242,12 +3242,12 @@ s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore\n- * @hw: pointer to hardware structure\n- * @mask: Mask to specify which semaphore to acquire\n+ * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore\n+ * @hw: pointer to hardware structure\n+ * @mask: Mask to specify which semaphore to acquire\n *\n- * Acquires the SWFW semaphore through the GSSR register for the specified\n- * function (CSR, PHY0, PHY1, EEPROM, Flash)\n+ * Acquires the SWFW semaphore through the GSSR register for the specified\n+ * function (CSR, PHY0, PHY1, EEPROM, Flash)\n **/\n s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)\n {\n@@ -3289,12 +3289,12 @@ s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)\n }\n \n /**\n- * ixgbe_release_swfw_sync - Release SWFW semaphore\n- * @hw: pointer to hardware structure\n- * @mask: Mask to specify which semaphore to release\n+ * ixgbe_release_swfw_sync - Release SWFW semaphore\n+ * @hw: pointer to hardware structure\n+ * @mask: Mask to specify which semaphore to release\n *\n- * Releases the SWFW semaphore through the GSSR register for the specified\n- * function (CSR, PHY0, PHY1, EEPROM, Flash)\n+ * Releases the SWFW semaphore through the GSSR register for the specified\n+ * function (CSR, PHY0, PHY1, EEPROM, Flash)\n **/\n void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)\n {\n@@ -3313,11 +3313,11 @@ void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)\n }\n \n /**\n- * ixgbe_disable_sec_rx_path_generic - Stops the receive data path\n- * @hw: pointer to hardware structure\n+ * ixgbe_disable_sec_rx_path_generic - Stops the receive data path\n+ * @hw: pointer to hardware structure\n *\n- * Stops the receive data path and waits for the HW to internally empty\n- * the Rx security block\n+ * Stops the receive data path and waits for the HW to internally empty\n+ * the Rx security block\n **/\n s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)\n {\n@@ -3350,12 +3350,12 @@ s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read\n- * @hw: pointer to hardware structure\n- * @locked: bool to indicate whether the SW/FW lock was taken\n- * @reg_val: Value we read from AUTOC\n+ * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read\n+ * @hw: pointer to hardware structure\n+ * @locked: bool to indicate whether the SW/FW lock was taken\n+ * @reg_val: Value we read from AUTOC\n *\n- * The default case requires no protection so just to the register read.\n+ * The default case requires no protection so just to the register read.\n */\n s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)\n {\n@@ -3369,7 +3369,7 @@ s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)\n * @hw: pointer to hardware structure\n * @reg_val: value to write to AUTOC\n * @locked: bool to indicate whether the SW/FW lock was already taken by\n- * previous read.\n+ * previous read.\n *\n * The default case requires no protection so just to the register write.\n */\n@@ -3382,10 +3382,10 @@ s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)\n }\n \n /**\n- * ixgbe_enable_sec_rx_path_generic - Enables the receive data path\n- * @hw: pointer to hardware structure\n+ * ixgbe_enable_sec_rx_path_generic - Enables the receive data path\n+ * @hw: pointer to hardware structure\n *\n- * Enables the receive data path.\n+ * Enables the receive data path.\n **/\n s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)\n {\n@@ -3402,11 +3402,11 @@ s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit\n- * @hw: pointer to hardware structure\n- * @regval: register value to write to RXCTRL\n+ * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit\n+ * @hw: pointer to hardware structure\n+ * @regval: register value to write to RXCTRL\n *\n- * Enables the Rx DMA unit\n+ * Enables the Rx DMA unit\n **/\n s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)\n {\n@@ -3421,9 +3421,9 @@ s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)\n }\n \n /**\n- * ixgbe_blink_led_start_generic - Blink LED based on index.\n- * @hw: pointer to hardware structure\n- * @index: led number to blink\n+ * ixgbe_blink_led_start_generic - Blink LED based on index.\n+ * @hw: pointer to hardware structure\n+ * @index: led number to blink\n **/\n s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)\n {\n@@ -3471,9 +3471,9 @@ s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)\n }\n \n /**\n- * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.\n- * @hw: pointer to hardware structure\n- * @index: led number to stop blinking\n+ * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.\n+ * @hw: pointer to hardware structure\n+ * @index: led number to stop blinking\n **/\n s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)\n {\n@@ -3510,13 +3510,13 @@ s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)\n }\n \n /**\n- * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM\n- * @hw: pointer to hardware structure\n- * @san_mac_offset: SAN MAC address offset\n+ * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM\n+ * @hw: pointer to hardware structure\n+ * @san_mac_offset: SAN MAC address offset\n *\n- * This function will read the EEPROM location for the SAN MAC address\n- * pointer, and returns the value at that location. This is used in both\n- * get and set mac_addr routines.\n+ * This function will read the EEPROM location for the SAN MAC address\n+ * pointer, and returns the value at that location. This is used in both\n+ * get and set mac_addr routines.\n **/\n STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,\n \t\t\t\t\t u16 *san_mac_offset)\n@@ -3541,14 +3541,14 @@ STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM\n- * @hw: pointer to hardware structure\n- * @san_mac_addr: SAN MAC address\n+ * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM\n+ * @hw: pointer to hardware structure\n+ * @san_mac_addr: SAN MAC address\n *\n- * Reads the SAN MAC address from the EEPROM, if it's available. This is\n- * per-port, so set_lan_id() must be called before reading the addresses.\n- * set_lan_id() is called by identify_sfp(), but this cannot be relied\n- * upon for non-SFP connections, so we must call it here.\n+ * Reads the SAN MAC address from the EEPROM, if it's available. This is\n+ * per-port, so set_lan_id() must be called before reading the addresses.\n+ * set_lan_id() is called by identify_sfp(), but this cannot be relied\n+ * upon for non-SFP connections, so we must call it here.\n **/\n s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)\n {\n@@ -3597,11 +3597,11 @@ s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)\n }\n \n /**\n- * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM\n- * @hw: pointer to hardware structure\n- * @san_mac_addr: SAN MAC address\n+ * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM\n+ * @hw: pointer to hardware structure\n+ * @san_mac_addr: SAN MAC address\n *\n- * Write a SAN MAC address to the EEPROM.\n+ * Write a SAN MAC address to the EEPROM.\n **/\n s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)\n {\n@@ -3633,11 +3633,11 @@ s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)\n }\n \n /**\n- * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count\n+ * @hw: pointer to hardware structure\n *\n- * Read PCIe configuration space, and get the MSI-X vector count from\n- * the capabilities table.\n+ * Read PCIe configuration space, and get the MSI-X vector count from\n+ * the capabilities table.\n **/\n u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)\n {\n@@ -3678,13 +3678,13 @@ u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address\n- * @hw: pointer to hardware structure\n- * @addr: Address to put into receive address register\n- * @vmdq: VMDq pool to assign\n+ * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address\n+ * @hw: pointer to hardware structure\n+ * @addr: Address to put into receive address register\n+ * @vmdq: VMDq pool to assign\n *\n- * Puts an ethernet address into a receive address register, or\n- * finds the rar that it is aleady in; adds to the pool list\n+ * Puts an ethernet address into a receive address register, or\n+ * finds the rar that it is aleady in; adds to the pool list\n **/\n s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)\n {\n@@ -3747,10 +3747,10 @@ s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)\n }\n \n /**\n- * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address\n- * @hw: pointer to hardware struct\n- * @rar: receive address register index to disassociate\n- * @vmdq: VMDq pool index to remove from the rar\n+ * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address\n+ * @hw: pointer to hardware struct\n+ * @rar: receive address register index to disassociate\n+ * @vmdq: VMDq pool index to remove from the rar\n **/\n s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n {\n@@ -3801,10 +3801,10 @@ s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n }\n \n /**\n- * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address\n- * @hw: pointer to hardware struct\n- * @rar: receive address register index to associate with a VMDq index\n- * @vmdq: VMDq pool index\n+ * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address\n+ * @hw: pointer to hardware struct\n+ * @rar: receive address register index to associate with a VMDq index\n+ * @vmdq: VMDq pool index\n **/\n s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n {\n@@ -3833,14 +3833,14 @@ s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n }\n \n /**\n- * This function should only be involved in the IOV mode.\n- * In IOV mode, Default pool is next pool after the number of\n- * VFs advertized and not 0.\n- * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]\n+ * This function should only be involved in the IOV mode.\n+ * In IOV mode, Default pool is next pool after the number of\n+ * VFs advertized and not 0.\n+ * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]\n *\n- * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address\n- * @hw: pointer to hardware struct\n- * @vmdq: VMDq pool index\n+ * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address\n+ * @hw: pointer to hardware struct\n+ * @vmdq: VMDq pool index\n **/\n s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)\n {\n@@ -3860,8 +3860,8 @@ s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)\n }\n \n /**\n- * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array\n+ * @hw: pointer to hardware structure\n **/\n s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)\n {\n@@ -3877,14 +3877,14 @@ s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot\n- * @hw: pointer to hardware structure\n- * @vlan: VLAN id to write to VLAN filter\n- * @vlvf_bypass: true to find vlanid only, false returns first empty slot if\n+ * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot\n+ * @hw: pointer to hardware structure\n+ * @vlan: VLAN id to write to VLAN filter\n+ * @vlvf_bypass: true to find vlanid only, false returns first empty slot if\n *\t\t vlanid not found\n *\n *\n- * return the VLVF index where this VLAN id should be placed\n+ * return the VLVF index where this VLAN id should be placed\n *\n **/\n s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)\n@@ -3928,14 +3928,14 @@ s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)\n }\n \n /**\n- * ixgbe_set_vfta_generic - Set VLAN filter table\n- * @hw: pointer to hardware structure\n- * @vlan: VLAN id to write to VLAN filter\n- * @vind: VMDq output index that maps queue to VLAN id in VLVFB\n- * @vlan_on: boolean flag to turn on/off VLAN\n- * @vlvf_bypass: boolean flag indicating updating default pool is okay\n+ * ixgbe_set_vfta_generic - Set VLAN filter table\n+ * @hw: pointer to hardware structure\n+ * @vlan: VLAN id to write to VLAN filter\n+ * @vind: VMDq output index that maps queue to VLAN id in VLVFB\n+ * @vlan_on: boolean flag to turn on/off VLAN\n+ * @vlvf_bypass: boolean flag indicating updating default pool is okay\n *\n- * Turn on/off specified VLAN in the VLAN filter table.\n+ * Turn on/off specified VLAN in the VLAN filter table.\n **/\n s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,\n \t\t\t bool vlan_on, bool vlvf_bypass)\n@@ -3992,17 +3992,17 @@ s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,\n }\n \n /**\n- * ixgbe_set_vlvf_generic - Set VLAN Pool Filter\n- * @hw: pointer to hardware structure\n- * @vlan: VLAN id to write to VLAN filter\n- * @vind: VMDq output index that maps queue to VLAN id in VLVFB\n- * @vlan_on: boolean flag to turn on/off VLAN in VLVF\n- * @vfta_delta: pointer to the difference between the current value of VFTA\n+ * ixgbe_set_vlvf_generic - Set VLAN Pool Filter\n+ * @hw: pointer to hardware structure\n+ * @vlan: VLAN id to write to VLAN filter\n+ * @vind: VMDq output index that maps queue to VLAN id in VLVFB\n+ * @vlan_on: boolean flag to turn on/off VLAN in VLVF\n+ * @vfta_delta: pointer to the difference between the current value of VFTA\n *\t\t and the desired value\n- * @vfta: the desired value of the VFTA\n- * @vlvf_bypass: boolean flag indicating updating default pool is okay\n+ * @vfta: the desired value of the VFTA\n+ * @vlvf_bypass: boolean flag indicating updating default pool is okay\n *\n- * Turn on/off specified bit in VLVF table.\n+ * Turn on/off specified bit in VLVF table.\n **/\n s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,\n \t\t\t bool vlan_on, u32 *vfta_delta, u32 vfta,\n@@ -4081,10 +4081,10 @@ s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,\n }\n \n /**\n- * ixgbe_clear_vfta_generic - Clear VLAN filter table\n- * @hw: pointer to hardware structure\n+ * ixgbe_clear_vfta_generic - Clear VLAN filter table\n+ * @hw: pointer to hardware structure\n *\n- * Clears the VLAN filer table, and the VMDq index associated with the filter\n+ * Clears the VLAN filer table, and the VMDq index associated with the filter\n **/\n s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)\n {\n@@ -4105,11 +4105,11 @@ s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_toggle_txdctl_generic - Toggle VF's queues\n- * @hw: pointer to hardware structure\n- * @vf_number: VF index\n+ * ixgbe_toggle_txdctl_generic - Toggle VF's queues\n+ * @hw: pointer to hardware structure\n+ * @vf_number: VF index\n *\n- * Enable and disable each queue in VF.\n+ * Enable and disable each queue in VF.\n */\n s32 ixgbe_toggle_txdctl_generic(struct ixgbe_hw *hw, u32 vf_number)\n {\n@@ -4160,11 +4160,11 @@ s32 ixgbe_toggle_txdctl_generic(struct ixgbe_hw *hw, u32 vf_number)\n }\n \n /**\n- * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix\n- * @hw: pointer to hardware structure\n+ * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix\n+ * @hw: pointer to hardware structure\n *\n- * Contains the logic to identify if we need to verify link for the\n- * crosstalk fix\n+ * Contains the logic to identify if we need to verify link for the\n+ * crosstalk fix\n **/\n static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)\n {\n@@ -4186,13 +4186,13 @@ static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_check_mac_link_generic - Determine link and speed status\n- * @hw: pointer to hardware structure\n- * @speed: pointer to link speed\n- * @link_up: true when link is up\n- * @link_up_wait_to_complete: bool used to wait for link up or not\n+ * ixgbe_check_mac_link_generic - Determine link and speed status\n+ * @hw: pointer to hardware structure\n+ * @speed: pointer to link speed\n+ * @link_up: true when link is up\n+ * @link_up_wait_to_complete: bool used to wait for link up or not\n *\n- * Reads the links register to determine if link is up and the current speed\n+ * Reads the links register to determine if link is up and the current speed\n **/\n s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n \t\t\t\t bool *link_up, bool link_up_wait_to_complete)\n@@ -4299,14 +4299,14 @@ s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n }\n \n /**\n- * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from\n- * the EEPROM\n- * @hw: pointer to hardware structure\n- * @wwnn_prefix: the alternative WWNN prefix\n- * @wwpn_prefix: the alternative WWPN prefix\n+ * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from\n+ * the EEPROM\n+ * @hw: pointer to hardware structure\n+ * @wwnn_prefix: the alternative WWNN prefix\n+ * @wwpn_prefix: the alternative WWPN prefix\n *\n- * This function will read the EEPROM from the alternative SAN MAC address\n- * block to check the support for the alternative WWNN/WWPN prefix support.\n+ * This function will read the EEPROM from the alternative SAN MAC address\n+ * block to check the support for the alternative WWNN/WWPN prefix support.\n **/\n s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,\n \t\t\t\t u16 *wwpn_prefix)\n@@ -4357,11 +4357,11 @@ s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,\n }\n \n /**\n- * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM\n- * @hw: pointer to hardware structure\n- * @bs: the fcoe boot status\n+ * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM\n+ * @hw: pointer to hardware structure\n+ * @bs: the fcoe boot status\n *\n- * This function will read the FCOE boot status from the iSCSI FCOE block\n+ * This function will read the FCOE boot status from the iSCSI FCOE block\n **/\n s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)\n {\n@@ -4406,10 +4406,10 @@ s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)\n }\n \n /**\n- * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing\n- * @hw: pointer to hardware structure\n- * @enable: enable or disable switch for MAC anti-spoofing\n- * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing\n+ * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing\n+ * @hw: pointer to hardware structure\n+ * @enable: enable or disable switch for MAC anti-spoofing\n+ * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing\n *\n **/\n void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)\n@@ -4430,10 +4430,10 @@ void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)\n }\n \n /**\n- * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing\n- * @hw: pointer to hardware structure\n- * @enable: enable or disable switch for VLAN anti-spoofing\n- * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing\n+ * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing\n+ * @hw: pointer to hardware structure\n+ * @enable: enable or disable switch for VLAN anti-spoofing\n+ * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing\n *\n **/\n void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)\n@@ -4454,12 +4454,12 @@ void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)\n }\n \n /**\n- * ixgbe_get_device_caps_generic - Get additional device capabilities\n- * @hw: pointer to hardware structure\n- * @device_caps: the EEPROM word with the extra device capabilities\n+ * ixgbe_get_device_caps_generic - Get additional device capabilities\n+ * @hw: pointer to hardware structure\n+ * @device_caps: the EEPROM word with the extra device capabilities\n *\n- * This function will read the EEPROM location for the device capabilities,\n- * and return the word through device_caps.\n+ * This function will read the EEPROM location for the device capabilities,\n+ * and return the word through device_caps.\n **/\n s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)\n {\n@@ -4471,8 +4471,8 @@ s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)\n }\n \n /**\n- * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering\n- * @hw: pointer to hardware structure\n+ * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering\n+ * @hw: pointer to hardware structure\n *\n **/\n void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)\n@@ -4499,11 +4499,11 @@ void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_calculate_checksum - Calculate checksum for buffer\n- * @buffer: pointer to EEPROM\n- * @length: size of EEPROM to calculate a checksum for\n- * Calculates the checksum for some buffer on a specified length. The\n- * checksum calculated is returned.\n+ * ixgbe_calculate_checksum - Calculate checksum for buffer\n+ * @buffer: pointer to EEPROM\n+ * @length: size of EEPROM to calculate a checksum for\n+ * Calculates the checksum for some buffer on a specified length. The\n+ * checksum calculated is returned.\n **/\n u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)\n {\n@@ -4522,18 +4522,18 @@ u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)\n }\n \n /**\n- * ixgbe_hic_unlocked - Issue command to manageability block unlocked\n- * @hw: pointer to the HW structure\n- * @buffer: command to write and where the return status will be placed\n- * @length: length of buffer, must be multiple of 4 bytes\n- * @timeout: time in ms to wait for command completion\n+ * ixgbe_hic_unlocked - Issue command to manageability block unlocked\n+ * @hw: pointer to the HW structure\n+ * @buffer: command to write and where the return status will be placed\n+ * @length: length of buffer, must be multiple of 4 bytes\n+ * @timeout: time in ms to wait for command completion\n *\n- * Communicates with the manageability block. On success return IXGBE_SUCCESS\n- * else returns semaphore error when encountering an error acquiring\n- * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.\n+ * Communicates with the manageability block. On success return IXGBE_SUCCESS\n+ * else returns semaphore error when encountering an error acquiring\n+ * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.\n *\n- * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held\n- * by the caller.\n+ * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held\n+ * by the caller.\n **/\n s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,\n \t\t u32 timeout)\n@@ -4603,22 +4603,22 @@ s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,\n }\n \n /**\n- * ixgbe_host_interface_command - Issue command to manageability block\n- * @hw: pointer to the HW structure\n- * @buffer: contains the command to write and where the return status will\n- * be placed\n- * @length: length of buffer, must be multiple of 4 bytes\n- * @timeout: time in ms to wait for command completion\n- * @return_data: read and return data from the buffer (true) or not (false)\n- * Needed because FW structures are big endian and decoding of\n- * these fields can be 8 bit or 16 bit based on command. Decoding\n- * is not easily understood without making a table of commands.\n- * So we will leave this up to the caller to read back the data\n- * in these cases.\n+ * ixgbe_host_interface_command - Issue command to manageability block\n+ * @hw: pointer to the HW structure\n+ * @buffer: contains the command to write and where the return status will\n+ * be placed\n+ * @length: length of buffer, must be multiple of 4 bytes\n+ * @timeout: time in ms to wait for command completion\n+ * @return_data: read and return data from the buffer (true) or not (false)\n+ * Needed because FW structures are big endian and decoding of\n+ * these fields can be 8 bit or 16 bit based on command. Decoding\n+ * is not easily understood without making a table of commands.\n+ * So we will leave this up to the caller to read back the data\n+ * in these cases.\n *\n- * Communicates with the manageability block. On success return IXGBE_SUCCESS\n- * else returns semaphore error when encountering an error acquiring\n- * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.\n+ * Communicates with the manageability block. On success return IXGBE_SUCCESS\n+ * else returns semaphore error when encountering an error acquiring\n+ * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.\n **/\n s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,\n \t\t\t\t u32 length, u32 timeout, bool return_data)\n@@ -4700,19 +4700,19 @@ s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,\n }\n \n /**\n- * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware\n- * @hw: pointer to the HW structure\n- * @maj: driver version major number\n- * @min: driver version minor number\n- * @build: driver version build number\n- * @sub: driver version sub build number\n- * @len: unused\n- * @driver_ver: unused\n+ * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware\n+ * @hw: pointer to the HW structure\n+ * @maj: driver version major number\n+ * @min: driver version minor number\n+ * @build: driver version build number\n+ * @sub: driver version sub build number\n+ * @len: unused\n+ * @driver_ver: unused\n *\n- * Sends driver version number to firmware through the manageability\n- * block. On success return IXGBE_SUCCESS\n- * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring\n- * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.\n+ * Sends driver version number to firmware through the manageability\n+ * block. On success return IXGBE_SUCCESS\n+ * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring\n+ * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.\n **/\n s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,\n \t\t\t\t u8 build, u8 sub, u16 len,\n@@ -4893,10 +4893,10 @@ STATIC const u8 ixgbe_emc_therm_limit[4] = {\n };\n \n /**\n- * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data\n+ * @hw: pointer to hardware structure\n *\n- * Returns the thermal sensor data structure\n+ * Returns the thermal sensor data structure\n **/\n s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)\n {\n@@ -4967,11 +4967,11 @@ s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds\n+ * @hw: pointer to hardware structure\n *\n- * Inits the thermal sensor thresholds according to the NVM map\n- * and save off the threshold and location values into mac.thermal_sensor_data\n+ * Inits the thermal sensor thresholds according to the NVM map\n+ * and save off the threshold and location values into mac.thermal_sensor_data\n **/\n s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)\n {\n@@ -5048,13 +5048,13 @@ s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_get_orom_version - Return option ROM from EEPROM\n+ * ixgbe_get_orom_version - Return option ROM from EEPROM\n *\n- * @hw: pointer to hardware structure\n- * @nvm_ver: pointer to output structure\n+ * @hw: pointer to hardware structure\n+ * @nvm_ver: pointer to output structure\n *\n- * if valid option ROM version, nvm_ver->or_valid set to true\n- * else nvm_ver->or_valid is false.\n+ * if valid option ROM version, nvm_ver->or_valid set to true\n+ * else nvm_ver->or_valid is false.\n **/\n void ixgbe_get_orom_version(struct ixgbe_hw *hw,\n \t\t\t struct ixgbe_nvm_version *nvm_ver)\n@@ -5086,13 +5086,13 @@ void ixgbe_get_orom_version(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_get_oem_prod_version - Return OEM Product version\n+ * ixgbe_get_oem_prod_version - Return OEM Product version\n *\n- * @hw: pointer to hardware structure\n- * @nvm_ver: pointer to output structure\n+ * @hw: pointer to hardware structure\n+ * @nvm_ver: pointer to output structure\n *\n- * if valid OEM product version, nvm_ver->oem_valid set to true\n- * else nvm_ver->oem_valid is false.\n+ * if valid OEM product version, nvm_ver->oem_valid set to true\n+ * else nvm_ver->oem_valid is false.\n **/\n void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,\n \t\t\t\tstruct ixgbe_nvm_version *nvm_ver)\n@@ -5130,12 +5130,12 @@ void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_get_etk_id - Return Etrack ID from EEPROM\n+ * ixgbe_get_etk_id - Return Etrack ID from EEPROM\n *\n- * @hw: pointer to hardware structure\n- * @nvm_ver: pointer to output structure\n+ * @hw: pointer to hardware structure\n+ * @nvm_ver: pointer to output structure\n *\n- * word read errors will return 0xFFFF\n+ * word read errors will return 0xFFFF\n **/\n void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver)\n {\n@@ -5261,12 +5261,12 @@ bool ixgbe_mng_enabled(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed\n- * @hw: pointer to hardware structure\n- * @speed: new link speed\n- * @autoneg_wait_to_complete: true when waiting for completion is needed\n+ * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed\n+ * @hw: pointer to hardware structure\n+ * @speed: new link speed\n+ * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n- * Set the link speed in the MAC and/or PHY register and restarts link.\n+ * Set the link speed in the MAC and/or PHY register and restarts link.\n **/\n s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,\n \t\t\t\t\t ixgbe_link_speed speed,\n@@ -5406,11 +5406,11 @@ s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_set_soft_rate_select_speed - Set module link speed\n- * @hw: pointer to hardware structure\n- * @speed: link speed to set\n+ * ixgbe_set_soft_rate_select_speed - Set module link speed\n+ * @hw: pointer to hardware structure\n+ * @speed: link speed to set\n *\n- * Set module link speed via the soft rate select.\n+ * Set module link speed via the soft rate select.\n */\n void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,\n \t\t\t\t\tixgbe_link_speed speed)\ndiff --git a/drivers/net/ixgbe/base/ixgbe_dcb.c b/drivers/net/ixgbe/base/ixgbe_dcb.c\nindex 53def2146..41469c10d 100644\n--- a/drivers/net/ixgbe/base/ixgbe_dcb.c\n+++ b/drivers/net/ixgbe/base/ixgbe_dcb.c\n@@ -270,11 +270,11 @@ void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *cfg, int direction,\n * The following rules are checked:\n * 1. The sum of bandwidth percentages of all Bandwidth Groups must total 100%.\n * 2. The sum of bandwidth percentages of all Traffic Classes within a Bandwidth\n- * Group must total 100.\n+ * Group must total 100.\n * 3. A Traffic Class should not be set to both Link Strict Priority\n- * and Group Strict Priority.\n+ * and Group Strict Priority.\n * 4. Link strict Bandwidth Groups can only have link strict traffic classes\n- * with zero bandwidth.\n+ * with zero bandwidth.\n */\n s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *dcb_config)\n {\ndiff --git a/drivers/net/ixgbe/base/ixgbe_hv_vf.c b/drivers/net/ixgbe/base/ixgbe_hv_vf.c\nindex 6005c4ac9..b7ad44ab8 100644\n--- a/drivers/net/ixgbe/base/ixgbe_hv_vf.c\n+++ b/drivers/net/ixgbe/base/ixgbe_hv_vf.c\n@@ -182,10 +182,10 @@ static s32 ixgbevf_hv_set_rlpml_vf(struct ixgbe_hw *hw, u16 max_size)\n }\n \n /**\n- * ixgbevf_hv_negotiate_api_version_vf - Negotiate supported API version\n- * @hw: pointer to the HW structure\n- * @api: integer containing requested API version\n- * Hyper-V version - only ixgbe_mbox_api_10 supported.\n+ * ixgbevf_hv_negotiate_api_version_vf - Negotiate supported API version\n+ * @hw: pointer to the HW structure\n+ * @api: integer containing requested API version\n+ * Hyper-V version - only ixgbe_mbox_api_10 supported.\n **/\n static int ixgbevf_hv_negotiate_api_version_vf(struct ixgbe_hw *hw, int api)\n {\n@@ -199,13 +199,13 @@ static int ixgbevf_hv_negotiate_api_version_vf(struct ixgbe_hw *hw, int api)\n }\n \n /**\n- * ixgbevf_hv_init_ops_vf - Initialize the pointers for vf\n- * @hw: pointer to hardware structure\n+ * ixgbevf_hv_init_ops_vf - Initialize the pointers for vf\n+ * @hw: pointer to hardware structure\n *\n- * This will assign function pointers, adapter-specific functions can\n- * override the assignment of generic function pointers by assigning\n- * their own adapter-specific function pointers.\n- * Does not touch the hardware.\n+ * This will assign function pointers, adapter-specific functions can\n+ * override the assignment of generic function pointers by assigning\n+ * their own adapter-specific function pointers.\n+ * Does not touch the hardware.\n **/\n s32 ixgbevf_hv_init_ops_vf(struct ixgbe_hw *hw)\n {\ndiff --git a/drivers/net/ixgbe/base/ixgbe_mbx.c b/drivers/net/ixgbe/base/ixgbe_mbx.c\nindex 058bf814e..0d6bb74f9 100644\n--- a/drivers/net/ixgbe/base/ixgbe_mbx.c\n+++ b/drivers/net/ixgbe/base/ixgbe_mbx.c\n@@ -6,13 +6,13 @@\n #include \"ixgbe_mbx.h\"\n \n /**\n- * ixgbe_read_mbx - Reads a message from the mailbox\n- * @hw: pointer to the HW structure\n- * @msg: The message buffer\n- * @size: Length of buffer\n- * @mbx_id: id of mailbox to read\n+ * ixgbe_read_mbx - Reads a message from the mailbox\n+ * @hw: pointer to the HW structure\n+ * @msg: The message buffer\n+ * @size: Length of buffer\n+ * @mbx_id: id of mailbox to read\n *\n- * returns SUCCESS if it successfully read message from buffer\n+ * returns SUCCESS if it successfully read message from buffer\n **/\n s32 ixgbe_read_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)\n {\n@@ -32,13 +32,13 @@ s32 ixgbe_read_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)\n }\n \n /**\n- * ixgbe_write_mbx - Write a message to the mailbox\n- * @hw: pointer to the HW structure\n- * @msg: The message buffer\n- * @size: Length of buffer\n- * @mbx_id: id of mailbox to write\n+ * ixgbe_write_mbx - Write a message to the mailbox\n+ * @hw: pointer to the HW structure\n+ * @msg: The message buffer\n+ * @size: Length of buffer\n+ * @mbx_id: id of mailbox to write\n *\n- * returns SUCCESS if it successfully copied message into the buffer\n+ * returns SUCCESS if it successfully copied message into the buffer\n **/\n s32 ixgbe_write_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)\n {\n@@ -58,11 +58,11 @@ s32 ixgbe_write_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)\n }\n \n /**\n- * ixgbe_check_for_msg - checks to see if someone sent us mail\n- * @hw: pointer to the HW structure\n- * @mbx_id: id of mailbox to check\n+ * ixgbe_check_for_msg - checks to see if someone sent us mail\n+ * @hw: pointer to the HW structure\n+ * @mbx_id: id of mailbox to check\n *\n- * returns SUCCESS if the Status bit was found or else ERR_MBX\n+ * returns SUCCESS if the Status bit was found or else ERR_MBX\n **/\n s32 ixgbe_check_for_msg(struct ixgbe_hw *hw, u16 mbx_id)\n {\n@@ -78,11 +78,11 @@ s32 ixgbe_check_for_msg(struct ixgbe_hw *hw, u16 mbx_id)\n }\n \n /**\n- * ixgbe_check_for_ack - checks to see if someone sent us ACK\n- * @hw: pointer to the HW structure\n- * @mbx_id: id of mailbox to check\n+ * ixgbe_check_for_ack - checks to see if someone sent us ACK\n+ * @hw: pointer to the HW structure\n+ * @mbx_id: id of mailbox to check\n *\n- * returns SUCCESS if the Status bit was found or else ERR_MBX\n+ * returns SUCCESS if the Status bit was found or else ERR_MBX\n **/\n s32 ixgbe_check_for_ack(struct ixgbe_hw *hw, u16 mbx_id)\n {\n@@ -98,11 +98,11 @@ s32 ixgbe_check_for_ack(struct ixgbe_hw *hw, u16 mbx_id)\n }\n \n /**\n- * ixgbe_check_for_rst - checks to see if other side has reset\n- * @hw: pointer to the HW structure\n- * @mbx_id: id of mailbox to check\n+ * ixgbe_check_for_rst - checks to see if other side has reset\n+ * @hw: pointer to the HW structure\n+ * @mbx_id: id of mailbox to check\n *\n- * returns SUCCESS if the Status bit was found or else ERR_MBX\n+ * returns SUCCESS if the Status bit was found or else ERR_MBX\n **/\n s32 ixgbe_check_for_rst(struct ixgbe_hw *hw, u16 mbx_id)\n {\n@@ -118,11 +118,11 @@ s32 ixgbe_check_for_rst(struct ixgbe_hw *hw, u16 mbx_id)\n }\n \n /**\n- * ixgbe_clear_mbx - Clear Mailbox Memory\n- * @hw: pointer to the HW structure\n- * @vf_number: id of mailbox to write\n+ * ixgbe_clear_mbx - Clear Mailbox Memory\n+ * @hw: pointer to the HW structure\n+ * @vf_number: id of mailbox to write\n *\n- * Set VFMBMEM of given VF to 0x0.\n+ * Set VFMBMEM of given VF to 0x0.\n **/\n s32 ixgbe_clear_mbx(struct ixgbe_hw *hw, u16 vf_number)\n {\n@@ -138,11 +138,11 @@ s32 ixgbe_clear_mbx(struct ixgbe_hw *hw, u16 vf_number)\n }\n \n /**\n- * ixgbe_poll_for_msg - Wait for message notification\n- * @hw: pointer to the HW structure\n- * @mbx_id: id of mailbox to write\n+ * ixgbe_poll_for_msg - Wait for message notification\n+ * @hw: pointer to the HW structure\n+ * @mbx_id: id of mailbox to write\n *\n- * returns SUCCESS if it successfully received a message notification\n+ * returns SUCCESS if it successfully received a message notification\n **/\n STATIC s32 ixgbe_poll_for_msg(struct ixgbe_hw *hw, u16 mbx_id)\n {\n@@ -170,11 +170,11 @@ STATIC s32 ixgbe_poll_for_msg(struct ixgbe_hw *hw, u16 mbx_id)\n }\n \n /**\n- * ixgbe_poll_for_ack - Wait for message acknowledgment\n- * @hw: pointer to the HW structure\n- * @mbx_id: id of mailbox to write\n+ * ixgbe_poll_for_ack - Wait for message acknowledgment\n+ * @hw: pointer to the HW structure\n+ * @mbx_id: id of mailbox to write\n *\n- * returns SUCCESS if it successfully received a message acknowledgment\n+ * returns SUCCESS if it successfully received a message acknowledgment\n **/\n STATIC s32 ixgbe_poll_for_ack(struct ixgbe_hw *hw, u16 mbx_id)\n {\n@@ -202,14 +202,14 @@ STATIC s32 ixgbe_poll_for_ack(struct ixgbe_hw *hw, u16 mbx_id)\n }\n \n /**\n- * ixgbe_read_posted_mbx - Wait for message notification and receive message\n- * @hw: pointer to the HW structure\n- * @msg: The message buffer\n- * @size: Length of buffer\n- * @mbx_id: id of mailbox to write\n+ * ixgbe_read_posted_mbx - Wait for message notification and receive message\n+ * @hw: pointer to the HW structure\n+ * @msg: The message buffer\n+ * @size: Length of buffer\n+ * @mbx_id: id of mailbox to write\n *\n- * returns SUCCESS if it successfully received a message notification and\n- * copied it into the receive buffer.\n+ * returns SUCCESS if it successfully received a message notification and\n+ * copied it into the receive buffer.\n **/\n s32 ixgbe_read_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)\n {\n@@ -231,14 +231,14 @@ s32 ixgbe_read_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)\n }\n \n /**\n- * ixgbe_write_posted_mbx - Write a message to the mailbox, wait for ack\n- * @hw: pointer to the HW structure\n- * @msg: The message buffer\n- * @size: Length of buffer\n- * @mbx_id: id of mailbox to write\n+ * ixgbe_write_posted_mbx - Write a message to the mailbox, wait for ack\n+ * @hw: pointer to the HW structure\n+ * @msg: The message buffer\n+ * @size: Length of buffer\n+ * @mbx_id: id of mailbox to write\n *\n- * returns SUCCESS if it successfully copied message into the buffer and\n- * received an ack to that message within delay * timeout period\n+ * returns SUCCESS if it successfully copied message into the buffer and\n+ * received an ack to that message within delay * timeout period\n **/\n s32 ixgbe_write_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size,\n \t\t\t u16 mbx_id)\n@@ -263,10 +263,10 @@ s32 ixgbe_write_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size,\n }\n \n /**\n- * ixgbe_init_mbx_ops_generic - Initialize MB function pointers\n- * @hw: pointer to the HW structure\n+ * ixgbe_init_mbx_ops_generic - Initialize MB function pointers\n+ * @hw: pointer to the HW structure\n *\n- * Setups up the mailbox read and write message function pointers\n+ * Setups up the mailbox read and write message function pointers\n **/\n void ixgbe_init_mbx_ops_generic(struct ixgbe_hw *hw)\n {\n@@ -277,11 +277,11 @@ void ixgbe_init_mbx_ops_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_read_v2p_mailbox - read v2p mailbox\n- * @hw: pointer to the HW structure\n+ * ixgbe_read_v2p_mailbox - read v2p mailbox\n+ * @hw: pointer to the HW structure\n *\n- * This function is used to read the v2p mailbox without losing the read to\n- * clear status bits.\n+ * This function is used to read the v2p mailbox without losing the read to\n+ * clear status bits.\n **/\n STATIC u32 ixgbe_read_v2p_mailbox(struct ixgbe_hw *hw)\n {\n@@ -294,12 +294,12 @@ STATIC u32 ixgbe_read_v2p_mailbox(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_check_for_bit_vf - Determine if a status bit was set\n- * @hw: pointer to the HW structure\n- * @mask: bitmask for bits to be tested and cleared\n+ * ixgbe_check_for_bit_vf - Determine if a status bit was set\n+ * @hw: pointer to the HW structure\n+ * @mask: bitmask for bits to be tested and cleared\n *\n- * This function is used to check for the read to clear bits within\n- * the V2P mailbox.\n+ * This function is used to check for the read to clear bits within\n+ * the V2P mailbox.\n **/\n STATIC s32 ixgbe_check_for_bit_vf(struct ixgbe_hw *hw, u32 mask)\n {\n@@ -315,11 +315,11 @@ STATIC s32 ixgbe_check_for_bit_vf(struct ixgbe_hw *hw, u32 mask)\n }\n \n /**\n- * ixgbe_check_for_msg_vf - checks to see if the PF has sent mail\n- * @hw: pointer to the HW structure\n- * @mbx_id: id of mailbox to check\n+ * ixgbe_check_for_msg_vf - checks to see if the PF has sent mail\n+ * @hw: pointer to the HW structure\n+ * @mbx_id: id of mailbox to check\n *\n- * returns SUCCESS if the PF has set the Status bit or else ERR_MBX\n+ * returns SUCCESS if the PF has set the Status bit or else ERR_MBX\n **/\n STATIC s32 ixgbe_check_for_msg_vf(struct ixgbe_hw *hw, u16 mbx_id)\n {\n@@ -337,11 +337,11 @@ STATIC s32 ixgbe_check_for_msg_vf(struct ixgbe_hw *hw, u16 mbx_id)\n }\n \n /**\n- * ixgbe_check_for_ack_vf - checks to see if the PF has ACK'd\n- * @hw: pointer to the HW structure\n- * @mbx_id: id of mailbox to check\n+ * ixgbe_check_for_ack_vf - checks to see if the PF has ACK'd\n+ * @hw: pointer to the HW structure\n+ * @mbx_id: id of mailbox to check\n *\n- * returns SUCCESS if the PF has set the ACK bit or else ERR_MBX\n+ * returns SUCCESS if the PF has set the ACK bit or else ERR_MBX\n **/\n STATIC s32 ixgbe_check_for_ack_vf(struct ixgbe_hw *hw, u16 mbx_id)\n {\n@@ -359,11 +359,11 @@ STATIC s32 ixgbe_check_for_ack_vf(struct ixgbe_hw *hw, u16 mbx_id)\n }\n \n /**\n- * ixgbe_check_for_rst_vf - checks to see if the PF has reset\n- * @hw: pointer to the HW structure\n- * @mbx_id: id of mailbox to check\n+ * ixgbe_check_for_rst_vf - checks to see if the PF has reset\n+ * @hw: pointer to the HW structure\n+ * @mbx_id: id of mailbox to check\n *\n- * returns true if the PF has set the reset done bit or else false\n+ * returns true if the PF has set the reset done bit or else false\n **/\n STATIC s32 ixgbe_check_for_rst_vf(struct ixgbe_hw *hw, u16 mbx_id)\n {\n@@ -382,10 +382,10 @@ STATIC s32 ixgbe_check_for_rst_vf(struct ixgbe_hw *hw, u16 mbx_id)\n }\n \n /**\n- * ixgbe_obtain_mbx_lock_vf - obtain mailbox lock\n- * @hw: pointer to the HW structure\n+ * ixgbe_obtain_mbx_lock_vf - obtain mailbox lock\n+ * @hw: pointer to the HW structure\n *\n- * return SUCCESS if we obtained the mailbox lock\n+ * return SUCCESS if we obtained the mailbox lock\n **/\n STATIC s32 ixgbe_obtain_mbx_lock_vf(struct ixgbe_hw *hw)\n {\n@@ -404,13 +404,13 @@ STATIC s32 ixgbe_obtain_mbx_lock_vf(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_write_mbx_vf - Write a message to the mailbox\n- * @hw: pointer to the HW structure\n- * @msg: The message buffer\n- * @size: Length of buffer\n- * @mbx_id: id of mailbox to write\n+ * ixgbe_write_mbx_vf - Write a message to the mailbox\n+ * @hw: pointer to the HW structure\n+ * @msg: The message buffer\n+ * @size: Length of buffer\n+ * @mbx_id: id of mailbox to write\n *\n- * returns SUCCESS if it successfully copied message into the buffer\n+ * returns SUCCESS if it successfully copied message into the buffer\n **/\n STATIC s32 ixgbe_write_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size,\n \t\t\t u16 mbx_id)\n@@ -446,13 +446,13 @@ STATIC s32 ixgbe_write_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size,\n }\n \n /**\n- * ixgbe_read_mbx_vf - Reads a message from the inbox intended for vf\n- * @hw: pointer to the HW structure\n- * @msg: The message buffer\n- * @size: Length of buffer\n- * @mbx_id: id of mailbox to read\n+ * ixgbe_read_mbx_vf - Reads a message from the inbox intended for vf\n+ * @hw: pointer to the HW structure\n+ * @msg: The message buffer\n+ * @size: Length of buffer\n+ * @mbx_id: id of mailbox to read\n *\n- * returns SUCCESS if it successfully read message from buffer\n+ * returns SUCCESS if it successfully read message from buffer\n **/\n STATIC s32 ixgbe_read_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size,\n \t\t\t u16 mbx_id)\n@@ -483,10 +483,10 @@ STATIC s32 ixgbe_read_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size,\n }\n \n /**\n- * ixgbe_init_mbx_params_vf - set initial values for vf mailbox\n- * @hw: pointer to the HW structure\n+ * ixgbe_init_mbx_params_vf - set initial values for vf mailbox\n+ * @hw: pointer to the HW structure\n *\n- * Initializes the hw->mbx struct to correct values for vf mailbox\n+ * Initializes the hw->mbx struct to correct values for vf mailbox\n */\n void ixgbe_init_mbx_params_vf(struct ixgbe_hw *hw)\n {\n@@ -529,11 +529,11 @@ STATIC s32 ixgbe_check_for_bit_pf(struct ixgbe_hw *hw, u32 mask, s32 index)\n }\n \n /**\n- * ixgbe_check_for_msg_pf - checks to see if the VF has sent mail\n- * @hw: pointer to the HW structure\n- * @vf_number: the VF index\n+ * ixgbe_check_for_msg_pf - checks to see if the VF has sent mail\n+ * @hw: pointer to the HW structure\n+ * @vf_number: the VF index\n *\n- * returns SUCCESS if the VF has set the Status bit or else ERR_MBX\n+ * returns SUCCESS if the VF has set the Status bit or else ERR_MBX\n **/\n STATIC s32 ixgbe_check_for_msg_pf(struct ixgbe_hw *hw, u16 vf_number)\n {\n@@ -553,11 +553,11 @@ STATIC s32 ixgbe_check_for_msg_pf(struct ixgbe_hw *hw, u16 vf_number)\n }\n \n /**\n- * ixgbe_check_for_ack_pf - checks to see if the VF has ACKed\n- * @hw: pointer to the HW structure\n- * @vf_number: the VF index\n+ * ixgbe_check_for_ack_pf - checks to see if the VF has ACKed\n+ * @hw: pointer to the HW structure\n+ * @vf_number: the VF index\n *\n- * returns SUCCESS if the VF has set the Status bit or else ERR_MBX\n+ * returns SUCCESS if the VF has set the Status bit or else ERR_MBX\n **/\n STATIC s32 ixgbe_check_for_ack_pf(struct ixgbe_hw *hw, u16 vf_number)\n {\n@@ -577,11 +577,11 @@ STATIC s32 ixgbe_check_for_ack_pf(struct ixgbe_hw *hw, u16 vf_number)\n }\n \n /**\n- * ixgbe_check_for_rst_pf - checks to see if the VF has reset\n- * @hw: pointer to the HW structure\n- * @vf_number: the VF index\n+ * ixgbe_check_for_rst_pf - checks to see if the VF has reset\n+ * @hw: pointer to the HW structure\n+ * @vf_number: the VF index\n *\n- * returns SUCCESS if the VF has set the Status bit or else ERR_MBX\n+ * returns SUCCESS if the VF has set the Status bit or else ERR_MBX\n **/\n STATIC s32 ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, u16 vf_number)\n {\n@@ -616,11 +616,11 @@ STATIC s32 ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, u16 vf_number)\n }\n \n /**\n- * ixgbe_obtain_mbx_lock_pf - obtain mailbox lock\n- * @hw: pointer to the HW structure\n- * @vf_number: the VF index\n+ * ixgbe_obtain_mbx_lock_pf - obtain mailbox lock\n+ * @hw: pointer to the HW structure\n+ * @vf_number: the VF index\n *\n- * return SUCCESS if we obtained the mailbox lock\n+ * return SUCCESS if we obtained the mailbox lock\n **/\n STATIC s32 ixgbe_obtain_mbx_lock_pf(struct ixgbe_hw *hw, u16 vf_number)\n {\n@@ -645,13 +645,13 @@ STATIC s32 ixgbe_obtain_mbx_lock_pf(struct ixgbe_hw *hw, u16 vf_number)\n }\n \n /**\n- * ixgbe_write_mbx_pf - Places a message in the mailbox\n- * @hw: pointer to the HW structure\n- * @msg: The message buffer\n- * @size: Length of buffer\n- * @vf_number: the VF index\n+ * ixgbe_write_mbx_pf - Places a message in the mailbox\n+ * @hw: pointer to the HW structure\n+ * @msg: The message buffer\n+ * @size: Length of buffer\n+ * @vf_number: the VF index\n *\n- * returns SUCCESS if it successfully copied message into the buffer\n+ * returns SUCCESS if it successfully copied message into the buffer\n **/\n STATIC s32 ixgbe_write_mbx_pf(struct ixgbe_hw *hw, u32 *msg, u16 size,\n \t\t\t u16 vf_number)\n@@ -686,15 +686,15 @@ STATIC s32 ixgbe_write_mbx_pf(struct ixgbe_hw *hw, u32 *msg, u16 size,\n }\n \n /**\n- * ixgbe_read_mbx_pf - Read a message from the mailbox\n- * @hw: pointer to the HW structure\n- * @msg: The message buffer\n- * @size: Length of buffer\n- * @vf_number: the VF index\n+ * ixgbe_read_mbx_pf - Read a message from the mailbox\n+ * @hw: pointer to the HW structure\n+ * @msg: The message buffer\n+ * @size: Length of buffer\n+ * @vf_number: the VF index\n *\n- * This function copies a message from the mailbox buffer to the caller's\n- * memory buffer. The presumption is that the caller knows that there was\n- * a message due to a VF request so no polling for message is needed.\n+ * This function copies a message from the mailbox buffer to the caller's\n+ * memory buffer. The presumption is that the caller knows that there was\n+ * a message due to a VF request so no polling for message is needed.\n **/\n STATIC s32 ixgbe_read_mbx_pf(struct ixgbe_hw *hw, u32 *msg, u16 size,\n \t\t\t u16 vf_number)\n@@ -724,11 +724,11 @@ STATIC s32 ixgbe_read_mbx_pf(struct ixgbe_hw *hw, u32 *msg, u16 size,\n }\n \n /**\n- * ixgbe_clear_mbx_pf - Clear Mailbox Memory\n- * @hw: pointer to the HW structure\n- * @vf_number: the VF index\n+ * ixgbe_clear_mbx_pf - Clear Mailbox Memory\n+ * @hw: pointer to the HW structure\n+ * @vf_number: the VF index\n *\n- * Set VFMBMEM of given VF to 0x0.\n+ * Set VFMBMEM of given VF to 0x0.\n **/\n STATIC s32 ixgbe_clear_mbx_pf(struct ixgbe_hw *hw, u16 vf_number)\n {\n@@ -745,10 +745,10 @@ STATIC s32 ixgbe_clear_mbx_pf(struct ixgbe_hw *hw, u16 vf_number)\n }\n \n /**\n- * ixgbe_init_mbx_params_pf - set initial values for pf mailbox\n- * @hw: pointer to the HW structure\n+ * ixgbe_init_mbx_params_pf - set initial values for pf mailbox\n+ * @hw: pointer to the HW structure\n *\n- * Initializes the hw->mbx struct to correct values for pf mailbox\n+ * Initializes the hw->mbx struct to correct values for pf mailbox\n */\n void ixgbe_init_mbx_params_pf(struct ixgbe_hw *hw)\n {\ndiff --git a/drivers/net/ixgbe/base/ixgbe_phy.c b/drivers/net/ixgbe/base/ixgbe_phy.c\nindex a8243fa97..13f00ac67 100644\n--- a/drivers/net/ixgbe/base/ixgbe_phy.c\n+++ b/drivers/net/ixgbe/base/ixgbe_phy.c\n@@ -214,10 +214,10 @@ s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,\n }\n \n /**\n- * ixgbe_init_phy_ops_generic - Inits PHY function ptrs\n- * @hw: pointer to the hardware structure\n+ * ixgbe_init_phy_ops_generic - Inits PHY function ptrs\n+ * @hw: pointer to the hardware structure\n *\n- * Initialize the function pointers.\n+ * Initialize the function pointers.\n **/\n s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)\n {\n@@ -288,10 +288,10 @@ static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)\n }\n \n /**\n- * ixgbe_identify_phy_generic - Get physical layer module\n- * @hw: pointer to hardware structure\n+ * ixgbe_identify_phy_generic - Get physical layer module\n+ * @hw: pointer to hardware structure\n *\n- * Determines the physical layer module found on the current adapter.\n+ * Determines the physical layer module found on the current adapter.\n **/\n s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)\n {\n@@ -367,9 +367,9 @@ s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_validate_phy_addr - Determines phy address is valid\n- * @hw: pointer to hardware structure\n- * @phy_addr: PHY address\n+ * ixgbe_validate_phy_addr - Determines phy address is valid\n+ * @hw: pointer to hardware structure\n+ * @phy_addr: PHY address\n *\n **/\n bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)\n@@ -392,8 +392,8 @@ bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)\n }\n \n /**\n- * ixgbe_get_phy_id - Get the phy type\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_phy_id - Get the phy type\n+ * @hw: pointer to hardware structure\n *\n **/\n s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)\n@@ -423,8 +423,8 @@ s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_get_phy_type_from_id - Get the phy type\n- * @phy_id: PHY ID information\n+ * ixgbe_get_phy_type_from_id - Get the phy type\n+ * @phy_id: PHY ID information\n *\n **/\n enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)\n@@ -464,8 +464,8 @@ enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)\n }\n \n /**\n- * ixgbe_reset_phy_generic - Performs a PHY reset\n- * @hw: pointer to hardware structure\n+ * ixgbe_reset_phy_generic - Performs a PHY reset\n+ * @hw: pointer to hardware structure\n **/\n s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)\n {\n@@ -543,12 +543,12 @@ s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without\n- * the SWFW lock\n- * @hw: pointer to hardware structure\n- * @reg_addr: 32 bit address of PHY register to read\n- * @device_type: 5 bit device type\n- * @phy_data: Pointer to read data from PHY register\n+ * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without\n+ * the SWFW lock\n+ * @hw: pointer to hardware structure\n+ * @reg_addr: 32 bit address of PHY register to read\n+ * @device_type: 5 bit device type\n+ * @phy_data: Pointer to read data from PHY register\n **/\n s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,\n \t\t\t u16 *phy_data)\n@@ -625,12 +625,12 @@ s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,\n }\n \n /**\n- * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register\n- * using the SWFW lock - this function is needed in most cases\n- * @hw: pointer to hardware structure\n- * @reg_addr: 32 bit address of PHY register to read\n- * @device_type: 5 bit device type\n- * @phy_data: Pointer to read data from PHY register\n+ * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register\n+ * using the SWFW lock - this function is needed in most cases\n+ * @hw: pointer to hardware structure\n+ * @reg_addr: 32 bit address of PHY register to read\n+ * @device_type: 5 bit device type\n+ * @phy_data: Pointer to read data from PHY register\n **/\n s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,\n \t\t\t u32 device_type, u16 *phy_data)\n@@ -651,12 +651,12 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,\n }\n \n /**\n- * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register\n- * without SWFW lock\n- * @hw: pointer to hardware structure\n- * @reg_addr: 32 bit PHY register to write\n- * @device_type: 5 bit device type\n- * @phy_data: Data to write to the PHY register\n+ * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register\n+ * without SWFW lock\n+ * @hw: pointer to hardware structure\n+ * @reg_addr: 32 bit PHY register to write\n+ * @device_type: 5 bit device type\n+ * @phy_data: Data to write to the PHY register\n **/\n s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,\n \t\t\t\tu32 device_type, u16 phy_data)\n@@ -725,12 +725,12 @@ s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,\n }\n \n /**\n- * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register\n- * using SWFW lock- this function is needed in most cases\n- * @hw: pointer to hardware structure\n- * @reg_addr: 32 bit PHY register to write\n- * @device_type: 5 bit device type\n- * @phy_data: Data to write to the PHY register\n+ * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register\n+ * using SWFW lock- this function is needed in most cases\n+ * @hw: pointer to hardware structure\n+ * @reg_addr: 32 bit PHY register to write\n+ * @device_type: 5 bit device type\n+ * @phy_data: Data to write to the PHY register\n **/\n s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,\n \t\t\t\tu32 device_type, u16 phy_data)\n@@ -752,10 +752,10 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,\n }\n \n /**\n- * ixgbe_setup_phy_link_generic - Set and restart auto-neg\n- * @hw: pointer to hardware structure\n+ * ixgbe_setup_phy_link_generic - Set and restart auto-neg\n+ * @hw: pointer to hardware structure\n *\n- * Restart auto-negotiation and PHY and waits for completion.\n+ * Restart auto-negotiation and PHY and waits for completion.\n **/\n s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)\n {\n@@ -843,10 +843,10 @@ s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities\n- * @hw: pointer to hardware structure\n- * @speed: new link speed\n- * @autoneg_wait_to_complete: unused\n+ * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities\n+ * @hw: pointer to hardware structure\n+ * @speed: new link speed\n+ * @autoneg_wait_to_complete: unused\n **/\n s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,\n \t\t\t\t ixgbe_link_speed speed,\n@@ -928,10 +928,10 @@ static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities\n- * @hw: pointer to hardware structure\n- * @speed: pointer to link speed\n- * @autoneg: boolean auto-negotiation value\n+ * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities\n+ * @hw: pointer to hardware structure\n+ * @speed: pointer to link speed\n+ * @autoneg: boolean auto-negotiation value\n **/\n s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,\n \t\t\t\t\t ixgbe_link_speed *speed,\n@@ -950,13 +950,13 @@ s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_check_phy_link_tnx - Determine link and speed status\n- * @hw: pointer to hardware structure\n- * @speed: current link speed\n- * @link_up: true is link is up, false otherwise\n+ * ixgbe_check_phy_link_tnx - Determine link and speed status\n+ * @hw: pointer to hardware structure\n+ * @speed: current link speed\n+ * @link_up: true is link is up, false otherwise\n *\n- * Reads the VS1 register to determine if link is up and the current speed for\n- * the PHY.\n+ * Reads the VS1 register to determine if link is up and the current speed for\n+ * the PHY.\n **/\n s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n \t\t\t bool *link_up)\n@@ -1079,9 +1079,9 @@ s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version\n- * @hw: pointer to hardware structure\n- * @firmware_version: pointer to the PHY Firmware Version\n+ * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version\n+ * @hw: pointer to hardware structure\n+ * @firmware_version: pointer to the PHY Firmware Version\n **/\n s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,\n \t\t\t\t u16 *firmware_version)\n@@ -1098,9 +1098,9 @@ s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version\n- * @hw: pointer to hardware structure\n- * @firmware_version: pointer to the PHY Firmware Version\n+ * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version\n+ * @hw: pointer to hardware structure\n+ * @firmware_version: pointer to the PHY Firmware Version\n **/\n s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,\n \t\t\t\t\t u16 *firmware_version)\n@@ -1117,8 +1117,8 @@ s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_reset_phy_nl - Performs a PHY reset\n- * @hw: pointer to hardware structure\n+ * ixgbe_reset_phy_nl - Performs a PHY reset\n+ * @hw: pointer to hardware structure\n **/\n s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)\n {\n@@ -1233,10 +1233,10 @@ s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_identify_module_generic - Identifies module type\n- * @hw: pointer to hardware structure\n+ * ixgbe_identify_module_generic - Identifies module type\n+ * @hw: pointer to hardware structure\n *\n- * Determines HW type and calls appropriate function.\n+ * Determines HW type and calls appropriate function.\n **/\n s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)\n {\n@@ -1263,10 +1263,10 @@ s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_identify_sfp_module_generic - Identifies SFP modules\n- * @hw: pointer to hardware structure\n+ * ixgbe_identify_sfp_module_generic - Identifies SFP modules\n+ * @hw: pointer to hardware structure\n *\n- * Searches for and identifies the SFP module and assigns appropriate PHY type.\n+ * Searches for and identifies the SFP module and assigns appropriate PHY type.\n **/\n s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)\n {\n@@ -1558,10 +1558,10 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type\n+ * @hw: pointer to hardware structure\n *\n- * Determines physical layer capabilities of the current SFP.\n+ * Determines physical layer capabilities of the current SFP.\n */\n u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)\n {\n@@ -1620,10 +1620,10 @@ u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules\n- * @hw: pointer to hardware structure\n+ * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules\n+ * @hw: pointer to hardware structure\n *\n- * Searches for and identifies the QSFP module and assigns appropriate PHY type\n+ * Searches for and identifies the QSFP module and assigns appropriate PHY type\n **/\n s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)\n {\n@@ -1813,13 +1813,13 @@ s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence\n- * @hw: pointer to hardware structure\n- * @list_offset: offset to the SFP ID list\n- * @data_offset: offset to the SFP data block\n+ * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence\n+ * @hw: pointer to hardware structure\n+ * @list_offset: offset to the SFP ID list\n+ * @data_offset: offset to the SFP data block\n *\n- * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if\n- * so it returns the offsets to the phy init sequence block.\n+ * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if\n+ * so it returns the offsets to the phy init sequence block.\n **/\n s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,\n \t\t\t\t\tu16 *list_offset,\n@@ -1910,12 +1910,12 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface\n- * @hw: pointer to hardware structure\n- * @byte_offset: EEPROM byte offset to read\n- * @eeprom_data: value read\n+ * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: EEPROM byte offset to read\n+ * @eeprom_data: value read\n *\n- * Performs byte read operation to SFP module's EEPROM over I2C interface.\n+ * Performs byte read operation to SFP module's EEPROM over I2C interface.\n **/\n s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\t\t u8 *eeprom_data)\n@@ -1928,12 +1928,12 @@ s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,\n }\n \n /**\n- * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface\n- * @hw: pointer to hardware structure\n- * @byte_offset: byte offset at address 0xA2\n- * @sff8472_data: value read\n+ * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: byte offset at address 0xA2\n+ * @sff8472_data: value read\n *\n- * Performs byte read operation to SFP module's SFF-8472 data over I2C\n+ * Performs byte read operation to SFP module's SFF-8472 data over I2C\n **/\n STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\t\t\t u8 *sff8472_data)\n@@ -1944,12 +1944,12 @@ STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,\n }\n \n /**\n- * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface\n- * @hw: pointer to hardware structure\n- * @byte_offset: EEPROM byte offset to write\n- * @eeprom_data: value to write\n+ * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: EEPROM byte offset to write\n+ * @eeprom_data: value to write\n *\n- * Performs byte write operation to SFP module's EEPROM over I2C interface.\n+ * Performs byte write operation to SFP module's EEPROM over I2C interface.\n **/\n s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\t\t u8 eeprom_data)\n@@ -1977,15 +1977,15 @@ STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)\n }\n \n /**\n- * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C\n- * @hw: pointer to hardware structure\n- * @byte_offset: byte offset to read\n- * @dev_addr: address to read from\n- * @data: value read\n- * @lock: true if to take and release semaphore\n+ * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: byte offset to read\n+ * @dev_addr: address to read from\n+ * @data: value read\n+ * @lock: true if to take and release semaphore\n *\n- * Performs byte read operation to SFP module's EEPROM over I2C interface at\n- * a specified device address.\n+ * Performs byte read operation to SFP module's EEPROM over I2C interface at\n+ * a specified device address.\n **/\n STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\t\t\t u8 dev_addr, u8 *data, bool lock)\n@@ -2069,14 +2069,14 @@ STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,\n }\n \n /**\n- * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C\n- * @hw: pointer to hardware structure\n- * @byte_offset: byte offset to read\n- * @dev_addr: address to read from\n- * @data: value read\n+ * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: byte offset to read\n+ * @dev_addr: address to read from\n+ * @data: value read\n *\n- * Performs byte read operation to SFP module's EEPROM over I2C interface at\n- * a specified device address.\n+ * Performs byte read operation to SFP module's EEPROM over I2C interface at\n+ * a specified device address.\n **/\n s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\t\tu8 dev_addr, u8 *data)\n@@ -2086,14 +2086,14 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,\n }\n \n /**\n- * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C\n- * @hw: pointer to hardware structure\n- * @byte_offset: byte offset to read\n- * @dev_addr: address to read from\n- * @data: value read\n+ * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: byte offset to read\n+ * @dev_addr: address to read from\n+ * @data: value read\n *\n- * Performs byte read operation to SFP module's EEPROM over I2C interface at\n- * a specified device address.\n+ * Performs byte read operation to SFP module's EEPROM over I2C interface at\n+ * a specified device address.\n **/\n s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\t\t\t u8 dev_addr, u8 *data)\n@@ -2103,15 +2103,15 @@ s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,\n }\n \n /**\n- * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C\n- * @hw: pointer to hardware structure\n- * @byte_offset: byte offset to write\n- * @dev_addr: address to write to\n- * @data: value to write\n- * @lock: true if to take and release semaphore\n+ * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: byte offset to write\n+ * @dev_addr: address to write to\n+ * @data: value to write\n+ * @lock: true if to take and release semaphore\n *\n- * Performs byte write operation to SFP module's EEPROM over I2C interface at\n- * a specified device address.\n+ * Performs byte write operation to SFP module's EEPROM over I2C interface at\n+ * a specified device address.\n **/\n STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\t\t\t u8 dev_addr, u8 data, bool lock)\n@@ -2175,14 +2175,14 @@ STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,\n }\n \n /**\n- * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C\n- * @hw: pointer to hardware structure\n- * @byte_offset: byte offset to write\n- * @dev_addr: address to write to\n- * @data: value to write\n+ * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: byte offset to write\n+ * @dev_addr: address to write to\n+ * @data: value to write\n *\n- * Performs byte write operation to SFP module's EEPROM over I2C interface at\n- * a specified device address.\n+ * Performs byte write operation to SFP module's EEPROM over I2C interface at\n+ * a specified device address.\n **/\n s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\t\t u8 dev_addr, u8 data)\n@@ -2192,14 +2192,14 @@ s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,\n }\n \n /**\n- * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C\n- * @hw: pointer to hardware structure\n- * @byte_offset: byte offset to write\n- * @dev_addr: address to write to\n- * @data: value to write\n+ * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: byte offset to write\n+ * @dev_addr: address to write to\n+ * @data: value to write\n *\n- * Performs byte write operation to SFP module's EEPROM over I2C interface at\n- * a specified device address.\n+ * Performs byte write operation to SFP module's EEPROM over I2C interface at\n+ * a specified device address.\n **/\n s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\t\t\t u8 dev_addr, u8 data)\n@@ -2209,11 +2209,11 @@ s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,\n }\n \n /**\n- * ixgbe_i2c_start - Sets I2C start condition\n- * @hw: pointer to hardware structure\n+ * ixgbe_i2c_start - Sets I2C start condition\n+ * @hw: pointer to hardware structure\n *\n- * Sets I2C start condition (High -> Low on SDA while SCL is High)\n- * Set bit-bang mode on X550 hardware.\n+ * Sets I2C start condition (High -> Low on SDA while SCL is High)\n+ * Set bit-bang mode on X550 hardware.\n **/\n STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)\n {\n@@ -2243,12 +2243,12 @@ STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_i2c_stop - Sets I2C stop condition\n- * @hw: pointer to hardware structure\n+ * ixgbe_i2c_stop - Sets I2C stop condition\n+ * @hw: pointer to hardware structure\n *\n- * Sets I2C stop condition (Low -> High on SDA while SCL is High)\n- * Disables bit-bang mode and negates data output enable on X550\n- * hardware.\n+ * Sets I2C stop condition (Low -> High on SDA while SCL is High)\n+ * Disables bit-bang mode and negates data output enable on X550\n+ * hardware.\n **/\n STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)\n {\n@@ -2280,11 +2280,11 @@ STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C\n- * @hw: pointer to hardware structure\n- * @data: data byte to clock in\n+ * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C\n+ * @hw: pointer to hardware structure\n+ * @data: data byte to clock in\n *\n- * Clocks in one byte data via I2C data/clock\n+ * Clocks in one byte data via I2C data/clock\n **/\n STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)\n {\n@@ -2303,11 +2303,11 @@ STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)\n }\n \n /**\n- * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C\n- * @hw: pointer to hardware structure\n- * @data: data byte clocked out\n+ * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C\n+ * @hw: pointer to hardware structure\n+ * @data: data byte clocked out\n *\n- * Clocks out one byte data via I2C data/clock\n+ * Clocks out one byte data via I2C data/clock\n **/\n STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)\n {\n@@ -2337,10 +2337,10 @@ STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)\n }\n \n /**\n- * ixgbe_get_i2c_ack - Polls for I2C ACK\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_i2c_ack - Polls for I2C ACK\n+ * @hw: pointer to hardware structure\n *\n- * Clocks in/out one bit via I2C data/clock\n+ * Clocks in/out one bit via I2C data/clock\n **/\n STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)\n {\n@@ -2389,11 +2389,11 @@ STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock\n- * @hw: pointer to hardware structure\n- * @data: read data value\n+ * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock\n+ * @hw: pointer to hardware structure\n+ * @data: read data value\n *\n- * Clocks in one bit via I2C data/clock\n+ * Clocks in one bit via I2C data/clock\n **/\n STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)\n {\n@@ -2425,11 +2425,11 @@ STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)\n }\n \n /**\n- * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock\n- * @hw: pointer to hardware structure\n- * @data: data value to write\n+ * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock\n+ * @hw: pointer to hardware structure\n+ * @data: data value to write\n *\n- * Clocks out one bit via I2C data/clock\n+ * Clocks out one bit via I2C data/clock\n **/\n STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)\n {\n@@ -2461,12 +2461,12 @@ STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)\n }\n \n /**\n- * ixgbe_raise_i2c_clk - Raises the I2C SCL clock\n- * @hw: pointer to hardware structure\n- * @i2cctl: Current value of I2CCTL register\n+ * ixgbe_raise_i2c_clk - Raises the I2C SCL clock\n+ * @hw: pointer to hardware structure\n+ * @i2cctl: Current value of I2CCTL register\n *\n- * Raises the I2C clock line '0'->'1'\n- * Negates the I2C clock output enable on X550 hardware.\n+ * Raises the I2C clock line '0'->'1'\n+ * Negates the I2C clock output enable on X550 hardware.\n **/\n STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)\n {\n@@ -2497,12 +2497,12 @@ STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)\n }\n \n /**\n- * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock\n- * @hw: pointer to hardware structure\n- * @i2cctl: Current value of I2CCTL register\n+ * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock\n+ * @hw: pointer to hardware structure\n+ * @i2cctl: Current value of I2CCTL register\n *\n- * Lowers the I2C clock line '1'->'0'\n- * Asserts the I2C clock output enable on X550 hardware.\n+ * Lowers the I2C clock line '1'->'0'\n+ * Asserts the I2C clock output enable on X550 hardware.\n **/\n STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)\n {\n@@ -2519,13 +2519,13 @@ STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)\n }\n \n /**\n- * ixgbe_set_i2c_data - Sets the I2C data bit\n- * @hw: pointer to hardware structure\n- * @i2cctl: Current value of I2CCTL register\n- * @data: I2C data value (0 or 1) to set\n+ * ixgbe_set_i2c_data - Sets the I2C data bit\n+ * @hw: pointer to hardware structure\n+ * @i2cctl: Current value of I2CCTL register\n+ * @data: I2C data value (0 or 1) to set\n *\n- * Sets the I2C data bit\n- * Asserts the I2C data output enable on X550 hardware.\n+ * Sets the I2C data bit\n+ * Asserts the I2C data output enable on X550 hardware.\n **/\n STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)\n {\n@@ -2567,12 +2567,12 @@ STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)\n }\n \n /**\n- * ixgbe_get_i2c_data - Reads the I2C SDA data bit\n- * @hw: pointer to hardware structure\n- * @i2cctl: Current value of I2CCTL register\n+ * ixgbe_get_i2c_data - Reads the I2C SDA data bit\n+ * @hw: pointer to hardware structure\n+ * @i2cctl: Current value of I2CCTL register\n *\n- * Returns the I2C data bit value\n- * Negates the I2C data output enable on X550 hardware.\n+ * Returns the I2C data bit value\n+ * Negates the I2C data output enable on X550 hardware.\n **/\n STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)\n {\n@@ -2597,11 +2597,11 @@ STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)\n }\n \n /**\n- * ixgbe_i2c_bus_clear - Clears the I2C bus\n- * @hw: pointer to hardware structure\n+ * ixgbe_i2c_bus_clear - Clears the I2C bus\n+ * @hw: pointer to hardware structure\n *\n- * Clears the I2C bus by sending nine clock pulses.\n- * Used when data line is stuck low.\n+ * Clears the I2C bus by sending nine clock pulses.\n+ * Used when data line is stuck low.\n **/\n void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)\n {\n@@ -2634,10 +2634,10 @@ void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.\n- * @hw: pointer to hardware structure\n+ * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.\n+ * @hw: pointer to hardware structure\n *\n- * Checks if the LASI temp alarm status was triggered due to overtemp\n+ * Checks if the LASI temp alarm status was triggered due to overtemp\n **/\n s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)\n {\ndiff --git a/drivers/net/ixgbe/base/ixgbe_vf.c b/drivers/net/ixgbe/base/ixgbe_vf.c\nindex 4b2484606..2a3e25834 100644\n--- a/drivers/net/ixgbe/base/ixgbe_vf.c\n+++ b/drivers/net/ixgbe/base/ixgbe_vf.c\n@@ -15,13 +15,13 @@\n #endif\n \n /**\n- * ixgbe_init_ops_vf - Initialize the pointers for vf\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_ops_vf - Initialize the pointers for vf\n+ * @hw: pointer to hardware structure\n *\n- * This will assign function pointers, adapter-specific functions can\n- * override the assignment of generic function pointers by assigning\n- * their own adapter-specific function pointers.\n- * Does not touch the hardware.\n+ * This will assign function pointers, adapter-specific functions can\n+ * override the assignment of generic function pointers by assigning\n+ * their own adapter-specific function pointers.\n+ * Does not touch the hardware.\n **/\n s32 ixgbe_init_ops_vf(struct ixgbe_hw *hw)\n {\n@@ -63,7 +63,7 @@ s32 ixgbe_init_ops_vf(struct ixgbe_hw *hw)\n }\n \n /* ixgbe_virt_clr_reg - Set register to default (power on) state.\n- * @hw: pointer to hardware structure\n+ * @hw: pointer to hardware structure\n */\n static void ixgbe_virt_clr_reg(struct ixgbe_hw *hw)\n {\n@@ -106,13 +106,13 @@ static void ixgbe_virt_clr_reg(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_start_hw_vf - Prepare hardware for Tx/Rx\n- * @hw: pointer to hardware structure\n+ * ixgbe_start_hw_vf - Prepare hardware for Tx/Rx\n+ * @hw: pointer to hardware structure\n *\n- * Starts the hardware by filling the bus info structure and media type, clears\n- * all on chip counters, initializes receive address registers, multicast\n- * table, VLAN filter table, calls routine to set up link and flow control\n- * settings, and leaves transmit and receive units disabled and uninitialized\n+ * Starts the hardware by filling the bus info structure and media type, clears\n+ * all on chip counters, initializes receive address registers, multicast\n+ * table, VLAN filter table, calls routine to set up link and flow control\n+ * settings, and leaves transmit and receive units disabled and uninitialized\n **/\n s32 ixgbe_start_hw_vf(struct ixgbe_hw *hw)\n {\n@@ -123,11 +123,11 @@ s32 ixgbe_start_hw_vf(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_init_hw_vf - virtual function hardware initialization\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_hw_vf - virtual function hardware initialization\n+ * @hw: pointer to hardware structure\n *\n- * Initialize the hardware by resetting the hardware and then starting\n- * the hardware\n+ * Initialize the hardware by resetting the hardware and then starting\n+ * the hardware\n **/\n s32 ixgbe_init_hw_vf(struct ixgbe_hw *hw)\n {\n@@ -139,11 +139,11 @@ s32 ixgbe_init_hw_vf(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_reset_hw_vf - Performs hardware reset\n- * @hw: pointer to hardware structure\n+ * ixgbe_reset_hw_vf - Performs hardware reset\n+ * @hw: pointer to hardware structure\n *\n- * Resets the hardware by resetting the transmit and receive units, masks and\n- * clears all interrupts.\n+ * Resets the hardware by resetting the transmit and receive units, masks and\n+ * clears all interrupts.\n **/\n s32 ixgbe_reset_hw_vf(struct ixgbe_hw *hw)\n {\n@@ -211,13 +211,13 @@ s32 ixgbe_reset_hw_vf(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_stop_adapter_vf - Generic stop Tx/Rx units\n- * @hw: pointer to hardware structure\n+ * ixgbe_stop_adapter_vf - Generic stop Tx/Rx units\n+ * @hw: pointer to hardware structure\n *\n- * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,\n- * disables transmit and receive units. The adapter_stopped flag is used by\n- * the shared code and drivers to determine if the adapter is in a stopped\n- * state and should not touch the hardware.\n+ * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,\n+ * disables transmit and receive units. The adapter_stopped flag is used by\n+ * the shared code and drivers to determine if the adapter is in a stopped\n+ * state and should not touch the hardware.\n **/\n s32 ixgbe_stop_adapter_vf(struct ixgbe_hw *hw)\n {\n@@ -257,16 +257,16 @@ s32 ixgbe_stop_adapter_vf(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_mta_vector - Determines bit-vector in multicast table to set\n- * @hw: pointer to hardware structure\n- * @mc_addr: the multicast address\n+ * ixgbe_mta_vector - Determines bit-vector in multicast table to set\n+ * @hw: pointer to hardware structure\n+ * @mc_addr: the multicast address\n *\n- * Extracts the 12 bits, from a multicast address, to determine which\n- * bit-vector to set in the multicast table. The hardware uses 12 bits, from\n- * incoming rx multicast addresses, to determine the bit-vector to check in\n- * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set\n- * by the MO field of the MCSTCTRL. The MO field is set during initialization\n- * to mc_filter_type.\n+ * Extracts the 12 bits, from a multicast address, to determine which\n+ * bit-vector to set in the multicast table. The hardware uses 12 bits, from\n+ * incoming rx multicast addresses, to determine the bit-vector to check in\n+ * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set\n+ * by the MO field of the MCSTCTRL. The MO field is set during initialization\n+ * to mc_filter_type.\n **/\n STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)\n {\n@@ -309,12 +309,12 @@ STATIC s32 ixgbevf_write_msg_read_ack(struct ixgbe_hw *hw, u32 *msg,\n }\n \n /**\n- * ixgbe_set_rar_vf - set device MAC address\n- * @hw: pointer to hardware structure\n- * @index: Receive address register to write\n- * @addr: Address to put into receive address register\n- * @vmdq: VMDq \"set\" or \"pool\" index\n- * @enable_addr: set flag that address is active\n+ * ixgbe_set_rar_vf - set device MAC address\n+ * @hw: pointer to hardware structure\n+ * @index: Receive address register to write\n+ * @addr: Address to put into receive address register\n+ * @vmdq: VMDq \"set\" or \"pool\" index\n+ * @enable_addr: set flag that address is active\n **/\n s32 ixgbe_set_rar_vf(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,\n \t\t u32 enable_addr)\n@@ -342,14 +342,14 @@ s32 ixgbe_set_rar_vf(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,\n }\n \n /**\n- * ixgbe_update_mc_addr_list_vf - Update Multicast addresses\n- * @hw: pointer to the HW structure\n- * @mc_addr_list: array of multicast addresses to program\n- * @mc_addr_count: number of multicast addresses to program\n- * @next: caller supplied function to return next address in list\n- * @clear: unused\n+ * ixgbe_update_mc_addr_list_vf - Update Multicast addresses\n+ * @hw: pointer to the HW structure\n+ * @mc_addr_list: array of multicast addresses to program\n+ * @mc_addr_count: number of multicast addresses to program\n+ * @next: caller supplied function to return next address in list\n+ * @clear: unused\n *\n- * Updates the Multicast Table Array.\n+ * Updates the Multicast Table Array.\n **/\n s32 ixgbe_update_mc_addr_list_vf(struct ixgbe_hw *hw, u8 *mc_addr_list,\n \t\t\t\t u32 mc_addr_count, ixgbe_mc_addr_itr next,\n@@ -391,11 +391,11 @@ s32 ixgbe_update_mc_addr_list_vf(struct ixgbe_hw *hw, u8 *mc_addr_list,\n }\n \n /**\n- * ixgbevf_update_xcast_mode - Update Multicast mode\n- * @hw: pointer to the HW structure\n- * @xcast_mode: new multicast mode\n+ * ixgbevf_update_xcast_mode - Update Multicast mode\n+ * @hw: pointer to the HW structure\n+ * @xcast_mode: new multicast mode\n *\n- * Updates the Multicast Mode of VF.\n+ * Updates the Multicast Mode of VF.\n **/\n s32 ixgbevf_update_xcast_mode(struct ixgbe_hw *hw, int xcast_mode)\n {\n@@ -428,14 +428,14 @@ s32 ixgbevf_update_xcast_mode(struct ixgbe_hw *hw, int xcast_mode)\n }\n \n /**\n- * ixgbe_set_vfta_vf - Set/Unset vlan filter table address\n- * @hw: pointer to the HW structure\n- * @vlan: 12 bit VLAN ID\n- * @vind: unused by VF drivers\n- * @vlan_on: if true then set bit, else clear bit\n- * @vlvf_bypass: boolean flag indicating updating default pool is okay\n+ * ixgbe_set_vfta_vf - Set/Unset vlan filter table address\n+ * @hw: pointer to the HW structure\n+ * @vlan: 12 bit VLAN ID\n+ * @vind: unused by VF drivers\n+ * @vlan_on: if true then set bit, else clear bit\n+ * @vlvf_bypass: boolean flag indicating updating default pool is okay\n *\n- * Turn on/off specified VLAN in the VLAN filter table.\n+ * Turn on/off specified VLAN in the VLAN filter table.\n **/\n s32 ixgbe_set_vfta_vf(struct ixgbe_hw *hw, u32 vlan, u32 vind,\n \t\t bool vlan_on, bool vlvf_bypass)\n@@ -457,10 +457,10 @@ s32 ixgbe_set_vfta_vf(struct ixgbe_hw *hw, u32 vlan, u32 vind,\n }\n \n /**\n- * ixgbe_get_num_of_tx_queues_vf - Get number of TX queues\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_num_of_tx_queues_vf - Get number of TX queues\n+ * @hw: pointer to hardware structure\n *\n- * Returns the number of transmit queues for the given adapter.\n+ * Returns the number of transmit queues for the given adapter.\n **/\n u32 ixgbe_get_num_of_tx_queues_vf(struct ixgbe_hw *hw)\n {\n@@ -469,10 +469,10 @@ u32 ixgbe_get_num_of_tx_queues_vf(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_get_num_of_rx_queues_vf - Get number of RX queues\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_num_of_rx_queues_vf - Get number of RX queues\n+ * @hw: pointer to hardware structure\n *\n- * Returns the number of receive queues for the given adapter.\n+ * Returns the number of receive queues for the given adapter.\n **/\n u32 ixgbe_get_num_of_rx_queues_vf(struct ixgbe_hw *hw)\n {\n@@ -526,12 +526,12 @@ s32 ixgbevf_set_uc_addr_vf(struct ixgbe_hw *hw, u32 index, u8 *addr)\n }\n \n /**\n- * ixgbe_setup_mac_link_vf - Setup MAC link settings\n- * @hw: pointer to hardware structure\n- * @speed: new link speed\n- * @autoneg_wait_to_complete: true when waiting for completion is needed\n+ * ixgbe_setup_mac_link_vf - Setup MAC link settings\n+ * @hw: pointer to hardware structure\n+ * @speed: new link speed\n+ * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n- * Set the link speed in the AUTOC register and restarts link.\n+ * Set the link speed in the AUTOC register and restarts link.\n **/\n s32 ixgbe_setup_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n \t\t\t bool autoneg_wait_to_complete)\n@@ -541,13 +541,13 @@ s32 ixgbe_setup_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n }\n \n /**\n- * ixgbe_check_mac_link_vf - Get link/speed status\n- * @hw: pointer to hardware structure\n- * @speed: pointer to link speed\n- * @link_up: true is link is up, false otherwise\n- * @autoneg_wait_to_complete: true when waiting for completion is needed\n+ * ixgbe_check_mac_link_vf - Get link/speed status\n+ * @hw: pointer to hardware structure\n+ * @speed: pointer to link speed\n+ * @link_up: true is link is up, false otherwise\n+ * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n- * Reads the links register to determine if link is up and the current speed\n+ * Reads the links register to determine if link is up and the current speed\n **/\n s32 ixgbe_check_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n \t\t\t bool *link_up, bool autoneg_wait_to_complete)\n@@ -644,9 +644,9 @@ s32 ixgbe_check_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n }\n \n /**\n- * ixgbevf_rlpml_set_vf - Set the maximum receive packet length\n- * @hw: pointer to the HW structure\n- * @max_size: value to assign to max frame size\n+ * ixgbevf_rlpml_set_vf - Set the maximum receive packet length\n+ * @hw: pointer to the HW structure\n+ * @max_size: value to assign to max frame size\n **/\n s32 ixgbevf_rlpml_set_vf(struct ixgbe_hw *hw, u16 max_size)\n {\n@@ -667,9 +667,9 @@ s32 ixgbevf_rlpml_set_vf(struct ixgbe_hw *hw, u16 max_size)\n }\n \n /**\n- * ixgbevf_negotiate_api_version - Negotiate supported API version\n- * @hw: pointer to the HW structure\n- * @api: integer containing requested API version\n+ * ixgbevf_negotiate_api_version - Negotiate supported API version\n+ * @hw: pointer to the HW structure\n+ * @api: integer containing requested API version\n **/\n int ixgbevf_negotiate_api_version(struct ixgbe_hw *hw, int api)\n {\ndiff --git a/drivers/net/ixgbe/base/ixgbe_x540.c b/drivers/net/ixgbe/base/ixgbe_x540.c\nindex d65f47c18..838bfc8b5 100644\n--- a/drivers/net/ixgbe/base/ixgbe_x540.c\n+++ b/drivers/net/ixgbe/base/ixgbe_x540.c\n@@ -20,11 +20,11 @@ STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);\n STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);\n \n /**\n- * ixgbe_init_ops_X540 - Inits func ptrs and MAC type\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_ops_X540 - Inits func ptrs and MAC type\n+ * @hw: pointer to hardware structure\n *\n- * Initialize the function pointers and assign the MAC type for X540.\n- * Does not touch the hardware.\n+ * Initialize the function pointers and assign the MAC type for X540.\n+ * Does not touch the hardware.\n **/\n s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)\n {\n@@ -126,12 +126,12 @@ s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_get_link_capabilities_X540 - Determines link capabilities\n- * @hw: pointer to hardware structure\n- * @speed: pointer to link speed\n- * @autoneg: true when autoneg or autotry is enabled\n+ * ixgbe_get_link_capabilities_X540 - Determines link capabilities\n+ * @hw: pointer to hardware structure\n+ * @speed: pointer to link speed\n+ * @autoneg: true when autoneg or autotry is enabled\n *\n- * Determines the link capabilities by reading the AUTOC register.\n+ * Determines the link capabilities by reading the AUTOC register.\n **/\n s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,\n \t\t\t\t ixgbe_link_speed *speed,\n@@ -143,10 +143,10 @@ s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_get_media_type_X540 - Get media type\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_media_type_X540 - Get media type\n+ * @hw: pointer to hardware structure\n *\n- * Returns the media type (fiber, copper, backplane)\n+ * Returns the media type (fiber, copper, backplane)\n **/\n enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)\n {\n@@ -155,10 +155,10 @@ enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities\n- * @hw: pointer to hardware structure\n- * @speed: new link speed\n- * @autoneg_wait_to_complete: true when waiting for completion is needed\n+ * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities\n+ * @hw: pointer to hardware structure\n+ * @speed: new link speed\n+ * @autoneg_wait_to_complete: true when waiting for completion is needed\n **/\n s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,\n \t\t\t ixgbe_link_speed speed,\n@@ -169,11 +169,11 @@ s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_reset_hw_X540 - Perform hardware reset\n- * @hw: pointer to hardware structure\n+ * ixgbe_reset_hw_X540 - Perform hardware reset\n+ * @hw: pointer to hardware structure\n *\n- * Resets the hardware by resetting the transmit and receive units, masks\n- * and clears all interrupts, and perform a reset.\n+ * Resets the hardware by resetting the transmit and receive units, masks\n+ * and clears all interrupts, and perform a reset.\n **/\n s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)\n {\n@@ -271,12 +271,12 @@ s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx\n- * @hw: pointer to hardware structure\n+ * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx\n+ * @hw: pointer to hardware structure\n *\n- * Starts the hardware using the generic start_hw function\n- * and the generation start_hw function.\n- * Then performs revision-specific operations, if any.\n+ * Starts the hardware using the generic start_hw function\n+ * and the generation start_hw function.\n+ * Then performs revision-specific operations, if any.\n **/\n s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)\n {\n@@ -295,10 +295,10 @@ s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type\n+ * @hw: pointer to hardware structure\n *\n- * Determines physical layer capabilities of the current configuration.\n+ * Determines physical layer capabilities of the current configuration.\n **/\n u64 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)\n {\n@@ -320,11 +320,11 @@ u64 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params\n+ * @hw: pointer to hardware structure\n *\n- * Initializes the EEPROM parameters ixgbe_eeprom_info within the\n- * ixgbe_hw struct in order to set up EEPROM access.\n+ * Initializes the EEPROM parameters ixgbe_eeprom_info within the\n+ * ixgbe_hw struct in order to set up EEPROM access.\n **/\n s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)\n {\n@@ -352,12 +352,12 @@ s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_read_eerd_X540- Read EEPROM word using EERD\n- * @hw: pointer to hardware structure\n- * @offset: offset of word in the EEPROM to read\n- * @data: word read from the EEPROM\n+ * ixgbe_read_eerd_X540- Read EEPROM word using EERD\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to read\n+ * @data: word read from the EEPROM\n *\n- * Reads a 16 bit word from the EEPROM using the EERD register.\n+ * Reads a 16 bit word from the EEPROM using the EERD register.\n **/\n s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)\n {\n@@ -376,13 +376,13 @@ s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)\n }\n \n /**\n- * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD\n- * @hw: pointer to hardware structure\n- * @offset: offset of word in the EEPROM to read\n- * @words: number of words\n- * @data: word(s) read from the EEPROM\n+ * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to read\n+ * @words: number of words\n+ * @data: word(s) read from the EEPROM\n *\n- * Reads a 16 bit word(s) from the EEPROM using the EERD register.\n+ * Reads a 16 bit word(s) from the EEPROM using the EERD register.\n **/\n s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,\n \t\t\t\tu16 offset, u16 words, u16 *data)\n@@ -403,12 +403,12 @@ s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR\n- * @hw: pointer to hardware structure\n- * @offset: offset of word in the EEPROM to write\n- * @data: word write to the EEPROM\n+ * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to write\n+ * @data: word write to the EEPROM\n *\n- * Write a 16 bit word to the EEPROM using the EEWR register.\n+ * Write a 16 bit word to the EEPROM using the EEWR register.\n **/\n s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)\n {\n@@ -427,13 +427,13 @@ s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)\n }\n \n /**\n- * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR\n- * @hw: pointer to hardware structure\n- * @offset: offset of word in the EEPROM to write\n- * @words: number of words\n- * @data: word(s) write to the EEPROM\n+ * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to write\n+ * @words: number of words\n+ * @data: word(s) write to the EEPROM\n *\n- * Write a 16 bit word(s) to the EEPROM using the EEWR register.\n+ * Write a 16 bit word(s) to the EEPROM using the EEWR register.\n **/\n s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,\n \t\t\t\t u16 offset, u16 words, u16 *data)\n@@ -454,14 +454,14 @@ s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum\n+ * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum\n *\n- * This function does not use synchronization for EERD and EEWR. It can\n- * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.\n+ * This function does not use synchronization for EERD and EEWR. It can\n+ * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.\n *\n- * @hw: pointer to hardware structure\n+ * @hw: pointer to hardware structure\n *\n- * Returns a negative error code on error, or the 16-bit checksum\n+ * Returns a negative error code on error, or the 16-bit checksum\n **/\n s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)\n {\n@@ -532,12 +532,12 @@ s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum\n- * @hw: pointer to hardware structure\n- * @checksum_val: calculated checksum\n+ * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum\n+ * @hw: pointer to hardware structure\n+ * @checksum_val: calculated checksum\n *\n- * Performs checksum calculation and validates the EEPROM checksum. If the\n- * caller does not need checksum_val, the value can be NULL.\n+ * Performs checksum calculation and validates the EEPROM checksum. If the\n+ * caller does not need checksum_val, the value can be NULL.\n **/\n s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,\n \t\t\t\t\tu16 *checksum_val)\n@@ -644,11 +644,11 @@ s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device\n- * @hw: pointer to hardware structure\n+ * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device\n+ * @hw: pointer to hardware structure\n *\n- * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy\n- * EEPROM from shadow RAM to the flash device.\n+ * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy\n+ * EEPROM from shadow RAM to the flash device.\n **/\n s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)\n {\n@@ -691,11 +691,11 @@ s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_poll_flash_update_done_X540 - Poll flash update status\n- * @hw: pointer to hardware structure\n+ * ixgbe_poll_flash_update_done_X540 - Poll flash update status\n+ * @hw: pointer to hardware structure\n *\n- * Polls the FLUDONE (bit 26) of the EEC Register to determine when the\n- * flash update is done.\n+ * Polls the FLUDONE (bit 26) of the EEC Register to determine when the\n+ * flash update is done.\n **/\n STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)\n {\n@@ -722,12 +722,12 @@ STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore\n- * @hw: pointer to hardware structure\n- * @mask: Mask to specify which semaphore to acquire\n+ * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore\n+ * @hw: pointer to hardware structure\n+ * @mask: Mask to specify which semaphore to acquire\n *\n- * Acquires the SWFW semaphore thought the SW_FW_SYNC register for\n- * the specified function (CSR, PHY0, PHY1, NVM, Flash)\n+ * Acquires the SWFW semaphore thought the SW_FW_SYNC register for\n+ * the specified function (CSR, PHY0, PHY1, NVM, Flash)\n **/\n s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)\n {\n@@ -819,12 +819,12 @@ s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)\n }\n \n /**\n- * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore\n- * @hw: pointer to hardware structure\n- * @mask: Mask to specify which semaphore to release\n+ * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore\n+ * @hw: pointer to hardware structure\n+ * @mask: Mask to specify which semaphore to release\n *\n- * Releases the SWFW semaphore through the SW_FW_SYNC register\n- * for the specified function (CSR, PHY0, PHY1, EVM, Flash)\n+ * Releases the SWFW semaphore through the SW_FW_SYNC register\n+ * for the specified function (CSR, PHY0, PHY1, EVM, Flash)\n **/\n void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)\n {\n@@ -846,10 +846,10 @@ void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)\n }\n \n /**\n- * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore\n+ * @hw: pointer to hardware structure\n *\n- * Sets the hardware semaphores so SW/FW can gain control of shared resources\n+ * Sets the hardware semaphores so SW/FW can gain control of shared resources\n **/\n STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)\n {\n@@ -904,10 +904,10 @@ STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore\n- * @hw: pointer to hardware structure\n+ * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore\n+ * @hw: pointer to hardware structure\n *\n- * This function clears hardware semaphore bits.\n+ * This function clears hardware semaphore bits.\n **/\n STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)\n {\n@@ -929,11 +929,11 @@ STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_init_swfw_sync_X540 - Release hardware semaphore\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_swfw_sync_X540 - Release hardware semaphore\n+ * @hw: pointer to hardware structure\n *\n- * This function reset hardware semaphore bits for a semaphore that may\n- * have be left locked due to a catastrophic failure.\n+ * This function reset hardware semaphore bits for a semaphore that may\n+ * have be left locked due to a catastrophic failure.\n **/\n void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw)\n {\n@@ -964,7 +964,7 @@ void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw)\n * @index: led number to blink\n *\n * Devices that implement the version 2 interface:\n- * X540\n+ * X540\n **/\n s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)\n {\n@@ -1005,7 +1005,7 @@ s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)\n * @index: led number to stop blinking\n *\n * Devices that implement the version 2 interface:\n- * X540\n+ * X540\n **/\n s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)\n {\ndiff --git a/drivers/net/ixgbe/base/ixgbe_x550.c b/drivers/net/ixgbe/base/ixgbe_x550.c\nindex c64cbfab1..5750f79eb 100644\n--- a/drivers/net/ixgbe/base/ixgbe_x550.c\n+++ b/drivers/net/ixgbe/base/ixgbe_x550.c\n@@ -15,11 +15,11 @@ STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);\n STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);\n \n /**\n- * ixgbe_init_ops_X550 - Inits func ptrs and MAC type\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_ops_X550 - Inits func ptrs and MAC type\n+ * @hw: pointer to hardware structure\n *\n- * Initialize the function pointers and assign the MAC type for X550.\n- * Does not touch the hardware.\n+ * Initialize the function pointers and assign the MAC type for X550.\n+ * Does not touch the hardware.\n **/\n s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)\n {\n@@ -718,7 +718,7 @@ static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)\n * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs\n * @hw: pointer to hardware structure\n *\n- * Called at init time to set up flow control.\n+ * Called at init time to set up flow control.\n */\n static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)\n {\n@@ -844,11 +844,11 @@ s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_dmac_config_X550\n- * @hw: pointer to hardware structure\n+ * ixgbe_dmac_config_X550\n+ * @hw: pointer to hardware structure\n *\n- * Configure DMA coalescing. If enabling dmac, dmac is activated.\n- * When disabling dmac, dmac enable dmac bit is cleared.\n+ * Configure DMA coalescing. If enabling dmac, dmac is activated.\n+ * When disabling dmac, dmac enable dmac bit is cleared.\n **/\n s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)\n {\n@@ -892,11 +892,11 @@ s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_dmac_config_tcs_X550\n- * @hw: pointer to hardware structure\n+ * ixgbe_dmac_config_tcs_X550\n+ * @hw: pointer to hardware structure\n *\n- * Configure DMA coalescing threshold per TC. The dmac enable bit must\n- * be cleared before configuring.\n+ * Configure DMA coalescing threshold per TC. The dmac enable bit must\n+ * be cleared before configuring.\n **/\n s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)\n {\n@@ -948,10 +948,10 @@ s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_dmac_update_tcs_X550\n- * @hw: pointer to hardware structure\n+ * ixgbe_dmac_update_tcs_X550\n+ * @hw: pointer to hardware structure\n *\n- * Disables dmac, updates per TC settings, and then enables dmac.\n+ * Disables dmac, updates per TC settings, and then enables dmac.\n **/\n s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)\n {\n@@ -975,11 +975,11 @@ s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params\n+ * @hw: pointer to hardware structure\n *\n- * Initializes the EEPROM parameters ixgbe_eeprom_info within the\n- * ixgbe_hw struct in order to set up EEPROM access.\n+ * Initializes the EEPROM parameters ixgbe_eeprom_info within the\n+ * ixgbe_hw struct in order to set up EEPROM access.\n **/\n s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)\n {\n@@ -1034,10 +1034,10 @@ void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,\n }\n \n /**\n- * ixgbe_set_ethertype_anti_spoofing_X550 - Configure Ethertype anti-spoofing\n- * @hw: pointer to hardware structure\n- * @enable: enable or disable switch for Ethertype anti-spoofing\n- * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing\n+ * ixgbe_set_ethertype_anti_spoofing_X550 - Configure Ethertype anti-spoofing\n+ * @hw: pointer to hardware structure\n+ * @enable: enable or disable switch for Ethertype anti-spoofing\n+ * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing\n *\n **/\n void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,\n@@ -1092,12 +1092,12 @@ STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)\n }\n \n /**\n- * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register\n- * of the IOSF device\n- * @hw: pointer to hardware structure\n- * @reg_addr: 32 bit PHY register to write\n- * @device_type: 3 bit device type\n- * @data: Data to write to the register\n+ * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register\n+ * of the IOSF device\n+ * @hw: pointer to hardware structure\n+ * @reg_addr: 32 bit PHY register to write\n+ * @device_type: 3 bit device type\n+ * @data: Data to write to the register\n **/\n s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,\n \t\t\t u32 device_type, u32 data)\n@@ -1139,11 +1139,11 @@ s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,\n }\n \n /**\n- * ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device\n- * @hw: pointer to hardware structure\n- * @reg_addr: 32 bit PHY register to write\n- * @device_type: 3 bit device type\n- * @data: Pointer to read data from the register\n+ * ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device\n+ * @hw: pointer to hardware structure\n+ * @reg_addr: 32 bit PHY register to write\n+ * @device_type: 3 bit device type\n+ * @data: Pointer to read data from the register\n **/\n s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,\n \t\t\t u32 device_type, u32 *data)\n@@ -1253,12 +1253,12 @@ s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register\n- * of the IOSF device\n- * @hw: pointer to hardware structure\n- * @reg_addr: 32 bit PHY register to write\n- * @device_type: 3 bit device type\n- * @data: Data to write to the register\n+ * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register\n+ * of the IOSF device\n+ * @hw: pointer to hardware structure\n+ * @reg_addr: 32 bit PHY register to write\n+ * @device_type: 3 bit device type\n+ * @data: Data to write to the register\n **/\n s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,\n \t\t\t\t u32 device_type, u32 data)\n@@ -1284,11 +1284,11 @@ s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,\n }\n \n /**\n- * ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device\n- * @hw: pointer to hardware structure\n- * @reg_addr: 32 bit PHY register to write\n- * @device_type: 3 bit device type\n- * @data: Pointer to read data from the register\n+ * ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device\n+ * @hw: pointer to hardware structure\n+ * @reg_addr: 32 bit PHY register to write\n+ * @device_type: 3 bit device type\n+ * @data: Pointer to read data from the register\n **/\n s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,\n \t\t\t\t u32 device_type, u32 *data)\n@@ -1319,10 +1319,10 @@ s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,\n }\n \n /**\n- * ixgbe_disable_mdd_X550\n- * @hw: pointer to hardware structure\n+ * ixgbe_disable_mdd_X550\n+ * @hw: pointer to hardware structure\n *\n- * Disable malicious driver detection\n+ * Disable malicious driver detection\n **/\n void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)\n {\n@@ -1342,10 +1342,10 @@ void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_enable_mdd_X550\n- * @hw: pointer to hardware structure\n+ * ixgbe_enable_mdd_X550\n+ * @hw: pointer to hardware structure\n *\n- * Enable malicious driver detection\n+ * Enable malicious driver detection\n **/\n void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)\n {\n@@ -1365,11 +1365,11 @@ void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_restore_mdd_vf_X550\n- * @hw: pointer to hardware structure\n- * @vf: vf index\n+ * ixgbe_restore_mdd_vf_X550\n+ * @hw: pointer to hardware structure\n+ * @vf: vf index\n *\n- * Restore VF that was disabled during malicious driver detection event\n+ * Restore VF that was disabled during malicious driver detection event\n **/\n void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)\n {\n@@ -1405,11 +1405,11 @@ void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)\n }\n \n /**\n- * ixgbe_mdd_event_X550\n- * @hw: pointer to hardware structure\n- * @vf_bitmap: vf bitmap of malicious vfs\n+ * ixgbe_mdd_event_X550\n+ * @hw: pointer to hardware structure\n+ * @vf_bitmap: vf bitmap of malicious vfs\n *\n- * Handle malicious driver detection event.\n+ * Handle malicious driver detection event.\n **/\n void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)\n {\n@@ -1462,10 +1462,10 @@ void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)\n }\n \n /**\n- * ixgbe_get_media_type_X550em - Get media type\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_media_type_X550em - Get media type\n+ * @hw: pointer to hardware structure\n *\n- * Returns the media type (fiber, copper, backplane)\n+ * Returns the media type (fiber, copper, backplane)\n */\n enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)\n {\n@@ -1511,9 +1511,9 @@ enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported\n- * @hw: pointer to hardware structure\n- * @linear: true if SFP module is linear\n+ * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported\n+ * @hw: pointer to hardware structure\n+ * @linear: true if SFP module is linear\n */\n STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)\n {\n@@ -1549,10 +1549,10 @@ STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)\n }\n \n /**\n- * ixgbe_identify_sfp_module_X550em - Identifies SFP modules\n- * @hw: pointer to hardware structure\n+ * ixgbe_identify_sfp_module_X550em - Identifies SFP modules\n+ * @hw: pointer to hardware structure\n *\n- * Searches for and identifies the SFP module and assigns appropriate PHY type.\n+ * Searches for and identifies the SFP module and assigns appropriate PHY type.\n **/\n s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)\n {\n@@ -1573,8 +1573,8 @@ s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops\n- * @hw: pointer to hardware structure\n+ * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops\n+ * @hw: pointer to hardware structure\n */\n s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)\n {\n@@ -1787,8 +1787,8 @@ STATIC s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n }\n \n /**\n- * ixgbe_init_mac_link_ops_X550em - init mac link function pointers\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_mac_link_ops_X550em - init mac link function pointers\n+ * @hw: pointer to hardware structure\n */\n void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)\n {\n@@ -1849,10 +1849,10 @@ void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_get_link_capabilities_x550em - Determines link capabilities\n- * @hw: pointer to hardware structure\n- * @speed: pointer to link speed\n- * @autoneg: true when autoneg or autotry is enabled\n+ * ixgbe_get_link_capabilities_x550em - Determines link capabilities\n+ * @hw: pointer to hardware structure\n+ * @speed: pointer to link speed\n+ * @autoneg: true when autoneg or autotry is enabled\n */\n s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,\n \t\t\t\t ixgbe_link_speed *speed,\n@@ -1941,7 +1941,7 @@ s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,\n * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause\n * @hw: pointer to hardware structure\n * @lsc: pointer to boolean flag which indicates whether external Base T\n- * PHY interrupt is lsc\n+ * PHY interrupt is lsc\n *\n * Determime if external Base T PHY interrupt cause is high temperature\n * failure alarm or link status change.\n@@ -2127,11 +2127,11 @@ STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.\n- * @hw: pointer to hardware structure\n- * @speed: link speed\n+ * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.\n+ * @hw: pointer to hardware structure\n+ * @speed: link speed\n *\n- * Configures the integrated KR PHY.\n+ * Configures the integrated KR PHY.\n **/\n STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,\n \t\t\t\t ixgbe_link_speed speed)\n@@ -2229,11 +2229,11 @@ static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register\n- * @hw: pointer to hardware structure\n+ * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register\n+ * @hw: pointer to hardware structure\n *\n- * Read NW_MNG_IF_SEL register and save field values, and check for valid field\n- * values.\n+ * Read NW_MNG_IF_SEL register and save field values, and check for valid field\n+ * values.\n **/\n STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)\n {\n@@ -2256,12 +2256,12 @@ STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_init_phy_ops_X550em - PHY/SFP specific init\n- * @hw: pointer to hardware structure\n+ * ixgbe_init_phy_ops_X550em - PHY/SFP specific init\n+ * @hw: pointer to hardware structure\n *\n- * Initialize any function pointers that were not able to be\n- * set during init_shared_code because the PHY/SFP type was\n- * not known. Perform the SFP init if necessary.\n+ * Initialize any function pointers that were not able to be\n+ * set during init_shared_code because the PHY/SFP type was\n+ * not known. Perform the SFP init if necessary.\n */\n s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)\n {\n@@ -2378,7 +2378,7 @@ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)\n \n /**\n * ixgbe_set_mdio_speed - Set MDIO clock speed\n- * @hw: pointer to hardware structure\n+ * @hw: pointer to hardware structure\n */\n STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)\n {\n@@ -2409,12 +2409,12 @@ STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_reset_hw_X550em - Perform hardware reset\n- * @hw: pointer to hardware structure\n+ * ixgbe_reset_hw_X550em - Perform hardware reset\n+ * @hw: pointer to hardware structure\n *\n- * Resets the hardware by resetting the transmit and receive units, masks\n- * and clears all interrupts, perform a PHY reset, and perform a link (MAC)\n- * reset.\n+ * Resets the hardware by resetting the transmit and receive units, masks\n+ * and clears all interrupts, perform a PHY reset, and perform a link (MAC)\n+ * reset.\n */\n s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)\n {\n@@ -2589,8 +2589,8 @@ s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_setup_kr_x550em - Configure the KR PHY.\n- * @hw: pointer to hardware structure\n+ * ixgbe_setup_kr_x550em - Configure the KR PHY.\n+ * @hw: pointer to hardware structure\n **/\n s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)\n {\n@@ -2605,12 +2605,12 @@ s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP\n- * @hw: pointer to hardware structure\n- * @speed: new link speed\n- * @autoneg_wait_to_complete: unused\n+ * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP\n+ * @hw: pointer to hardware structure\n+ * @speed: new link speed\n+ * @autoneg_wait_to_complete: unused\n *\n- * Configure the external PHY and the integrated KR PHY for SFP support.\n+ * Configure the external PHY and the integrated KR PHY for SFP support.\n **/\n s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,\n \t\t\t\t ixgbe_link_speed speed,\n@@ -2650,12 +2650,12 @@ s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode\n- * @hw: pointer to hardware structure\n- * @speed: the link speed to force\n+ * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode\n+ * @hw: pointer to hardware structure\n+ * @speed: the link speed to force\n *\n- * Configures the integrated PHY for native SFI mode. Used to connect the\n- * internal PHY directly to an SFP cage, without autonegotiation.\n+ * Configures the integrated PHY for native SFI mode. Used to connect the\n+ * internal PHY directly to an SFP cage, without autonegotiation.\n **/\n STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)\n {\n@@ -2699,12 +2699,12 @@ STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)\n }\n \n /**\n- * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP\n- * @hw: pointer to hardware structure\n- * @speed: new link speed\n- * @autoneg_wait_to_complete: unused\n+ * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP\n+ * @hw: pointer to hardware structure\n+ * @speed: new link speed\n+ * @autoneg_wait_to_complete: unused\n *\n- * Configure the integrated PHY for SFP support.\n+ * Configure the integrated PHY for SFP support.\n **/\n s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,\n \t\t\t\t ixgbe_link_speed speed,\n@@ -2804,10 +2804,10 @@ s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration\n- * @hw: pointer to hardware structure\n+ * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration\n+ * @hw: pointer to hardware structure\n *\n- * iXfI configuration needed for ixgbe_mac_X550EM_x devices.\n+ * iXfI configuration needed for ixgbe_mac_X550EM_x devices.\n **/\n STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)\n {\n@@ -2873,12 +2873,12 @@ STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.\n- * @hw: pointer to hardware structure\n- * @speed: the link speed to force\n+ * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.\n+ * @hw: pointer to hardware structure\n+ * @speed: the link speed to force\n *\n- * Configures the integrated KR PHY to use iXFI mode. Used to connect an\n- * internal and external PHY at a specific speed, without autonegotiation.\n+ * Configures the integrated KR PHY to use iXFI mode. Used to connect an\n+ * internal and external PHY at a specific speed, without autonegotiation.\n **/\n STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)\n {\n@@ -3034,10 +3034,10 @@ s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.\n- * @hw: pointer to hardware structure\n+ * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.\n+ * @hw: pointer to hardware structure\n *\n- * Configures the integrated KR PHY to use internal loopback mode.\n+ * Configures the integrated KR PHY to use internal loopback mode.\n **/\n s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)\n {\n@@ -3101,13 +3101,13 @@ s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command\n- * assuming that the semaphore is already obtained.\n- * @hw: pointer to hardware structure\n- * @offset: offset of word in the EEPROM to read\n- * @data: word read from the EEPROM\n+ * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command\n+ * assuming that the semaphore is already obtained.\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to read\n+ * @data: word read from the EEPROM\n *\n- * Reads a 16 bit word from the EEPROM using the hostif.\n+ * Reads a 16 bit word from the EEPROM using the hostif.\n **/\n s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)\n {\n@@ -3144,13 +3144,13 @@ s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)\n }\n \n /**\n- * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif\n- * @hw: pointer to hardware structure\n- * @offset: offset of word in the EEPROM to read\n- * @words: number of words\n- * @data: word(s) read from the EEPROM\n+ * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to read\n+ * @words: number of words\n+ * @data: word(s) read from the EEPROM\n *\n- * Reads a 16 bit word(s) from the EEPROM using the hostif.\n+ * Reads a 16 bit word(s) from the EEPROM using the hostif.\n **/\n s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,\n \t\t\t\t u16 offset, u16 words, u16 *data)\n@@ -3219,12 +3219,12 @@ s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,\n }\n \n /**\n- * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif\n- * @hw: pointer to hardware structure\n- * @offset: offset of word in the EEPROM to write\n- * @data: word write to the EEPROM\n+ * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to write\n+ * @data: word write to the EEPROM\n *\n- * Write a 16 bit word to the EEPROM using the hostif.\n+ * Write a 16 bit word to the EEPROM using the hostif.\n **/\n s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,\n \t\t\t\t u16 data)\n@@ -3252,12 +3252,12 @@ s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,\n }\n \n /**\n- * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif\n- * @hw: pointer to hardware structure\n- * @offset: offset of word in the EEPROM to write\n- * @data: word write to the EEPROM\n+ * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to write\n+ * @data: word write to the EEPROM\n *\n- * Write a 16 bit word to the EEPROM using the hostif.\n+ * Write a 16 bit word to the EEPROM using the hostif.\n **/\n s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,\n \t\t\t u16 data)\n@@ -3279,13 +3279,13 @@ s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,\n }\n \n /**\n- * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif\n- * @hw: pointer to hardware structure\n- * @offset: offset of word in the EEPROM to write\n- * @words: number of words\n- * @data: word(s) write to the EEPROM\n+ * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to write\n+ * @words: number of words\n+ * @data: word(s) write to the EEPROM\n *\n- * Write a 16 bit word(s) to the EEPROM using the hostif.\n+ * Write a 16 bit word(s) to the EEPROM using the hostif.\n **/\n s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,\n \t\t\t\t u16 offset, u16 words, u16 *data)\n@@ -3391,12 +3391,12 @@ STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,\n }\n \n /**\n- * ixgbe_calc_checksum_X550 - Calculates and returns the checksum\n- * @hw: pointer to hardware structure\n- * @buffer: pointer to buffer containing calculated checksum\n- * @buffer_size: size of buffer\n+ * ixgbe_calc_checksum_X550 - Calculates and returns the checksum\n+ * @hw: pointer to hardware structure\n+ * @buffer: pointer to buffer containing calculated checksum\n+ * @buffer_size: size of buffer\n *\n- * Returns a negative error code on error, or the 16-bit checksum\n+ * Returns a negative error code on error, or the 16-bit checksum\n **/\n s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)\n {\n@@ -3474,10 +3474,10 @@ s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)\n }\n \n /**\n- * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum\n- * @hw: pointer to hardware structure\n+ * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum\n+ * @hw: pointer to hardware structure\n *\n- * Returns a negative error code on error, or the 16-bit checksum\n+ * Returns a negative error code on error, or the 16-bit checksum\n **/\n s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)\n {\n@@ -3485,12 +3485,12 @@ s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum\n- * @hw: pointer to hardware structure\n- * @checksum_val: calculated checksum\n+ * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum\n+ * @hw: pointer to hardware structure\n+ * @checksum_val: calculated checksum\n *\n- * Performs checksum calculation and validates the EEPROM checksum. If the\n- * caller does not need checksum_val, the value can be NULL.\n+ * Performs checksum calculation and validates the EEPROM checksum. If the\n+ * caller does not need checksum_val, the value can be NULL.\n **/\n s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)\n {\n@@ -3579,10 +3579,10 @@ s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device\n- * @hw: pointer to hardware structure\n+ * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device\n+ * @hw: pointer to hardware structure\n *\n- * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.\n+ * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.\n **/\n s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)\n {\n@@ -3604,10 +3604,10 @@ s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type\n- * @hw: pointer to hardware structure\n+ * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type\n+ * @hw: pointer to hardware structure\n *\n- * Determines physical layer capabilities of the current configuration.\n+ * Determines physical layer capabilities of the current configuration.\n **/\n u64 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)\n {\n@@ -3748,7 +3748,7 @@ void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)\n \n /**\n * ixgbe_enter_lplu_x550em - Transition to low power states\n- * @hw: pointer to hardware structure\n+ * @hw: pointer to hardware structure\n *\n * Configures Low Power Link Up on transition to low power states\n * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the\n@@ -3856,8 +3856,8 @@ s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)\n \n /**\n * ixgbe_get_lcd_x550em - Determine lowest common denominator\n- * @hw: pointer to hardware structure\n- * @lcd_speed: pointer to lowest common link speed\n+ * @hw: pointer to hardware structure\n+ * @lcd_speed: pointer to lowest common link speed\n *\n * Determine lowest common link speed with link partner.\n **/\n@@ -3893,10 +3893,10 @@ s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)\n }\n \n /**\n- * ixgbe_setup_fc_X550em - Set up flow control\n- * @hw: pointer to hardware structure\n+ * ixgbe_setup_fc_X550em - Set up flow control\n+ * @hw: pointer to hardware structure\n *\n- * Called at init time to set up flow control.\n+ * Called at init time to set up flow control.\n **/\n s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)\n {\n@@ -3983,10 +3983,10 @@ s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37\n- * @hw: pointer to hardware structure\n+ * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37\n+ * @hw: pointer to hardware structure\n *\n- * Enable flow control according to IEEE clause 37.\n+ * Enable flow control according to IEEE clause 37.\n **/\n void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)\n {\n@@ -4061,8 +4061,8 @@ void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings\n- * @hw: pointer to hardware structure\n+ * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings\n+ * @hw: pointer to hardware structure\n *\n **/\n void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)\n@@ -4072,10 +4072,10 @@ void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37\n- * @hw: pointer to hardware structure\n+ * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37\n+ * @hw: pointer to hardware structure\n *\n- * Enable flow control according to IEEE clause 37.\n+ * Enable flow control according to IEEE clause 37.\n **/\n void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)\n {\n@@ -4127,10 +4127,10 @@ void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_setup_fc_backplane_x550em_a - Set up flow control\n- * @hw: pointer to hardware structure\n+ * ixgbe_setup_fc_backplane_x550em_a - Set up flow control\n+ * @hw: pointer to hardware structure\n *\n- * Called at init time to set up flow control.\n+ * Called at init time to set up flow control.\n **/\n s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)\n {\n@@ -4235,11 +4235,11 @@ STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)\n }\n \n /**\n- * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore\n- * @hw: pointer to hardware structure\n- * @mask: Mask to specify which semaphore to acquire\n+ * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore\n+ * @hw: pointer to hardware structure\n+ * @mask: Mask to specify which semaphore to acquire\n *\n- * Acquires the SWFW semaphore and sets the I2C MUX\n+ * Acquires the SWFW semaphore and sets the I2C MUX\n **/\n s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)\n {\n@@ -4258,11 +4258,11 @@ s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)\n }\n \n /**\n- * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore\n- * @hw: pointer to hardware structure\n- * @mask: Mask to specify which semaphore to release\n+ * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore\n+ * @hw: pointer to hardware structure\n+ * @mask: Mask to specify which semaphore to release\n *\n- * Releases the SWFW semaphore and sets the I2C MUX\n+ * Releases the SWFW semaphore and sets the I2C MUX\n **/\n void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)\n {\n@@ -4275,11 +4275,11 @@ void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)\n }\n \n /**\n- * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore\n- * @hw: pointer to hardware structure\n- * @mask: Mask to specify which semaphore to acquire\n+ * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore\n+ * @hw: pointer to hardware structure\n+ * @mask: Mask to specify which semaphore to acquire\n *\n- * Acquires the SWFW semaphore and get the shared phy token as needed\n+ * Acquires the SWFW semaphore and get the shared phy token as needed\n */\n STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)\n {\n@@ -4325,11 +4325,11 @@ STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)\n }\n \n /**\n- * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore\n- * @hw: pointer to hardware structure\n- * @mask: Mask to specify which semaphore to release\n+ * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore\n+ * @hw: pointer to hardware structure\n+ * @mask: Mask to specify which semaphore to release\n *\n- * Releases the SWFW semaphore and puts the shared phy token as needed\n+ * Releases the SWFW semaphore and puts the shared phy token as needed\n */\n STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)\n {\n@@ -4345,15 +4345,15 @@ STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)\n }\n \n /**\n- * ixgbe_read_phy_reg_x550a - Reads specified PHY register\n- * @hw: pointer to hardware structure\n- * @reg_addr: 32 bit address of PHY register to read\n- * @device_type: 5 bit device type\n- * @phy_data: Pointer to read data from PHY register\n+ * ixgbe_read_phy_reg_x550a - Reads specified PHY register\n+ * @hw: pointer to hardware structure\n+ * @reg_addr: 32 bit address of PHY register to read\n+ * @device_type: 5 bit device type\n+ * @phy_data: Pointer to read data from PHY register\n *\n- * Reads a value from a specified PHY register using the SWFW lock and PHY\n- * Token. The PHY Token is needed since the MDIO is shared between to MAC\n- * instances.\n+ * Reads a value from a specified PHY register using the SWFW lock and PHY\n+ * Token. The PHY Token is needed since the MDIO is shared between to MAC\n+ * instances.\n **/\n s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,\n \t\t\t u32 device_type, u16 *phy_data)\n@@ -4374,14 +4374,14 @@ s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,\n }\n \n /**\n- * ixgbe_write_phy_reg_x550a - Writes specified PHY register\n- * @hw: pointer to hardware structure\n- * @reg_addr: 32 bit PHY register to write\n- * @device_type: 5 bit device type\n- * @phy_data: Data to write to the PHY register\n+ * ixgbe_write_phy_reg_x550a - Writes specified PHY register\n+ * @hw: pointer to hardware structure\n+ * @reg_addr: 32 bit PHY register to write\n+ * @device_type: 5 bit device type\n+ * @phy_data: Data to write to the PHY register\n *\n- * Writes a value to specified PHY register using the SWFW lock and PHY Token.\n- * The PHY Token is needed since the MDIO is shared between to MAC instances.\n+ * Writes a value to specified PHY register using the SWFW lock and PHY Token.\n+ * The PHY Token is needed since the MDIO is shared between to MAC instances.\n **/\n s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,\n \t\t\t\tu32 device_type, u16 phy_data)\n@@ -4532,8 +4532,8 @@ s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n }\n \n /**\n- * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI\n- * @hw: pointer to hardware structure\n+ * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI\n+ * @hw: pointer to hardware structure\n **/\n s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)\n {\n@@ -4549,9 +4549,9 @@ s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.\n- * @hw: pointer to hardware structure\n- * @led_idx: led number to turn on\n+ * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.\n+ * @hw: pointer to hardware structure\n+ * @led_idx: led number to turn on\n **/\n s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)\n {\n@@ -4574,9 +4574,9 @@ s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)\n }\n \n /**\n- * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.\n- * @hw: pointer to hardware structure\n- * @led_idx: led number to turn off\n+ * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.\n+ * @hw: pointer to hardware structure\n+ * @led_idx: led number to turn off\n **/\n s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)\n {\n@@ -4599,19 +4599,19 @@ s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)\n }\n \n /**\n- * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware\n- * @hw: pointer to the HW structure\n- * @maj: driver version major number\n- * @min: driver version minor number\n- * @build: driver version build number\n- * @sub: driver version sub build number\n- * @len: length of driver_ver string\n- * @driver_ver: driver string\n+ * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware\n+ * @hw: pointer to the HW structure\n+ * @maj: driver version major number\n+ * @min: driver version minor number\n+ * @build: driver version build number\n+ * @sub: driver version sub build number\n+ * @len: length of driver_ver string\n+ * @driver_ver: driver string\n *\n- * Sends driver version number to firmware through the manageability\n- * block. On success return IXGBE_SUCCESS\n- * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring\n- * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.\n+ * Sends driver version number to firmware through the manageability\n+ * block. On success return IXGBE_SUCCESS\n+ * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring\n+ * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.\n **/\n s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,\n \t\t\t u8 build, u8 sub, u16 len, const char *driver_ver)\n", "prefixes": [ "09/21" ] }