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GET /api/patches/71058/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 71058,
    "url": "http://patches.dpdk.org/api/patches/71058/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200609120001.35110-52-qi.z.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20200609120001.35110-52-qi.z.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20200609120001.35110-52-qi.z.zhang@intel.com",
    "date": "2020-06-09T12:00:00",
    "name": "[v2,51/52] net/ice/base: add 1G SGMII PHY type",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "27ed415ef87dfa4566b7c9131b20acc3912c880f",
    "submitter": {
        "id": 504,
        "url": "http://patches.dpdk.org/api/people/504/?format=api",
        "name": "Qi Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "delegate": {
        "id": 31221,
        "url": "http://patches.dpdk.org/api/users/31221/?format=api",
        "username": "yexl",
        "first_name": "xiaolong",
        "last_name": "ye",
        "email": "xiaolong.ye@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200609120001.35110-52-qi.z.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 10359,
            "url": "http://patches.dpdk.org/api/series/10359/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=10359",
            "date": "2020-06-09T11:59:09",
            "name": "net/ice: base code update",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/10359/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/71058/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/71058/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CC598A0516;\n\tTue,  9 Jun 2020 14:05:24 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1A9F71C117;\n\tTue,  9 Jun 2020 13:57:44 +0200 (CEST)",
            "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by dpdk.org (Postfix) with ESMTP id CBB031C042\n for <dev@dpdk.org>; Tue,  9 Jun 2020 13:57:42 +0200 (CEST)",
            "from fmsmga005.fm.intel.com ([10.253.24.32])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Jun 2020 04:57:42 -0700",
            "from dpdk51.sh.intel.com ([10.67.111.82])\n by fmsmga005.fm.intel.com with ESMTP; 09 Jun 2020 04:57:40 -0700"
        ],
        "IronPort-SDR": [
            "\n Hx11oCtD0lho2D4A8EQp7V/G3DAWVOL72IuCaRfBQg7PSs+MPq8nIsilX0RhunouMZUuPpivxE\n wBGR54tb3hCQ==",
            "\n IWTP9/ewj4Py8AKRpcOKgtktRXAPkV2iWFcxlDVHPkB2fSa5kDOOxjvUs1TBwqXzNKd72nydBi\n EnhR9EnW+3Og=="
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.73,492,1583222400\"; d=\"scan'208\";a=\"473044402\"",
        "From": "Qi Zhang <qi.z.zhang@intel.com>",
        "To": "qiming.yang@intel.com",
        "Cc": "xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>",
        "Date": "Tue,  9 Jun 2020 20:00:00 +0800",
        "Message-Id": "<20200609120001.35110-52-qi.z.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.13.6",
        "In-Reply-To": "<20200609120001.35110-1-qi.z.zhang@intel.com>",
        "References": "<20200603024016.30636-1-qi.z.zhang@intel.com>\n <20200609120001.35110-1-qi.z.zhang@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v2 51/52] net/ice/base: add 1G SGMII PHY type",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "There isn't a case for 1G SGMII in ice_get_media_type() so add\nthe handling for it.\n\nAlso handle the special case where some direct attach\ncables may report that they support 1G SGMII, but\nthat is erroneous since SGMII is supposed to be a\nbackplane media type (between a MAC and a PHY). If\nthe driver doesn't handle this special case then a\nuser could see the 'Port' in ethtool change from\n'Direct attach Copper' to 'Backplane' when they have\nforced the speed to 1G, but the cable hasn't changed.\n\nLastly, change ice_aq_get_phy_caps() to save the\nmodule_type info if the function was called with\nICE_AQC_REPORT_TOPO_CAP. This call uses the media\ninformation to populate the module_type. If no\nmedia is present then the values in module_type\nwill be 0.\n\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h |  1 +\n drivers/net/ice/base/ice_common.c     | 20 ++++++++++++++++----\n 2 files changed, 17 insertions(+), 4 deletions(-)",
    "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex d9d43639f..f480917cd 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -1382,6 +1382,7 @@ struct ice_aqc_get_phy_caps_data {\n \tu8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];\n #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS\t\t\t0xA0\n #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS\t\t0x80\n+#define ICE_AQC_MOD_TYPE_IDENT\t\t\t\t1\n #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE\tBIT(0)\n #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE\tBIT(1)\n #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR\t\tBIT(4)\ndiff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex 1d28a1399..2c822d7d4 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -197,6 +197,10 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,\n \tif (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {\n \t\tpi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);\n \t\tpi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);\n+\t\tice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type,\n+\t\t\t   sizeof(pi->phy.link_info.module_type),\n+\t\t\t   ICE_NONDMA_TO_NONDMA);\n+\n \t}\n \n \treturn status;\n@@ -269,6 +273,18 @@ static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)\n \t\treturn ICE_MEDIA_UNKNOWN;\n \n \tif (hw_link_info->phy_type_low) {\n+\t\t/* 1G SGMII is a special case where some DA cable PHYs\n+\t\t * may show this as an option when it really shouldn't\n+\t\t * be since SGMII is meant to be between a MAC and a PHY\n+\t\t * in a backplane. Try to detect this case and handle it\n+\t\t */\n+\t\tif (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII &&\n+\t\t    (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==\n+\t\t    ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE ||\n+\t\t    hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==\n+\t\t    ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE))\n+\t\t\treturn ICE_MEDIA_DA;\n+\n \t\tswitch (hw_link_info->phy_type_low) {\n \t\tcase ICE_PHY_TYPE_LOW_1000BASE_SX:\n \t\tcase ICE_PHY_TYPE_LOW_1000BASE_LX:\n@@ -2474,10 +2490,6 @@ enum ice_status ice_update_link_info(struct ice_port_info *pi)\n \n \t\tstatus = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,\n \t\t\t\t\t     pcaps, NULL);\n-\t\tif (status == ICE_SUCCESS)\n-\t\t\tice_memcpy(li->module_type, &pcaps->module_type,\n-\t\t\t\t   sizeof(li->module_type),\n-\t\t\t\t   ICE_NONDMA_TO_NONDMA);\n \n \t\tice_free(hw, pcaps);\n \t}\n",
    "prefixes": [
        "v2",
        "51/52"
    ]
}