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GET /api/patches/71044/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 71044,
    "url": "http://patches.dpdk.org/api/patches/71044/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200609120001.35110-38-qi.z.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20200609120001.35110-38-qi.z.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20200609120001.35110-38-qi.z.zhang@intel.com",
    "date": "2020-06-09T11:59:46",
    "name": "[v2,37/52] net/ice/base: fix for memory leak",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "38612c74522b7b339943945bed41f42a39258786",
    "submitter": {
        "id": 504,
        "url": "http://patches.dpdk.org/api/people/504/?format=api",
        "name": "Qi Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "delegate": {
        "id": 31221,
        "url": "http://patches.dpdk.org/api/users/31221/?format=api",
        "username": "yexl",
        "first_name": "xiaolong",
        "last_name": "ye",
        "email": "xiaolong.ye@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200609120001.35110-38-qi.z.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 10359,
            "url": "http://patches.dpdk.org/api/series/10359/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=10359",
            "date": "2020-06-09T11:59:09",
            "name": "net/ice: base code update",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/10359/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/71044/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/71044/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DBD3BA0516;\n\tTue,  9 Jun 2020 14:02:35 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1C7671BFC1;\n\tTue,  9 Jun 2020 13:57:22 +0200 (CEST)",
            "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by dpdk.org (Postfix) with ESMTP id 196031BF81;\n Tue,  9 Jun 2020 13:57:15 +0200 (CEST)",
            "from fmsmga005.fm.intel.com ([10.253.24.32])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Jun 2020 04:57:15 -0700",
            "from dpdk51.sh.intel.com ([10.67.111.82])\n by fmsmga005.fm.intel.com with ESMTP; 09 Jun 2020 04:57:13 -0700"
        ],
        "IronPort-SDR": [
            "\n SYDAbF2C3VxmO5q725bigaIa8c96DOOjMUEeVyHciH9xwi31RkcN/MUfcZzGy/eEhmNcyJjp6L\n MTuCCYwcRrdQ==",
            "\n Eixm9PbifBOSLNK+ryDgry9oKhnl21dv1+ZAaKSUsYqwVVAo9uxhWxdNkAfqqC+oWcRJ6Sm/UQ\n gC2WgTLhNBwA=="
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.73,492,1583222400\"; d=\"scan'208\";a=\"473044220\"",
        "From": "Qi Zhang <qi.z.zhang@intel.com>",
        "To": "qiming.yang@intel.com",
        "Cc": "xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n stable@dpdk.org, Surabhi Boob <surabhi.boob@intel.com>,\n \"Paul M . Stillwell Jr\" <paul.m.stillwell.jr@intel.com>",
        "Date": "Tue,  9 Jun 2020 19:59:46 +0800",
        "Message-Id": "<20200609120001.35110-38-qi.z.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.13.6",
        "In-Reply-To": "<20200609120001.35110-1-qi.z.zhang@intel.com>",
        "References": "<20200603024016.30636-1-qi.z.zhang@intel.com>\n <20200609120001.35110-1-qi.z.zhang@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v2 37/52] net/ice/base: fix for memory leak",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Handles memory leaks during control queue initialization and\nbuffer allocation failures. The MACRO - ICE_FREE_CQ_BUFS is modified to\nre-use for this fix.\n\nFixes: 6c1f26be50a2 (\"net/ice/base: add control queue information\")\nCc: stable@dpdk.org\n\nSigned-off-by: Surabhi Boob <surabhi.boob@intel.com>\nSigned-off-by: Paul M. Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_controlq.c | 39 +++++++++++++++++++++++--------------\n 1 file changed, 24 insertions(+), 15 deletions(-)",
    "diff": "diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c\nindex 3ef86fa03..f278ef636 100644\n--- a/drivers/net/ice/base/ice_controlq.c\n+++ b/drivers/net/ice/base/ice_controlq.c\n@@ -182,7 +182,9 @@ ice_alloc_rq_bufs(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n \ti--;\n \tfor (; i >= 0; i--)\n \t\tice_free_dma_mem(hw, &cq->rq.r.rq_bi[i]);\n+\tcq->rq.r.rq_bi = NULL;\n \tice_free(hw, cq->rq.dma_head);\n+\tcq->rq.dma_head = NULL;\n \n \treturn ICE_ERR_NO_MEMORY;\n }\n@@ -220,7 +222,9 @@ ice_alloc_sq_bufs(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n \ti--;\n \tfor (; i >= 0; i--)\n \t\tice_free_dma_mem(hw, &cq->sq.r.sq_bi[i]);\n+\tcq->sq.r.sq_bi = NULL;\n \tice_free(hw, cq->sq.dma_head);\n+\tcq->sq.dma_head = NULL;\n \n \treturn ICE_ERR_NO_MEMORY;\n }\n@@ -279,6 +283,24 @@ ice_cfg_rq_regs(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n \treturn ICE_SUCCESS;\n }\n \n+#define ICE_FREE_CQ_BUFS(hw, qi, ring)\t\t\t\t\t\\\n+do {\t\t\t\t\t\t\t\t\t\\\n+\t/* free descriptors */\t\t\t\t\t\t\\\n+\tif ((qi)->ring.r.ring##_bi) {\t\t\t\t\t\\\n+\t\tint i;\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tfor (i = 0; i < (qi)->num_##ring##_entries; i++)\t\\\n+\t\t\tif ((qi)->ring.r.ring##_bi[i].pa)\t\t\\\n+\t\t\t\tice_free_dma_mem((hw),\t\t\t\\\n+\t\t\t\t\t&(qi)->ring.r.ring##_bi[i]);\t\\\n+\t}\t\t\t\t\t\t\t\t\\\n+\t/* free the buffer info list */\t\t\t\t\t\\\n+\tif ((qi)->ring.cmd_buf)\t\t\t\t\t\t\\\n+\t\tice_free(hw, (qi)->ring.cmd_buf);\t\t\t\\\n+\t/* free DMA head */\t\t\t\t\t\t\\\n+\tice_free(hw, (qi)->ring.dma_head);\t\t\t\t\\\n+} while (0)\n+\n /**\n  * ice_init_sq - main initialization routine for Control ATQ\n  * @hw: pointer to the hardware structure\n@@ -334,6 +356,7 @@ static enum ice_status ice_init_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n \tgoto init_ctrlq_exit;\n \n init_ctrlq_free_rings:\n+\tICE_FREE_CQ_BUFS(hw, cq, sq);\n \tice_free_cq_ring(hw, &cq->sq);\n \n init_ctrlq_exit:\n@@ -395,27 +418,13 @@ static enum ice_status ice_init_rq(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n \tgoto init_ctrlq_exit;\n \n init_ctrlq_free_rings:\n+\tICE_FREE_CQ_BUFS(hw, cq, rq);\n \tice_free_cq_ring(hw, &cq->rq);\n \n init_ctrlq_exit:\n \treturn ret_code;\n }\n \n-#define ICE_FREE_CQ_BUFS(hw, qi, ring)\t\t\t\t\t\\\n-do {\t\t\t\t\t\t\t\t\t\\\n-\tint i;\t\t\t\t\t\t\t\t\\\n-\t/* free descriptors */\t\t\t\t\t\t\\\n-\tfor (i = 0; i < (qi)->num_##ring##_entries; i++)\t\t\\\n-\t\tif ((qi)->ring.r.ring##_bi[i].pa)\t\t\t\\\n-\t\t\tice_free_dma_mem((hw),\t\t\t\t\\\n-\t\t\t\t\t &(qi)->ring.r.ring##_bi[i]);\t\\\n-\t/* free the buffer info list */\t\t\t\t\t\\\n-\tif ((qi)->ring.cmd_buf)\t\t\t\t\t\t\\\n-\t\tice_free(hw, (qi)->ring.cmd_buf);\t\t\t\\\n-\t/* free DMA head */\t\t\t\t\t\t\\\n-\tice_free(hw, (qi)->ring.dma_head);\t\t\t\t\\\n-} while (0)\n-\n /**\n  * ice_shutdown_sq - shutdown the Control ATQ\n  * @hw: pointer to the hardware structure\n",
    "prefixes": [
        "v2",
        "37/52"
    ]
}