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GET /api/patches/70767/?format=api
{ "id": 70767, "url": "http://patches.dpdk.org/api/patches/70767/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200603024016.30636-6-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200603024016.30636-6-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200603024016.30636-6-qi.z.zhang@intel.com", "date": "2020-06-03T02:39:29", "name": "[05/52] net/ice/base: consolidate implementation of MAC config set", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "470c14844e2656bc7be57f4a6a4a8fe5a0eeb5bb", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 31221, "url": "http://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200603024016.30636-6-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 10300, "url": "http://patches.dpdk.org/api/series/10300/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=10300", "date": "2020-06-03T02:39:24", "name": "net/ice: base code update", "version": 1, "mbox": "http://patches.dpdk.org/series/10300/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/70767/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/70767/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id F2792A04EF;\n\tWed, 3 Jun 2020 04:37:10 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1DCA71BFF6;\n\tWed, 3 Jun 2020 04:36:33 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by dpdk.org (Postfix) with ESMTP id 663381BF31\n for <dev@dpdk.org>; Wed, 3 Jun 2020 04:36:31 +0200 (CEST)", "from orsmga001.jf.intel.com ([10.7.209.18])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 02 Jun 2020 19:36:30 -0700", "from dpdk51.sh.intel.com ([10.67.111.82])\n by orsmga001.jf.intel.com with ESMTP; 02 Jun 2020 19:36:28 -0700" ], "IronPort-SDR": [ "\n A6+bfuGhG56rtNKBq3Rd121NmnReaDr1TSfpyev/6LN49RLwO4NG89OgOQnOogofDemKvm59/J\n SYqHRBq+QOmg==", "\n 1AX1JjT7R0cp6tQMIWshIBA1oTbxOHKhFH5bDH0lfVcRxlFFNGnhhOWTEz0PmoStayW50OF/Xv\n 6eS3vyKLp5/g==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.73,466,1583222400\"; d=\"scan'208\";a=\"347613890\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>,\n Jeb Cramer <jeb.j.cramer@intel.com>,\n \"Paul M . Stillwell Jr\" <paul.m.stillwell.jr@intel.com>", "Date": "Wed, 3 Jun 2020 10:39:29 +0800", "Message-Id": "<20200603024016.30636-6-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20200603024016.30636-1-qi.z.zhang@intel.com>", "References": "<20200603024016.30636-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 05/52] net/ice/base: consolidate implementation\n\tof MAC config set", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Consolidate implementation of ice_aq_set_mac_cfg for switch mode\nand NIC mode. As per the specification, the driver needs to call\nset_mac_cfg (opcode 0x0603) to be able to exercise jumbo frames.\n\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\nSigned-off-by: Jeb Cramer <jeb.j.cramer@intel.com>\nSigned-off-by: Paul M. Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_common.c | 65 ++++++++++++++++++++++-------------\n drivers/net/ice/base/ice_hw_autogen.h | 4 +--\n 2 files changed, 44 insertions(+), 25 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex 4b4555f6f..051eb8c64 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -410,6 +410,43 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,\n }\n \n /**\n+ * ice_fill_tx_timer_and_fc_thresh\n+ * @hw: pointer to the HW struct\n+ * @cmd: pointer to MAC cfg structure\n+ *\n+ * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command\n+ * descriptor\n+ */\n+static void\n+ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,\n+\t\t\t\tstruct ice_aqc_set_mac_cfg *cmd)\n+{\n+\tu16 fc_thres_val, tx_timer_val;\n+\tu32 val;\n+\n+\t/* We read back the transmit timer and fc threshold value of\n+\t * LFC. Thus, we will use index =\n+\t * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.\n+\t *\n+\t * Also, because we are opearating on transmit timer and fc\n+\t * threshold of LFC, we don't turn on any bit in tx_tmr_priority\n+\t */\n+#define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX\n+\n+\t/* Retrieve the transmit timer */\n+\tval = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));\n+\ttx_timer_val = val &\n+\t\tPRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;\n+\tcmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);\n+\n+\t/* Retrieve the fc threshold */\n+\tval = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));\n+\tfc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;\n+\n+\tcmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val);\n+}\n+\n+/**\n * ice_aq_set_mac_cfg\n * @hw: pointer to the HW struct\n * @max_frame_size: Maximum Frame Size to be supported\n@@ -420,10 +457,8 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,\n enum ice_status\n ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)\n {\n-\tu16 fc_threshold_val, tx_timer_val;\n \tstruct ice_aqc_set_mac_cfg *cmd;\n \tstruct ice_aq_desc desc;\n-\tu32 reg_val;\n \n \tcmd = &desc.params.set_mac_cfg;\n \n@@ -434,27 +469,7 @@ ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)\n \n \tcmd->max_frame_size = CPU_TO_LE16(max_frame_size);\n \n-\t/* We read back the transmit timer and fc threshold value of\n-\t * LFC. Thus, we will use index =\n-\t * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.\n-\t *\n-\t * Also, because we are opearating on transmit timer and fc\n-\t * threshold of LFC, we don't turn on any bit in tx_tmr_priority\n-\t */\n-#define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX\n-\n-\t/* Retrieve the transmit timer */\n-\treg_val = rd32(hw,\n-\t\t PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));\n-\ttx_timer_val = reg_val &\n-\t\tPRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;\n-\tcmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);\n-\n-\t/* Retrieve the fc threshold */\n-\treg_val = rd32(hw,\n-\t\t PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));\n-\tfc_threshold_val = reg_val & MAKEMASK(0xFFFF, 0);\n-\tcmd->fc_refresh_threshold = CPU_TO_LE16(fc_threshold_val);\n+\tice_fill_tx_timer_and_fc_thresh(hw, cmd);\n \n \treturn ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n }\n@@ -721,6 +736,10 @@ enum ice_status ice_init_hw(struct ice_hw *hw)\n \n \tif (status)\n \t\tgoto err_unroll_fltr_mgmt_struct;\n+\t/* enable jumbo frame support at MAC level */\n+\tstatus = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);\n+\tif (status)\n+\t\tgoto err_unroll_fltr_mgmt_struct;\n \t/* Obtain counter base index which would be used by flow director */\n \tstatus = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);\n \tif (status)\ndiff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h\nindex 1c9c84dfb..572f481b7 100644\n--- a/drivers/net/ice/base/ice_hw_autogen.h\n+++ b/drivers/net/ice/base/ice_hw_autogen.h\n@@ -5232,8 +5232,8 @@\n #define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)\n #define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3800 + ((_i) * 32)) /* _i=0...8 */ /* Reset Source: GLOBR */\n #define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8\n-#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_S 0\n-#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M MAKEMASK(0xFFFF, 0)\n+#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_S 0\n+#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M MAKEMASK(0xFFFF, 0)\n #define PRTMAC_HSEC_CTL_TX_SA_PART1\t\t0x001E3960 /* Reset Source: GLOBR */\n #define PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_S 0\n #define PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_M MAKEMASK(0xFFFFFFFF, 0)\n", "prefixes": [ "05/52" ] }