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GET /api/patches/7004/?format=api
{ "id": 7004, "url": "http://patches.dpdk.org/api/patches/7004/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1441859917-26475-27-git-send-email-xiao.w.wang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1441859917-26475-27-git-send-email-xiao.w.wang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1441859917-26475-27-git-send-email-xiao.w.wang@intel.com", "date": "2015-09-10T04:38:35", "name": "[dpdk-dev,26/28] fm10k: add 1588 clock owner message support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "32b7cdf6b61773620c5125f4d8834d47a201dc92", "submitter": { "id": 281, "url": "http://patches.dpdk.org/api/people/281/?format=api", "name": "Xiao Wang", "email": "xiao.w.wang@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1441859917-26475-27-git-send-email-xiao.w.wang@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/7004/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/7004/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 8652D9215;\n\tThu, 10 Sep 2015 06:39:47 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id 168339204\n\tfor <dev@dpdk.org>; Thu, 10 Sep 2015 06:39:44 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby orsmga102.jf.intel.com with ESMTP; 09 Sep 2015 21:39:46 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby FMSMGA003.fm.intel.com with ESMTP; 09 Sep 2015 21:39:44 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id t8A4dg39007923;\n\tThu, 10 Sep 2015 12:39:42 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid t8A4dcvX026698; Thu, 10 Sep 2015 12:39:40 +0800", "(from xiaowan1@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t8A4dcIa026694; \n\tThu, 10 Sep 2015 12:39:38 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.17,501,1437462000\"; d=\"scan'208\";a=\"558781505\"", "From": "Wang Xiao W <xiao.w.wang@intel.com>", "To": "dev@dpdk.org", "Date": "Thu, 10 Sep 2015 12:38:35 +0800", "Message-Id": "<1441859917-26475-27-git-send-email-xiao.w.wang@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1441859917-26475-1-git-send-email-xiao.w.wang@intel.com>", "References": "<1441859917-26475-1-git-send-email-xiao.w.wang@intel.com>", "Cc": "Wang Xiao W <xiao.w.wang@intel.com>", "Subject": "[dpdk-dev] [PATCH 26/28] fm10k: add 1588 clock owner message support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support for tx timestamp mode response message. The switch manager\nshould send this message whenever the owner changes or when a new port\nappears. To simplify logic, treat this as full clock ownership, and call\nit the CLOCK_OWNER message. Implement this as a hw->flags field, so that\nbase driver may use it to disable any functions which modify the clock\nincluding Tx timestamps, frequency adjustments, and offset adjustments.\nThis ensures only one PEP will be handling these at a time.\n\nSigned-off-by: Wang Xiao W <xiao.w.wang@intel.com>\n---\n drivers/net/fm10k/base/fm10k_osdep.h | 1 +\n drivers/net/fm10k/base/fm10k_pf.c | 47 ++++++++++++++++++++++++++++++++++++\n drivers/net/fm10k/base/fm10k_pf.h | 13 ++++++++++\n drivers/net/fm10k/base/fm10k_type.h | 2 ++\n 4 files changed, 63 insertions(+)", "diff": "diff --git a/drivers/net/fm10k/base/fm10k_osdep.h b/drivers/net/fm10k/base/fm10k_osdep.h\nindex 53c433c..64f09dc 100644\n--- a/drivers/net/fm10k/base/fm10k_osdep.h\n+++ b/drivers/net/fm10k/base/fm10k_osdep.h\n@@ -106,6 +106,7 @@ typedef int bool;\n #define FM10K_LE32_TO_CPU rte_le_to_cpu_32\n #define FM10K_CPU_TO_LE32 rte_cpu_to_le_32\n #define FM10K_CPU_TO_LE16 rte_cpu_to_le_16\n+#define le16_to_cpu rte_le_to_cpu_16\n \n #define FM10K_RMB rte_rmb\n #define FM10K_WMB rte_wmb\ndiff --git a/drivers/net/fm10k/base/fm10k_pf.c b/drivers/net/fm10k/base/fm10k_pf.c\nindex 0526077..396a2e0 100644\n--- a/drivers/net/fm10k/base/fm10k_pf.c\n+++ b/drivers/net/fm10k/base/fm10k_pf.c\n@@ -1852,6 +1852,48 @@ const struct fm10k_tlv_attr fm10k_1588_timestamp_msg_attr[] = {\n \tFM10K_TLV_ATTR_LAST\n };\n \n+const struct fm10k_tlv_attr fm10k_1588_clock_owner_attr[] = {\n+\tFM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_1588_CLOCK_OWNER,\n+\t\t\t\t sizeof(struct fm10k_swapi_1588_clock_owner)),\n+\tFM10K_TLV_ATTR_LAST\n+};\n+\n+/**\n+ * fm10k_msg_1588_clock_owner_pf - Message handler for clock ownership from SM\n+ * @hw: pointer to hardware structure\n+ * @results: pointer to array containing parsed data,\n+ * @mbx: Pointer to mailbox information structure\n+ *\n+ * This handler configures the FM10K_HW_FLAG_CLOCK_OWNER field for the PF\n+ */\n+s32 fm10k_msg_1588_clock_owner_pf(struct fm10k_hw *hw, u32 **results,\n+\t\t\t\t struct fm10k_mbx_info *mbx)\n+{\n+\tstruct fm10k_swapi_1588_clock_owner msg;\n+\tu16 glort;\n+\ts32 err;\n+\n+\tUNREFERENCED_1PARAMETER(mbx);\n+\tDEBUGFUNC(\"fm10k_msg_1588_clock_owner\");\n+\n+\terr = fm10k_tlv_attr_get_le_struct(\n+\t\tresults[FM10K_PF_ATTR_ID_1588_CLOCK_OWNER],\n+\t\t&msg, sizeof(msg));\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* We own the clock iff the glort matches us and the enabled field is\n+\t * true. Otherwise, the clock must belong to some other port.\n+\t */\n+\tglort = le16_to_cpu(msg.glort);\n+\tif (fm10k_glort_valid_pf(hw, glort) && msg.enabled)\n+\t\thw->flags |= FM10K_HW_FLAG_CLOCK_OWNER;\n+\telse\n+\t\thw->flags &= ~FM10K_HW_FLAG_CLOCK_OWNER;\n+\n+\treturn FM10K_SUCCESS;\n+}\n+\n /**\n * fm10k_adjust_systime_pf - Adjust systime frequency\n * @hw: pointer to hardware structure\n@@ -1871,6 +1913,10 @@ STATIC s32 fm10k_adjust_systime_pf(struct fm10k_hw *hw, s32 ppb)\n \n \tDEBUGFUNC(\"fm10k_adjust_systime_vf\");\n \n+\t/* ensure that we control the clock */\n+\tif (!(hw->flags & FM10K_HW_FLAG_CLOCK_OWNER))\n+\t\treturn FM10K_ERR_DEVICE_NOT_SUPPORTED;\n+\n \t/* if sw_addr is not set we don't have switch register access */\n \tif (!hw->sw_addr)\n \t\treturn ppb ? FM10K_ERR_PARAM : FM10K_SUCCESS;\n@@ -1936,6 +1982,7 @@ static const struct fm10k_msg_data fm10k_msg_data_pf[] = {\n \tFM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf),\n \tFM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf),\n \tFM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_msg_update_pvid_pf),\n+\tFM10K_PF_MSG_1588_CLOCK_OWNER_HANDLER(fm10k_msg_1588_clock_owner_pf),\n \tFM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),\n };\n \ndiff --git a/drivers/net/fm10k/base/fm10k_pf.h b/drivers/net/fm10k/base/fm10k_pf.h\nindex dd25c49..ae8a737 100644\n--- a/drivers/net/fm10k/base/fm10k_pf.h\n+++ b/drivers/net/fm10k/base/fm10k_pf.h\n@@ -57,6 +57,7 @@ enum fm10k_pf_tlv_msg_id_v1 {\n \tFM10K_PF_MSG_ID_SET_FLOW_STATE\t\t= 0x505,\n \tFM10K_PF_MSG_ID_GET_1588_INFO\t\t= 0x506,\n \tFM10K_PF_MSG_ID_1588_TIMESTAMP\t\t= 0x701,\n+\tFM10K_PF_MSG_ID_1588_CLOCK_OWNER\t= 0x702,\n };\n \n enum fm10k_pf_tlv_attr_id_v1 {\n@@ -75,6 +76,7 @@ enum fm10k_pf_tlv_attr_id_v1 {\n \tFM10K_PF_ATTR_ID_PORT\t\t\t= 0x0C,\n \tFM10K_PF_ATTR_ID_UPDATE_PVID\t\t= 0x0D,\n \tFM10K_PF_ATTR_ID_1588_TIMESTAMP\t\t= 0x10,\n+\tFM10K_PF_ATTR_ID_1588_CLOCK_OWNER\t= 0x12,\n };\n \n #define FM10K_MSG_LPORT_MAP_GLORT_SHIFT\t0\n@@ -125,6 +127,10 @@ struct fm10k_swapi_1588_timestamp {\n \t__le16 sglort;\n };\n \n+struct fm10k_swapi_1588_clock_owner {\n+\t__le16 glort;\n+\t__le16 enabled;\n+};\n \n #ifdef C99\n #pragma pack(pop)\n@@ -158,6 +164,13 @@ extern const struct fm10k_tlv_attr fm10k_1588_timestamp_msg_attr[];\n \tFM10K_MSG_HANDLER(FM10K_PF_MSG_ID_1588_TIMESTAMP, \\\n \t\t\t fm10k_1588_timestamp_msg_attr, func)\n \n+s32 fm10k_msg_1588_clock_owner_pf(struct fm10k_hw *, u32 **,\n+\t\t\t\t struct fm10k_mbx_info *);\n+extern const struct fm10k_tlv_attr fm10k_1588_clock_owner_attr[];\n+#define FM10K_PF_MSG_1588_CLOCK_OWNER_HANDLER(func) \\\n+\tFM10K_MSG_HANDLER(FM10K_PF_MSG_ID_1588_CLOCK_OWNER, \\\n+\t\t\t fm10k_1588_clock_owner_attr, func)\n+\n s32 fm10k_iov_msg_msix_pf(struct fm10k_hw *, u32 **, struct fm10k_mbx_info *);\n s32 fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw *, u32 **,\n \t\t\t struct fm10k_mbx_info *);\ndiff --git a/drivers/net/fm10k/base/fm10k_type.h b/drivers/net/fm10k/base/fm10k_type.h\nindex 7fdf8a4..e0fc08d 100644\n--- a/drivers/net/fm10k/base/fm10k_type.h\n+++ b/drivers/net/fm10k/base/fm10k_type.h\n@@ -805,6 +805,8 @@ struct fm10k_hw {\n \tu16 subsystem_device_id;\n \tu16 subsystem_vendor_id;\n \tu8 revision_id;\n+\tu32 flags;\n+#define FM10K_HW_FLAG_CLOCK_OWNER\t(u32)(1 << 0)\n };\n \n /* Number of Transmit and Receive Descriptors must be a multiple of 8 */\n", "prefixes": [ "dpdk-dev", "26/28" ] }