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GET /api/patches/68863/?format=api
{ "id": 68863, "url": "http://patches.dpdk.org/api/patches/68863/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1587250008-69892-3-git-send-email-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1587250008-69892-3-git-send-email-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1587250008-69892-3-git-send-email-nicolas.chautru@intel.com", "date": "2020-04-18T22:46:39", "name": "[v5,02/11] baseband/fpga_5gnr_fec: add register definition file", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "548cea1f2fbcff8384fdc0b06b3c37c295cad194", "submitter": { "id": 1314, "url": "http://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1587250008-69892-3-git-send-email-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 9494, "url": "http://patches.dpdk.org/api/series/9494/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=9494", "date": "2020-04-18T22:46:38", "name": "drivers/baseband: PMD for FPGA 5GNR FEC", "version": 5, "mbox": "http://patches.dpdk.org/series/9494/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/68863/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/68863/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CCECEA0598;\n\tSun, 19 Apr 2020 00:47:04 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 4CA7A1D447;\n\tSun, 19 Apr 2020 00:46:57 +0200 (CEST)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n by dpdk.org (Postfix) with ESMTP id 0461B1B951\n for <dev@dpdk.org>; Sun, 19 Apr 2020 00:46:53 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 18 Apr 2020 15:46:51 -0700", "from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210])\n by fmsmga005.fm.intel.com with ESMTP; 18 Apr 2020 15:46:51 -0700" ], "IronPort-SDR": [ "\n paPCDOY+9sDqy0DPbPCXrRu7jJXWTYCHLgawLWETW2OCePMKUgxCQq/Y/U4QAGq0h6GfpnqosO\n SzKETXwsWwjw==", "\n XS+aWYjybQqLNJ19S9HhPZc6bMXQq8Ku7wFLyki03rSSIIBI9UsxABmehs0yuan32JYE8uebTn\n BJ6/hGS/HnXw==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.72,400,1580803200\"; d=\"scan'208\";a=\"455111233\"", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\takhil.goyal@nxp.com", "Cc": "bruce.richardson@intel.com,\n\tNicolas Chautru <nicolas.chautru@intel.com>", "Date": "Sat, 18 Apr 2020 15:46:39 -0700", "Message-Id": "<1587250008-69892-3-git-send-email-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1587250008-69892-1-git-send-email-nicolas.chautru@intel.com>", "References": "<1587250008-69892-1-git-send-email-nicolas.chautru@intel.com>", "Subject": "[dpdk-dev] [PATCH v5 02/11] baseband/fpga_5gnr_fec: add register\n\tdefinition file", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add in the list of registers for the device and related\nHW specs definitions.\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\n---\n drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h | 189 +++++++++++++++++++++++++\n 1 file changed, 189 insertions(+)", "diff": "diff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h\nindex 0c481e2..8db623f 100644\n--- a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h\n+++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h\n@@ -30,6 +30,195 @@\n #define FPGA_5GNR_FEC_PF_DEVICE_ID (0x0D8F)\n #define FPGA_5GNR_FEC_VF_DEVICE_ID (0x0D90)\n \n+/* Align DMA descriptors to 256 bytes - cache-aligned */\n+#define FPGA_RING_DESC_ENTRY_LENGTH (8)\n+/* Ring size is in 256 bits (32 bytes) units */\n+#define FPGA_RING_DESC_LEN_UNIT_BYTES (32)\n+/* Maximum size of queue */\n+#define FPGA_RING_MAX_SIZE (1024)\n+#define FPGA_FLR_TIMEOUT_UNIT (16.384)\n+\n+#define FPGA_NUM_UL_QUEUES (32)\n+#define FPGA_NUM_DL_QUEUES (32)\n+#define FPGA_TOTAL_NUM_QUEUES (FPGA_NUM_UL_QUEUES + FPGA_NUM_DL_QUEUES)\n+#define FPGA_NUM_INTR_VEC (FPGA_TOTAL_NUM_QUEUES - RTE_INTR_VEC_RXTX_OFFSET)\n+\n+#define FPGA_INVALID_HW_QUEUE_ID (0xFFFFFFFF)\n+\n+#define FPGA_QUEUE_FLUSH_TIMEOUT_US (1000)\n+#define FPGA_HARQ_RDY_TIMEOUT (10)\n+#define FPGA_TIMEOUT_CHECK_INTERVAL (5)\n+#define FPGA_DDR_OVERFLOW (0x10)\n+\n+#define FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES 8\n+#define FPGA_5GNR_FEC_DDR_RD_DATA_LEN_IN_BYTES 8\n+\n+\n+/* FPGA 5GNR FEC Register mapping on BAR0 */\n+enum {\n+\tFPGA_5GNR_FEC_VERSION_ID = 0x00000000, /* len: 4B */\n+\tFPGA_5GNR_FEC_CONFIGURATION = 0x00000004, /* len: 2B */\n+\tFPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /* len: 1B */\n+\tFPGA_5GNR_FEC_LOAD_BALANCE_FACTOR = 0x0000000a, /* len: 2B */\n+\tFPGA_5GNR_FEC_RING_DESC_LEN = 0x0000000c, /* len: 2B */\n+\tFPGA_5GNR_FEC_FLR_TIME_OUT = 0x0000000e, /* len: 2B */\n+\tFPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /* len: 4B */\n+\tFPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001c, /* len: 4B */\n+\tFPGA_5GNR_FEC_QUEUE_MAP = 0x00000040, /* len: 256B */\n+\tFPGA_5GNR_FEC_RING_CTRL_REGS = 0x00000200, /* len: 2048B */\n+\tFPGA_5GNR_FEC_DDR4_WR_ADDR_REGS = 0x00000A00, /* len: 4B */\n+\tFPGA_5GNR_FEC_DDR4_WR_DATA_REGS = 0x00000A08, /* len: 8B */\n+\tFPGA_5GNR_FEC_DDR4_WR_DONE_REGS = 0x00000A10, /* len: 1B */\n+\tFPGA_5GNR_FEC_DDR4_RD_ADDR_REGS = 0x00000A18, /* len: 4B */\n+\tFPGA_5GNR_FEC_DDR4_RD_DONE_REGS = 0x00000A20, /* len: 1B */\n+\tFPGA_5GNR_FEC_DDR4_RD_RDY_REGS = 0x00000A28, /* len: 1B */\n+\tFPGA_5GNR_FEC_DDR4_RD_DATA_REGS = 0x00000A30, /* len: 8B */\n+\tFPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS = 0x00000A38, /* len: 1B */\n+\tFPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS = 0x00000A40, /* len: 1B */\n+\tFPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS = 0x00000A48 /* len: 4B */\n+};\n+\n+/* FPGA 5GNR FEC Ring Control Registers */\n+enum {\n+\tFPGA_5GNR_FEC_RING_HEAD_ADDR = 0x00000008,\n+\tFPGA_5GNR_FEC_RING_SIZE = 0x00000010,\n+\tFPGA_5GNR_FEC_RING_MISC = 0x00000014,\n+\tFPGA_5GNR_FEC_RING_ENABLE = 0x00000015,\n+\tFPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN = 0x00000016,\n+\tFPGA_5GNR_FEC_RING_SHADOW_TAIL = 0x00000018,\n+\tFPGA_5GNR_FEC_RING_HEAD_POINT = 0x0000001C\n+};\n+\n+/* FPGA 5GNR FEC DESCRIPTOR ERROR */\n+enum {\n+\tDESC_ERR_NO_ERR = 0x0,\n+\tDESC_ERR_K_P_OUT_OF_RANGE = 0x1,\n+\tDESC_ERR_Z_C_NOT_LEGAL = 0x2,\n+\tDESC_ERR_DESC_OFFSET_ERR = 0x3,\n+\tDESC_ERR_DESC_READ_FAIL = 0x8,\n+\tDESC_ERR_DESC_READ_TIMEOUT = 0x9,\n+\tDESC_ERR_DESC_READ_TLP_POISONED = 0xA,\n+\tDESC_ERR_CB_READ_FAIL = 0xC,\n+\tDESC_ERR_CB_READ_TIMEOUT = 0xD,\n+\tDESC_ERR_CB_READ_TLP_POISONED = 0xE,\n+\tDESC_ERR_HBSTORE_ERR = 0xF\n+};\n+\n+\n+/* FPGA 5GNR FEC DMA Encoding Request Descriptor */\n+struct __attribute__((__packed__)) fpga_dma_enc_desc {\n+\tuint32_t done:1,\n+\t\trsrvd0:7,\n+\t\terror:4,\n+\t\trsrvd1:4,\n+\t\tnum_null:10,\n+\t\trsrvd2:6;\n+\tuint32_t ncb:15,\n+\t\trsrvd3:1,\n+\t\tk0:16;\n+\tuint32_t irq_en:1,\n+\t\tcrc_en:1,\n+\t\trsrvd4:1,\n+\t\tqm_idx:3,\n+\t\tbg_idx:1,\n+\t\tzc:9,\n+\t\tdesc_idx:10,\n+\t\trsrvd5:6;\n+\tuint16_t rm_e;\n+\tuint16_t k_;\n+\tuint32_t out_addr_lw;\n+\tuint32_t out_addr_hi;\n+\tuint32_t in_addr_lw;\n+\tuint32_t in_addr_hi;\n+\n+\tunion {\n+\t\tstruct {\n+\t\t\t/* Virtual addresses used to retrieve SW context info */\n+\t\t\tvoid *op_addr;\n+\t\t\t/* Stores information about total number of Code Blocks\n+\t\t\t * in currently processed Transport Block\n+\t\t\t */\n+\t\t\tuint64_t cbs_in_op;\n+\t\t};\n+\n+\t\tuint8_t sw_ctxt[FPGA_RING_DESC_LEN_UNIT_BYTES *\n+\t\t\t\t\t(FPGA_RING_DESC_ENTRY_LENGTH - 1)];\n+\t};\n+};\n+\n+\n+/* FPGA 5GNR DPC FEC DMA Decoding Request Descriptor */\n+struct __attribute__((__packed__)) fpga_dma_dec_desc {\n+\tuint32_t done:1,\n+\t\titer:5,\n+\t\tet_pass:1,\n+\t\tcrcb_pass:1,\n+\t\terror:4,\n+\t\tqm_idx:3,\n+\t\tmax_iter:5,\n+\t\tbg_idx:1,\n+\t\trsrvd0:1,\n+\t\tharqin_en:1,\n+\t\tzc:9;\n+\tuint32_t hbstroe_offset:22,\n+\t\tnum_null:10;\n+\tuint32_t irq_en:1,\n+\t\tncb:15,\n+\t\tdesc_idx:10,\n+\t\tdrop_crc24b:1,\n+\t\tcrc24b_ind:1,\n+\t\trv:2,\n+\t\tet_dis:1,\n+\t\trsrvd2:1;\n+\tuint32_t harq_input_length:16,\n+\t\trm_e:16;/*the inbound data byte length*/\n+\tuint32_t out_addr_lw;\n+\tuint32_t out_addr_hi;\n+\tuint32_t in_addr_lw;\n+\tuint32_t in_addr_hi;\n+\n+\tunion {\n+\t\tstruct {\n+\t\t\t/* Virtual addresses used to retrieve SW context info */\n+\t\t\tvoid *op_addr;\n+\t\t\t/* Stores information about total number of Code Blocks\n+\t\t\t * in currently processed Transport Block\n+\t\t\t */\n+\t\t\tuint8_t cbs_in_op;\n+\t\t};\n+\n+\t\tuint32_t sw_ctxt[8 * (FPGA_RING_DESC_ENTRY_LENGTH - 1)];\n+\t};\n+};\n+\n+/* FPGA 5GNR DMA Descriptor */\n+union fpga_dma_desc {\n+\tstruct fpga_dma_enc_desc enc_req;\n+\tstruct fpga_dma_dec_desc dec_req;\n+};\n+\n+/* FPGA 5GNR FEC Ring Control Register */\n+struct __attribute__((__packed__)) fpga_ring_ctrl_reg {\n+\tuint64_t ring_base_addr;\n+\tuint64_t ring_head_addr;\n+\tuint16_t ring_size:11;\n+\tuint16_t rsrvd0;\n+\tunion { /* Miscellaneous register */\n+\t\tuint8_t misc;\n+\t\tuint8_t max_ul_dec:5,\n+\t\t\tmax_ul_dec_en:1,\n+\t\t\trsrvd1:2;\n+\t};\n+\tuint8_t enable;\n+\tuint8_t flush_queue_en;\n+\tuint8_t rsrvd2;\n+\tuint16_t shadow_tail;\n+\tuint16_t rsrvd3;\n+\tuint16_t head_point;\n+\tuint16_t rsrvd4;\n+\n+};\n+\n /* Private data structure for each FPGA FEC device */\n struct fpga_5gnr_fec_device {\n \t/** Base address of MMIO registers (BAR0) */\n", "prefixes": [ "v5", "02/11" ] }