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GET /api/patches/68722/?format=api
{ "id": 68722, "url": "http://patches.dpdk.org/api/patches/68722/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1587098436-7493-9-git-send-email-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1587098436-7493-9-git-send-email-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1587098436-7493-9-git-send-email-nicolas.chautru@intel.com", "date": "2020-04-17T04:40:33", "name": "[v3,08/11] baseband/fpga_5gnr_fec: add configure function", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "fd1267b0c8cdea7fd973384508527393da633049", "submitter": { "id": 1314, "url": "http://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1587098436-7493-9-git-send-email-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 9446, "url": "http://patches.dpdk.org/api/series/9446/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=9446", "date": "2020-04-17T04:40:25", "name": "drivers/baseband: PMD for FPGA 5GNR FEC", "version": 3, "mbox": "http://patches.dpdk.org/series/9446/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/68722/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/68722/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 17CD6A0588;\n\tFri, 17 Apr 2020 06:43:13 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 0869F1DE8A;\n\tFri, 17 Apr 2020 06:41:52 +0200 (CEST)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by dpdk.org (Postfix) with ESMTP id 4636B1DE23\n for <dev@dpdk.org>; Fri, 17 Apr 2020 06:41:41 +0200 (CEST)", "from orsmga002.jf.intel.com ([10.7.209.21])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 16 Apr 2020 21:41:41 -0700", "from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210])\n by orsmga002.jf.intel.com with ESMTP; 16 Apr 2020 21:41:39 -0700" ], "IronPort-SDR": [ "\n y/8zC/RFtuoE4Bm1vfTMO9mB+tnZmx+01ek3MKqeQSgGOY+aJhRWoI7/L6mkPP4HXiBvXLqsrg\n xl9QId54l6Mw==", "\n Bxn6rQ2SROYXiPzl5cwV6b7pGY2h43bHheDaCJl1YwyV/ovHO+95BZyUtxsCXGVr/T7bV1basB\n PV8rI3yt0lLQ==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.72,393,1580803200\"; d=\"scan'208\";a=\"272304075\"", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\takhil.goyal@nxp.com", "Cc": "bruce.richardson@intel.com,\n\tNicolas Chautru <nicolas.chautru@intel.com>", "Date": "Thu, 16 Apr 2020 21:40:33 -0700", "Message-Id": "<1587098436-7493-9-git-send-email-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1587098436-7493-1-git-send-email-nicolas.chautru@intel.com>", "References": "<1587098436-7493-1-git-send-email-nicolas.chautru@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 08/11] baseband/fpga_5gnr_fec: add configure\n\tfunction", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add configure function to configure the PF from within\nthe bbdev-test itself without external application\nconfiguration the device.\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\n---\n app/test-bbdev/test_bbdev_perf.c | 57 ++++++\n doc/guides/bbdevs/fpga_5gnr_fec.rst | 123 +++++++++++++\n drivers/baseband/fpga_5gnr_fec/Makefile | 3 +\n drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 196 +++++++++++++++++++++\n .../rte_pmd_bbdev_fpga_5gnr_fec_version.map | 7 +\n .../baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h | 74 ++++++++\n 6 files changed, 460 insertions(+)\n create mode 100644 drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h", "diff": "diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c\nindex 6ec17e5..45c0d62 100644\n--- a/app/test-bbdev/test_bbdev_perf.c\n+++ b/app/test-bbdev/test_bbdev_perf.c\n@@ -39,6 +39,19 @@\n #define FLR_4G_TIMEOUT 610\n #endif\n \n+#ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC\n+#include <rte_pmd_fpga_5gnr_fec.h>\n+#define FPGA_5GNR_PF_DRIVER_NAME (\"intel_fpga_5gnr_fec_pf\")\n+#define FPGA_5GNR_VF_DRIVER_NAME (\"intel_fpga_5gnr_fec_vf\")\n+#define VF_UL_5G_QUEUE_VALUE 4\n+#define VF_DL_5G_QUEUE_VALUE 4\n+#define UL_5G_BANDWIDTH 3\n+#define DL_5G_BANDWIDTH 3\n+#define UL_5G_LOAD_BALANCE 128\n+#define DL_5G_LOAD_BALANCE 128\n+#define FLR_5G_TIMEOUT 610\n+#endif\n+\n #define OPS_CACHE_SIZE 256U\n #define OPS_POOL_SIZE_MIN 511U /* 0.5K per queue */\n \n@@ -596,6 +609,50 @@ typedef int (test_case_function)(struct active_device *ad,\n \t\t\t\tinfo->dev_name);\n \t}\n #endif\n+#ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC\n+\tif ((get_init_device() == true) &&\n+\t\t(!strcmp(info->drv.driver_name, FPGA_5GNR_PF_DRIVER_NAME))) {\n+\t\tstruct fpga_5gnr_fec_conf conf;\n+\t\tunsigned int i;\n+\n+\t\tprintf(\"Configure FPGA 5GNR FEC Driver %s with default values\\n\",\n+\t\t\t\tinfo->drv.driver_name);\n+\n+\t\t/* clear default configuration before initialization */\n+\t\tmemset(&conf, 0, sizeof(struct fpga_5gnr_fec_conf));\n+\n+\t\t/* Set PF mode :\n+\t\t * true if PF is used for data plane\n+\t\t * false for VFs\n+\t\t */\n+\t\tconf.pf_mode_en = true;\n+\n+\t\tfor (i = 0; i < FPGA_5GNR_FEC_NUM_VFS; ++i) {\n+\t\t\t/* Number of UL queues per VF (fpga supports 8 VFs) */\n+\t\t\tconf.vf_ul_queues_number[i] = VF_UL_5G_QUEUE_VALUE;\n+\t\t\t/* Number of DL queues per VF (fpga supports 8 VFs) */\n+\t\t\tconf.vf_dl_queues_number[i] = VF_DL_5G_QUEUE_VALUE;\n+\t\t}\n+\n+\t\t/* UL bandwidth. Needed for schedule algorithm */\n+\t\tconf.ul_bandwidth = UL_5G_BANDWIDTH;\n+\t\t/* DL bandwidth */\n+\t\tconf.dl_bandwidth = DL_5G_BANDWIDTH;\n+\n+\t\t/* UL & DL load Balance Factor to 64 */\n+\t\tconf.ul_load_balance = UL_5G_LOAD_BALANCE;\n+\t\tconf.dl_load_balance = DL_5G_LOAD_BALANCE;\n+\n+\t\t/**< FLR timeout value */\n+\t\tconf.flr_time_out = FLR_5G_TIMEOUT;\n+\n+\t\t/* setup FPGA PF with configuration information */\n+\t\tret = fpga_5gnr_fec_configure(info->dev_name, &conf);\n+\t\tTEST_ASSERT_SUCCESS(ret,\n+\t\t\t\t\"Failed to configure 5G FPGA PF for bbdev %s\",\n+\t\t\t\tinfo->dev_name);\n+\t}\n+#endif\n \tnb_queues = RTE_MIN(rte_lcore_count(), info->drv.max_num_queues);\n \tnb_queues = RTE_MIN(nb_queues, (unsigned int) MAX_QUEUES);\n \ndiff --git a/doc/guides/bbdevs/fpga_5gnr_fec.rst b/doc/guides/bbdevs/fpga_5gnr_fec.rst\nindex 7eab7a4..5641b1a 100644\n--- a/doc/guides/bbdevs/fpga_5gnr_fec.rst\n+++ b/doc/guides/bbdevs/fpga_5gnr_fec.rst\n@@ -166,6 +166,129 @@ name is different:\n echo <num-of-vfs> > /sys/bus/pci/devices/0000\\:<b>\\:<d>.<f>/sriov_numvfs\n \n \n+Configure the VFs through PF\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+The PCI virtual functions must be configured before working or getting assigned\n+to VMs/Containers. The configuration involves allocating the number of hardware\n+queues, priorities, load balance, bandwidth and other settings necessary for the\n+device to perform FEC functions.\n+\n+This configuration needs to be executed at least once after reboot or PCI FLR and can\n+be achieved by using the function ``fpga_5gnr_fec_configure()``, which sets up the\n+parameters defined in ``fpga_5gnr_fec_conf`` structure:\n+\n+.. code-block:: c\n+\n+ struct fpga_5gnr_fec_conf {\n+ bool pf_mode_en;\n+ uint8_t vf_ul_queues_number[FPGA_5GNR_FEC_NUM_VFS];\n+ uint8_t vf_dl_queues_number[FPGA_5GNR_FEC_NUM_VFS];\n+ uint8_t ul_bandwidth;\n+ uint8_t dl_bandwidth;\n+ uint8_t ul_load_balance;\n+ uint8_t dl_load_balance;\n+ uint16_t flr_time_out;\n+ };\n+\n+- ``pf_mode_en``: identifies whether only PF is to be used, or the VFs. PF and\n+ VFs are mutually exclusive and cannot run simultaneously.\n+ Set to 1 for PF mode enabled.\n+ If PF mode is enabled all queues available in the device are assigned\n+ exclusively to PF and 0 queues given to VFs.\n+\n+- ``vf_*l_queues_number``: defines the hardware queue mapping for every VF.\n+\n+- ``*l_bandwidth``: in case of congestion on PCIe interface. The device\n+ allocates different bandwidth to UL and DL. The weight is configured by this\n+ setting. The unit of weight is 3 code blocks. For example, if the code block\n+ cbps (code block per second) ratio between UL and DL is 12:1, then the\n+ configuration value should be set to 36:3. The schedule algorithm is based\n+ on code block regardless the length of each block.\n+\n+- ``*l_load_balance``: hardware queues are load-balanced in a round-robin\n+ fashion. Queues get filled first-in first-out until they reach a pre-defined\n+ watermark level, if exceeded, they won't get assigned new code blocks..\n+ This watermark is defined by this setting.\n+\n+ If all hardware queues exceeds the watermark, no code blocks will be\n+ streamed in from UL/DL code block FIFO.\n+\n+- ``flr_time_out``: specifies how many 16.384us to be FLR time out. The\n+ time_out = flr_time_out x 16.384us. For instance, if you want to set 10ms for\n+ the FLR time out then set this setting to 0x262=610.\n+\n+\n+An example configuration code calling the function ``fpga_5gnr_fec_configure()`` is shown\n+below:\n+\n+.. code-block:: c\n+\n+ struct fpga_5gnr_fec_conf conf;\n+ unsigned int i;\n+\n+ memset(&conf, 0, sizeof(struct fpga_5gnr_fec_conf));\n+ conf.pf_mode_en = 1;\n+\n+ for (i = 0; i < FPGA_5GNR_FEC_NUM_VFS; ++i) {\n+ conf.vf_ul_queues_number[i] = 4;\n+ conf.vf_dl_queues_number[i] = 4;\n+ }\n+ conf.ul_bandwidth = 12;\n+ conf.dl_bandwidth = 5;\n+ conf.dl_load_balance = 64;\n+ conf.ul_load_balance = 64;\n+\n+ /* setup FPGA PF */\n+ ret = fpga_5gnr_fec_configure(info->dev_name, &conf);\n+ TEST_ASSERT_SUCCESS(ret,\n+ \"Failed to configure 4G FPGA PF for bbdev %s\",\n+ info->dev_name);\n+\n+\n+Test Application\n+----------------\n+\n+BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing\n+the functionality of FPGA 5GNR FEC encode and decode, depending on the device's\n+capabilities. The test application is located under app->test-bbdev folder and has the\n+following options:\n+\n+.. code-block:: console\n+\n+ \"-p\", \"--testapp-path\": specifies path to the bbdev test app.\n+ \"-e\", \"--eal-params\"\t: EAL arguments which are passed to the test app.\n+ \"-t\", \"--timeout\"\t: Timeout in seconds (default=300).\n+ \"-c\", \"--test-cases\"\t: Defines test cases to run. Run all if not specified.\n+ \"-v\", \"--test-vector\"\t: Test vector path (default=dpdk_path+/app/test-bbdev/test_vectors/bbdev_null.data).\n+ \"-n\", \"--num-ops\"\t: Number of operations to process on device (default=32).\n+ \"-b\", \"--burst-size\"\t: Operations enqueue/dequeue burst size (default=32).\n+ \"-l\", \"--num-lcores\"\t: Number of lcores to run (default=16).\n+ \"-i\", \"--init-device\" : Initialise PF device with default values.\n+\n+\n+To execute the test application tool using simple decode or encode data,\n+type one of the following:\n+\n+.. code-block:: console\n+\n+ ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_dec_default.data\n+ ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_enc_default.data\n+\n+\n+The test application ``test-bbdev.py``, supports the ability to configure the PF device with\n+a default set of values, if the \"-i\" or \"- -init-device\" option is included. The default values\n+are defined in test_bbdev_perf.c as:\n+\n+- VF_UL_QUEUE_VALUE 4\n+- VF_DL_QUEUE_VALUE 4\n+- UL_BANDWIDTH 3\n+- DL_BANDWIDTH 3\n+- UL_LOAD_BALANCE 128\n+- DL_LOAD_BALANCE 128\n+- FLR_TIMEOUT 610\n+\n+\n Test Vectors\n ~~~~~~~~~~~~\n \ndiff --git a/drivers/baseband/fpga_5gnr_fec/Makefile b/drivers/baseband/fpga_5gnr_fec/Makefile\nindex 3f5c511..ffbbf3c 100644\n--- a/drivers/baseband/fpga_5gnr_fec/Makefile\n+++ b/drivers/baseband/fpga_5gnr_fec/Makefile\n@@ -23,4 +23,7 @@ LIBABIVER := 1\n # library source files\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC) += rte_fpga_5gnr_fec.c\n \n+# export include files\n+SYMLINK-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC)-include += rte_pmd_fpga_5gnr_fec.h\n+\n include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\nindex 94413e2..ef608de 100644\n--- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n+++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n@@ -21,6 +21,7 @@\n #include <rte_bbdev_pmd.h>\n \n #include \"fpga_5gnr_fec.h\"\n+#include \"rte_pmd_fpga_5gnr_fec.h\"\n \n /* 5GNR SW PMD logging ID */\n static int fpga_5gnr_fec_logtype;\n@@ -1629,6 +1630,201 @@\n \treturn 0;\n }\n \n+static inline void\n+set_default_fpga_conf(struct fpga_5gnr_fec_conf *def_conf)\n+{\n+\t/* clear default configuration before initialization */\n+\tmemset(def_conf, 0, sizeof(struct fpga_5gnr_fec_conf));\n+\t/* Set pf mode to true */\n+\tdef_conf->pf_mode_en = true;\n+\n+\t/* Set ratio between UL and DL to 1:1 (unit of weight is 3 CBs) */\n+\tdef_conf->ul_bandwidth = 3;\n+\tdef_conf->dl_bandwidth = 3;\n+\n+\t/* Set Load Balance Factor to 64 */\n+\tdef_conf->dl_load_balance = 64;\n+\tdef_conf->ul_load_balance = 64;\n+}\n+\n+/* Initial configuration of FPGA 5GNR FEC device */\n+int\n+fpga_5gnr_fec_configure(const char *dev_name,\n+\t\tconst struct fpga_5gnr_fec_conf *conf)\n+{\n+\tuint32_t payload_32, address;\n+\tuint16_t payload_16;\n+\tuint8_t payload_8;\n+\tuint16_t q_id, vf_id, total_q_id, total_ul_q_id, total_dl_q_id;\n+\tstruct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);\n+\tstruct fpga_5gnr_fec_conf def_conf;\n+\n+\tif (bbdev == NULL) {\n+\t\trte_bbdev_log(ERR,\n+\t\t\t\t\"Invalid dev_name (%s), or device is not yet initialised\",\n+\t\t\t\tdev_name);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tstruct fpga_5gnr_fec_device *d = bbdev->data->dev_private;\n+\n+\tif (conf == NULL) {\n+\t\trte_bbdev_log(ERR,\n+\t\t\t\t\"FPGA Configuration was not provided. Default configuration will be loaded.\");\n+\t\tset_default_fpga_conf(&def_conf);\n+\t\tconf = &def_conf;\n+\t}\n+\n+\t/*\n+\t * Configure UL:DL ratio.\n+\t * [7:0]: UL weight\n+\t * [15:8]: DL weight\n+\t */\n+\tpayload_16 = (conf->dl_bandwidth << 8) | conf->ul_bandwidth;\n+\taddress = FPGA_5GNR_FEC_CONFIGURATION;\n+\tfpga_reg_write_16(d->mmio_base, address, payload_16);\n+\n+\t/* Clear all queues registers */\n+\tpayload_32 = FPGA_INVALID_HW_QUEUE_ID;\n+\tfor (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {\n+\t\taddress = (q_id << 2) + FPGA_5GNR_FEC_QUEUE_MAP;\n+\t\tfpga_reg_write_32(d->mmio_base, address, payload_32);\n+\t}\n+\n+\t/*\n+\t * If PF mode is enabled allocate all queues for PF only.\n+\t *\n+\t * For VF mode each VF can have different number of UL and DL queues.\n+\t * Total number of queues to configure cannot exceed FPGA\n+\t * capabilities - 64 queues - 32 queues for UL and 32 queues for DL.\n+\t * Queues mapping is done according to configuration:\n+\t *\n+\t * UL queues:\n+\t * | Q_ID | VF_ID |\n+\t * | 0 | 0 |\n+\t * | ... | 0 |\n+\t * | conf->vf_dl_queues_number[0] - 1 | 0 |\n+\t * | conf->vf_dl_queues_number[0] | 1 |\n+\t * | ... | 1 |\n+\t * | conf->vf_dl_queues_number[1] - 1 | 1 |\n+\t * | ... | ... |\n+\t * | conf->vf_dl_queues_number[7] - 1 | 7 |\n+\t *\n+\t * DL queues:\n+\t * | Q_ID | VF_ID |\n+\t * | 32 | 0 |\n+\t * | ... | 0 |\n+\t * | conf->vf_ul_queues_number[0] - 1 | 0 |\n+\t * | conf->vf_ul_queues_number[0] | 1 |\n+\t * | ... | 1 |\n+\t * | conf->vf_ul_queues_number[1] - 1 | 1 |\n+\t * | ... | ... |\n+\t * | conf->vf_ul_queues_number[7] - 1 | 7 |\n+\t *\n+\t * Example of configuration:\n+\t * conf->vf_ul_queues_number[0] = 4; -> 4 UL queues for VF0\n+\t * conf->vf_dl_queues_number[0] = 4; -> 4 DL queues for VF0\n+\t * conf->vf_ul_queues_number[1] = 2; -> 2 UL queues for VF1\n+\t * conf->vf_dl_queues_number[1] = 2; -> 2 DL queues for VF1\n+\t *\n+\t * UL:\n+\t * | Q_ID | VF_ID |\n+\t * | 0 | 0 |\n+\t * | 1 | 0 |\n+\t * | 2 | 0 |\n+\t * | 3 | 0 |\n+\t * | 4 | 1 |\n+\t * | 5 | 1 |\n+\t *\n+\t * DL:\n+\t * | Q_ID | VF_ID |\n+\t * | 32 | 0 |\n+\t * | 33 | 0 |\n+\t * | 34 | 0 |\n+\t * | 35 | 0 |\n+\t * | 36 | 1 |\n+\t * | 37 | 1 |\n+\t */\n+\tif (conf->pf_mode_en) {\n+\t\tpayload_32 = 0x1;\n+\t\tfor (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {\n+\t\t\taddress = (q_id << 2) + FPGA_5GNR_FEC_QUEUE_MAP;\n+\t\t\tfpga_reg_write_32(d->mmio_base, address, payload_32);\n+\t\t}\n+\t} else {\n+\t\t/* Calculate total number of UL and DL queues to configure */\n+\t\ttotal_ul_q_id = total_dl_q_id = 0;\n+\t\tfor (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) {\n+\t\t\ttotal_ul_q_id += conf->vf_ul_queues_number[vf_id];\n+\t\t\ttotal_dl_q_id += conf->vf_dl_queues_number[vf_id];\n+\t\t}\n+\t\ttotal_q_id = total_dl_q_id + total_ul_q_id;\n+\t\t/*\n+\t\t * Check if total number of queues to configure does not exceed\n+\t\t * FPGA capabilities (64 queues - 32 UL and 32 DL queues)\n+\t\t */\n+\t\tif ((total_ul_q_id > FPGA_NUM_UL_QUEUES) ||\n+\t\t\t(total_dl_q_id > FPGA_NUM_DL_QUEUES) ||\n+\t\t\t(total_q_id > FPGA_TOTAL_NUM_QUEUES)) {\n+\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\t\"FPGA Configuration failed. Too many queues to configure: UL_Q %u, DL_Q %u, FPGA_Q %u\",\n+\t\t\t\t\ttotal_ul_q_id, total_dl_q_id,\n+\t\t\t\t\tFPGA_TOTAL_NUM_QUEUES);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\ttotal_ul_q_id = 0;\n+\t\tfor (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) {\n+\t\t\tfor (q_id = 0; q_id < conf->vf_ul_queues_number[vf_id];\n+\t\t\t\t\t++q_id, ++total_ul_q_id) {\n+\t\t\t\taddress = (total_ul_q_id << 2) +\n+\t\t\t\t\t\tFPGA_5GNR_FEC_QUEUE_MAP;\n+\t\t\t\tpayload_32 = ((0x80 + vf_id) << 16) | 0x1;\n+\t\t\t\tfpga_reg_write_32(d->mmio_base, address,\n+\t\t\t\t\t\tpayload_32);\n+\t\t\t}\n+\t\t}\n+\t\ttotal_dl_q_id = 0;\n+\t\tfor (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) {\n+\t\t\tfor (q_id = 0; q_id < conf->vf_dl_queues_number[vf_id];\n+\t\t\t\t\t++q_id, ++total_dl_q_id) {\n+\t\t\t\taddress = ((total_dl_q_id + FPGA_NUM_UL_QUEUES)\n+\t\t\t\t\t\t<< 2) + FPGA_5GNR_FEC_QUEUE_MAP;\n+\t\t\t\tpayload_32 = ((0x80 + vf_id) << 16) | 0x1;\n+\t\t\t\tfpga_reg_write_32(d->mmio_base, address,\n+\t\t\t\t\t\tpayload_32);\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\t/* Setting Load Balance Factor */\n+\tpayload_16 = (conf->dl_load_balance << 8) | (conf->ul_load_balance);\n+\taddress = FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR;\n+\tfpga_reg_write_16(d->mmio_base, address, payload_16);\n+\n+\t/* Setting length of ring descriptor entry */\n+\tpayload_16 = FPGA_RING_DESC_ENTRY_LENGTH;\n+\taddress = FPGA_5GNR_FEC_RING_DESC_LEN;\n+\tfpga_reg_write_16(d->mmio_base, address, payload_16);\n+\n+\t/* Setting FLR timeout value */\n+\tpayload_16 = conf->flr_time_out;\n+\taddress = FPGA_5GNR_FEC_FLR_TIME_OUT;\n+\tfpga_reg_write_16(d->mmio_base, address, payload_16);\n+\n+\t/* Queue PF/VF mapping table is ready */\n+\tpayload_8 = 0x1;\n+\taddress = FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE;\n+\tfpga_reg_write_8(d->mmio_base, address, payload_8);\n+\n+\trte_bbdev_log_debug(\"PF FPGA 5GNR FEC configuration complete for %s\",\n+\t\t\tdev_name);\n+\n+#ifdef RTE_LIBRTE_BBDEV_DEBUG\n+\tprint_static_reg_debug_info(d->mmio_base);\n+#endif\n+\treturn 0;\n+}\n+\n /* FPGA 5GNR FEC PCI PF address map */\n static struct rte_pci_id pci_id_fpga_5gnr_fec_pf_map[] = {\n \t{\ndiff --git a/drivers/baseband/fpga_5gnr_fec/rte_pmd_bbdev_fpga_5gnr_fec_version.map b/drivers/baseband/fpga_5gnr_fec/rte_pmd_bbdev_fpga_5gnr_fec_version.map\nindex f9f17e4..b0fb971 100644\n--- a/drivers/baseband/fpga_5gnr_fec/rte_pmd_bbdev_fpga_5gnr_fec_version.map\n+++ b/drivers/baseband/fpga_5gnr_fec/rte_pmd_bbdev_fpga_5gnr_fec_version.map\n@@ -1,3 +1,10 @@\n DPDK_20.0 {\n \tlocal: *;\n };\n+\n+EXPERIMENTAL {\n+\tglobal:\n+\n+\tfpga_5gnr_fec_configure;\n+\n+};\ndiff --git a/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h\nnew file mode 100644\nindex 0000000..70a4acf\n--- /dev/null\n+++ b/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h\n@@ -0,0 +1,74 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+\n+#ifndef _RTE_PMD_FPGA_5GNR_FEC_H_\n+#define _RTE_PMD_FPGA_5GNR_FEC_H_\n+\n+#include <stdint.h>\n+#include <stdbool.h>\n+\n+/**\n+ * @file rte_pmd_fpga_5gnr_fec.h\n+ *\n+ * Interface for Intel(R) FGPA 5GNR FEC device configuration at the host level,\n+ * directly accessible by the application.\n+ * Configuration related to 5GNR functionality is done through\n+ * librte_bbdev library.\n+ *\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice\n+ */\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+/** Number of Virtual Functions FGPA 4G FEC supports */\n+#define FPGA_5GNR_FEC_NUM_VFS 8\n+\n+/**\n+ * Structure to pass FPGA 4G FEC configuration.\n+ */\n+struct fpga_5gnr_fec_conf {\n+\t/** 1 if PF is used for dataplane, 0 for VFs */\n+\tbool pf_mode_en;\n+\t/** Number of UL queues per VF */\n+\tuint8_t vf_ul_queues_number[FPGA_5GNR_FEC_NUM_VFS];\n+\t/** Number of DL queues per VF */\n+\tuint8_t vf_dl_queues_number[FPGA_5GNR_FEC_NUM_VFS];\n+\t/** UL bandwidth. Needed for schedule algorithm */\n+\tuint8_t ul_bandwidth;\n+\t/** DL bandwidth. Needed for schedule algorithm */\n+\tuint8_t dl_bandwidth;\n+\t/** UL Load Balance */\n+\tuint8_t ul_load_balance;\n+\t/** DL Load Balance */\n+\tuint8_t dl_load_balance;\n+\t/** FLR timeout value */\n+\tuint16_t flr_time_out;\n+};\n+\n+/**\n+ * Configure Intel(R) FPGA 5GNR FEC device\n+ *\n+ * @param dev_name\n+ * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.\n+ * It can also be retrieved for a bbdev device from the dev_name field in the\n+ * rte_bbdev_info structure returned by rte_bbdev_info_get().\n+ * @param conf\n+ * Configuration to apply to FPGA 4G FEC.\n+ *\n+ * @return\n+ * Zero on success, negative value on failure.\n+ */\n+__rte_experimental\n+int\n+fpga_5gnr_fec_configure(const char *dev_name,\n+\t\tconst struct fpga_5gnr_fec_conf *conf);\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_PMD_FPGA_5GNR_FEC_H_ */\n", "prefixes": [ "v3", "08/11" ] }