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GET /api/patches/68717/?format=api
{ "id": 68717, "url": "http://patches.dpdk.org/api/patches/68717/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1587098436-7493-4-git-send-email-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1587098436-7493-4-git-send-email-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1587098436-7493-4-git-send-email-nicolas.chautru@intel.com", "date": "2020-04-17T04:40:28", "name": "[v3,03/11] baseband/fpga_5gnr_fec: add device info_get function", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "34855115089e5a8e6307cb9ed0e0158b36b61806", "submitter": { "id": 1314, "url": "http://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1587098436-7493-4-git-send-email-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 9446, "url": "http://patches.dpdk.org/api/series/9446/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=9446", "date": "2020-04-17T04:40:25", "name": "drivers/baseband: PMD for FPGA 5GNR FEC", "version": 3, "mbox": "http://patches.dpdk.org/series/9446/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/68717/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/68717/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9FFA8A0588;\n\tFri, 17 Apr 2020 06:42:07 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1D4AB1DE41;\n\tFri, 17 Apr 2020 06:41:43 +0200 (CEST)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by dpdk.org (Postfix) with ESMTP id 810E81DE1A\n for <dev@dpdk.org>; Fri, 17 Apr 2020 06:41:38 +0200 (CEST)", "from orsmga002.jf.intel.com ([10.7.209.21])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 16 Apr 2020 21:41:37 -0700", "from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210])\n by orsmga002.jf.intel.com with ESMTP; 16 Apr 2020 21:41:37 -0700" ], "IronPort-SDR": [ "\n ngK5tznrBhHTb/EaCC8UcCz8Mq49nI0kKzb/vyCoM7m0QbCbgydeNAhugYjVHyVnLtgHilTO6+\n CZkTgTerIkOA==", "\n qFSvpTSHzoKs2MbnqdI7nPRF1ge/+Cs2MN+NU/E5R5052GcYuziNhICGRlv0KiIMP3xtFS7BhR\n PdKqvyAJxGiw==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.72,393,1580803200\"; d=\"scan'208\";a=\"272304045\"", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\takhil.goyal@nxp.com", "Cc": "bruce.richardson@intel.com,\n\tNicolas Chautru <nicolas.chautru@intel.com>", "Date": "Thu, 16 Apr 2020 21:40:28 -0700", "Message-Id": "<1587098436-7493-4-git-send-email-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1587098436-7493-1-git-send-email-nicolas.chautru@intel.com>", "References": "<1587098436-7493-1-git-send-email-nicolas.chautru@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 03/11] baseband/fpga_5gnr_fec: add device\n\tinfo_get function", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add in the \"info_get\" function to the driver, to allow us to query the\ndevice.\nNo capability are available yet.\nLinking bbdev-test to support the PMD with null capability.\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\n---\n app/test-bbdev/Makefile | 3 ++\n app/test-bbdev/meson.build | 3 ++\n drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h | 9 ++++\n drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 53 ++++++++++++++++++++++\n 4 files changed, 68 insertions(+)", "diff": "diff --git a/app/test-bbdev/Makefile b/app/test-bbdev/Makefile\nindex 8272d2b..dc29557 100644\n--- a/app/test-bbdev/Makefile\n+++ b/app/test-bbdev/Makefile\n@@ -23,5 +23,8 @@ LDLIBS += -lm\n ifeq ($(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC),y)\n LDLIBS += -lrte_pmd_bbdev_fpga_lte_fec\n endif\n+ifeq ($(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC),y)\n+LDLIBS += -lrte_pmd_bbdev_fpga_5gnr_fec\n+endif\n \n include $(RTE_SDK)/mk/rte.app.mk\ndiff --git a/app/test-bbdev/meson.build b/app/test-bbdev/meson.build\nindex 0d9f684..18ab6a8 100644\n--- a/app/test-bbdev/meson.build\n+++ b/app/test-bbdev/meson.build\n@@ -9,3 +9,6 @@ deps += ['bbdev', 'bus_vdev']\n if dpdk_conf.has('RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC')\n \tdeps += ['pmd_bbdev_fpga_lte_fec']\n endif\n+if dpdk_conf.has('RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC')\n+\tdeps += ['pmd_bbdev_fpga_5gnr_fec']\n+endif\ndiff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h\nindex 8db623f..167d440 100644\n--- a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h\n+++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h\n@@ -227,4 +227,13 @@ struct fpga_5gnr_fec_device {\n \tbool pf_device;\n };\n \n+/* Read a register of FPGA 5GNR FEC device */\n+static inline uint32_t\n+fpga_reg_read_32(void *mmio_base, uint32_t offset)\n+{\n+\tvoid *reg_addr = RTE_PTR_ADD(mmio_base, offset);\n+\tuint32_t ret = *((volatile uint32_t *)(reg_addr));\n+\treturn rte_le_to_cpu_32(ret);\n+}\n+\n #endif /* _FPGA_5GNR_FEC_H_ */\ndiff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\nindex ae0ec11..b3f2d0e 100644\n--- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n+++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n@@ -28,8 +28,61 @@\n \treturn 0;\n }\n \n+static void\n+fpga_dev_info_get(struct rte_bbdev *dev,\n+\t\tstruct rte_bbdev_driver_info *dev_info)\n+{\n+\tstruct fpga_5gnr_fec_device *d = dev->data->dev_private;\n+\tuint32_t q_id = 0;\n+\n+\tstatic const struct rte_bbdev_op_cap bbdev_capabilities[] = {\n+\t\tRTE_BBDEV_END_OF_CAPABILITIES_LIST()\n+\t};\n+\n+\t/* Check the HARQ DDR size available */\n+\tuint8_t timeout_counter = 0;\n+\tuint32_t harq_buf_ready = fpga_reg_read_32(d->mmio_base,\n+\t\t\tFPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS);\n+\twhile (harq_buf_ready != 1) {\n+\t\tusleep(FPGA_TIMEOUT_CHECK_INTERVAL);\n+\t\ttimeout_counter++;\n+\t\tharq_buf_ready = fpga_reg_read_32(d->mmio_base,\n+\t\t\t\tFPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS);\n+\t\tif (timeout_counter > FPGA_HARQ_RDY_TIMEOUT) {\n+\t\t\trte_bbdev_log(ERR, \"HARQ Buffer not ready %d\",\n+\t\t\t\t\tharq_buf_ready);\n+\t\t\tharq_buf_ready = 1;\n+\t\t}\n+\t}\n+\tuint32_t harq_buf_size = fpga_reg_read_32(d->mmio_base,\n+\t\t\tFPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS);\n+\n+\tstatic struct rte_bbdev_queue_conf default_queue_conf;\n+\tdefault_queue_conf.socket = dev->data->socket_id;\n+\tdefault_queue_conf.queue_size = FPGA_RING_MAX_SIZE;\n+\n+\tdev_info->driver_name = dev->device->driver->name;\n+\tdev_info->queue_size_lim = FPGA_RING_MAX_SIZE;\n+\tdev_info->hardware_accelerated = true;\n+\tdev_info->min_alignment = 64;\n+\tdev_info->harq_buffer_size = (harq_buf_size >> 10) + 1;\n+\tdev_info->default_queue_conf = default_queue_conf;\n+\tdev_info->capabilities = bbdev_capabilities;\n+\tdev_info->cpu_flag_reqs = NULL;\n+\n+\t/* Calculates number of queues assigned to device */\n+\tdev_info->max_num_queues = 0;\n+\tfor (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {\n+\t\tuint32_t hw_q_id = fpga_reg_read_32(d->mmio_base,\n+\t\t\t\tFPGA_5GNR_FEC_QUEUE_MAP + (q_id << 2));\n+\t\tif (hw_q_id != FPGA_INVALID_HW_QUEUE_ID)\n+\t\t\tdev_info->max_num_queues++;\n+\t}\n+}\n+\n static const struct rte_bbdev_ops fpga_ops = {\n \t.close = fpga_dev_close,\n+\t.info_get = fpga_dev_info_get,\n };\n \n /* Initialization Function */\n", "prefixes": [ "v3", "03/11" ] }