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GET /api/patches/68669/?format=api
{ "id": 68669, "url": "http://patches.dpdk.org/api/patches/68669/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200416122438.32319-2-adamx.dybkowski@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200416122438.32319-2-adamx.dybkowski@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200416122438.32319-2-adamx.dybkowski@intel.com", "date": "2020-04-16T12:24:38", "name": "[v2,1/1] crypto/qat: support plain SHA1..SHA512 hashes", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3ffc579d498d3590d28ca3cf9089aaf8a6d1ad39", "submitter": { "id": 1322, "url": "http://patches.dpdk.org/api/people/1322/?format=api", "name": "Dybkowski, AdamX", "email": "adamx.dybkowski@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200416122438.32319-2-adamx.dybkowski@intel.com/mbox/", "series": [ { "id": 9424, "url": "http://patches.dpdk.org/api/series/9424/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=9424", "date": "2020-04-16T12:24:37", "name": "crypto/qat: support plain SHA1..SHA512 hashes", "version": 2, "mbox": "http://patches.dpdk.org/series/9424/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/68669/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/68669/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EC0CBA0588;\n\tThu, 16 Apr 2020 14:24:49 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 9AD431DC55;\n\tThu, 16 Apr 2020 14:24:45 +0200 (CEST)", "from mga06.intel.com (mga06.intel.com [134.134.136.31])\n by dpdk.org (Postfix) with ESMTP id 4D0381DC35\n for <dev@dpdk.org>; Thu, 16 Apr 2020 14:24:42 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 16 Apr 2020 05:24:41 -0700", "from adamdybx-mobl.ger.corp.intel.com (HELO\n addy-VirtualBox.ger.corp.intel.com) ([10.104.125.85])\n by fmsmga002.fm.intel.com with ESMTP; 16 Apr 2020 05:24:40 -0700" ], "IronPort-SDR": [ "\n PN5MhxactdN4sQ6ml1uxlSE7tWBYqwpK0ovGpzk+4BWmOiuytqB3IYfSHPAoEpgj6Yg9yXB+zC\n ZY83ZuitsfUQ==", "\n 1mtqET1IqLMgD4bvu3YfCp7deasNlzhafI9uFejruxfn2hGkrAldFiLI/rbCaSteFP6HO8k5HU\n HEx9Uo0Bo0Dg==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.72,390,1580803200\"; d=\"scan'208\";a=\"288879656\"", "From": "Adam Dybkowski <adamx.dybkowski@intel.com>", "To": "dev@dpdk.org,\n\tfiona.trahe@intel.com,\n\takhil.goyal@nxp.com", "Cc": "Adam Dybkowski <adamx.dybkowski@intel.com>", "Date": "Thu, 16 Apr 2020 14:24:38 +0200", "Message-Id": "<20200416122438.32319-2-adamx.dybkowski@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200416122438.32319-1-adamx.dybkowski@intel.com>", "References": "<20200414122426.2511-1-adamx.dybkowski@intel.com>\n <20200416122438.32319-1-adamx.dybkowski@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 1/1] crypto/qat: support plain SHA1..SHA512\n\thashes", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds support for plain SHA-1, SHA-224, SHA-256,\nSHA-384 and SHA-512 hashes to QAT PMD.\n\nSigned-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>\nAcked-by: Fiona Trahe <fiona.trahe@intel.com>\n---\n doc/guides/cryptodevs/features/qat.ini | 5 +\n doc/guides/cryptodevs/qat.rst | 5 +\n doc/guides/rel_notes/release_20_05.rst | 5 +\n drivers/crypto/qat/qat_sym_capabilities.h | 105 ++++++++++++++++++++\n drivers/crypto/qat/qat_sym_session.c | 113 ++++++++++++++++++++--\n drivers/crypto/qat/qat_sym_session.h | 1 +\n 6 files changed, 227 insertions(+), 7 deletions(-)", "diff": "diff --git a/doc/guides/cryptodevs/features/qat.ini b/doc/guides/cryptodevs/features/qat.ini\nindex 6e350eb81..a72241997 100644\n--- a/doc/guides/cryptodevs/features/qat.ini\n+++ b/doc/guides/cryptodevs/features/qat.ini\n@@ -44,10 +44,15 @@ ZUC EEA3 = Y\n [Auth]\n NULL = Y\n MD5 HMAC = Y\n+SHA1 = Y\n SHA1 HMAC = Y\n+SHA224 = Y\n SHA224 HMAC = Y\n+SHA256 = Y\n SHA256 HMAC = Y\n+SHA384 = Y\n SHA384 HMAC = Y\n+SHA512 = Y\n SHA512 HMAC = Y\n AES GMAC = Y\n SNOW3G UIA2 = Y\ndiff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst\nindex c79e686de..7e781b962 100644\n--- a/doc/guides/cryptodevs/qat.rst\n+++ b/doc/guides/cryptodevs/qat.rst\n@@ -52,10 +52,15 @@ Cipher algorithms:\n \n Hash algorithms:\n \n+* ``RTE_CRYPTO_AUTH_SHA1``\n * ``RTE_CRYPTO_AUTH_SHA1_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA224``\n * ``RTE_CRYPTO_AUTH_SHA224_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA256``\n * ``RTE_CRYPTO_AUTH_SHA256_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA384``\n * ``RTE_CRYPTO_AUTH_SHA384_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA512``\n * ``RTE_CRYPTO_AUTH_SHA512_HMAC``\n * ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``\n * ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``\ndiff --git a/doc/guides/rel_notes/release_20_05.rst b/doc/guides/rel_notes/release_20_05.rst\nindex 184967844..2e4966daf 100644\n--- a/doc/guides/rel_notes/release_20_05.rst\n+++ b/doc/guides/rel_notes/release_20_05.rst\n@@ -81,6 +81,11 @@ New Features\n by making use of the event device capabilities. The event mode currently supports\n only inline IPsec protocol offload.\n \n+* **Added plain SHA-1,224,256,384,512 support to QAT PMD.**\n+\n+ Added support for plain SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512 hashes\n+ to QAT PMD.\n+\n \n Removed Items\n -------------\ndiff --git a/drivers/crypto/qat/qat_sym_capabilities.h b/drivers/crypto/qat/qat_sym_capabilities.h\nindex 27e57aaaf..ff691ce35 100644\n--- a/drivers/crypto/qat/qat_sym_capabilities.h\n+++ b/drivers/crypto/qat/qat_sym_capabilities.h\n@@ -6,6 +6,111 @@\n #define _QAT_SYM_CAPABILITIES_H_\n \n #define QAT_BASE_GEN1_SYM_CAPABILITIES\t\t\t\t\t\\\n+\t{\t/* SHA1 */\t\t\t\t\t\t\\\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\t\t\t\\\n+\t\t{.sym = {\t\t\t\t\t\t\\\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\t\\\n+\t\t\t{.auth = {\t\t\t\t\t\\\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA1,\t\t\\\n+\t\t\t\t.block_size = 64,\t\t\t\\\n+\t\t\t\t.key_size = {\t\t\t\t\\\n+\t\t\t\t\t.min = 0,\t\t\t\\\n+\t\t\t\t\t.max = 0,\t\t\t\\\n+\t\t\t\t\t.increment = 0\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t\t.digest_size = {\t\t\t\\\n+\t\t\t\t\t.min = 1,\t\t\t\\\n+\t\t\t\t\t.max = 20,\t\t\t\\\n+\t\t\t\t\t.increment = 1\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t\t.iv_size = { 0 }\t\t\t\\\n+\t\t\t}, }\t\t\t\t\t\t\\\n+\t\t}, }\t\t\t\t\t\t\t\\\n+\t},\t\t\t\t\t\t\t\t\\\n+\t{\t/* SHA224 */\t\t\t\t\t\t\\\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\t\t\t\\\n+\t\t{.sym = {\t\t\t\t\t\t\\\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\t\\\n+\t\t\t{.auth = {\t\t\t\t\t\\\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA224,\t\t\\\n+\t\t\t\t.block_size = 64,\t\t\t\\\n+\t\t\t\t.key_size = {\t\t\t\t\\\n+\t\t\t\t\t.min = 0,\t\t\t\\\n+\t\t\t\t\t.max = 0,\t\t\t\\\n+\t\t\t\t\t.increment = 0\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t\t.digest_size = {\t\t\t\\\n+\t\t\t\t\t.min = 1,\t\t\t\\\n+\t\t\t\t\t.max = 28,\t\t\t\\\n+\t\t\t\t\t.increment = 1\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t\t.iv_size = { 0 }\t\t\t\\\n+\t\t\t}, }\t\t\t\t\t\t\\\n+\t\t}, }\t\t\t\t\t\t\t\\\n+\t},\t\t\t\t\t\t\t\t\\\n+\t{\t/* SHA256 */\t\t\t\t\t\t\\\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\t\t\t\\\n+\t\t{.sym = {\t\t\t\t\t\t\\\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\t\\\n+\t\t\t{.auth = {\t\t\t\t\t\\\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA256,\t\t\\\n+\t\t\t\t.block_size = 64,\t\t\t\\\n+\t\t\t\t.key_size = {\t\t\t\t\\\n+\t\t\t\t\t.min = 0,\t\t\t\\\n+\t\t\t\t\t.max = 0,\t\t\t\\\n+\t\t\t\t\t.increment = 0\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t\t.digest_size = {\t\t\t\\\n+\t\t\t\t\t.min = 1,\t\t\t\\\n+\t\t\t\t\t.max = 32,\t\t\t\\\n+\t\t\t\t\t.increment = 1\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t\t.iv_size = { 0 }\t\t\t\\\n+\t\t\t}, }\t\t\t\t\t\t\\\n+\t\t}, }\t\t\t\t\t\t\t\\\n+\t},\t\t\t\t\t\t\t\t\\\n+\t{\t/* SHA384 */\t\t\t\t\t\t\\\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\t\t\t\\\n+\t\t{.sym = {\t\t\t\t\t\t\\\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\t\\\n+\t\t\t{.auth = {\t\t\t\t\t\\\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA384,\t\t\\\n+\t\t\t\t.block_size = 128,\t\t\t\\\n+\t\t\t\t.key_size = {\t\t\t\t\\\n+\t\t\t\t\t.min = 0,\t\t\t\\\n+\t\t\t\t\t.max = 0,\t\t\t\\\n+\t\t\t\t\t.increment = 0\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t\t.digest_size = {\t\t\t\\\n+\t\t\t\t\t.min = 1,\t\t\t\\\n+\t\t\t\t\t.max = 48,\t\t\t\\\n+\t\t\t\t\t.increment = 1\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t\t.iv_size = { 0 }\t\t\t\\\n+\t\t\t}, }\t\t\t\t\t\t\\\n+\t\t}, }\t\t\t\t\t\t\t\\\n+\t},\t\t\t\t\t\t\t\t\\\n+\t{\t/* SHA512 */\t\t\t\t\t\t\\\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\t\t\t\\\n+\t\t{.sym = {\t\t\t\t\t\t\\\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\t\\\n+\t\t\t{.auth = {\t\t\t\t\t\\\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA512,\t\t\\\n+\t\t\t\t.block_size = 128,\t\t\t\\\n+\t\t\t\t.key_size = {\t\t\t\t\\\n+\t\t\t\t\t.min = 0,\t\t\t\\\n+\t\t\t\t\t.max = 0,\t\t\t\\\n+\t\t\t\t\t.increment = 0\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t\t.digest_size = {\t\t\t\\\n+\t\t\t\t\t.min = 1,\t\t\t\\\n+\t\t\t\t\t.max = 64,\t\t\t\\\n+\t\t\t\t\t.increment = 1\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t\t.iv_size = { 0 }\t\t\t\\\n+\t\t\t}, }\t\t\t\t\t\t\\\n+\t\t}, }\t\t\t\t\t\t\t\\\n+\t},\t\t\t\t\t\t\t\t\\\n \t{\t/* SHA1 HMAC */\t\t\t\t\t\t\\\n \t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\t\t\t\\\n \t\t{.sym = {\t\t\t\t\t\t\\\ndiff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c\nindex fd2cc382e..3727d564d 100644\n--- a/drivers/crypto/qat/qat_sym_session.c\n+++ b/drivers/crypto/qat/qat_sym_session.c\n@@ -19,6 +19,41 @@\n #include \"qat_sym_session.h\"\n #include \"qat_sym_pmd.h\"\n \n+/* SHA1 - 20 bytes - Initialiser state can be found in FIPS stds 180-2 */\n+static const uint8_t sha1InitialState[] = {\n+\t0x67, 0x45, 0x23, 0x01, 0xef, 0xcd, 0xab, 0x89, 0x98, 0xba,\n+\t0xdc, 0xfe, 0x10, 0x32, 0x54, 0x76, 0xc3, 0xd2, 0xe1, 0xf0};\n+\n+/* SHA 224 - 32 bytes - Initialiser state can be found in FIPS stds 180-2 */\n+static const uint8_t sha224InitialState[] = {\n+\t0xc1, 0x05, 0x9e, 0xd8, 0x36, 0x7c, 0xd5, 0x07, 0x30, 0x70, 0xdd,\n+\t0x17, 0xf7, 0x0e, 0x59, 0x39, 0xff, 0xc0, 0x0b, 0x31, 0x68, 0x58,\n+\t0x15, 0x11, 0x64, 0xf9, 0x8f, 0xa7, 0xbe, 0xfa, 0x4f, 0xa4};\n+\n+/* SHA 256 - 32 bytes - Initialiser state can be found in FIPS stds 180-2 */\n+static const uint8_t sha256InitialState[] = {\n+\t0x6a, 0x09, 0xe6, 0x67, 0xbb, 0x67, 0xae, 0x85, 0x3c, 0x6e, 0xf3,\n+\t0x72, 0xa5, 0x4f, 0xf5, 0x3a, 0x51, 0x0e, 0x52, 0x7f, 0x9b, 0x05,\n+\t0x68, 0x8c, 0x1f, 0x83, 0xd9, 0xab, 0x5b, 0xe0, 0xcd, 0x19};\n+\n+/* SHA 384 - 64 bytes - Initialiser state can be found in FIPS stds 180-2 */\n+static const uint8_t sha384InitialState[] = {\n+\t0xcb, 0xbb, 0x9d, 0x5d, 0xc1, 0x05, 0x9e, 0xd8, 0x62, 0x9a, 0x29,\n+\t0x2a, 0x36, 0x7c, 0xd5, 0x07, 0x91, 0x59, 0x01, 0x5a, 0x30, 0x70,\n+\t0xdd, 0x17, 0x15, 0x2f, 0xec, 0xd8, 0xf7, 0x0e, 0x59, 0x39, 0x67,\n+\t0x33, 0x26, 0x67, 0xff, 0xc0, 0x0b, 0x31, 0x8e, 0xb4, 0x4a, 0x87,\n+\t0x68, 0x58, 0x15, 0x11, 0xdb, 0x0c, 0x2e, 0x0d, 0x64, 0xf9, 0x8f,\n+\t0xa7, 0x47, 0xb5, 0x48, 0x1d, 0xbe, 0xfa, 0x4f, 0xa4};\n+\n+/* SHA 512 - 64 bytes - Initialiser state can be found in FIPS stds 180-2 */\n+static const uint8_t sha512InitialState[] = {\n+\t0x6a, 0x09, 0xe6, 0x67, 0xf3, 0xbc, 0xc9, 0x08, 0xbb, 0x67, 0xae,\n+\t0x85, 0x84, 0xca, 0xa7, 0x3b, 0x3c, 0x6e, 0xf3, 0x72, 0xfe, 0x94,\n+\t0xf8, 0x2b, 0xa5, 0x4f, 0xf5, 0x3a, 0x5f, 0x1d, 0x36, 0xf1, 0x51,\n+\t0x0e, 0x52, 0x7f, 0xad, 0xe6, 0x82, 0xd1, 0x9b, 0x05, 0x68, 0x8c,\n+\t0x2b, 0x3e, 0x6c, 0x1f, 0x1f, 0x83, 0xd9, 0xab, 0xfb, 0x41, 0xbd,\n+\t0x6b, 0x5b, 0xe0, 0xcd, 0x19, 0x13, 0x7e, 0x21, 0x79};\n+\n /** Frees a context previously created\n * Depends on openssl libcrypto\n */\n@@ -665,8 +700,29 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \n \tsession->auth_iv.offset = auth_xform->iv.offset;\n \tsession->auth_iv.length = auth_xform->iv.length;\n+\tsession->auth_mode = ICP_QAT_HW_AUTH_MODE1;\n \n \tswitch (auth_xform->algo) {\n+\tcase RTE_CRYPTO_AUTH_SHA1:\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;\n+\t\tsession->auth_mode = ICP_QAT_HW_AUTH_MODE0;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA224:\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;\n+\t\tsession->auth_mode = ICP_QAT_HW_AUTH_MODE0;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA256:\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;\n+\t\tsession->auth_mode = ICP_QAT_HW_AUTH_MODE0;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA384:\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;\n+\t\tsession->auth_mode = ICP_QAT_HW_AUTH_MODE0;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA512:\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;\n+\t\tsession->auth_mode = ICP_QAT_HW_AUTH_MODE0;\n+\t\tbreak;\n \tcase RTE_CRYPTO_AUTH_SHA1_HMAC:\n \t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;\n \t\tbreak;\n@@ -722,11 +778,6 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \t\t}\n \t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3;\n \t\tbreak;\n-\tcase RTE_CRYPTO_AUTH_SHA1:\n-\tcase RTE_CRYPTO_AUTH_SHA256:\n-\tcase RTE_CRYPTO_AUTH_SHA512:\n-\tcase RTE_CRYPTO_AUTH_SHA224:\n-\tcase RTE_CRYPTO_AUTH_SHA384:\n \tcase RTE_CRYPTO_AUTH_MD5:\n \tcase RTE_CRYPTO_AUTH_AES_CBC_MAC:\n \t\tQAT_LOG(ERR, \"Crypto: Unsupported hash alg %u\",\n@@ -811,6 +862,8 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,\n \tsession->cipher_iv.offset = xform->aead.iv.offset;\n \tsession->cipher_iv.length = xform->aead.iv.length;\n \n+\tsession->auth_mode = ICP_QAT_HW_AUTH_MODE1;\n+\n \tswitch (aead_xform->algo) {\n \tcase RTE_CRYPTO_AEAD_AES_GCM:\n \t\tif (qat_sym_validate_aes_key(aead_xform->key.length,\n@@ -1661,10 +1714,11 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,\n \thash = (struct icp_qat_hw_auth_setup *)cdesc->cd_cur_ptr;\n \thash->auth_config.reserved = 0;\n \thash->auth_config.config =\n-\t\t\tICP_QAT_HW_AUTH_CONFIG_BUILD(ICP_QAT_HW_AUTH_MODE1,\n+\t\t\tICP_QAT_HW_AUTH_CONFIG_BUILD(cdesc->auth_mode,\n \t\t\t\tcdesc->qat_hash_alg, digestsize);\n \n-\tif (cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2\n+\tif (cdesc->auth_mode == ICP_QAT_HW_AUTH_MODE0\n+\t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2\n \t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9\n \t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3\n \t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC\n@@ -1687,6 +1741,15 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,\n \t */\n \tswitch (cdesc->qat_hash_alg) {\n \tcase ICP_QAT_HW_AUTH_ALGO_SHA1:\n+\t\tif (cdesc->auth_mode == ICP_QAT_HW_AUTH_MODE0) {\n+\t\t\t/* Plain SHA-1 */\n+\t\t\trte_memcpy(cdesc->cd_cur_ptr, sha1InitialState,\n+\t\t\t\t\tsizeof(sha1InitialState));\n+\t\t\tstate1_size = qat_hash_get_state1_size(\n+\t\t\t\t\tcdesc->qat_hash_alg);\n+\t\t\tbreak;\n+\t\t}\n+\t\t/* SHA-1 HMAC */\n \t\tif (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA1, authkey,\n \t\t\tauthkeylen, cdesc->cd_cur_ptr, &state1_size,\n \t\t\tcdesc->aes_cmac)) {\n@@ -1696,6 +1759,15 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,\n \t\tstate2_size = RTE_ALIGN_CEIL(ICP_QAT_HW_SHA1_STATE2_SZ, 8);\n \t\tbreak;\n \tcase ICP_QAT_HW_AUTH_ALGO_SHA224:\n+\t\tif (cdesc->auth_mode == ICP_QAT_HW_AUTH_MODE0) {\n+\t\t\t/* Plain SHA-224 */\n+\t\t\trte_memcpy(cdesc->cd_cur_ptr, sha224InitialState,\n+\t\t\t\t\tsizeof(sha224InitialState));\n+\t\t\tstate1_size = qat_hash_get_state1_size(\n+\t\t\t\t\tcdesc->qat_hash_alg);\n+\t\t\tbreak;\n+\t\t}\n+\t\t/* SHA-224 HMAC */\n \t\tif (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA224, authkey,\n \t\t\tauthkeylen, cdesc->cd_cur_ptr, &state1_size,\n \t\t\tcdesc->aes_cmac)) {\n@@ -1705,6 +1777,15 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,\n \t\tstate2_size = ICP_QAT_HW_SHA224_STATE2_SZ;\n \t\tbreak;\n \tcase ICP_QAT_HW_AUTH_ALGO_SHA256:\n+\t\tif (cdesc->auth_mode == ICP_QAT_HW_AUTH_MODE0) {\n+\t\t\t/* Plain SHA-256 */\n+\t\t\trte_memcpy(cdesc->cd_cur_ptr, sha256InitialState,\n+\t\t\t\t\tsizeof(sha256InitialState));\n+\t\t\tstate1_size = qat_hash_get_state1_size(\n+\t\t\t\t\tcdesc->qat_hash_alg);\n+\t\t\tbreak;\n+\t\t}\n+\t\t/* SHA-256 HMAC */\n \t\tif (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA256, authkey,\n \t\t\tauthkeylen, cdesc->cd_cur_ptr,\t&state1_size,\n \t\t\tcdesc->aes_cmac)) {\n@@ -1714,6 +1795,15 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,\n \t\tstate2_size = ICP_QAT_HW_SHA256_STATE2_SZ;\n \t\tbreak;\n \tcase ICP_QAT_HW_AUTH_ALGO_SHA384:\n+\t\tif (cdesc->auth_mode == ICP_QAT_HW_AUTH_MODE0) {\n+\t\t\t/* Plain SHA-384 */\n+\t\t\trte_memcpy(cdesc->cd_cur_ptr, sha384InitialState,\n+\t\t\t\t\tsizeof(sha384InitialState));\n+\t\t\tstate1_size = qat_hash_get_state1_size(\n+\t\t\t\t\tcdesc->qat_hash_alg);\n+\t\t\tbreak;\n+\t\t}\n+\t\t/* SHA-384 HMAC */\n \t\tif (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA384, authkey,\n \t\t\tauthkeylen, cdesc->cd_cur_ptr, &state1_size,\n \t\t\tcdesc->aes_cmac)) {\n@@ -1723,6 +1813,15 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,\n \t\tstate2_size = ICP_QAT_HW_SHA384_STATE2_SZ;\n \t\tbreak;\n \tcase ICP_QAT_HW_AUTH_ALGO_SHA512:\n+\t\tif (cdesc->auth_mode == ICP_QAT_HW_AUTH_MODE0) {\n+\t\t\t/* Plain SHA-512 */\n+\t\t\trte_memcpy(cdesc->cd_cur_ptr, sha512InitialState,\n+\t\t\t\t\tsizeof(sha512InitialState));\n+\t\t\tstate1_size = qat_hash_get_state1_size(\n+\t\t\t\t\tcdesc->qat_hash_alg);\n+\t\t\tbreak;\n+\t\t}\n+\t\t/* SHA-512 HMAC */\n \t\tif (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA512, authkey,\n \t\t\tauthkeylen, cdesc->cd_cur_ptr,\t&state1_size,\n \t\t\tcdesc->aes_cmac)) {\ndiff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h\nindex 5a01c8179..e6538f627 100644\n--- a/drivers/crypto/qat/qat_sym_session.h\n+++ b/drivers/crypto/qat/qat_sym_session.h\n@@ -67,6 +67,7 @@ struct qat_sym_session {\n \tenum icp_qat_hw_cipher_mode qat_mode;\n \tenum icp_qat_hw_auth_algo qat_hash_alg;\n \tenum icp_qat_hw_auth_op auth_op;\n+\tenum icp_qat_hw_auth_mode auth_mode;\n \tvoid *bpi_ctx;\n \tstruct qat_sym_cd cd;\n \tuint8_t *cd_cur_ptr;\n", "prefixes": [ "v2", "1/1" ] }