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{
    "id": 68564,
    "url": "http://patches.dpdk.org/api/patches/68564/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1586962156-11179-8-git-send-email-venkatkumar.duvvuru@broadcom.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1586962156-11179-8-git-send-email-venkatkumar.duvvuru@broadcom.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1586962156-11179-8-git-send-email-venkatkumar.duvvuru@broadcom.com",
    "date": "2020-04-15T14:49:12",
    "name": "[07/11] net/bnxt: use hashing for flow template matching",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "bdcbe5a9622f9a7c59a0193ebb24491cc90954b7",
    "submitter": {
        "id": 1635,
        "url": "http://patches.dpdk.org/api/people/1635/?format=api",
        "name": "Venkat Duvvuru",
        "email": "venkatkumar.duvvuru@broadcom.com"
    },
    "delegate": {
        "id": 1766,
        "url": "http://patches.dpdk.org/api/users/1766/?format=api",
        "username": "ajitkhaparde",
        "first_name": "Ajit",
        "last_name": "Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1586962156-11179-8-git-send-email-venkatkumar.duvvuru@broadcom.com/mbox/",
    "series": [
        {
            "id": 9397,
            "url": "http://patches.dpdk.org/api/series/9397/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=9397",
            "date": "2020-04-15T14:49:05",
            "name": "enhancements to host based flow table management",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/9397/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/68564/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/68564/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
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        "X-Received": "by 2002:a62:3147:: with SMTP id x68mr28078484pfx.62.1586962241655;\n Wed, 15 Apr 2020 07:50:41 -0700 (PDT)",
        "From": "Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>",
        "To": "dev@dpdk.org",
        "Cc": "Kishore Padmanabha <kishore.padmanabha@broadcom.com>,\n Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>",
        "Date": "Wed, 15 Apr 2020 20:19:12 +0530",
        "Message-Id": "\n <1586962156-11179-8-git-send-email-venkatkumar.duvvuru@broadcom.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "\n <1586962156-11179-1-git-send-email-venkatkumar.duvvuru@broadcom.com>",
        "References": "\n <1586962156-11179-1-git-send-email-venkatkumar.duvvuru@broadcom.com>",
        "Subject": "[dpdk-dev] [PATCH 07/11] net/bnxt: use hashing for flow template\n\tmatching",
        "X-BeenThere": "dev@dpdk.org",
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    },
    "content": "From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>\n\nCurrently, all the flow templates are sequentially searched to find out\nwhether there is a matching template for the incoming RTE_FLOW offload\nrequest. As sequential search will have performance concerns, this\npatch will address it by using hash algorithm to find out the flow\ntemplate. This change resulted in creation of computed fields to\nremove the fields that do not participate in the hash calculations.\nThe field bitmap is created for this purpose.\n\nReviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>\nSigned-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>\nSigned-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>\n---\n drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c         |  23 +-\n drivers/net/bnxt/tf_ulp/ulp_mapper.c            |   4 +-\n drivers/net/bnxt/tf_ulp/ulp_matcher.c           | 214 +++++++----------\n drivers/net/bnxt/tf_ulp/ulp_rte_parser.c        | 282 ++++++++++++----------\n drivers/net/bnxt/tf_ulp/ulp_rte_parser.h        |   4 +\n drivers/net/bnxt/tf_ulp/ulp_template_db.c       | 307 ++++++++++--------------\n drivers/net/bnxt/tf_ulp/ulp_template_db.h       | 280 +++++++++++++--------\n drivers/net/bnxt/tf_ulp/ulp_template_field_db.h | 171 ++++---------\n drivers/net/bnxt/tf_ulp/ulp_template_struct.h   |  50 ++--\n drivers/net/bnxt/tf_ulp/ulp_utils.c             |  33 +++\n drivers/net/bnxt/tf_ulp/ulp_utils.h             |  17 +-\n 11 files changed, 686 insertions(+), 699 deletions(-)",
    "diff": "diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c\nindex 9326401..7f7aa24 100644\n--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c\n+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c\n@@ -61,11 +61,11 @@ bnxt_ulp_flow_validate_args(const struct rte_flow_attr *attr,\n \n /* Function to create the rte flow. */\n static struct rte_flow *\n-bnxt_ulp_flow_create(struct rte_eth_dev\t\t\t*dev,\n-\t\t     const struct rte_flow_attr\t\t*attr,\n-\t\t     const struct rte_flow_item\t\tpattern[],\n-\t\t     const struct rte_flow_action\tactions[],\n-\t\t     struct rte_flow_error\t\t*error)\n+bnxt_ulp_flow_create(struct rte_eth_dev *dev,\n+\t\t     const struct rte_flow_attr *attr,\n+\t\t     const struct rte_flow_item pattern[],\n+\t\t     const struct rte_flow_action actions[],\n+\t\t     struct rte_flow_error *error)\n {\n \tstruct bnxt_ulp_mapper_create_parms mapper_cparms = { 0 };\n \tstruct ulp_rte_parser_params params;\n@@ -73,8 +73,6 @@ bnxt_ulp_flow_create(struct rte_eth_dev\t\t\t*dev,\n \tuint32_t class_id, act_tmpl;\n \tstruct rte_flow *flow_id;\n \tuint32_t fid;\n-\tuint8_t\t*buffer;\n-\tuint32_t vnic;\n \tint ret;\n \n \tif (bnxt_ulp_flow_validate_args(attr,\n@@ -97,14 +95,9 @@ bnxt_ulp_flow_create(struct rte_eth_dev\t\t\t*dev,\n \t\tparams.dir = ULP_DIR_EGRESS;\n \n \t/* copy the device port id and direction for further processing */\n-\tbuffer = params.hdr_field[BNXT_ULP_HDR_FIELD_SVIF_INDEX].spec;\n-\trte_memcpy(buffer, &dev->data->port_id, sizeof(uint16_t));\n-\n-\t/* Set the implicit vnic in the action property */\n-\tvnic = (uint32_t)bnxt_get_vnic_id(dev->data->port_id);\n-\tvnic = htonl(vnic);\n-\trte_memcpy(&params.act_prop.act_details[BNXT_ULP_ACT_PROP_IDX_VNIC],\n-\t\t   &vnic, BNXT_ULP_ACT_PROP_SZ_VNIC);\n+\tULP_UTIL_CHF_IDX_WR(&params, BNXT_ULP_CHF_IDX_INCOMING_IF,\n+\t\t\t    dev->data->port_id);\n+\tULP_UTIL_CHF_IDX_WR(&params, BNXT_ULP_CHF_IDX_DIRECTION, params.dir);\n \n \t/* Parse the rte flow pattern */\n \tret = bnxt_ulp_rte_parser_hdr_parse(pattern, &params);\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c\nindex dd44938..b8907b6 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c\n@@ -357,7 +357,7 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms,\n \t(void)tf_free_identifier(tfp, &free_parms);\n \n \tBNXT_TF_DBG(ERR, \"Ident process failed for %s:%s\\n\",\n-\t\t    ident->name,\n+\t\t    ident->description,\n \t\t    (tbl->direction == TF_DIR_RX) ? \"RX\" : \"TX\");\n \treturn rc;\n }\n@@ -405,7 +405,7 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms,\n \t\t\treturn -EINVAL;\n \t\t}\n \t\tbreak;\n-\tcase BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP_SZ:\n+\tcase BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ:\n \t\tif (!ulp_operand_read(fld->result_operand,\n \t\t\t\t      (uint8_t *)&idx, sizeof(uint16_t))) {\n \t\t\tBNXT_TF_DBG(ERR, \"%s operand read failed\\n\", name);\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.c b/drivers/net/bnxt/tf_ulp/ulp_matcher.c\nindex e04bfa0..e5f23ef 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_matcher.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.c\n@@ -6,40 +6,32 @@\n #include \"ulp_matcher.h\"\n #include \"ulp_utils.h\"\n \n-/* Utility function to check if bitmap is zero */\n-static inline\n-int ulp_field_mask_is_zero(uint8_t *bitmap, uint32_t size)\n+/* Utility function to calculate the class matcher hash */\n+static uint32_t\n+ulp_matcher_class_hash_calculate(uint64_t hi_sig, uint64_t lo_sig)\n {\n-\twhile (size-- > 0) {\n-\t\tif (*bitmap != 0)\n-\t\t\treturn 0;\n-\t\tbitmap++;\n-\t}\n-\treturn 1;\n-}\n+\tuint64_t hash;\n \n-/* Utility function to check if bitmap is all ones */\n-static inline int\n-ulp_field_mask_is_ones(uint8_t *bitmap, uint32_t size)\n-{\n-\twhile (size-- > 0) {\n-\t\tif (*bitmap != 0xFF)\n-\t\t\treturn 0;\n-\t\tbitmap++;\n-\t}\n-\treturn 1;\n+\thi_sig |= ((hi_sig % BNXT_ULP_CLASS_HID_HIGH_PRIME) <<\n+\t\t   BNXT_ULP_CLASS_HID_SHFTL);\n+\tlo_sig |= ((lo_sig % BNXT_ULP_CLASS_HID_LOW_PRIME) <<\n+\t\t   (BNXT_ULP_CLASS_HID_SHFTL + 2));\n+\thash = hi_sig ^ lo_sig;\n+\thash = (hash >> BNXT_ULP_CLASS_HID_SHFTR) & BNXT_ULP_CLASS_HID_MASK;\n+\treturn (uint32_t)hash;\n }\n \n-/* Utility function to check if bitmap is non zero */\n-static inline int\n-ulp_field_mask_notzero(uint8_t *bitmap, uint32_t size)\n+/* Utility function to calculate the action matcher hash */\n+static uint32_t\n+ulp_matcher_action_hash_calculate(uint64_t hi_sig)\n {\n-\twhile (size-- > 0) {\n-\t\tif (*bitmap != 0)\n-\t\t\treturn 1;\n-\t\tbitmap++;\n-\t}\n-\treturn 0;\n+\tuint64_t hash;\n+\n+\thi_sig |= ((hi_sig % BNXT_ULP_ACT_HID_HIGH_PRIME) <<\n+\t\t   BNXT_ULP_ACT_HID_SHFTL);\n+\thash = hi_sig;\n+\thash = (hash >> BNXT_ULP_ACT_HID_SHFTR) & BNXT_ULP_ACT_HID_MASK;\n+\treturn (uint32_t)hash;\n }\n \n /* Utility function to mask the computed and internal proto headers. */\n@@ -56,10 +48,6 @@ ulp_matcher_hdr_fields_normalize(struct ulp_rte_hdr_bitmap *hdr1,\n \tULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_OI_VLAN);\n \tULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_IO_VLAN);\n \tULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_II_VLAN);\n-\tULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_O_L3);\n-\tULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_O_L4);\n-\tULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_I_L3);\n-\tULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_I_L4);\n }\n \n /*\n@@ -70,82 +58,55 @@ int32_t\n ulp_matcher_pattern_match(struct ulp_rte_parser_params *params,\n \t\t\t  uint32_t *class_id)\n {\n-\tstruct bnxt_ulp_header_match_info\t*sel_hdr_match;\n-\tuint32_t\t\t\t\thdr_num, idx, jdx;\n-\tuint32_t\t\t\t\tmatch = 0;\n-\tstruct ulp_rte_hdr_bitmap\t\thdr_bitmap_masked;\n-\tuint32_t\t\t\t\tstart_idx;\n-\tstruct ulp_rte_hdr_field\t\t*m_field;\n-\tstruct bnxt_ulp_matcher_field_info\t*sf;\n-\tstruct ulp_rte_hdr_bitmap *hdr_bitmap = &params->hdr_bitmap;\n-\tstruct ulp_rte_act_bitmap *act_bitmap = &params->act_bitmap;\n-\tstruct ulp_rte_hdr_field *hdr_field = params->hdr_field;\n-\n-\t/* Select the ingress or egress template to match against */\n-\tif (params->dir == ULP_DIR_INGRESS) {\n-\t\tsel_hdr_match = ulp_ingress_hdr_match_list;\n-\t\thdr_num = BNXT_ULP_INGRESS_HDR_MATCH_SZ;\n+\tstruct ulp_rte_hdr_bitmap hdr_bitmap_masked;\n+\tstruct bnxt_ulp_class_match_info *class_match;\n+\tuint32_t class_hid;\n+\tuint8_t vf_to_vf;\n+\tuint16_t tmpl_id;\n+\n+\t/* Remove the hdr bit maps that are internal or computed */\n+\tulp_matcher_hdr_fields_normalize(&params->hdr_bitmap,\n+\t\t\t\t\t &hdr_bitmap_masked);\n+\n+\t/* determine vf to vf flow */\n+\tif (params->dir == ULP_DIR_EGRESS &&\n+\t    ULP_BITMAP_ISSET(params->act_bitmap.bits,\n+\t\t\t     BNXT_ULP_ACTION_BIT_VNIC)) {\n+\t\tvf_to_vf = 1;\n \t} else {\n-\t\tsel_hdr_match = ulp_egress_hdr_match_list;\n-\t\thdr_num = BNXT_ULP_EGRESS_HDR_MATCH_SZ;\n+\t\tvf_to_vf = 0;\n \t}\n \n-\t/* Remove the hdr bit maps that are internal or computed */\n-\tulp_matcher_hdr_fields_normalize(hdr_bitmap, &hdr_bitmap_masked);\n-\n-\t/* Loop through the list of class templates to find the match */\n-\tfor (idx = 0; idx < hdr_num; idx++, sel_hdr_match++) {\n-\t\tif (ULP_BITSET_CMP(&sel_hdr_match->hdr_bitmap,\n-\t\t\t\t   &hdr_bitmap_masked)) {\n-\t\t\t/* no match found */\n-\t\t\tBNXT_TF_DBG(DEBUG, \"Pattern Match failed template=%d\\n\",\n-\t\t\t\t    idx);\n-\t\t\tcontinue;\n-\t\t}\n-\t\tmatch = ULP_BITMAP_ISSET(act_bitmap->bits,\n-\t\t\t\t\t BNXT_ULP_ACTION_BIT_VNIC);\n-\t\tif (match != sel_hdr_match->act_vnic) {\n-\t\t\t/* no match found */\n-\t\t\tBNXT_TF_DBG(DEBUG, \"Vnic Match failed template=%d\\n\",\n-\t\t\t\t    idx);\n-\t\t\tcontinue;\n-\t\t} else {\n-\t\t\tmatch = 1;\n-\t\t}\n-\n-\t\t/* Found a matching hdr bitmap, match the fields next */\n-\t\tstart_idx = sel_hdr_match->start_idx;\n-\t\tfor (jdx = 0; jdx < sel_hdr_match->num_entries; jdx++) {\n-\t\t\tm_field = &hdr_field[jdx + BNXT_ULP_HDR_FIELD_LAST - 1];\n-\t\t\tsf = &ulp_field_match[start_idx + jdx];\n-\t\t\tswitch (sf->mask_opcode) {\n-\t\t\tcase BNXT_ULP_FMF_MASK_ANY:\n-\t\t\t\tmatch &= ulp_field_mask_is_zero(m_field->mask,\n-\t\t\t\t\t\t\t\tm_field->size);\n-\t\t\t\tbreak;\n-\t\t\tcase BNXT_ULP_FMF_MASK_EXACT:\n-\t\t\t\tmatch &= ulp_field_mask_is_ones(m_field->mask,\n-\t\t\t\t\t\t\t\tm_field->size);\n-\t\t\t\tbreak;\n-\t\t\tcase BNXT_ULP_FMF_MASK_WILDCARD:\n-\t\t\t\tmatch &= ulp_field_mask_notzero(m_field->mask,\n-\t\t\t\t\t\t\t\tm_field->size);\n-\t\t\t\tbreak;\n-\t\t\tcase BNXT_ULP_FMF_MASK_IGNORE:\n-\t\t\tdefault:\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tif (!match)\n-\t\t\t\tbreak;\n-\t\t}\n-\t\tif (match) {\n-\t\t\tBNXT_TF_DBG(DEBUG,\n-\t\t\t\t    \"Found matching pattern template %d\\n\",\n-\t\t\t\t    sel_hdr_match->class_tmpl_id);\n-\t\t\t*class_id = sel_hdr_match->class_tmpl_id;\n-\t\t\treturn BNXT_TF_RC_SUCCESS;\n-\t\t}\n+\t/* calculate the hash of the given flow */\n+\tclass_hid = ulp_matcher_class_hash_calculate(hdr_bitmap_masked.bits,\n+\t\t\t\t\t\t     params->fld_bitmap.bits);\n+\n+\t/* validate the calculate hash values */\n+\tif (class_hid >= BNXT_ULP_CLASS_SIG_TBL_MAX_SZ)\n+\t\tgoto error;\n+\ttmpl_id = ulp_class_sig_tbl[class_hid];\n+\tif (!tmpl_id)\n+\t\tgoto error;\n+\n+\tclass_match = &ulp_class_match_list[tmpl_id];\n+\tif (ULP_BITMAP_CMP(&hdr_bitmap_masked, &class_match->hdr_sig)) {\n+\t\tBNXT_TF_DBG(DEBUG, \"Proto Header does not match\\n\");\n+\t\tgoto error;\n+\t}\n+\tif (ULP_BITMAP_CMP(&params->fld_bitmap, &class_match->field_sig)) {\n+\t\tBNXT_TF_DBG(DEBUG, \"Field signature does not match\\n\");\n+\t\tgoto error;\n \t}\n+\tif (vf_to_vf != class_match->act_vnic) {\n+\t\tBNXT_TF_DBG(DEBUG, \"Vnic Match failed\\n\");\n+\t\tgoto error;\n+\t}\n+\tBNXT_TF_DBG(DEBUG, \"Found matching pattern template %d\\n\",\n+\t\t    class_match->class_tid);\n+\t*class_id = class_match->class_tid;\n+\treturn BNXT_TF_RC_SUCCESS;\n+\n+error:\n \tBNXT_TF_DBG(DEBUG, \"Did not find any matching template\\n\");\n \t*class_id = 0;\n \treturn BNXT_TF_RC_ERROR;\n@@ -159,29 +120,30 @@ int32_t\n ulp_matcher_action_match(struct ulp_rte_parser_params *params,\n \t\t\t uint32_t *act_id)\n {\n-\tstruct bnxt_ulp_action_match_info\t*sel_act_match;\n-\tuint32_t\t\t\t\tact_num, idx;\n-\tstruct ulp_rte_act_bitmap *act_bitmap = &params->act_bitmap;\n-\n-\t/* Select the ingress or egress template to match against */\n-\tif (params->dir == ULP_DIR_INGRESS) {\n-\t\tsel_act_match = ulp_ingress_act_match_list;\n-\t\tact_num = BNXT_ULP_INGRESS_ACT_MATCH_SZ;\n-\t} else {\n-\t\tsel_act_match = ulp_egress_act_match_list;\n-\t\tact_num = BNXT_ULP_EGRESS_ACT_MATCH_SZ;\n-\t}\n+\tuint32_t act_hid;\n+\tuint16_t tmpl_id;\n+\tstruct bnxt_ulp_act_match_info *act_match;\n+\n+\t/* calculate the hash of the given flow action */\n+\tact_hid = ulp_matcher_action_hash_calculate(params->act_bitmap.bits);\n \n-\t/* Loop through the list of action templates to find the match */\n-\tfor (idx = 0; idx < act_num; idx++, sel_act_match++) {\n-\t\tif (!ULP_BITSET_CMP(&sel_act_match->act_bitmap,\n-\t\t\t\t    act_bitmap)) {\n-\t\t\t*act_id = sel_act_match->act_tmpl_id;\n-\t\t\tBNXT_TF_DBG(DEBUG, \"Found matching act template %u\\n\",\n-\t\t\t\t    *act_id);\n-\t\t\treturn BNXT_TF_RC_SUCCESS;\n-\t\t}\n+\t/* validate the calculate hash values */\n+\tif (act_hid >= BNXT_ULP_ACT_SIG_TBL_MAX_SZ)\n+\t\tgoto error;\n+\ttmpl_id = ulp_act_sig_tbl[act_hid];\n+\tif (!tmpl_id)\n+\t\tgoto error;\n+\n+\tact_match = &ulp_act_match_list[tmpl_id];\n+\tif (ULP_BITMAP_CMP(&params->act_bitmap, &act_match->act_sig)) {\n+\t\tBNXT_TF_DBG(DEBUG, \"Action Header does not match\\n\");\n+\t\tgoto error;\n \t}\n+\t*act_id = act_match->act_tid;\n+\tBNXT_TF_DBG(DEBUG, \"Found matching action template %u\\n\", *act_id);\n+\treturn BNXT_TF_RC_SUCCESS;\n+\n+error:\n \tBNXT_TF_DBG(DEBUG, \"Did not find any matching action template\\n\");\n \t*act_id = 0;\n \treturn BNXT_TF_RC_ERROR;\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c\nindex 2980e03..873f864 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c\n@@ -11,25 +11,6 @@\n #include \"ulp_utils.h\"\n #include \"tfp.h\"\n \n-/* Inline Func to read integer that is stored in big endian format */\n-static inline void ulp_util_field_int_read(uint8_t *buffer,\n-\t\t\t\t\t   uint32_t *val)\n-{\n-\tuint32_t temp_val;\n-\n-\tmemcpy(&temp_val, buffer, sizeof(uint32_t));\n-\t*val = rte_be_to_cpu_32(temp_val);\n-}\n-\n-/* Inline Func to write integer that is stored in big endian format */\n-static inline void ulp_util_field_int_write(uint8_t *buffer,\n-\t\t\t\t\t    uint32_t val)\n-{\n-\tuint32_t temp_val = rte_cpu_to_be_32(val);\n-\n-\tmemcpy(buffer, &temp_val, sizeof(uint32_t));\n-}\n-\n /* Utility function to skip the void items. */\n static inline int32_t\n ulp_rte_item_skip_void(const struct rte_flow_item **item, uint32_t increment)\n@@ -45,6 +26,25 @@ ulp_rte_item_skip_void(const struct rte_flow_item **item, uint32_t increment)\n \treturn 0;\n }\n \n+/* Utility function to update the field_bitmap */\n+static void\n+ulp_rte_parser_field_bitmap_update(struct ulp_rte_parser_params *params,\n+\t\t\t\t   uint32_t idx)\n+{\n+\tstruct ulp_rte_hdr_field *field;\n+\n+\tfield = &params->hdr_field[idx];\n+\tif (ulp_bitmap_notzero(field->mask, field->size)) {\n+\t\tULP_INDEX_BITMAP_SET(params->fld_bitmap.bits, idx);\n+\t\t/* Not exact match */\n+\t\tif (!ulp_bitmap_is_ones(field->mask, field->size))\n+\t\t\tULP_BITMAP_SET(params->fld_bitmap.bits,\n+\t\t\t\t       BNXT_ULP_MATCH_TYPE_BITMASK_WM);\n+\t} else {\n+\t\tULP_INDEX_BITMAP_RESET(params->fld_bitmap.bits, idx);\n+\t}\n+}\n+\n /* Utility function to copy field spec items */\n static struct ulp_rte_hdr_field *\n ulp_rte_parser_fld_copy(struct ulp_rte_hdr_field *field,\n@@ -64,9 +64,10 @@ ulp_rte_prsr_mask_copy(struct ulp_rte_parser_params *params,\n \t\t       const void *buffer,\n \t\t       uint32_t size)\n {\n-\tstruct ulp_rte_hdr_field\t*field = &params->hdr_field[*idx];\n+\tstruct ulp_rte_hdr_field *field = &params->hdr_field[*idx];\n \n \tmemcpy(field->mask, buffer, size);\n+\tulp_rte_parser_field_bitmap_update(params, *idx);\n \t*idx = *idx + 1;\n }\n \n@@ -81,7 +82,11 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[],\n \tconst struct rte_flow_item *item = pattern;\n \tstruct bnxt_ulp_rte_hdr_info *hdr_info;\n \n-\tparams->field_idx = BNXT_ULP_HDR_FIELD_LAST;\n+\tparams->field_idx = BNXT_ULP_PROTO_HDR_SVIF_NUM;\n+\tif (params->dir == ULP_DIR_EGRESS)\n+\t\tULP_BITMAP_SET(params->hdr_bitmap.bits,\n+\t\t\t       BNXT_ULP_FLOW_DIR_BITMASK_EGR);\n+\n \t/* Parse all the items in the pattern */\n \twhile (item && item->type != RTE_FLOW_ITEM_TYPE_END) {\n \t\t/* get the header information from the flow_hdr_info table */\n@@ -141,6 +146,8 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],\n \t\t}\n \t\taction_item++;\n \t}\n+\t/* update the implied VNIC */\n+\tulp_rte_parser_vnic_process(params);\n \treturn BNXT_TF_RC_SUCCESS;\n }\n \n@@ -153,69 +160,78 @@ ulp_rte_parser_svif_set(struct ulp_rte_parser_params *params,\n {\n \tuint16_t port_id = svif;\n \tuint32_t dir = 0;\n+\tstruct ulp_rte_hdr_field *hdr_field;\n \n \tif (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_SVIF)) {\n \t\tBNXT_TF_DBG(ERR,\n-\t\t\t    \"SVIF already set,\"\n-\t\t\t    \" multiple sources not supported\\n\");\n+\t\t\t    \"SVIF already set,multiple source not support'd\\n\");\n \t\treturn BNXT_TF_RC_ERROR;\n \t}\n \n-\t/* Update the hdr_bitmap with BNXT_ULP_HDR_PROTO_SVIF. */\n+\t/*update the hdr_bitmap with BNXT_ULP_HDR_PROTO_SVIF */\n \tULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_SVIF);\n \n \tif (proto == RTE_FLOW_ITEM_TYPE_PORT_ID) {\n-\t\t/* perform the conversion from dpdk port to svif */\n-\t\tdir = params->dir;\n+\t\tdir = ULP_UTIL_CHF_IDX_RD(params,\n+\t\t\t\t\t  BNXT_ULP_CHF_IDX_DIRECTION);\n+\t\t/* perform the conversion from dpdk port to bnxt svif */\n \t\tif (dir == ULP_DIR_EGRESS)\n \t\t\tsvif = bnxt_get_svif(port_id, true);\n \t\telse\n \t\t\tsvif = bnxt_get_svif(port_id, false);\n \t}\n-\n-\tmemcpy(params->hdr_field[BNXT_ULP_HDR_FIELD_SVIF_INDEX].spec,\n-\t       &svif, sizeof(svif));\n-\tmemcpy(params->hdr_field[BNXT_ULP_HDR_FIELD_SVIF_INDEX].mask,\n-\t       &mask, sizeof(mask));\n-\tparams->hdr_field[BNXT_ULP_HDR_FIELD_SVIF_INDEX].size = sizeof(svif);\n+\thdr_field = &params->hdr_field[BNXT_ULP_PROTO_HDR_FIELD_SVIF_IDX];\n+\tmemcpy(hdr_field->spec, &svif, sizeof(svif));\n+\tmemcpy(hdr_field->mask, &mask, sizeof(mask));\n+\thdr_field->size = sizeof(svif);\n \treturn BNXT_TF_RC_SUCCESS;\n }\n \n-/* Function to handle the parsing of the RTE port id\n- */\n+/* Function to handle the parsing of the RTE port id */\n int32_t\n ulp_rte_parser_svif_process(struct ulp_rte_parser_params *params)\n {\n \tuint16_t port_id = 0;\n-\tuint8_t\t*buffer;\n \tuint16_t svif_mask = 0xFFFF;\n \n \tif (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_SVIF))\n \t\treturn BNXT_TF_RC_SUCCESS;\n \n-\t/* SVIF not set. So get the port id and direction */\n-\tbuffer = params->hdr_field[BNXT_ULP_HDR_FIELD_SVIF_INDEX].spec;\n-\tmemcpy(&port_id, buffer, sizeof(port_id));\n-\tmemset(buffer, 0, RTE_PARSER_FLOW_HDR_FIELD_SIZE);\n+\t/* SVIF not set. So get the port id */\n+\tport_id = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_INCOMING_IF);\n \n-\treturn ulp_rte_parser_svif_set(params,\n-\t\t\t\t       RTE_FLOW_ITEM_TYPE_PORT_ID,\n+\t/* Update the SVIF details */\n+\treturn ulp_rte_parser_svif_set(params, RTE_FLOW_ITEM_TYPE_PORT_ID,\n \t\t\t\t       port_id, svif_mask);\n }\n \n+/* Function to handle the implicit VNIC RTE port id */\n+int32_t\n+ulp_rte_parser_vnic_process(struct ulp_rte_parser_params *params)\n+{\n+\tstruct ulp_rte_act_bitmap *act = &params->act_bitmap;\n+\n+\tif (ULP_BITMAP_ISSET(act->bits, BNXT_ULP_ACTION_BIT_VNIC) ||\n+\t    ULP_BITMAP_ISSET(act->bits, BNXT_ULP_ACTION_BIT_VPORT))\n+\t\treturn BNXT_TF_RC_SUCCESS;\n+\n+\t/* Update the vnic details */\n+\tulp_rte_pf_act_handler(NULL, params);\n+\treturn BNXT_TF_RC_SUCCESS;\n+}\n+\n /* Function to handle the parsing of RTE Flow item PF Header. */\n int32_t\n ulp_rte_pf_hdr_handler(const struct rte_flow_item *item,\n \t\t       struct ulp_rte_parser_params *params)\n {\n \tuint16_t port_id = 0;\n-\tuint8_t\t*buffer;\n \tuint16_t svif_mask = 0xFFFF;\n \n-\tbuffer = params->hdr_field[BNXT_ULP_HDR_FIELD_SVIF_INDEX].spec;\n-\tmemcpy(&port_id, buffer, sizeof(port_id));\n-\tmemset(buffer, 0, RTE_PARSER_FLOW_HDR_FIELD_SIZE);\n+\t/* Get the port id */\n+\tport_id = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_INCOMING_IF);\n \n+\t/* Update the SVIF details */\n \treturn ulp_rte_parser_svif_set(params,\n \t\t\t\t       item->type,\n \t\t\t\t       port_id, svif_mask);\n@@ -345,15 +361,11 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,\n \tconst struct rte_flow_item_vlan *vlan_spec = item->spec;\n \tconst struct rte_flow_item_vlan *vlan_mask = item->mask;\n \tstruct ulp_rte_hdr_field *field;\n-\tstruct ulp_rte_hdr_bitmap *hdr_bitmap;\n+\tstruct ulp_rte_hdr_bitmap\t*hdr_bit;\n \tuint32_t idx = params->vlan_idx;\n \tuint16_t vlan_tag, priority;\n-\tuint32_t outer_vtag_num = 0, inner_vtag_num = 0;\n-\tuint8_t *outer_tag_buff;\n-\tuint8_t *inner_tag_buff;\n-\n-\touter_tag_buff = params->hdr_field[BNXT_ULP_HDR_FIELD_O_VTAG_NUM].spec;\n-\tinner_tag_buff = params->hdr_field[BNXT_ULP_HDR_FIELD_I_VTAG_NUM].spec;\n+\tuint32_t outer_vtag_num;\n+\tuint32_t inner_vtag_num;\n \n \t/*\n \t * Copy the rte_flow_item for vlan into hdr_field using Vlan\n@@ -393,64 +405,53 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,\n \tparams->vlan_idx += BNXT_ULP_PROTO_HDR_S_VLAN_NUM;\n \n \t/* Get the outer tag and inner tag counts */\n-\tulp_util_field_int_read(outer_tag_buff, &outer_vtag_num);\n-\tulp_util_field_int_read(inner_tag_buff, &inner_vtag_num);\n+\touter_vtag_num = ULP_UTIL_CHF_IDX_RD(params,\n+\t\t\t\t\t     BNXT_ULP_CHF_IDX_O_VTAG_NUM);\n+\tinner_vtag_num = ULP_UTIL_CHF_IDX_RD(params,\n+\t\t\t\t\t     BNXT_ULP_CHF_IDX_I_VTAG_NUM);\n \n \t/* Update the hdr_bitmap of the vlans */\n-\thdr_bitmap  = &params->hdr_bitmap;\n-\tif (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_ETH) &&\n-\t    !ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_OO_VLAN)) {\n+\thdr_bit = &params->hdr_bitmap;\n+\tif (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&\n+\t    !ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OO_VLAN)) {\n \t\t/* Set the outer vlan bit and update the vlan tag num */\n-\t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_OO_VLAN);\n+\t\tULP_BITMAP_SET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OO_VLAN);\n \t\touter_vtag_num++;\n-\t\tulp_util_field_int_write(outer_tag_buff, outer_vtag_num);\n-\t\tparams->hdr_field[BNXT_ULP_HDR_FIELD_O_VTAG_NUM].size =\n-\t\t\t\t\t\t\tsizeof(uint32_t);\n-\t} else if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_ETH) &&\n-\t\t   ULP_BITMAP_ISSET(hdr_bitmap->bits,\n-\t\t\t\t    BNXT_ULP_HDR_BIT_OO_VLAN) &&\n-\t\t   !ULP_BITMAP_ISSET(hdr_bitmap->bits,\n-\t\t\t\t     BNXT_ULP_HDR_BIT_OI_VLAN)) {\n+\t\tULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_VTAG_NUM,\n+\t\t\t\t    outer_vtag_num);\n+\t\tULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_VTAG_PRESENT, 1);\n+\t} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&\n+\t\t   ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OO_VLAN) &&\n+\t\t   !ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OI_VLAN)) {\n \t\t/* Set the outer vlan bit and update the vlan tag num */\n-\t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_OI_VLAN);\n+\t\tULP_BITMAP_SET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OI_VLAN);\n \t\touter_vtag_num++;\n-\t\tulp_util_field_int_write(outer_tag_buff, outer_vtag_num);\n-\t\tparams->hdr_field[BNXT_ULP_HDR_FIELD_O_VTAG_NUM].size =\n-\t\t\t\t\t\t\t    sizeof(uint32_t);\n-\t} else if (ULP_BITMAP_ISSET(hdr_bitmap->bits,\n-\t\t\t\t    BNXT_ULP_HDR_BIT_O_ETH) &&\n-\t\t   ULP_BITMAP_ISSET(hdr_bitmap->bits,\n-\t\t\t\t    BNXT_ULP_HDR_BIT_OO_VLAN) &&\n-\t\t   ULP_BITMAP_ISSET(hdr_bitmap->bits,\n-\t\t\t\t    BNXT_ULP_HDR_BIT_OI_VLAN) &&\n-\t\t   ULP_BITMAP_ISSET(hdr_bitmap->bits,\n-\t\t\t\t    BNXT_ULP_HDR_BIT_I_ETH) &&\n-\t\t   !ULP_BITMAP_ISSET(hdr_bitmap->bits,\n-\t\t\t\t     BNXT_ULP_HDR_BIT_IO_VLAN)) {\n+\t\tULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_VTAG_NUM,\n+\t\t\t\t    outer_vtag_num);\n+\t\tULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_TWO_VTAGS, 1);\n+\t} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&\n+\t\t   ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OO_VLAN) &&\n+\t\t   ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OI_VLAN) &&\n+\t\t   ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) &&\n+\t\t   !ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_IO_VLAN)) {\n \t\t/* Set the inner vlan bit and update the vlan tag num */\n-\t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_IO_VLAN);\n+\t\tULP_BITMAP_SET(hdr_bit->bits, BNXT_ULP_HDR_BIT_IO_VLAN);\n \t\tinner_vtag_num++;\n-\t\tulp_util_field_int_write(inner_tag_buff, inner_vtag_num);\n-\t\tparams->hdr_field[BNXT_ULP_HDR_FIELD_I_VTAG_NUM].size =\n-\t\t\t\t\t\t\t    sizeof(uint32_t);\n-\t} else if (ULP_BITMAP_ISSET(hdr_bitmap->bits,\n-\t\t\t\t    BNXT_ULP_HDR_BIT_O_ETH) &&\n-\t\t   ULP_BITMAP_ISSET(hdr_bitmap->bits,\n-\t\t\t\t    BNXT_ULP_HDR_BIT_OO_VLAN) &&\n-\t\t   ULP_BITMAP_ISSET(hdr_bitmap->bits,\n-\t\t\t\t    BNXT_ULP_HDR_BIT_OI_VLAN) &&\n-\t\t   ULP_BITMAP_ISSET(hdr_bitmap->bits,\n-\t\t\t\t    BNXT_ULP_HDR_BIT_I_ETH) &&\n-\t\t   ULP_BITMAP_ISSET(hdr_bitmap->bits,\n-\t\t\t\t    BNXT_ULP_HDR_BIT_IO_VLAN) &&\n-\t\t   !ULP_BITMAP_ISSET(hdr_bitmap->bits,\n-\t\t\t\t     BNXT_ULP_HDR_BIT_II_VLAN)) {\n+\t\tULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_VTAG_NUM,\n+\t\t\t\t    inner_vtag_num);\n+\t\tULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_VTAG_PRESENT, 1);\n+\t} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&\n+\t\t   ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OO_VLAN) &&\n+\t\t   ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OI_VLAN) &&\n+\t\t   ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) &&\n+\t\t   ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_IO_VLAN) &&\n+\t\t   !ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_II_VLAN)) {\n \t\t/* Set the inner vlan bit and update the vlan tag num */\n-\t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_II_VLAN);\n+\t\tULP_BITMAP_SET(hdr_bit->bits, BNXT_ULP_HDR_BIT_II_VLAN);\n \t\tinner_vtag_num++;\n-\t\tulp_util_field_int_write(inner_tag_buff, inner_vtag_num);\n-\t\tparams->hdr_field[BNXT_ULP_HDR_FIELD_I_VTAG_NUM].size =\n-\t\t\t\t\t\t\t    sizeof(uint32_t);\n+\t\tULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_VTAG_NUM,\n+\t\t\t\t    inner_vtag_num);\n+\t\tULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_TWO_VTAGS, 1);\n \t} else {\n \t\tBNXT_TF_DBG(ERR, \"Error Parsing:Vlan hdr found withtout eth\\n\");\n \t\treturn BNXT_TF_RC_ERROR;\n@@ -469,8 +470,10 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,\n \tstruct ulp_rte_hdr_bitmap *hdr_bitmap = &params->hdr_bitmap;\n \tuint32_t idx = params->field_idx;\n \tuint32_t size;\n+\tuint32_t inner_l3, outer_l3;\n \n-\tif (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_L3)) {\n+\tinner_l3 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_I_L3);\n+\tif (inner_l3) {\n \t\tBNXT_TF_DBG(ERR, \"Parse Error:Third L3 header not supported\\n\");\n \t\treturn BNXT_TF_RC_ERROR;\n \t}\n@@ -557,14 +560,17 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,\n \tparams->field_idx += BNXT_ULP_PROTO_HDR_IPV4_NUM;\n \n \t/* Set the ipv4 header bitmap and computed l3 header bitmaps */\n-\tif (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_L3) ||\n+\touter_l3 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_O_L3);\n+\tif (outer_l3 ||\n \t    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) ||\n \t    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) {\n \t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV4);\n-\t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_L3);\n+\t\tinner_l3++;\n+\t\tULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_L3, inner_l3);\n \t} else {\n \t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4);\n-\t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_L3);\n+\t\touter_l3++;\n+\t\tULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_L3, outer_l3);\n \t}\n \treturn BNXT_TF_RC_SUCCESS;\n }\n@@ -580,8 +586,10 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,\n \tstruct ulp_rte_hdr_bitmap *hdr_bitmap = &params->hdr_bitmap;\n \tuint32_t idx = params->field_idx;\n \tuint32_t size;\n+\tuint32_t inner_l3, outer_l3;\n \n-\tif (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_L3)) {\n+\tinner_l3 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_I_L3);\n+\tif (inner_l3) {\n \t\tBNXT_TF_DBG(ERR, \"Parse Error: 3'rd L3 header not supported\\n\");\n \t\treturn BNXT_TF_RC_ERROR;\n \t}\n@@ -640,14 +648,15 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,\n \tparams->field_idx += BNXT_ULP_PROTO_HDR_IPV6_NUM;\n \n \t/* Set the ipv6 header bitmap and computed l3 header bitmaps */\n-\tif (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_L3) ||\n+\touter_l3 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_O_L3);\n+\tif (outer_l3 ||\n \t    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) ||\n \t    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) {\n \t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV6);\n-\t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_L3);\n+\t\tULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_L3, 1);\n \t} else {\n \t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6);\n-\t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_L3);\n+\t\tULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_L3, 1);\n \t}\n \treturn BNXT_TF_RC_SUCCESS;\n }\n@@ -663,8 +672,10 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,\n \tstruct ulp_rte_hdr_bitmap *hdr_bitmap = &params->hdr_bitmap;\n \tuint32_t idx = params->field_idx;\n \tuint32_t size;\n+\tuint32_t inner_l4, outer_l4;\n \n-\tif (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_L4)) {\n+\tinner_l4 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_I_L4);\n+\tif (inner_l4) {\n \t\tBNXT_TF_DBG(ERR, \"Parse Err:Third L4 header not supported\\n\");\n \t\treturn BNXT_TF_RC_ERROR;\n \t}\n@@ -710,14 +721,15 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,\n \tparams->field_idx += BNXT_ULP_PROTO_HDR_UDP_NUM;\n \n \t/* Set the udp header bitmap and computed l4 header bitmaps */\n-\tif (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_L4) ||\n+\touter_l4 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_O_L4);\n+\tif (outer_l4 ||\n \t    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) ||\n \t    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) {\n \t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_UDP);\n-\t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_L4);\n+\t\tULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_L4, 1);\n \t} else {\n \t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP);\n-\t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_L4);\n+\t\tULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_L4, 1);\n \t}\n \treturn BNXT_TF_RC_SUCCESS;\n }\n@@ -733,8 +745,10 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,\n \tstruct ulp_rte_hdr_bitmap *hdr_bitmap = &params->hdr_bitmap;\n \tuint32_t idx = params->field_idx;\n \tuint32_t size;\n+\tuint32_t inner_l4, outer_l4;\n \n-\tif (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_L4)) {\n+\tinner_l4 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_I_L4);\n+\tif (inner_l4) {\n \t\tBNXT_TF_DBG(ERR, \"Parse Error:Third L4 header not supported\\n\");\n \t\treturn BNXT_TF_RC_ERROR;\n \t}\n@@ -817,14 +831,15 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,\n \tparams->field_idx += BNXT_ULP_PROTO_HDR_TCP_NUM;\n \n \t/* Set the udp header bitmap and computed l4 header bitmaps */\n-\tif (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_L4) ||\n+\touter_l4 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_O_L4);\n+\tif (outer_l4 ||\n \t    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) ||\n \t    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) {\n \t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_TCP);\n-\t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_L4);\n+\t\tULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_L4, 1);\n \t} else {\n \t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP);\n-\t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_L4);\n+\t\tULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_L4, 1);\n \t}\n \treturn BNXT_TF_RC_SUCCESS;\n }\n@@ -1181,22 +1196,19 @@ ulp_rte_count_act_handler(const struct rte_flow_action *action_item,\n /* Function to handle the parsing of RTE Flow action PF. */\n int32_t\n ulp_rte_pf_act_handler(const struct rte_flow_action *action_item __rte_unused,\n-\t\t       struct ulp_rte_parser_params *param)\n+\t\t       struct ulp_rte_parser_params *params)\n {\n-\tuint8_t *svif_buf;\n-\tuint8_t *vnic_buffer;\n \tuint32_t svif;\n \n \t/* Update the hdr_bitmap with vnic bit */\n-\tULP_BITMAP_SET(param->act_bitmap.bits, BNXT_ULP_ACTION_BIT_VNIC);\n+\tULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_VNIC);\n \n \t/* copy the PF of the current device into VNIC Property */\n-\tsvif_buf = &param->act_prop.act_details[BNXT_ULP_ACT_PROP_IDX_VNIC];\n-\tulp_util_field_int_read(svif_buf, &svif);\n-\tsvif = (uint32_t)bnxt_get_vnic_id(svif);\n-\tsvif = htonl(svif);\n-\tvnic_buffer = &param->act_prop.act_details[BNXT_ULP_ACT_PROP_IDX_VNIC];\n-\tulp_util_field_int_write(vnic_buffer, svif);\n+\tsvif = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_INCOMING_IF);\n+\tsvif = bnxt_get_vnic_id(svif);\n+\tsvif = rte_cpu_to_be_32(svif);\n+\tmemcpy(&params->act_prop.act_details[BNXT_ULP_ACT_PROP_IDX_VNIC],\n+\t       &svif, BNXT_ULP_ACT_PROP_SZ_VNIC);\n \n \treturn BNXT_TF_RC_SUCCESS;\n }\n@@ -1207,6 +1219,7 @@ ulp_rte_vf_act_handler(const struct rte_flow_action *action_item,\n \t\t       struct ulp_rte_parser_params *param)\n {\n \tconst struct rte_flow_action_vf *vf_action;\n+\tuint32_t pid;\n \n \tvf_action = action_item->conf;\n \tif (vf_action) {\n@@ -1216,9 +1229,10 @@ ulp_rte_vf_act_handler(const struct rte_flow_action *action_item,\n \t\t\treturn BNXT_TF_RC_PARSE_ERR;\n \t\t}\n \t\t/* TBD: Update the computed VNIC using VF conversion */\n+\t\tpid = bnxt_get_vnic_id(vf_action->id);\n+\t\tpid = rte_cpu_to_be_32(pid);\n \t\tmemcpy(&param->act_prop.act_details[BNXT_ULP_ACT_PROP_IDX_VNIC],\n-\t\t       &vf_action->id,\n-\t\t       BNXT_ULP_ACT_PROP_SZ_VNIC);\n+\t\t       &pid, BNXT_ULP_ACT_PROP_SZ_VNIC);\n \t}\n \n \t/* Update the hdr_bitmap with count */\n@@ -1232,6 +1246,7 @@ ulp_rte_port_id_act_handler(const struct rte_flow_action *act_item,\n \t\t\t    struct ulp_rte_parser_params *param)\n {\n \tconst struct rte_flow_action_port_id *port_id;\n+\tuint32_t pid;\n \n \tport_id = act_item->conf;\n \tif (port_id) {\n@@ -1241,9 +1256,10 @@ ulp_rte_port_id_act_handler(const struct rte_flow_action *act_item,\n \t\t\treturn BNXT_TF_RC_PARSE_ERR;\n \t\t}\n \t\t/* TBD: Update the computed VNIC using port conversion */\n+\t\tpid = bnxt_get_vnic_id(port_id->id);\n+\t\tpid = rte_cpu_to_be_32(pid);\n \t\tmemcpy(&param->act_prop.act_details[BNXT_ULP_ACT_PROP_IDX_VNIC],\n-\t\t       &port_id->id,\n-\t\t       BNXT_ULP_ACT_PROP_SZ_VNIC);\n+\t\t       &pid, BNXT_ULP_ACT_PROP_SZ_VNIC);\n \t}\n \n \t/* Update the hdr_bitmap with count */\n@@ -1257,6 +1273,7 @@ ulp_rte_phy_port_act_handler(const struct rte_flow_action *action_item,\n \t\t\t     struct ulp_rte_parser_params *prm)\n {\n \tconst struct rte_flow_action_phy_port *phy_port;\n+\tuint32_t pid;\n \n \tphy_port = action_item->conf;\n \tif (phy_port) {\n@@ -1265,9 +1282,10 @@ ulp_rte_phy_port_act_handler(const struct rte_flow_action *action_item,\n \t\t\t\t    \"Parse Err:Port Original not supported\\n\");\n \t\t\treturn BNXT_TF_RC_PARSE_ERR;\n \t\t}\n+\t\tpid = bnxt_get_vnic_id(phy_port->index);\n+\t\tpid = rte_cpu_to_be_32(pid);\n \t\tmemcpy(&prm->act_prop.act_details[BNXT_ULP_ACT_PROP_IDX_VPORT],\n-\t\t       &phy_port->index,\n-\t\t       BNXT_ULP_ACT_PROP_SZ_VPORT);\n+\t\t       &pid, BNXT_ULP_ACT_PROP_SZ_VPORT);\n \t}\n \n \t/* Update the hdr_bitmap with count */\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h\nindex 4cc9dcc..cbc8a43 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h\n@@ -24,6 +24,10 @@\n int32_t\n ulp_rte_parser_svif_process(struct ulp_rte_parser_params *params);\n \n+/* Function to handle the implicit VNIC RTE port id */\n+int32_t\n+ulp_rte_parser_vnic_process(struct ulp_rte_parser_params *params);\n+\n /*\n  * Function to handle the parsing of RTE Flows and placing\n  * the RTE flow items into the ulp structures.\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.c b/drivers/net/bnxt/tf_ulp/ulp_template_db.c\nindex 411f1e3..25a558a 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2014-2019 Broadcom\n+ * Copyright(c) 2014-2020 Broadcom\n  * All rights reserved.\n  */\n \n@@ -30,6 +30,8 @@ uint32_t ulp_act_prop_map_table[] = {\n \t\tBNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM,\n \t[BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM] =\n \t\tBNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM,\n+\t[BNXT_ULP_ACT_PROP_IDX_PORT_ID] =\n+\t\tBNXT_ULP_ACT_PROP_SZ_PORT_ID,\n \t[BNXT_ULP_ACT_PROP_IDX_VNIC] =\n \t\tBNXT_ULP_ACT_PROP_SZ_VNIC,\n \t[BNXT_ULP_ACT_PROP_IDX_VPORT] =\n@@ -505,8 +507,55 @@ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = {\n \t}\n };\n \n+uint32_t bnxt_ulp_encap_vtag_map[] = {\n+\t[0] = BNXT_ULP_ENCAP_VTAG_ENCODING_NOP,\n+\t[1] = BNXT_ULP_ENCAP_VTAG_ENCODING_STAG_ECAP_PRI,\n+\t[2] = BNXT_ULP_ENCAP_VTAG_ENCODING_DTAG_ECAP_PRI\n+};\n+\n+uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {\n+\t[BNXT_ULP_CLASS_HID_0092] = 1\n+};\n+\n+struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n+\t[1] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0092,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF0_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF0_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 0,\n+\t.act_vnic = 0,\n+\t.wc_pri = 0\n+\t}\n+};\n+\n+uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {\n+\t[BNXT_ULP_ACT_HID_0029] = 1\n+};\n+\n+struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n+\t[1] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_0029,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACTION_BIT_MARK |\n+\t\tBNXT_ULP_ACTION_BIT_RSS |\n+\t\tBNXT_ULP_ACTION_BIT_VNIC |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.act_tid = 0\n+\t}\n+};\n+\n struct bnxt_ulp_mapper_tbl_list_info ulp_class_tmpl_list[] = {\n-\t[((0 << BNXT_ULP_LOG2_MAX_NUM_DEV) | BNXT_ULP_DEVICE_ID_WH_PLUS)] = {\n+\t[((0 << BNXT_ULP_LOG2_MAX_NUM_DEV) |\n+\t\tBNXT_ULP_DEVICE_ID_WH_PLUS)] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.num_tbls = 3,\n \t.start_tbl_idx = 0\n@@ -528,7 +577,7 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.ident_start_idx = 0,\n-\t.ident_nums = 1,\n+\t.ident_nums = 2,\n \t.mark_enable = BNXT_ULP_MARK_ENABLE_NO,\n \t.critical_resource = 0,\n \t.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED\n@@ -546,7 +595,7 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {\n \t.result_start_idx = 13,\n \t.result_bit_size = 38,\n \t.result_num_fields = 8,\n-\t.ident_start_idx = 1,\n+\t.ident_start_idx = 2,\n \t.ident_nums = 1,\n \t.mark_enable = BNXT_ULP_MARK_ENABLE_NO,\n \t.critical_resource = 0,\n@@ -560,12 +609,11 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {\n \t.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,\n \t.key_start_idx = 55,\n \t.blob_key_bit_size = 448,\n-\t.key_bit_size = 197,\n+\t.key_bit_size = 448,\n \t.key_num_fields = 11,\n \t.result_start_idx = 21,\n \t.result_bit_size = 64,\n \t.result_num_fields = 9,\n-\t.ident_start_idx = 2,\n \t.ident_nums = 0,\n \t.mark_enable = BNXT_ULP_MARK_ENABLE_YES,\n \t.critical_resource = 1,\n@@ -595,24 +643,22 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {\n \t{\n \t.field_bit_size = 48,\n \t.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,\n-\t.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},\n-\t.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,\n-\t.spec_operand = {(BNXT_ULP_HF0_O_ETH_DMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_HF0_O_ETH_DMAC & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n+\t.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,\n+\t.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n \t{\n \t.field_bit_size = 8,\n \t.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD,\n-\t.mask_operand = {(BNXT_ULP_HF0_SVIF_INDEX >> 8) & 0xff,\n-\t\tBNXT_ULP_HF0_SVIF_INDEX & 0xff,\n+\t.mask_operand = {(BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,\n+\t\tBNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n \t.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,\n-\t.spec_operand = {(BNXT_ULP_HF0_SVIF_INDEX >> 8) & 0xff,\n-\t\tBNXT_ULP_HF0_SVIF_INDEX & 0xff,\n+\t.spec_operand = {(BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,\n+\t\tBNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n@@ -859,8 +905,9 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {\n \t.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n \t.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,\n-\t.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.spec_operand = {BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n \t{\n \t.field_bit_size = 1,\n@@ -895,8 +942,9 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {\n \t.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n \t.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,\n-\t.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.spec_operand = {BNXT_ULP_SYM_TL4_HDR_TYPE_UDP,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n \t{\n \t.field_bit_size = 1,\n@@ -949,14 +997,15 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {\n \t.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n \t.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,\n-\t.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.spec_operand = {BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n \t{\n \t.field_bit_size = 1,\n \t.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,\n-\t.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n+\t.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n+\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},\n \t.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,\n \t.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n@@ -967,7 +1016,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {\n \t.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n \t.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,\n-\t.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n \t{\n@@ -1003,8 +1052,9 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {\n \t.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n \t.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,\n-\t.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.spec_operand = {BNXT_ULP_SYM_TL2_HDR_TYPE_DIX,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n \t{\n \t.field_bit_size = 1,\n@@ -1012,7 +1062,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {\n \t.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n \t.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,\n-\t.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n \t{\n@@ -1038,9 +1088,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {\n \t.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,\n \t.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n \t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},\n-\t.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,\n-\t.spec_operand = {0x40, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,\n+\t.spec_operand = {(BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 & 0xff,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n \t{\n \t.field_bit_size = 1,\n@@ -1103,8 +1155,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {\n \t.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n \t.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,\n-\t.spec_operand = {(BNXT_ULP_HF0_O_UDP_DST_PORT >> 8) & 0xff,\n-\t\tBNXT_ULP_HF0_O_UDP_DST_PORT & 0xff,\n+\t.spec_operand = {(BNXT_ULP_HF0_IDX_O_UDP_DST_PORT >> 8) & 0xff,\n+\t\tBNXT_ULP_HF0_IDX_O_UDP_DST_PORT & 0xff,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n@@ -1114,8 +1166,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {\n \t.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n \t.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,\n-\t.spec_operand = {(BNXT_ULP_HF0_O_UDP_SRC_PORT >> 8) & 0xff,\n-\t\tBNXT_ULP_HF0_O_UDP_SRC_PORT & 0xff,\n+\t.spec_operand = {(BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT >> 8) & 0xff,\n+\t\tBNXT_ULP_HF0_IDX_O_UDP_SRC_PORT & 0xff,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n@@ -1135,8 +1187,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {\n \t.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n \t.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,\n-\t.spec_operand = {(BNXT_ULP_HF0_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_HF0_O_IPV4_DST_ADDR & 0xff,\n+\t.spec_operand = {(BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR & 0xff,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n@@ -1146,8 +1198,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {\n \t.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n \t.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,\n-\t.spec_operand = {(BNXT_ULP_HF0_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_HF0_O_IPV4_SRC_ADDR & 0xff,\n+\t.spec_operand = {(BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR & 0xff,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n@@ -1156,11 +1208,9 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {\n \t.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,\n \t.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n-\t.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,\n-\t.spec_operand = {(BNXT_ULP_HF0_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_HF0_O_ETH_SMAC & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,\n+\t.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n \t{\n \t.field_bit_size = 24,\n@@ -1187,124 +1237,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {\n \t.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,\n \t.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n-\t.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,\n-\t.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t}\n-};\n-\n-struct bnxt_ulp_header_match_info ulp_ingress_hdr_match_list[] = {\n-\t{\n-\t.hdr_bitmap = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP },\n-\t.start_idx = 0,\n-\t.num_entries = 24,\n-\t.class_tmpl_id = 0,\n-\t.act_vnic = 0\n-\t}\n-};\n-\n-struct bnxt_ulp_header_match_info ulp_egress_hdr_match_list[] = {\n-};\n-\n-struct bnxt_ulp_matcher_field_info ulp_field_match[] = {\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_EXACT,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_EXACT,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_ANY,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_ANY,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_EXACT,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_EXACT,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_EXACT,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_EXACT,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n-\t},\n-\t{\n-\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n-\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,\n+\t.spec_operand = {(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t}\n };\n \n@@ -1319,9 +1256,11 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {\n \t},\n \t{\n \t.field_bit_size = 7,\n-\t.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,\n-\t.result_operand = {0x40, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,\n+\t.result_operand = {(BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 & 0xff,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n \t{\n \t.field_bit_size = 1,\n@@ -1410,8 +1349,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {\n \t{\n \t.field_bit_size = 10,\n \t.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,\n-\t.result_operand = {(0x00fd >> 8) & 0xff,\n-\t\t0x00fd & 0xff,\n+\t.result_operand = {(0x00f9 >> 8) & 0xff,\n+\t\t0x00f9 & 0xff,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n@@ -1423,9 +1362,11 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {\n \t},\n \t{\n \t.field_bit_size = 8,\n-\t.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,\n-\t.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,\n+\t.result_operand = {(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n \t{\n \t.field_bit_size = 1,\n@@ -1462,7 +1403,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {\n \t{\n \t.field_bit_size = 5,\n \t.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,\n-\t.result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t.result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n \t{\n@@ -1502,6 +1443,13 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {\n struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = {\n \t{\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.ident_type = TF_IDENT_TYPE_PROF_FUNC,\n+\t.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0,\n+\t.ident_bit_size = 7,\n+\t.ident_bit_pos = 47\n+\t},\n+\t{\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.ident_type = TF_IDENT_TYPE_L2_CTXT,\n \t.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,\n \t.ident_bit_size = 10,\n@@ -1516,20 +1464,9 @@ struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = {\n \t}\n };\n \n-struct bnxt_ulp_action_match_info ulp_ingress_act_match_list[] = {\n-\t{\n-\t.act_bitmap = { .bits =\n-\t\tBNXT_ULP_ACTION_BIT_MARK |\n-\t\tBNXT_ULP_ACTION_BIT_RSS },\n-\t.act_tmpl_id = 0\n-\t}\n-};\n-\n-struct bnxt_ulp_action_match_info ulp_egress_act_match_list[] = {\n-};\n-\n struct bnxt_ulp_mapper_tbl_list_info ulp_act_tmpl_list[] = {\n-\t[((0 << BNXT_ULP_LOG2_MAX_NUM_DEV) | BNXT_ULP_DEVICE_ID_WH_PLUS)] = {\n+\t[((0 << BNXT_ULP_LOG2_MAX_NUM_DEV) |\n+\t\tBNXT_ULP_DEVICE_ID_WH_PLUS)] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.num_tbls = 1,\n \t.start_tbl_idx = 0\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h\nindex dfab266..94d4253 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2014-2019 Broadcom\n+ * Copyright(c) 2014-2020 Broadcom\n  * All rights reserved.\n  */\n \n@@ -11,12 +11,23 @@\n #ifndef ULP_TEMPLATE_DB_H_\n #define ULP_TEMPLATE_DB_H_\n \n+#define BNXT_ULP_REGFILE_MAX_SZ 15\n #define BNXT_ULP_MAX_NUM_DEVICES 4\n #define BNXT_ULP_LOG2_MAX_NUM_DEV 2\n-#define BNXT_ULP_INGRESS_HDR_MATCH_SZ 2\n-#define BNXT_ULP_EGRESS_HDR_MATCH_SZ 1\n-#define BNXT_ULP_INGRESS_ACT_MATCH_SZ 2\n-#define BNXT_ULP_EGRESS_ACT_MATCH_SZ 1\n+#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 256\n+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 2\n+#define BNXT_ULP_CLASS_HID_LOW_PRIME 7919\n+#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7919\n+#define BNXT_ULP_CLASS_HID_SHFTR 0\n+#define BNXT_ULP_CLASS_HID_SHFTL 23\n+#define BNXT_ULP_CLASS_HID_MASK 255\n+#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 256\n+#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 2\n+#define BNXT_ULP_ACT_HID_LOW_PRIME 7919\n+#define BNXT_ULP_ACT_HID_HIGH_PRIME 7919\n+#define BNXT_ULP_ACT_HID_SHFTR 0\n+#define BNXT_ULP_ACT_HID_SHFTL 23\n+#define BNXT_ULP_ACT_HID_MASK 255\n \n enum bnxt_ulp_action_bit {\n \tBNXT_ULP_ACTION_BIT_MARK             = 0x0000000000000001,\n@@ -54,24 +65,20 @@ enum bnxt_ulp_hdr_bit {\n \tBNXT_ULP_HDR_BIT_O_ETH               = 0x0000000000000002,\n \tBNXT_ULP_HDR_BIT_OO_VLAN             = 0x0000000000000004,\n \tBNXT_ULP_HDR_BIT_OI_VLAN             = 0x0000000000000008,\n-\tBNXT_ULP_HDR_BIT_O_L3                = 0x0000000000000010,\n-\tBNXT_ULP_HDR_BIT_O_IPV4              = 0x0000000000000020,\n-\tBNXT_ULP_HDR_BIT_O_IPV6              = 0x0000000000000040,\n-\tBNXT_ULP_HDR_BIT_O_L4                = 0x0000000000000080,\n-\tBNXT_ULP_HDR_BIT_O_TCP               = 0x0000000000000100,\n-\tBNXT_ULP_HDR_BIT_O_UDP               = 0x0000000000000200,\n-\tBNXT_ULP_HDR_BIT_T_VXLAN             = 0x0000000000000400,\n-\tBNXT_ULP_HDR_BIT_T_GRE               = 0x0000000000000800,\n-\tBNXT_ULP_HDR_BIT_I_ETH               = 0x0000000000001000,\n-\tBNXT_ULP_HDR_BIT_IO_VLAN             = 0x0000000000002000,\n-\tBNXT_ULP_HDR_BIT_II_VLAN             = 0x0000000000004000,\n-\tBNXT_ULP_HDR_BIT_I_L3                = 0x0000000000008000,\n-\tBNXT_ULP_HDR_BIT_I_IPV4              = 0x0000000000010000,\n-\tBNXT_ULP_HDR_BIT_I_IPV6              = 0x0000000000020000,\n-\tBNXT_ULP_HDR_BIT_I_L4                = 0x0000000000040000,\n-\tBNXT_ULP_HDR_BIT_I_TCP               = 0x0000000000080000,\n-\tBNXT_ULP_HDR_BIT_I_UDP               = 0x0000000000100000,\n-\tBNXT_ULP_HDR_BIT_LAST                = 0x0000000000200000\n+\tBNXT_ULP_HDR_BIT_O_IPV4              = 0x0000000000000010,\n+\tBNXT_ULP_HDR_BIT_O_IPV6              = 0x0000000000000020,\n+\tBNXT_ULP_HDR_BIT_O_TCP               = 0x0000000000000040,\n+\tBNXT_ULP_HDR_BIT_O_UDP               = 0x0000000000000080,\n+\tBNXT_ULP_HDR_BIT_T_VXLAN             = 0x0000000000000100,\n+\tBNXT_ULP_HDR_BIT_T_GRE               = 0x0000000000000200,\n+\tBNXT_ULP_HDR_BIT_I_ETH               = 0x0000000000000400,\n+\tBNXT_ULP_HDR_BIT_IO_VLAN             = 0x0000000000000800,\n+\tBNXT_ULP_HDR_BIT_II_VLAN             = 0x0000000000001000,\n+\tBNXT_ULP_HDR_BIT_I_IPV4              = 0x0000000000002000,\n+\tBNXT_ULP_HDR_BIT_I_IPV6              = 0x0000000000004000,\n+\tBNXT_ULP_HDR_BIT_I_TCP               = 0x0000000000008000,\n+\tBNXT_ULP_HDR_BIT_I_UDP               = 0x0000000000010000,\n+\tBNXT_ULP_HDR_BIT_LAST                = 0x0000000000020000\n };\n \n enum bnxt_ulp_act_type {\n@@ -82,30 +89,42 @@ enum bnxt_ulp_act_type {\n };\n \n enum bnxt_ulp_byte_order {\n-\tBNXT_ULP_BYTE_ORDER_BE,\n-\tBNXT_ULP_BYTE_ORDER_LE,\n-\tBNXT_ULP_BYTE_ORDER_LAST\n+\tBNXT_ULP_BYTE_ORDER_BE = 0,\n+\tBNXT_ULP_BYTE_ORDER_LE = 1,\n+\tBNXT_ULP_BYTE_ORDER_LAST = 2\n };\n \n-enum bnxt_ulp_device_id {\n-\tBNXT_ULP_DEVICE_ID_WH_PLUS,\n-\tBNXT_ULP_DEVICE_ID_THOR,\n-\tBNXT_ULP_DEVICE_ID_STINGRAY,\n-\tBNXT_ULP_DEVICE_ID_STINGRAY2,\n-\tBNXT_ULP_DEVICE_ID_LAST\n+enum bnxt_ulp_chf_idx {\n+\tBNXT_ULP_CHF_IDX_MPLS_TAG_NUM = 0,\n+\tBNXT_ULP_CHF_IDX_O_VTAG_NUM = 1,\n+\tBNXT_ULP_CHF_IDX_O_VTAG_PRESENT = 2,\n+\tBNXT_ULP_CHF_IDX_O_TWO_VTAGS = 3,\n+\tBNXT_ULP_CHF_IDX_I_VTAG_NUM = 4,\n+\tBNXT_ULP_CHF_IDX_I_VTAG_PRESENT = 5,\n+\tBNXT_ULP_CHF_IDX_I_TWO_VTAGS = 6,\n+\tBNXT_ULP_CHF_IDX_INCOMING_IF = 7,\n+\tBNXT_ULP_CHF_IDX_DIRECTION = 8,\n+\tBNXT_ULP_CHF_IDX_SVIF = 9,\n+\tBNXT_ULP_CHF_IDX_O_L3 = 10,\n+\tBNXT_ULP_CHF_IDX_I_L3 = 11,\n+\tBNXT_ULP_CHF_IDX_O_L4 = 12,\n+\tBNXT_ULP_CHF_IDX_I_L4 = 13,\n+\tBNXT_ULP_CHF_IDX_LAST = 14\n };\n \n-enum bnxt_ulp_fmf_mask {\n-\tBNXT_ULP_FMF_MASK_IGNORE,\n-\tBNXT_ULP_FMF_MASK_ANY,\n-\tBNXT_ULP_FMF_MASK_EXACT,\n-\tBNXT_ULP_FMF_MASK_WILDCARD,\n-\tBNXT_ULP_FMF_MASK_LAST\n+enum bnxt_ulp_device_id {\n+\tBNXT_ULP_DEVICE_ID_WH_PLUS = 0,\n+\tBNXT_ULP_DEVICE_ID_THOR = 1,\n+\tBNXT_ULP_DEVICE_ID_STINGRAY = 2,\n+\tBNXT_ULP_DEVICE_ID_STINGRAY2 = 3,\n+\tBNXT_ULP_DEVICE_ID_LAST = 4\n };\n \n-enum bnxt_ulp_fmf_spec {\n-\tBNXT_ULP_FMF_SPEC_IGNORE = 0,\n-\tBNXT_ULP_FMF_SPEC_LAST = 1\n+enum bnxt_ulp_hdr_type {\n+\tBNXT_ULP_HDR_TYPE_NOT_SUPPORTED = 0,\n+\tBNXT_ULP_HDR_TYPE_SUPPORTED = 1,\n+\tBNXT_ULP_HDR_TYPE_END = 2,\n+\tBNXT_ULP_HDR_TYPE_LAST = 3\n };\n \n enum bnxt_ulp_mark_enable {\n@@ -114,21 +133,6 @@ enum bnxt_ulp_mark_enable {\n \tBNXT_ULP_MARK_ENABLE_LAST = 2\n };\n \n-enum bnxt_ulp_hdr_field {\n-\tBNXT_ULP_HDR_FIELD_MPLS_TAG_NUM = 0,\n-\tBNXT_ULP_HDR_FIELD_O_VTAG_NUM = 1,\n-\tBNXT_ULP_HDR_FIELD_I_VTAG_NUM = 2,\n-\tBNXT_ULP_HDR_FIELD_SVIF_INDEX = 3,\n-\tBNXT_ULP_HDR_FIELD_LAST = 4\n-};\n-\n-enum bnxt_ulp_hdr_type {\n-\tBNXT_ULP_HDR_TYPE_NOT_SUPPORTED = 0,\n-\tBNXT_ULP_HDR_TYPE_SUPPORTED = 1,\n-\tBNXT_ULP_HDR_TYPE_END = 2,\n-\tBNXT_ULP_HDR_TYPE_LAST = 3\n-};\n-\n enum bnxt_ulp_mask_opc {\n \tBNXT_ULP_MASK_OPC_SET_TO_CONSTANT = 0,\n \tBNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD = 1,\n@@ -137,6 +141,12 @@ enum bnxt_ulp_mask_opc {\n \tBNXT_ULP_MASK_OPC_LAST = 4\n };\n \n+enum bnxt_ulp_match_type {\n+\tBNXT_ULP_MATCH_TYPE_EM = 0,\n+\tBNXT_ULP_MATCH_TYPE_WC = 1,\n+\tBNXT_ULP_MATCH_TYPE_LAST = 2\n+};\n+\n enum bnxt_ulp_priority {\n \tBNXT_ULP_PRIORITY_LEVEL_0 = 0,\n \tBNXT_ULP_PRIORITY_LEVEL_1 = 1,\n@@ -151,20 +161,22 @@ enum bnxt_ulp_priority {\n };\n \n enum bnxt_ulp_regfile_index {\n-\tBNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 0,\n-\tBNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 1,\n-\tBNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 2,\n-\tBNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 3,\n-\tBNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 4,\n-\tBNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 5,\n-\tBNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 6,\n-\tBNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 7,\n-\tBNXT_ULP_REGFILE_INDEX_ACTION_PTR_MAIN = 8,\n-\tBNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 9,\n-\tBNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 10,\n-\tBNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 11,\n-\tBNXT_ULP_REGFILE_INDEX_NOT_USED = 12,\n-\tBNXT_ULP_REGFILE_INDEX_LAST = 13\n+\tBNXT_ULP_REGFILE_INDEX_CLASS_TID = 0,\n+\tBNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 1,\n+\tBNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 2,\n+\tBNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 3,\n+\tBNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 4,\n+\tBNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 5,\n+\tBNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 6,\n+\tBNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 7,\n+\tBNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 8,\n+\tBNXT_ULP_REGFILE_INDEX_ACTION_PTR_MAIN = 9,\n+\tBNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 10,\n+\tBNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 11,\n+\tBNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 12,\n+\tBNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 13,\n+\tBNXT_ULP_REGFILE_INDEX_NOT_USED = 14,\n+\tBNXT_ULP_REGFILE_INDEX_LAST = 15\n };\n \n enum bnxt_ulp_resource_func {\n@@ -179,7 +191,7 @@ enum bnxt_ulp_resource_func {\n enum bnxt_ulp_result_opc {\n \tBNXT_ULP_RESULT_OPC_SET_TO_CONSTANT = 0,\n \tBNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP = 1,\n-\tBNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP_SZ = 2,\n+\tBNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 2,\n \tBNXT_ULP_RESULT_OPC_SET_TO_REGFILE = 3,\n \tBNXT_ULP_RESULT_OPC_LAST = 4\n };\n@@ -198,6 +210,45 @@ enum bnxt_ulp_spec_opc {\n \tBNXT_ULP_SPEC_OPC_LAST = 4\n };\n \n+enum bnxt_ulp_encap_vtag_encoding {\n+\tBNXT_ULP_ENCAP_VTAG_ENCODING_DTAG_ECAP_PRI = 4,\n+\tBNXT_ULP_ENCAP_VTAG_ENCODING_DTAG_REMAP_DIFFSERV = 5,\n+\tBNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_ECAP_PRI = 6,\n+\tBNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_DIFFSERV = 7,\n+\tBNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_0 = 8,\n+\tBNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_1 = 9,\n+\tBNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_2 = 10,\n+\tBNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_3 = 11,\n+\tBNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_4 = 12,\n+\tBNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_5 = 13,\n+\tBNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_6 = 14,\n+\tBNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_7 = 15,\n+\tBNXT_ULP_ENCAP_VTAG_ENCODING_NOP = 0,\n+\tBNXT_ULP_ENCAP_VTAG_ENCODING_STAG_ECAP_PRI = 1,\n+\tBNXT_ULP_ENCAP_VTAG_ENCODING_STAG_IVLAN_PRI = 2,\n+\tBNXT_ULP_ENCAP_VTAG_ENCODING_STAG_REMAP_DIFFSERV = 3\n+};\n+\n+enum bnxt_ulp_fdb_resource_flags {\n+\tBNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01,\n+\tBNXT_ULP_FDB_RESOURCE_FLAGS_DIR_INGR = 0x00\n+};\n+\n+enum bnxt_ulp_fdb_type {\n+\tBNXT_ULP_FDB_TYPE_DEFAULT = 1,\n+\tBNXT_ULP_FDB_TYPE_REGULAR = 0\n+};\n+\n+enum bnxt_ulp_flow_dir_bitmask {\n+\tBNXT_ULP_FLOW_DIR_BITMASK_EGR = 0x8000000000000000,\n+\tBNXT_ULP_FLOW_DIR_BITMASK_ING = 0x0000000000000000\n+};\n+\n+enum bnxt_ulp_match_type_bitmask {\n+\tBNXT_ULP_MATCH_TYPE_BITMASK_EM = 0x0000000000000000,\n+\tBNXT_ULP_MATCH_TYPE_BITMASK_WM = 0x0000000000000001\n+};\n+\n enum bnxt_ulp_sym {\n \tBNXT_ULP_SYM_BIG_ENDIAN = 0,\n \tBNXT_ULP_SYM_DECAP_FUNC_NONE = 0,\n@@ -208,6 +259,10 @@ enum bnxt_ulp_sym {\n \tBNXT_ULP_SYM_DECAP_FUNC_THRU_TL3 = 8,\n \tBNXT_ULP_SYM_DECAP_FUNC_THRU_TL4 = 9,\n \tBNXT_ULP_SYM_DECAP_FUNC_THRU_TUN = 10,\n+\tBNXT_ULP_SYM_ECV_CUSTOM_EN_NO = 0,\n+\tBNXT_ULP_SYM_ECV_CUSTOM_EN_YES = 1,\n+\tBNXT_ULP_SYM_ECV_L2_EN_NO = 0,\n+\tBNXT_ULP_SYM_ECV_L2_EN_YES = 1,\n \tBNXT_ULP_SYM_ECV_L3_TYPE_IPV4 = 4,\n \tBNXT_ULP_SYM_ECV_L3_TYPE_IPV6 = 5,\n \tBNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8847 = 6,\n@@ -224,6 +279,8 @@ enum bnxt_ulp_sym {\n \tBNXT_ULP_SYM_ECV_TUN_TYPE_NONE = 0,\n \tBNXT_ULP_SYM_ECV_TUN_TYPE_NVGRE = 4,\n \tBNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN = 2,\n+\tBNXT_ULP_SYM_ECV_VALID_NO = 0,\n+\tBNXT_ULP_SYM_ECV_VALID_YES = 1,\n \tBNXT_ULP_SYM_IP_PROTO_UDP = 17,\n \tBNXT_ULP_SYM_L2_HDR_TYPE_DIX = 0,\n \tBNXT_ULP_SYM_L2_HDR_TYPE_LLC = 2,\n@@ -244,8 +301,15 @@ enum bnxt_ulp_sym {\n \tBNXT_ULP_SYM_L4_HDR_TYPE_UPAR1 = 3,\n \tBNXT_ULP_SYM_L4_HDR_TYPE_UPAR2 = 4,\n \tBNXT_ULP_SYM_LITTLE_ENDIAN = 1,\n+\tBNXT_ULP_SYM_MATCH_TYPE_EM = 0,\n+\tBNXT_ULP_SYM_MATCH_TYPE_WM = 1,\n \tBNXT_ULP_SYM_NO = 0,\n \tBNXT_ULP_SYM_PKT_TYPE_L2 = 0,\n+\tBNXT_ULP_SYM_POP_VLAN_NO = 0,\n+\tBNXT_ULP_SYM_POP_VLAN_YES = 1,\n+\tBNXT_ULP_SYM_STINGRAY2_LOOPBACK_PORT = 3,\n+\tBNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT = 3,\n+\tBNXT_ULP_SYM_THOR_LOOPBACK_PORT = 3,\n \tBNXT_ULP_SYM_TL2_HDR_TYPE_DIX = 0,\n \tBNXT_ULP_SYM_TL3_HDR_TYPE_IPV4 = 0,\n \tBNXT_ULP_SYM_TL3_HDR_TYPE_IPV6 = 1,\n@@ -262,6 +326,7 @@ enum bnxt_ulp_sym {\n \tBNXT_ULP_SYM_TUN_HDR_TYPE_UPAR1 = 8,\n \tBNXT_ULP_SYM_TUN_HDR_TYPE_UPAR2 = 9,\n \tBNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN = 0,\n+\tBNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT = 3,\n \tBNXT_ULP_SYM_YES = 1\n };\n \n@@ -274,6 +339,7 @@ enum bnxt_ulp_act_prop_sz {\n \tBNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE = 4,\n \tBNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM = 4,\n \tBNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM = 4,\n+\tBNXT_ULP_ACT_PROP_SZ_PORT_ID = 4,\n \tBNXT_ULP_ACT_PROP_SZ_VNIC = 4,\n \tBNXT_ULP_ACT_PROP_SZ_VPORT = 4,\n \tBNXT_ULP_ACT_PROP_SZ_MARK = 4,\n@@ -317,38 +383,46 @@ enum bnxt_ulp_act_prop_idx {\n \tBNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE = 20,\n \tBNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM = 24,\n \tBNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM = 28,\n-\tBNXT_ULP_ACT_PROP_IDX_VNIC = 32,\n-\tBNXT_ULP_ACT_PROP_IDX_VPORT = 36,\n-\tBNXT_ULP_ACT_PROP_IDX_MARK = 40,\n-\tBNXT_ULP_ACT_PROP_IDX_COUNT = 44,\n-\tBNXT_ULP_ACT_PROP_IDX_METER = 48,\n-\tBNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC = 52,\n-\tBNXT_ULP_ACT_PROP_IDX_SET_MAC_DST = 60,\n-\tBNXT_ULP_ACT_PROP_IDX_OF_PUSH_VLAN = 68,\n-\tBNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_PCP = 72,\n-\tBNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_VID = 76,\n-\tBNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC = 80,\n-\tBNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST = 84,\n-\tBNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC = 88,\n-\tBNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST = 104,\n-\tBNXT_ULP_ACT_PROP_IDX_SET_TP_SRC = 120,\n-\tBNXT_ULP_ACT_PROP_IDX_SET_TP_DST = 124,\n-\tBNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0 = 128,\n-\tBNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1 = 132,\n-\tBNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2 = 136,\n-\tBNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3 = 140,\n-\tBNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4 = 144,\n-\tBNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5 = 148,\n-\tBNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6 = 152,\n-\tBNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7 = 156,\n-\tBNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC = 160,\n-\tBNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC = 166,\n-\tBNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG = 172,\n-\tBNXT_ULP_ACT_PROP_IDX_ENCAP_IP = 180,\n-\tBNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 212,\n-\tBNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 228,\n-\tBNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 232,\n-\tBNXT_ULP_ACT_PROP_IDX_LAST = 264\n+\tBNXT_ULP_ACT_PROP_IDX_PORT_ID = 32,\n+\tBNXT_ULP_ACT_PROP_IDX_VNIC = 36,\n+\tBNXT_ULP_ACT_PROP_IDX_VPORT = 40,\n+\tBNXT_ULP_ACT_PROP_IDX_MARK = 44,\n+\tBNXT_ULP_ACT_PROP_IDX_COUNT = 48,\n+\tBNXT_ULP_ACT_PROP_IDX_METER = 52,\n+\tBNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC = 56,\n+\tBNXT_ULP_ACT_PROP_IDX_SET_MAC_DST = 64,\n+\tBNXT_ULP_ACT_PROP_IDX_OF_PUSH_VLAN = 72,\n+\tBNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_PCP = 76,\n+\tBNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_VID = 80,\n+\tBNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC = 84,\n+\tBNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST = 88,\n+\tBNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC = 92,\n+\tBNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST = 108,\n+\tBNXT_ULP_ACT_PROP_IDX_SET_TP_SRC = 124,\n+\tBNXT_ULP_ACT_PROP_IDX_SET_TP_DST = 128,\n+\tBNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0 = 132,\n+\tBNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1 = 136,\n+\tBNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2 = 140,\n+\tBNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3 = 144,\n+\tBNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4 = 148,\n+\tBNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5 = 152,\n+\tBNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6 = 156,\n+\tBNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7 = 160,\n+\tBNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC = 164,\n+\tBNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC = 170,\n+\tBNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG = 176,\n+\tBNXT_ULP_ACT_PROP_IDX_ENCAP_IP = 184,\n+\tBNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 216,\n+\tBNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 232,\n+\tBNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 236,\n+\tBNXT_ULP_ACT_PROP_IDX_LAST = 268\n+};\n+enum bnxt_ulp_class_hid {\n+\tBNXT_ULP_CLASS_HID_0092 = 0x0092\n+};\n+\n+enum bnxt_ulp_act_hid {\n+\tBNXT_ULP_ACT_HID_0029 = 0x0029\n };\n \n #endif /* _ULP_TEMPLATE_DB_H_ */\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h\nindex 1bc4449..587de8a 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h\n@@ -1,130 +1,63 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n  * Copyright(c) 2014-2020 Broadcom\n- * All rights reserved_\n+ * All rights reserved.\n  */\n \n-/* date: Mon Mar  9 02:37:53 2020\n- * version: 0_0\n- */\n-\n-#ifndef _ULP_HDR_FIELD_ENUMS_H_\n-#define _ULP_HDR_FIELD_ENUMS_H_\n+#ifndef ULP_HDR_FIELD_ENUMS_H_\n+#define ULP_HDR_FIELD_ENUMS_H_\n \n enum bnxt_ulp_hf0 {\n-\tBNXT_ULP_HF0_MPLS_TAG_NUM = 0,\n-\tBNXT_ULP_HF0_O_VTAG_NUM = 1,\n-\tBNXT_ULP_HF0_I_VTAG_NUM = 2,\n-\tBNXT_ULP_HF0_SVIF_INDEX = 3,\n-\tBNXT_ULP_HF0_O_ETH_DMAC = 4,\n-\tBNXT_ULP_HF0_O_ETH_SMAC = 5,\n-\tBNXT_ULP_HF0_O_ETH_TYPE = 6,\n-\tBNXT_ULP_HF0_OO_VLAN_CFI_PRI = 7,\n-\tBNXT_ULP_HF0_OO_VLAN_VID = 8,\n-\tBNXT_ULP_HF0_OO_VLAN_TYPE = 9,\n-\tBNXT_ULP_HF0_OI_VLAN_CFI_PRI = 10,\n-\tBNXT_ULP_HF0_OI_VLAN_VID = 11,\n-\tBNXT_ULP_HF0_OI_VLAN_TYPE = 12,\n-\tBNXT_ULP_HF0_O_IPV4_VER = 13,\n-\tBNXT_ULP_HF0_O_IPV4_TOS = 14,\n-\tBNXT_ULP_HF0_O_IPV4_LEN = 15,\n-\tBNXT_ULP_HF0_O_IPV4_FRAG_ID = 16,\n-\tBNXT_ULP_HF0_O_IPV4_FRAG_OFF = 17,\n-\tBNXT_ULP_HF0_O_IPV4_TTL = 18,\n-\tBNXT_ULP_HF0_O_IPV4_NEXT_PID = 19,\n-\tBNXT_ULP_HF0_O_IPV4_CSUM = 20,\n-\tBNXT_ULP_HF0_O_IPV4_SRC_ADDR = 21,\n-\tBNXT_ULP_HF0_O_IPV4_DST_ADDR = 22,\n-\tBNXT_ULP_HF0_O_UDP_SRC_PORT = 23,\n-\tBNXT_ULP_HF0_O_UDP_DST_PORT = 24,\n-\tBNXT_ULP_HF0_O_UDP_LENGTH = 25,\n-\tBNXT_ULP_HF0_O_UDP_CSUM = 26,\n-\tBNXT_ULP_HF0_T_VXLAN_FLAGS = 27,\n-\tBNXT_ULP_HF0_T_VXLAN_RSVD0 = 28,\n-\tBNXT_ULP_HF0_T_VXLAN_VNI = 29,\n-\tBNXT_ULP_HF0_T_VXLAN_RSVD1 = 30,\n-\tBNXT_ULP_HF0_I_ETH_DMAC = 31,\n-\tBNXT_ULP_HF0_I_ETH_SMAC = 32,\n-\tBNXT_ULP_HF0_I_ETH_TYPE = 33,\n-\tBNXT_ULP_HF0_IO_VLAN_CFI_PRI = 34,\n-\tBNXT_ULP_HF0_IO_VLAN_VID = 35,\n-\tBNXT_ULP_HF0_IO_VLAN_TYPE = 36,\n-\tBNXT_ULP_HF0_II_VLAN_CFI_PRI = 37,\n-\tBNXT_ULP_HF0_II_VLAN_VID = 38,\n-\tBNXT_ULP_HF0_II_VLAN_TYPE = 39,\n-\tBNXT_ULP_HF0_I_IPV4_VER = 40,\n-\tBNXT_ULP_HF0_I_IPV4_TOS = 41,\n-\tBNXT_ULP_HF0_I_IPV4_LEN = 42,\n-\tBNXT_ULP_HF0_I_IPV4_FRAG_ID = 43,\n-\tBNXT_ULP_HF0_I_IPV4_FRAG_OFF = 44,\n-\tBNXT_ULP_HF0_I_IPV4_TTL = 45,\n-\tBNXT_ULP_HF0_I_IPV4_NEXT_PID = 46,\n-\tBNXT_ULP_HF0_I_IPV4_CSUM = 47,\n-\tBNXT_ULP_HF0_I_IPV4_SRC_ADDR = 48,\n-\tBNXT_ULP_HF0_I_IPV4_DST_ADDR = 49,\n-\tBNXT_ULP_HF0_I_UDP_SRC_PORT = 50,\n-\tBNXT_ULP_HF0_I_UDP_DST_PORT = 51,\n-\tBNXT_ULP_HF0_I_UDP_LENGTH = 52,\n-\tBNXT_ULP_HF0_I_UDP_CSUM = 53\n-};\n-\n-enum bnxt_ulp_hf1 {\n-\tBNXT_ULP_HF1_MPLS_TAG_NUM = 0,\n-\tBNXT_ULP_HF1_O_VTAG_NUM = 1,\n-\tBNXT_ULP_HF1_I_VTAG_NUM = 2,\n-\tBNXT_ULP_HF1_SVIF_INDEX = 3,\n-\tBNXT_ULP_HF1_O_ETH_DMAC = 4,\n-\tBNXT_ULP_HF1_O_ETH_SMAC = 5,\n-\tBNXT_ULP_HF1_O_ETH_TYPE = 6,\n-\tBNXT_ULP_HF1_OO_VLAN_CFI_PRI = 7,\n-\tBNXT_ULP_HF1_OO_VLAN_VID = 8,\n-\tBNXT_ULP_HF1_OO_VLAN_TYPE = 9,\n-\tBNXT_ULP_HF1_OI_VLAN_CFI_PRI = 10,\n-\tBNXT_ULP_HF1_OI_VLAN_VID = 11,\n-\tBNXT_ULP_HF1_OI_VLAN_TYPE = 12,\n-\tBNXT_ULP_HF1_O_IPV4_VER = 13,\n-\tBNXT_ULP_HF1_O_IPV4_TOS = 14,\n-\tBNXT_ULP_HF1_O_IPV4_LEN = 15,\n-\tBNXT_ULP_HF1_O_IPV4_FRAG_ID = 16,\n-\tBNXT_ULP_HF1_O_IPV4_FRAG_OFF = 17,\n-\tBNXT_ULP_HF1_O_IPV4_TTL = 18,\n-\tBNXT_ULP_HF1_O_IPV4_NEXT_PID = 19,\n-\tBNXT_ULP_HF1_O_IPV4_CSUM = 20,\n-\tBNXT_ULP_HF1_O_IPV4_SRC_ADDR = 21,\n-\tBNXT_ULP_HF1_O_IPV4_DST_ADDR = 22,\n-\tBNXT_ULP_HF1_O_UDP_SRC_PORT = 23,\n-\tBNXT_ULP_HF1_O_UDP_DST_PORT = 24,\n-\tBNXT_ULP_HF1_O_UDP_LENGTH = 25,\n-\tBNXT_ULP_HF1_O_UDP_CSUM = 26\n+\tBNXT_ULP_HF0_IDX_SVIF_INDEX              = 0,\n+\tBNXT_ULP_HF0_IDX_O_ETH_DMAC              = 1,\n+\tBNXT_ULP_HF0_IDX_O_ETH_SMAC              = 2,\n+\tBNXT_ULP_HF0_IDX_O_ETH_TYPE              = 3,\n+\tBNXT_ULP_HF0_IDX_OO_VLAN_CFI_PRI         = 4,\n+\tBNXT_ULP_HF0_IDX_OO_VLAN_VID             = 5,\n+\tBNXT_ULP_HF0_IDX_OO_VLAN_TYPE            = 6,\n+\tBNXT_ULP_HF0_IDX_OI_VLAN_CFI_PRI         = 7,\n+\tBNXT_ULP_HF0_IDX_OI_VLAN_VID             = 8,\n+\tBNXT_ULP_HF0_IDX_OI_VLAN_TYPE            = 9,\n+\tBNXT_ULP_HF0_IDX_O_IPV4_VER              = 10,\n+\tBNXT_ULP_HF0_IDX_O_IPV4_TOS              = 11,\n+\tBNXT_ULP_HF0_IDX_O_IPV4_LEN              = 12,\n+\tBNXT_ULP_HF0_IDX_O_IPV4_FRAG_ID          = 13,\n+\tBNXT_ULP_HF0_IDX_O_IPV4_FRAG_OFF         = 14,\n+\tBNXT_ULP_HF0_IDX_O_IPV4_TTL              = 15,\n+\tBNXT_ULP_HF0_IDX_O_IPV4_NEXT_PID         = 16,\n+\tBNXT_ULP_HF0_IDX_O_IPV4_CSUM             = 17,\n+\tBNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR         = 18,\n+\tBNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR         = 19,\n+\tBNXT_ULP_HF0_IDX_O_UDP_SRC_PORT          = 20,\n+\tBNXT_ULP_HF0_IDX_O_UDP_DST_PORT          = 21,\n+\tBNXT_ULP_HF0_IDX_O_UDP_LENGTH            = 22,\n+\tBNXT_ULP_HF0_IDX_O_UDP_CSUM              = 23\n };\n \n-enum bnxt_ulp_hf2 {\n-\tBNXT_ULP_HF2_MPLS_TAG_NUM = 0,\n-\tBNXT_ULP_HF2_O_VTAG_NUM = 1,\n-\tBNXT_ULP_HF2_I_VTAG_NUM = 2,\n-\tBNXT_ULP_HF2_SVIF_INDEX = 3,\n-\tBNXT_ULP_HF2_O_ETH_DMAC = 4,\n-\tBNXT_ULP_HF2_O_ETH_SMAC = 5,\n-\tBNXT_ULP_HF2_O_ETH_TYPE = 6,\n-\tBNXT_ULP_HF2_OO_VLAN_CFI_PRI = 7,\n-\tBNXT_ULP_HF2_OO_VLAN_VID = 8,\n-\tBNXT_ULP_HF2_OO_VLAN_TYPE = 9,\n-\tBNXT_ULP_HF2_OI_VLAN_CFI_PRI = 10,\n-\tBNXT_ULP_HF2_OI_VLAN_VID = 11,\n-\tBNXT_ULP_HF2_OI_VLAN_TYPE = 12,\n-\tBNXT_ULP_HF2_O_IPV4_VER = 13,\n-\tBNXT_ULP_HF2_O_IPV4_TOS = 14,\n-\tBNXT_ULP_HF2_O_IPV4_LEN = 15,\n-\tBNXT_ULP_HF2_O_IPV4_FRAG_ID = 16,\n-\tBNXT_ULP_HF2_O_IPV4_FRAG_OFF = 17,\n-\tBNXT_ULP_HF2_O_IPV4_TTL = 18,\n-\tBNXT_ULP_HF2_O_IPV4_NEXT_PID = 19,\n-\tBNXT_ULP_HF2_O_IPV4_CSUM = 20,\n-\tBNXT_ULP_HF2_O_IPV4_SRC_ADDR = 21,\n-\tBNXT_ULP_HF2_O_IPV4_DST_ADDR = 22,\n-\tBNXT_ULP_HF2_O_UDP_SRC_PORT = 23,\n-\tBNXT_ULP_HF2_O_UDP_DST_PORT = 24,\n-\tBNXT_ULP_HF2_O_UDP_LENGTH = 25,\n-\tBNXT_ULP_HF2_O_UDP_CSUM = 26\n+enum bnxt_ulp_hf_bitmask0 {\n+\tBNXT_ULP_HF0_BITMASK_SVIF_INDEX          = 0x8000000000000000,\n+\tBNXT_ULP_HF0_BITMASK_O_ETH_DMAC          = 0x4000000000000000,\n+\tBNXT_ULP_HF0_BITMASK_O_ETH_SMAC          = 0x2000000000000000,\n+\tBNXT_ULP_HF0_BITMASK_O_ETH_TYPE          = 0x1000000000000000,\n+\tBNXT_ULP_HF0_BITMASK_OO_VLAN_CFI_PRI     = 0x0800000000000000,\n+\tBNXT_ULP_HF0_BITMASK_OO_VLAN_VID         = 0x0400000000000000,\n+\tBNXT_ULP_HF0_BITMASK_OO_VLAN_TYPE        = 0x0200000000000000,\n+\tBNXT_ULP_HF0_BITMASK_OI_VLAN_CFI_PRI     = 0x0100000000000000,\n+\tBNXT_ULP_HF0_BITMASK_OI_VLAN_VID         = 0x0080000000000000,\n+\tBNXT_ULP_HF0_BITMASK_OI_VLAN_TYPE        = 0x0040000000000000,\n+\tBNXT_ULP_HF0_BITMASK_O_IPV4_VER          = 0x0020000000000000,\n+\tBNXT_ULP_HF0_BITMASK_O_IPV4_TOS          = 0x0010000000000000,\n+\tBNXT_ULP_HF0_BITMASK_O_IPV4_LEN          = 0x0008000000000000,\n+\tBNXT_ULP_HF0_BITMASK_O_IPV4_FRAG_ID      = 0x0004000000000000,\n+\tBNXT_ULP_HF0_BITMASK_O_IPV4_FRAG_OFF     = 0x0002000000000000,\n+\tBNXT_ULP_HF0_BITMASK_O_IPV4_TTL          = 0x0001000000000000,\n+\tBNXT_ULP_HF0_BITMASK_O_IPV4_NEXT_PID     = 0x0000800000000000,\n+\tBNXT_ULP_HF0_BITMASK_O_IPV4_CSUM         = 0x0000400000000000,\n+\tBNXT_ULP_HF0_BITMASK_O_IPV4_SRC_ADDR     = 0x0000200000000000,\n+\tBNXT_ULP_HF0_BITMASK_O_IPV4_DST_ADDR     = 0x0000100000000000,\n+\tBNXT_ULP_HF0_BITMASK_O_UDP_SRC_PORT      = 0x0000080000000000,\n+\tBNXT_ULP_HF0_BITMASK_O_UDP_DST_PORT      = 0x0000040000000000,\n+\tBNXT_ULP_HF0_BITMASK_O_UDP_LENGTH        = 0x0000020000000000,\n+\tBNXT_ULP_HF0_BITMASK_O_UDP_CSUM          = 0x0000010000000000\n };\n \n #endif /* _ULP_HDR_FIELD_ENUMS_H_ */\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h\nindex 8adbf7a..c2d3ccb 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h\n@@ -28,11 +28,16 @@\n #define BNXT_ULP_PROTO_HDR_TCP_NUM\t9\n #define BNXT_ULP_PROTO_HDR_VXLAN_NUM\t4\n #define BNXT_ULP_PROTO_HDR_MAX\t\t128\n+#define BNXT_ULP_PROTO_HDR_FIELD_SVIF_IDX\t0\n \n struct ulp_rte_hdr_bitmap {\n \tuint64_t\tbits;\n };\n \n+struct ulp_rte_field_bitmap {\n+\tuint64_t\tbits;\n+};\n+\n /* Structure to store the protocol fields */\n #define RTE_PARSER_FLOW_HDR_FIELD_SIZE\t\t16\n struct ulp_rte_hdr_field {\n@@ -53,7 +58,9 @@ struct ulp_rte_act_prop {\n /* Structure to be used for passing all the parser functions */\n struct ulp_rte_parser_params {\n \tstruct ulp_rte_hdr_bitmap\thdr_bitmap;\n+\tstruct ulp_rte_field_bitmap\tfld_bitmap;\n \tstruct ulp_rte_hdr_field\thdr_field[BNXT_ULP_PROTO_HDR_MAX];\n+\tuint32_t\t\t\tcomp_fld[BNXT_ULP_CHF_IDX_LAST];\n \tuint32_t\t\t\tfield_idx;\n \tuint32_t\t\t\tvlan_idx;\n \tstruct ulp_rte_act_bitmap\tact_bitmap;\n@@ -72,11 +79,6 @@ struct bnxt_ulp_rte_hdr_info {\n /* Flow Parser Header Information Structure Array defined in template source*/\n extern struct bnxt_ulp_rte_hdr_info\tulp_hdr_info[];\n \n-struct bnxt_ulp_matcher_field_info {\n-\tenum bnxt_ulp_fmf_mask\tmask_opcode;\n-\tenum bnxt_ulp_fmf_spec\tspec_opcode;\n-};\n-\n /* Flow Parser Action Information Structure */\n struct bnxt_ulp_rte_act_info {\n \tenum bnxt_ulp_act_type\t\t\t\t\tact_type;\n@@ -98,12 +100,22 @@ struct bnxt_ulp_header_match_info {\n \tuint32_t\t\t\t\tact_vnic;\n };\n \n-/* Flow Matcher templates Structure Array defined in template source*/\n-extern struct bnxt_ulp_header_match_info  ulp_ingress_hdr_match_list[];\n-extern struct bnxt_ulp_header_match_info  ulp_egress_hdr_match_list[];\n+struct ulp_rte_bitmap {\n+\tuint64_t\tbits;\n+};\n+\n+struct bnxt_ulp_class_match_info {\n+\tstruct ulp_rte_bitmap\thdr_sig;\n+\tstruct ulp_rte_bitmap\tfield_sig;\n+\tuint32_t\t\tclass_hid;\n+\tuint32_t\t\tclass_tid;\n+\tuint8_t\t\t\tact_vnic;\n+\tuint8_t\t\t\twc_pri;\n+};\n \n-/* Flow field match Information Structure Array defined in template source*/\n-extern struct bnxt_ulp_matcher_field_info\tulp_field_match[];\n+/* Flow Matcher templates Structure for class entries */\n+extern uint16_t ulp_class_sig_tbl[];\n+extern struct bnxt_ulp_class_match_info ulp_class_match_list[];\n \n /* Flow Matcher Action structures */\n struct bnxt_ulp_action_match_info {\n@@ -111,9 +123,15 @@ struct bnxt_ulp_action_match_info {\n \tuint32_t\t\t\t\tact_tmpl_id;\n };\n \n-/* Flow Matcher templates Structure Array defined in template source */\n-extern struct bnxt_ulp_action_match_info  ulp_ingress_act_match_list[];\n-extern struct bnxt_ulp_action_match_info  ulp_egress_act_match_list[];\n+struct bnxt_ulp_act_match_info {\n+\tstruct ulp_rte_bitmap\tact_sig;\n+\tuint32_t\t\tact_hid;\n+\tuint32_t\t\tact_tid;\n+};\n+\n+/* Flow Matcher templates Structure for action entries */\n+extern\tuint16_t ulp_act_sig_tbl[];\n+extern struct bnxt_ulp_act_match_info ulp_act_match_list[];\n \n /* Device specific parameters */\n struct bnxt_ulp_device_params {\n@@ -179,7 +197,7 @@ struct bnxt_ulp_mapper_act_tbl_info {\n };\n \n struct bnxt_ulp_mapper_class_key_field_info {\n-\tuint8_t\t\t\tname[64];\n+\tuint8_t\t\t\tdescription[64];\n \tenum bnxt_ulp_mask_opc\tmask_opcode;\n \tenum bnxt_ulp_spec_opc\tspec_opcode;\n \tuint16_t\t\tfield_bit_size;\n@@ -188,14 +206,14 @@ struct bnxt_ulp_mapper_class_key_field_info {\n };\n \n struct bnxt_ulp_mapper_result_field_info {\n-\tuint8_t\t\t\t\tname[64];\n+\tuint8_t\t\t\t\tdescription[64];\n \tenum bnxt_ulp_result_opc\tresult_opcode;\n \tuint16_t\t\t\tfield_bit_size;\n \tuint8_t\t\t\t\tresult_operand[16];\n };\n \n struct bnxt_ulp_mapper_ident_info {\n-\tuint8_t\t\tname[64];\n+\tuint8_t\t\tdescription[64];\n \tuint32_t\tresource_func;\n \n \tuint16_t\tident_type;\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c\nindex 1d463cd..521109d 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c\n@@ -519,3 +519,36 @@ int32_t ulp_buffer_is_empty(const uint8_t *buf, uint32_t size)\n {\n \treturn buf[0] == 0 && !memcmp(buf, buf + 1, size - 1);\n }\n+\n+/* Function to check if bitmap is zero.Return 1 on success */\n+uint32_t ulp_bitmap_is_zero(uint8_t *bitmap, int32_t size)\n+{\n+\twhile (size-- > 0) {\n+\t\tif (*bitmap != 0)\n+\t\t\treturn 0;\n+\t\tbitmap++;\n+\t}\n+\treturn 1;\n+}\n+\n+/* Function to check if bitmap is ones. Return 1 on success */\n+uint32_t ulp_bitmap_is_ones(uint8_t *bitmap, int32_t size)\n+{\n+\twhile (size-- > 0) {\n+\t\tif (*bitmap != 0xFF)\n+\t\t\treturn 0;\n+\t\tbitmap++;\n+\t}\n+\treturn 1;\n+}\n+\n+/* Function to check if bitmap is not zero. Return 1 on success */\n+uint32_t ulp_bitmap_notzero(uint8_t *bitmap, int32_t size)\n+{\n+\twhile (size-- > 0) {\n+\t\tif (*bitmap != 0)\n+\t\t\treturn 1;\n+\t\tbitmap++;\n+\t}\n+\treturn 0;\n+}\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h\nindex db88546..e7f2e3b 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_utils.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h\n@@ -16,7 +16,7 @@\n #define ULP_BITMAP_SET(bitmap, val)\t((bitmap) |= (val))\n #define ULP_BITMAP_RESET(bitmap, val)\t((bitmap) &= ~(val))\n #define ULP_BITMAP_ISSET(bitmap, val)\t((bitmap) & (val))\n-#define ULP_BITSET_CMP(b1, b2)  memcmp(&(b1)->bits, \\\n+#define ULP_BITMAP_CMP(b1, b2)  memcmp(&(b1)->bits, \\\n \t\t\t\t&(b2)->bits, sizeof((b1)->bits))\n /*\n  * Macros for bitmap sets and gets\n@@ -50,6 +50,12 @@\n /* Macro to convert bits to bytes with no round off*/\n #define ULP_BITS_2_BYTE_NR(bits_x)\t((bits_x) / 8)\n \n+/* Macros to read the computed fields */\n+#define ULP_UTIL_CHF_IDX_RD(params, idx) \\\n+\trte_be_to_cpu_32((params)->comp_fld[(idx)])\n+\n+#define ULP_UTIL_CHF_IDX_WR(params, idx, val)\t\\\n+\t((params)->comp_fld[(idx)] = rte_cpu_to_be_32((val)))\n /*\n  * Making the blob statically sized to 128 bytes for now.\n  * The blob must be initialized with ulp_blob_init prior to using.\n@@ -276,4 +282,13 @@ ulp_encap_buffer_copy(uint8_t *dst,\n  */\n int32_t ulp_buffer_is_empty(const uint8_t *buf, uint32_t size);\n \n+/* Function to check if bitmap is zero.Return 1 on success */\n+uint32_t ulp_bitmap_is_zero(uint8_t *bitmap, int32_t size);\n+\n+/* Function to check if bitmap is ones. Return 1 on success */\n+uint32_t ulp_bitmap_is_ones(uint8_t *bitmap, int32_t size);\n+\n+/* Function to check if bitmap is not zero. Return 1 on success */\n+uint32_t ulp_bitmap_notzero(uint8_t *bitmap, int32_t size);\n+\n #endif /* _ULP_UTILS_H_ */\n",
    "prefixes": [
        "07/11"
    ]
}