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GET /api/patches/68160/?format=api
{ "id": 68160, "url": "http://patches.dpdk.org/api/patches/68160/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200410164127.54229-2-gavin.hu@arm.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200410164127.54229-2-gavin.hu@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200410164127.54229-2-gavin.hu@arm.com", "date": "2020-04-10T16:41:21", "name": "[RFC,v2,1/7] eal: introduce new class of barriers for DMA use cases", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "bcb63394d2c029347ce7c3803349d1dc393a4b98", "submitter": { "id": 1018, "url": "http://patches.dpdk.org/api/people/1018/?format=api", "name": "Gavin Hu", "email": "gavin.hu@arm.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200410164127.54229-2-gavin.hu@arm.com/mbox/", "series": [ { "id": 9308, "url": "http://patches.dpdk.org/api/series/9308/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=9308", "date": "2020-04-10T16:41:20", "name": "introduce new barrier class and use it for mlx5 PMD", "version": 2, "mbox": "http://patches.dpdk.org/series/9308/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/68160/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/68160/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BB67EA0598;\n\tFri, 10 Apr 2020 18:41:51 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6CF371D5D0;\n\tFri, 10 Apr 2020 18:41:48 +0200 (CEST)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by dpdk.org (Postfix) with ESMTP id DE2F41D5CF\n for <dev@dpdk.org>; Fri, 10 Apr 2020 18:41:46 +0200 (CEST)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5755930E;\n Fri, 10 Apr 2020 09:41:46 -0700 (PDT)", "from net-arm-thunderx2-01.shanghai.arm.com\n (net-arm-thunderx2-01.shanghai.arm.com [10.169.41.214])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 26E633F52E;\n Fri, 10 Apr 2020 09:41:41 -0700 (PDT)" ], "From": "Gavin Hu <gavin.hu@arm.com>", "To": "dev@dpdk.org", "Cc": "nd@arm.com, david.marchand@redhat.com, thomas@monjalon.net,\n rasland@mellanox.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com,\n konstantin.ananyev@intel.com, matan@mellanox.com, shahafs@mellanox.com,\n viacheslavo@mellanox.com, jerinj@marvell.com, Honnappa.Nagarahalli@arm.com,\n ruifeng.wang@arm.com, phil.yang@arm.com, joyce.kong@arm.com,\n steve.capper@arm.com", "Date": "Sat, 11 Apr 2020 00:41:21 +0800", "Message-Id": "<20200410164127.54229-2-gavin.hu@arm.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": [ "<20200410164127.54229-1-gavin.hu@arm.com>", "<20200213123854.203566-1-gavin.hu@arm.com>" ], "References": [ "<20200410164127.54229-1-gavin.hu@arm.com>", "<20200213123854.203566-1-gavin.hu@arm.com>" ], "Subject": "[dpdk-dev] [PATCH RFC v2 1/7] eal: introduce new class of barriers\n\tfor DMA use cases", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "In DPDK we use rte_*mb barriers to ensure that memory accesses to DMA\nregions are observed before MMIO accesses to hardware registers.\n\nOn AArch64, the rte_*mb barriers are implemented by \"DSB\" (Data\nSynchronisation Barrier) style instructions which are the strongest\nbarriers possible.\n\nRecently, however, it has been realised [1], that for devices where the\nMMIO regions are shared between all CPUs, that it is possible to relax\nthis memory barrier.\n\nThere are cases where we wish to retain the strength of the rte_*mb\nmemory barriers; thus rather than relax rte_*mb we opt instead to\nintroduce a new class of barrier rte_dma_*mb.\n\nFor AArch64, rte_dma_*mb will be implemented by a relaxed \"DMB OSH\"\nstyle of barrier.\n\nFor other architectures, we implement rte_dma_*mb as rte_*mb so this\nshould not result in any functional changes.\n\n[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/\ncommit/?id=22ec71615d824f4f11d38d0e55a88d8956b7e45f\n\nSigned-off-by: Gavin Hu <gavin.hu@arm.com>\nReviewed-by: Steve Capper <steve.capper@arm.com>\n---\n lib/librte_eal/arm/include/rte_atomic_32.h | 6 ++++\n lib/librte_eal/arm/include/rte_atomic_64.h | 6 ++++\n lib/librte_eal/include/generic/rte_atomic.h | 31 +++++++++++++++++++++\n lib/librte_eal/ppc/include/rte_atomic.h | 6 ++++\n lib/librte_eal/x86/include/rte_atomic.h | 6 ++++\n 5 files changed, 55 insertions(+)", "diff": "diff --git a/lib/librte_eal/arm/include/rte_atomic_32.h b/lib/librte_eal/arm/include/rte_atomic_32.h\nindex 7dc0d06d1..80208467e 100644\n--- a/lib/librte_eal/arm/include/rte_atomic_32.h\n+++ b/lib/librte_eal/arm/include/rte_atomic_32.h\n@@ -33,6 +33,12 @@ extern \"C\" {\n \n #define rte_io_rmb() rte_rmb()\n \n+#define rte_dma_mb() rte_mb()\n+\n+#define rte_dma_wmb() rte_wmb()\n+\n+#define rte_dma_rmb() rte_rmb()\n+\n #define rte_cio_wmb() rte_wmb()\n \n #define rte_cio_rmb() rte_rmb()\ndiff --git a/lib/librte_eal/arm/include/rte_atomic_64.h b/lib/librte_eal/arm/include/rte_atomic_64.h\nindex 7b7099cdc..608726c29 100644\n--- a/lib/librte_eal/arm/include/rte_atomic_64.h\n+++ b/lib/librte_eal/arm/include/rte_atomic_64.h\n@@ -37,6 +37,12 @@ extern \"C\" {\n \n #define rte_io_rmb() rte_rmb()\n \n+#define rte_dma_mb() asm volatile(\"dmb osh\" : : : \"memory\")\n+\n+#define rte_dma_wmb() asm volatile(\"dmb oshst\" : : : \"memory\")\n+\n+#define rte_dma_rmb() asm volatile(\"dmb oshld\" : : : \"memory\")\n+\n #define rte_cio_wmb() asm volatile(\"dmb oshst\" : : : \"memory\")\n \n #define rte_cio_rmb() asm volatile(\"dmb oshld\" : : : \"memory\")\ndiff --git a/lib/librte_eal/include/generic/rte_atomic.h b/lib/librte_eal/include/generic/rte_atomic.h\nindex e6ab15a97..042264c7e 100644\n--- a/lib/librte_eal/include/generic/rte_atomic.h\n+++ b/lib/librte_eal/include/generic/rte_atomic.h\n@@ -107,6 +107,37 @@ static inline void rte_io_wmb(void);\n static inline void rte_io_rmb(void);\n ///@}\n \n+/** @name DMA Memory Barrier\n+ */\n+///@{\n+/**\n+ * memory barrier for DMA use cases\n+ *\n+ * Guarantees that the LOAD and STORE operations that precede the rte_dma_mb()\n+ * call are visible to CPU and I/O device that is shared between all CPUs\n+ * before the LOAD and STORE operations that follow it.\n+ */\n+static inline void rte_dma_mb(void);\n+\n+/**\n+ * Write memory barrier for DMA use cases\n+ *\n+ * Guarantees that the STORE operations that precede the rte_dma_wmb() call are\n+ * visible to CPU and I/O device that is shared between all CPUs before the\n+ * STORE operations that follow it.\n+ */\n+static inline void rte_dma_wmb(void);\n+\n+/**\n+ * Read memory barrier for DMA use cases\n+ *\n+ * Guarantees that the LOAD operations that precede the rte_dma_rmb() call are\n+ * visible to CPU and IO device that is shared between all CPUs before the LOAD\n+ * operations that follow it.\n+ */\n+static inline void rte_dma_rmb(void);\n+///@}\n+\n /** @name Coherent I/O Memory Barrier\n *\n * Coherent I/O memory barrier is a lightweight version of I/O memory\ndiff --git a/lib/librte_eal/ppc/include/rte_atomic.h b/lib/librte_eal/ppc/include/rte_atomic.h\nindex 7e3e13118..faa36bb76 100644\n--- a/lib/librte_eal/ppc/include/rte_atomic.h\n+++ b/lib/librte_eal/ppc/include/rte_atomic.h\n@@ -36,6 +36,12 @@ extern \"C\" {\n \n #define rte_io_rmb() rte_rmb()\n \n+#define rte_dma_mb() rte_mb()\n+\n+#define rte_dma_wmb() rte_wmb()\n+\n+#define rte_dma_rmb() rte_rmb()\n+\n #define rte_cio_wmb() rte_wmb()\n \n #define rte_cio_rmb() rte_rmb()\ndiff --git a/lib/librte_eal/x86/include/rte_atomic.h b/lib/librte_eal/x86/include/rte_atomic.h\nindex 148398f50..0b1d452f3 100644\n--- a/lib/librte_eal/x86/include/rte_atomic.h\n+++ b/lib/librte_eal/x86/include/rte_atomic.h\n@@ -79,6 +79,12 @@ rte_smp_mb(void)\n \n #define rte_io_rmb() rte_compiler_barrier()\n \n+#define rte_dma_mb() rte_mb()\n+\n+#define rte_dma_wmb() rte_wmb()\n+\n+#define rte_dma_rmb() rte_rmb()\n+\n #define rte_cio_wmb() rte_compiler_barrier()\n \n #define rte_cio_rmb() rte_compiler_barrier()\n", "prefixes": [ "RFC", "v2", "1/7" ] }