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Update a patch.
GET /api/patches/67375/?format=api
{ "id": 67375, "url": "http://patches.dpdk.org/api/patches/67375/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1585526580-113508-10-git-send-email-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1585526580-113508-10-git-send-email-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1585526580-113508-10-git-send-email-nicolas.chautru@intel.com", "date": "2020-03-30T00:02:56", "name": "[v2,09/13] baseband/fpga_5gnr_fec: add debug functionality", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "51cfb8d7e6470844b8073f0de7aa08f70a12cf24", "submitter": { "id": 1314, "url": "http://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1585526580-113508-10-git-send-email-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 9086, "url": "http://patches.dpdk.org/api/series/9086/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=9086", "date": "2020-03-30T00:02:47", "name": "drivers/baseband: add PMD for FPGA 5GNR FEC", "version": 2, "mbox": "http://patches.dpdk.org/series/9086/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/67375/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/67375/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2A4B6A0562;\n\tMon, 30 Mar 2020 02:05:02 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 8F97D1C02D;\n\tMon, 30 Mar 2020 02:04:07 +0200 (CEST)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by dpdk.org (Postfix) with ESMTP id 89750374C\n for <dev@dpdk.org>; Mon, 30 Mar 2020 02:03:53 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 29 Mar 2020 17:03:51 -0700", "from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210])\n by orsmga003.jf.intel.com with ESMTP; 29 Mar 2020 17:03:51 -0700" ], "IronPort-SDR": [ "\n 3uQc06/yaTxeKcRPfHMBD1vo1EbxS6ZNVtqA3ZwzAQr/e1WieZvLeU4Cqrd6vTttkroVzoO1EL\n Z0EfKHh73R1A==", "\n KqFHKNl/afaGSaxYFWmrY5kZrKYYuZ4AMbX0TJpVeJUBbyEHf1krQumAcPqx6Yk54maTq+O9Jh\n c4BQi4UvQ/2Q==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.72,322,1580803200\"; d=\"scan'208\";a=\"248455355\"", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\takhil.goyal@nxp.com", "Cc": "bruce.richardson@intel.com,\n\tNicolas Chautru <nicolas.chautru@intel.com>", "Date": "Sun, 29 Mar 2020 17:02:56 -0700", "Message-Id": "<1585526580-113508-10-git-send-email-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1585526580-113508-1-git-send-email-nicolas.chautru@intel.com>", "References": "<1585526580-113508-1-git-send-email-nicolas.chautru@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 09/13] baseband/fpga_5gnr_fec: add debug\n\tfunctionality", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Adding functionality for debug mode to be more\nverbose and catch error from unsupported configuration.\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\n---\n drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 364 +++++++++++++++++++++\n 1 file changed, 364 insertions(+)", "diff": "diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\nindex 64d32e4..389257d 100644\n--- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n+++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n@@ -109,6 +109,169 @@\n \treturn rte_le_to_cpu_32(ret);\n }\n \n+#ifdef RTE_LIBRTE_BBDEV_DEBUG\n+\n+/* Read a register of FPGA 5GNR FEC device */\n+static uint16_t\n+fpga_reg_read_16(void *mmio_base, uint32_t offset)\n+{\n+\tvoid *reg_addr = RTE_PTR_ADD(mmio_base, offset);\n+\tuint16_t ret = *((volatile uint16_t *)(reg_addr));\n+\treturn rte_le_to_cpu_16(ret);\n+}\n+\n+/* Read Ring Control Register of FPGA 5GNR FEC device */\n+static inline void\n+print_ring_reg_debug_info(void *mmio_base, uint32_t offset)\n+{\n+\trte_bbdev_log_debug(\n+\t\t\"FPGA MMIO base address @ %p | Ring Control Register @ offset = 0x%08\"\n+\t\tPRIx32, mmio_base, offset);\n+\trte_bbdev_log_debug(\n+\t\t\"RING_BASE_ADDR = 0x%016\"PRIx64,\n+\t\tfpga_reg_read_64(mmio_base, offset));\n+\trte_bbdev_log_debug(\n+\t\t\"RING_HEAD_ADDR = 0x%016\"PRIx64,\n+\t\tfpga_reg_read_64(mmio_base, offset +\n+\t\t\t\tFPGA_5GNR_FEC_RING_HEAD_ADDR));\n+\trte_bbdev_log_debug(\n+\t\t\"RING_SIZE = 0x%04\"PRIx16,\n+\t\tfpga_reg_read_16(mmio_base, offset +\n+\t\t\t\tFPGA_5GNR_FEC_RING_SIZE));\n+\trte_bbdev_log_debug(\n+\t\t\"RING_MISC = 0x%02\"PRIx8,\n+\t\tfpga_reg_read_8(mmio_base, offset +\n+\t\t\t\tFPGA_5GNR_FEC_RING_MISC));\n+\trte_bbdev_log_debug(\n+\t\t\"RING_ENABLE = 0x%02\"PRIx8,\n+\t\tfpga_reg_read_8(mmio_base, offset +\n+\t\t\t\tFPGA_5GNR_FEC_RING_ENABLE));\n+\trte_bbdev_log_debug(\n+\t\t\"RING_FLUSH_QUEUE_EN = 0x%02\"PRIx8,\n+\t\tfpga_reg_read_8(mmio_base, offset +\n+\t\t\t\tFPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN));\n+\trte_bbdev_log_debug(\n+\t\t\"RING_SHADOW_TAIL = 0x%04\"PRIx16,\n+\t\tfpga_reg_read_16(mmio_base, offset +\n+\t\t\t\tFPGA_5GNR_FEC_RING_SHADOW_TAIL));\n+\trte_bbdev_log_debug(\n+\t\t\"RING_HEAD_POINT = 0x%04\"PRIx16,\n+\t\tfpga_reg_read_16(mmio_base, offset +\n+\t\t\t\tFPGA_5GNR_FEC_RING_HEAD_POINT));\n+}\n+\n+/* Read Static Register of FPGA 5GNR FEC device */\n+static inline void\n+print_static_reg_debug_info(void *mmio_base)\n+{\n+\tuint16_t config = fpga_reg_read_16(mmio_base,\n+\t\t\tFPGA_5GNR_FEC_CONFIGURATION);\n+\tuint8_t qmap_done = fpga_reg_read_8(mmio_base,\n+\t\t\tFPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE);\n+\tuint16_t lb_factor = fpga_reg_read_16(mmio_base,\n+\t\t\tFPGA_5GNR_FEC_LOAD_BALANCE_FACTOR);\n+\tuint16_t ring_desc_len = fpga_reg_read_16(mmio_base,\n+\t\t\tFPGA_5GNR_FEC_RING_DESC_LEN);\n+\tuint16_t flr_time_out = fpga_reg_read_16(mmio_base,\n+\t\t\tFPGA_5GNR_FEC_FLR_TIME_OUT);\n+\n+\trte_bbdev_log_debug(\"UL.DL Weights = %u.%u\",\n+\t\t\t((uint8_t)config), ((uint8_t)(config >> 8)));\n+\trte_bbdev_log_debug(\"UL.DL Load Balance = %u.%u\",\n+\t\t\t((uint8_t)lb_factor), ((uint8_t)(lb_factor >> 8)));\n+\trte_bbdev_log_debug(\"Queue-PF/VF Mapping Table = %s\",\n+\t\t\t(qmap_done > 0) ? \"READY\" : \"NOT-READY\");\n+\trte_bbdev_log_debug(\"Ring Descriptor Size = %u bytes\",\n+\t\t\tring_desc_len*FPGA_RING_DESC_LEN_UNIT_BYTES);\n+\trte_bbdev_log_debug(\"FLR Timeout = %f usec\",\n+\t\t\t(float)flr_time_out*FPGA_FLR_TIMEOUT_UNIT);\n+}\n+\n+/* Print decode DMA Descriptor of FPGA 5GNR Decoder device */\n+static void\n+print_dma_dec_desc_debug_info(union fpga_dma_desc *desc)\n+{\n+\trte_bbdev_log_debug(\"DMA response desc %p\\n\"\n+\t\t\"\\t-- done(%\"PRIu32\") | iter(%\"PRIu32\") | et_pass(%\"PRIu32\")\"\n+\t\t\" | crcb_pass (%\"PRIu32\") | error(%\"PRIu32\")\\n\"\n+\t\t\"\\t-- qm_idx(%\"PRIu32\") | max_iter(%\"PRIu32\") | \"\n+\t\t\"bg_idx (%\"PRIu32\") | harqin_en(%\"PRIu32\") | zc(%\"PRIu32\")\\n\"\n+\t\t\"\\t-- hbstroe_offset(%\"PRIu32\") | num_null (%\"PRIu32\") \"\n+\t\t\"| irq_en(%\"PRIu32\")\\n\"\n+\t\t\"\\t-- ncb(%\"PRIu32\") | desc_idx (%\"PRIu32\") | \"\n+\t\t\"drop_crc24b(%\"PRIu32\") | RV (%\"PRIu32\")\\n\"\n+\t\t\"\\t-- crc24b_ind(%\"PRIu32\") | et_dis (%\"PRIu32\")\\n\"\n+\t\t\"\\t-- harq_input_length(%\"PRIu32\") | rm_e(%\"PRIu32\")\\n\"\n+\t\t\"\\t-- cbs_in_op(%\"PRIu32\") | in_add (0x%08\"PRIx32\"%08\"PRIx32\")\"\n+\t\t\"| out_add (0x%08\"PRIx32\"%08\"PRIx32\")\",\n+\t\tdesc,\n+\t\t(uint32_t)desc->dec_req.done,\n+\t\t(uint32_t)desc->dec_req.iter,\n+\t\t(uint32_t)desc->dec_req.et_pass,\n+\t\t(uint32_t)desc->dec_req.crcb_pass,\n+\t\t(uint32_t)desc->dec_req.error,\n+\t\t(uint32_t)desc->dec_req.qm_idx,\n+\t\t(uint32_t)desc->dec_req.max_iter,\n+\t\t(uint32_t)desc->dec_req.bg_idx,\n+\t\t(uint32_t)desc->dec_req.harqin_en,\n+\t\t(uint32_t)desc->dec_req.zc,\n+\t\t(uint32_t)desc->dec_req.hbstroe_offset,\n+\t\t(uint32_t)desc->dec_req.num_null,\n+\t\t(uint32_t)desc->dec_req.irq_en,\n+\t\t(uint32_t)desc->dec_req.ncb,\n+\t\t(uint32_t)desc->dec_req.desc_idx,\n+\t\t(uint32_t)desc->dec_req.drop_crc24b,\n+\t\t(uint32_t)desc->dec_req.rv,\n+\t\t(uint32_t)desc->dec_req.crc24b_ind,\n+\t\t(uint32_t)desc->dec_req.et_dis,\n+\t\t(uint32_t)desc->dec_req.harq_input_length,\n+\t\t(uint32_t)desc->dec_req.rm_e,\n+\t\t(uint32_t)desc->dec_req.cbs_in_op,\n+\t\t(uint32_t)desc->dec_req.in_addr_hi,\n+\t\t(uint32_t)desc->dec_req.in_addr_lw,\n+\t\t(uint32_t)desc->dec_req.out_addr_hi,\n+\t\t(uint32_t)desc->dec_req.out_addr_lw);\n+\tuint32_t *word = (uint32_t *) desc;\n+\trte_bbdev_log_debug(\"%08\"PRIx32\"\\n%08\"PRIx32\"\\n%08\"PRIx32\"\\n%08\"PRIx32\"\\n\"\n+\t\t\t\"%08\"PRIx32\"\\n%08\"PRIx32\"\\n%08\"PRIx32\"\\n%08\"PRIx32\"\\n\",\n+\t\t\tword[0], word[1], word[2], word[3],\n+\t\t\tword[4], word[5], word[6], word[7]);\n+}\n+\n+/* Print decode DMA Descriptor of FPGA 5GNR encoder device */\n+static void\n+print_dma_enc_desc_debug_info(union fpga_dma_desc *desc)\n+{\n+\trte_bbdev_log_debug(\"DMA response desc %p\\n\"\n+\t\t\t\"%\"PRIu32\" %\"PRIu32\"\\n\"\n+\t\t\t\"K' %\"PRIu32\" E %\"PRIu32\" desc %\"PRIu32\" Z %\"PRIu32\"\\n\"\n+\t\t\t\"BG %\"PRIu32\" Qm %\"PRIu32\" CRC %\"PRIu32\" IRQ %\"PRIu32\"\\n\"\n+\t\t\t\"k0 %\"PRIu32\" Ncb %\"PRIu32\" F %\"PRIu32\"\\n\",\n+\t\t\tdesc,\n+\t\t\t(uint32_t)desc->enc_req.done,\n+\t\t\t(uint32_t)desc->enc_req.error,\n+\n+\t\t\t(uint32_t)desc->enc_req.k_,\n+\t\t\t(uint32_t)desc->enc_req.rm_e,\n+\t\t\t(uint32_t)desc->enc_req.desc_idx,\n+\t\t\t(uint32_t)desc->enc_req.zc,\n+\n+\t\t\t(uint32_t)desc->enc_req.bg_idx,\n+\t\t\t(uint32_t)desc->enc_req.qm_idx,\n+\t\t\t(uint32_t)desc->enc_req.crc_en,\n+\t\t\t(uint32_t)desc->enc_req.irq_en,\n+\n+\t\t\t(uint32_t)desc->enc_req.k0,\n+\t\t\t(uint32_t)desc->enc_req.ncb,\n+\t\t\t(uint32_t)desc->enc_req.num_null);\n+\tuint32_t *word = (uint32_t *) desc;\n+\trte_bbdev_log_debug(\"%08\"PRIx32\"\\n%08\"PRIx32\"\\n%08\"PRIx32\"\\n%08\"PRIx32\"\\n\"\n+\t\t\t\"%08\"PRIx32\"\\n%08\"PRIx32\"\\n%08\"PRIx32\"\\n%08\"PRIx32\"\\n\",\n+\t\t\tword[0], word[1], word[2], word[3],\n+\t\t\tword[4], word[5], word[6], word[7]);\n+}\n+\n+#endif\n \n static int\n fpga_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)\n@@ -445,6 +608,10 @@\n \trte_bbdev_log_debug(\"BBDEV queue[%d] set up for FPGA queue[%d]\",\n \t\t\tqueue_id, q_idx);\n \n+#ifdef RTE_LIBRTE_BBDEV_DEBUG\n+\t/* Read FPGA Ring Control Registers after configuration*/\n+\tprint_ring_reg_debug_info(d->mmio_base, ring_offset);\n+#endif\n \treturn 0;\n }\n \n@@ -569,6 +736,7 @@\n \t.queue_start = fpga_queue_start,\n \t.queue_release = fpga_queue_release,\n };\n+\n static inline void\n fpga_dma_enqueue(struct fpga_queue *q, uint16_t num_desc,\n \t\tstruct rte_bbdev_stats *queue_stats)\n@@ -813,6 +981,96 @@\n \treturn 0;\n }\n \n+#ifdef RTE_LIBRTE_BBDEV_DEBUG\n+/* Validates LDPC encoder parameters */\n+static int\n+validate_enc_op(struct rte_bbdev_enc_op *op __rte_unused)\n+{\n+\tstruct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc;\n+\tstruct rte_bbdev_op_enc_ldpc_cb_params *cb = NULL;\n+\tstruct rte_bbdev_op_enc_ldpc_tb_params *tb = NULL;\n+\n+\n+\tif (ldpc_enc->input.length >\n+\t\t\tRTE_BBDEV_LDPC_MAX_CB_SIZE >> 3) {\n+\t\trte_bbdev_log(ERR, \"CB size (%u) is too big, max: %d\",\n+\t\t\t\tldpc_enc->input.length,\n+\t\t\t\tRTE_BBDEV_LDPC_MAX_CB_SIZE);\n+\t\treturn -1;\n+\t}\n+\n+\tif (op->mempool == NULL) {\n+\t\trte_bbdev_log(ERR, \"Invalid mempool pointer\");\n+\t\treturn -1;\n+\t}\n+\tif (ldpc_enc->input.data == NULL) {\n+\t\trte_bbdev_log(ERR, \"Invalid input pointer\");\n+\t\treturn -1;\n+\t}\n+\tif (ldpc_enc->output.data == NULL) {\n+\t\trte_bbdev_log(ERR, \"Invalid output pointer\");\n+\t\treturn -1;\n+\t}\n+\tif ((ldpc_enc->basegraph > 2) || (ldpc_enc->basegraph == 0)) {\n+\t\trte_bbdev_log(ERR,\n+\t\t\t\t\"basegraph (%u) is out of range 1 <= value <= 2\",\n+\t\t\t\tldpc_enc->basegraph);\n+\t\treturn -1;\n+\t}\n+\tif (ldpc_enc->code_block_mode > 1) {\n+\t\trte_bbdev_log(ERR,\n+\t\t\t\t\"code_block_mode (%u) is out of range 0:Tb 1:CB\",\n+\t\t\t\tldpc_enc->code_block_mode);\n+\t\treturn -1;\n+\t}\n+\n+\tif (ldpc_enc->code_block_mode == 0) {\n+\t\ttb = &ldpc_enc->tb_params;\n+\t\tif (tb->c == 0) {\n+\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\t\"c (%u) is out of range 1 <= value <= %u\",\n+\t\t\t\t\ttb->c, RTE_BBDEV_LDPC_MAX_CODE_BLOCKS);\n+\t\t\treturn -1;\n+\t\t}\n+\t\tif (tb->cab > tb->c) {\n+\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\t\"cab (%u) is greater than c (%u)\",\n+\t\t\t\t\ttb->cab, tb->c);\n+\t\t\treturn -1;\n+\t\t}\n+\t\tif ((tb->ea < RTE_BBDEV_LDPC_MIN_CB_SIZE)\n+\t\t\t\t&& tb->r < tb->cab) {\n+\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\t\"ea (%u) is less than %u or it is not even\",\n+\t\t\t\t\ttb->ea, RTE_BBDEV_LDPC_MIN_CB_SIZE);\n+\t\t\treturn -1;\n+\t\t}\n+\t\tif ((tb->eb < RTE_BBDEV_LDPC_MIN_CB_SIZE)\n+\t\t\t\t&& tb->c > tb->cab) {\n+\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\t\"eb (%u) is less than %u\",\n+\t\t\t\t\ttb->eb, RTE_BBDEV_LDPC_MIN_CB_SIZE);\n+\t\t\treturn -1;\n+\t\t}\n+\t\tif (tb->r > (tb->c - 1)) {\n+\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\t\"r (%u) is greater than c - 1 (%u)\",\n+\t\t\t\t\ttb->r, tb->c - 1);\n+\t\t\treturn -1;\n+\t\t}\n+\t} else {\n+\t\tcb = &ldpc_enc->cb_params;\n+\t\tif (cb->e < RTE_BBDEV_LDPC_MIN_CB_SIZE) {\n+\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\t\"e (%u) is less than %u or it is not even\",\n+\t\t\t\t\tcb->e, RTE_BBDEV_LDPC_MIN_CB_SIZE);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+#endif\n+\n static inline char *\n mbuf_append(struct rte_mbuf *m_head, struct rte_mbuf *m, uint16_t len)\n {\n@@ -825,6 +1083,69 @@\n \treturn tail;\n }\n \n+#ifdef RTE_LIBRTE_BBDEV_DEBUG\n+/* Validates LDPC decoder parameters */\n+static int\n+validate_dec_op(struct rte_bbdev_dec_op *op __rte_unused)\n+{\n+\tstruct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec;\n+\tstruct rte_bbdev_op_dec_ldpc_cb_params *cb = NULL;\n+\tstruct rte_bbdev_op_dec_ldpc_tb_params *tb = NULL;\n+\n+\tif (op->mempool == NULL) {\n+\t\trte_bbdev_log(ERR, \"Invalid mempool pointer\");\n+\t\treturn -1;\n+\t}\n+\tif (ldpc_dec->rv_index > 3) {\n+\t\trte_bbdev_log(ERR,\n+\t\t\t\t\"rv_index (%u) is out of range 0 <= value <= 3\",\n+\t\t\t\tldpc_dec->rv_index);\n+\t\treturn -1;\n+\t}\n+\n+\tif (ldpc_dec->iter_max == 0) {\n+\t\trte_bbdev_log(ERR,\n+\t\t\t\t\"iter_max (%u) is equal to 0\",\n+\t\t\t\tldpc_dec->iter_max);\n+\t\treturn -1;\n+\t}\n+\n+\tif (ldpc_dec->code_block_mode > 1) {\n+\t\trte_bbdev_log(ERR,\n+\t\t\t\t\"code_block_mode (%u) is out of range 0 <= value <= 1\",\n+\t\t\t\tldpc_dec->code_block_mode);\n+\t\treturn -1;\n+\t}\n+\n+\tif (ldpc_dec->code_block_mode == 0) {\n+\t\ttb = &ldpc_dec->tb_params;\n+\t\tif (tb->c < 1) {\n+\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\t\"c (%u) is out of range 1 <= value <= %u\",\n+\t\t\t\t\ttb->c, RTE_BBDEV_LDPC_MAX_CODE_BLOCKS);\n+\t\t\treturn -1;\n+\t\t}\n+\t\tif (tb->cab > tb->c) {\n+\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\t\"cab (%u) is greater than c (%u)\",\n+\t\t\t\t\ttb->cab, tb->c);\n+\t\t\treturn -1;\n+\t\t}\n+\t} else {\n+\t\tcb = &ldpc_dec->cb_params;\n+\t\tif (cb->e < RTE_BBDEV_LDPC_MIN_CB_SIZE) {\n+\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\t\"e (%u) is out of range %u <= value <= %u\",\n+\t\t\t\t\tcb->e, RTE_BBDEV_LDPC_MIN_CB_SIZE,\n+\t\t\t\t\tRTE_BBDEV_LDPC_MAX_CB_SIZE);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+#endif\n+\n static inline int\n enqueue_ldpc_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op *op,\n \t\tuint16_t desc_offset)\n@@ -843,6 +1164,15 @@\n \tuint16_t ring_offset;\n \tuint16_t K, k_;\n \n+#ifdef RTE_LIBRTE_BBDEV_DEBUG\n+\t/* Validate op structure */\n+\t/* FIXME */\n+\tif (validate_enc_op(op) == -1) {\n+\t\trte_bbdev_log(ERR, \"LDPC encoder validation failed\");\n+\t\treturn -EINVAL;\n+\t}\n+#endif\n+\n \t/* Clear op status */\n \top->status = 0;\n \n@@ -904,6 +1234,9 @@\n \t\treturn -1;\n \t}\n \n+#ifdef RTE_LIBRTE_BBDEV_DEBUG\n+\tprint_dma_enc_desc_debug_info(desc);\n+#endif\n \treturn 1;\n }\n \n@@ -926,6 +1259,14 @@\n \tuint16_t out_offset = dec->hard_output.offset;\n \tuint32_t harq_offset = 0;\n \n+#ifdef RTE_LIBRTE_BBDEV_DEBUG\n+\t\t/* Validate op structure */\n+\t\tif (validate_dec_op(op) == -1) {\n+\t\t\trte_bbdev_log(ERR, \"LDPC decoder validation failed\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+#endif\n+\n \t/* Clear op status */\n \top->status = 0;\n \n@@ -997,6 +1338,10 @@\n \t\treturn -1;\n \t}\n \n+#ifdef RTE_LIBRTE_BBDEV_DEBUG\n+\tprint_dma_dec_desc_debug_info(desc);\n+#endif\n+\n \treturn 1;\n }\n \n@@ -1133,6 +1478,10 @@\n \n \trte_bbdev_log_debug(\"DMA response desc %p\", desc);\n \n+#ifdef RTE_LIBRTE_BBDEV_DEBUG\n+\tprint_dma_enc_desc_debug_info(desc);\n+#endif\n+\n \t*op = desc->enc_req.op_addr;\n \t/* Check the descriptor error field, return 1 on error */\n \tdesc_error = check_desc_error(desc->enc_req.error);\n@@ -1159,6 +1508,10 @@\n \t/* make sure the response is read atomically */\n \trte_smp_rmb();\n \n+#ifdef RTE_LIBRTE_BBDEV_DEBUG\n+\tprint_dma_dec_desc_debug_info(desc);\n+#endif\n+\n \t*op = desc->dec_req.op_addr;\n \n \tif (check_bit((*op)->ldpc_dec.op_flags,\n@@ -1314,6 +1667,17 @@\n \trte_bbdev_log_debug(\"bbdev id = %u [%s]\",\n \t\t\tbbdev->data->dev_id, dev_name);\n \n+\tstruct fpga_5gnr_fec_device *d = bbdev->data->dev_private;\n+\tuint32_t version_id = fpga_reg_read_32(d->mmio_base,\n+\t\t\tFPGA_5GNR_FEC_VERSION_ID);\n+\trte_bbdev_log(INFO, \"FEC FPGA RTL v%u.%u\",\n+\t\t((uint16_t)(version_id >> 16)), ((uint16_t)version_id));\n+\n+#ifdef RTE_LIBRTE_BBDEV_DEBUG\n+\tif (!strcmp(bbdev->device->driver->name,\n+\t\t\tRTE_STR(FPGA_5GNR_FEC_PF_DRIVER_NAME)))\n+\t\tprint_static_reg_debug_info(d->mmio_base);\n+#endif\n \treturn 0;\n }\n \n", "prefixes": [ "v2", "09/13" ] }