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GET /api/patches/66806/?format=api
{ "id": 66806, "url": "http://patches.dpdk.org/api/patches/66806/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1584459511-5353-23-git-send-email-venkatkumar.duvvuru@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1584459511-5353-23-git-send-email-venkatkumar.duvvuru@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1584459511-5353-23-git-send-email-venkatkumar.duvvuru@broadcom.com", "date": "2020-03-17T15:38:20", "name": "[22/33] net/bnxt: match rte flow items with flow template patterns", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8f251830246e8eb56d3111ae30dfdc305d6bca39", "submitter": { "id": 1635, "url": "http://patches.dpdk.org/api/people/1635/?format=api", "name": "Venkat Duvvuru", "email": "venkatkumar.duvvuru@broadcom.com" }, "delegate": { "id": 1766, "url": "http://patches.dpdk.org/api/users/1766/?format=api", "username": "ajitkhaparde", "first_name": "Ajit", "last_name": "Khaparde", "email": "ajit.khaparde@broadcom.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1584459511-5353-23-git-send-email-venkatkumar.duvvuru@broadcom.com/mbox/", "series": [ { "id": 8955, "url": "http://patches.dpdk.org/api/series/8955/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8955", "date": "2020-03-17T15:37:58", "name": "add support for host based flow table management", "version": 1, "mbox": "http://patches.dpdk.org/series/8955/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/66806/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/66806/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E4081A0565;\n\tTue, 17 Mar 2020 16:44:37 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 9CCF41C1B2;\n\tTue, 17 Mar 2020 16:39:50 +0100 (CET)", "from mail-wm1-f67.google.com (mail-wm1-f67.google.com\n [209.85.128.67]) by dpdk.org (Postfix) with ESMTP id 5066A1C0B6\n for <dev@dpdk.org>; Tue, 17 Mar 2020 16:39:49 +0100 (CET)", "by mail-wm1-f67.google.com with SMTP id 25so21993644wmk.3\n for <dev@dpdk.org>; Tue, 17 Mar 2020 08:39:49 -0700 (PDT)", "from S60.dhcp.broadcom.net ([192.19.234.250])\n by smtp.gmail.com with ESMTPSA id q4sm5052142wro.56.2020.03.17.08.39.46\n (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n Tue, 17 Mar 2020 08:39:48 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com;\n s=google;\n h=from:to:cc:subject:date:message-id:in-reply-to:references;\n bh=2SHZOOYmdPzOj/MtbJV9MkaeDZYJjjC3wBnk9RyCtgU=;\n b=cCe8SkcANI2btbbRZqKqMsFHxyB5gEpC0VAjX0kKKrPzqinFDt0Q4X0F4g+VQcsz5n\n AMIywZs8v79RdUeBBCmdJXgFn0rZoOfoDQNwwlBEY7ylBDCiXiU5zjs3TLcik/Z249h5\n oPoU1lDDaSqB7hHPkpt1r37KJgZtE5rqeafSw=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references;\n bh=2SHZOOYmdPzOj/MtbJV9MkaeDZYJjjC3wBnk9RyCtgU=;\n b=pbGwUxXFk/B/EfnxX7SD9KR7k/r74mAGFm3ttX5clZVFmyRQ85N8o/egf9XfyZ0ETT\n HgsAGo0YqDp2H5tq03zwU73iqXXs2IgB84toIuso6XB08bm/H2n0eLwQHiRUPmRneHFg\n Oroz+rf+nLs6JbHojrUUYZ4RPcmgAGQLMB9pfIzwgh3wjR5Q1GXHYS8TepzzJlp2qC8Z\n oMLEWw0CiL2nJCdAxvSYsSyjjcZ1HgrKJEksrGPSsHH5C0TWvaydCFR3DaqXHFb6qNxe\n gtAkW/v1jAXeHXCCQFOyqcOCeR/unmWynCg2crbjKPjQro9tT+gl0kPdg8Rl/WFp4Oy6\n qpQQ==", "X-Gm-Message-State": "ANhLgQ1GKD+yWiKJMlXL9Kw7Gmwl+WqPxQ6nIwP5yZlJRHomnSQzbHpq\n RVDvmHaoMPMRvAK1d2pMmRDjL4TRGFUFVP/EDHjSg4/LL++b7KuAIHvYJacsUBHK3Q2t+JWvrkv\n kdCIBr7ceF1E00XsxbxbY7Z/d6K+cBWvT9I0nZIkhiMy3pLUtXghGVDLPAz7Xrp6TqYd5", "X-Google-Smtp-Source": "\n ADFU+vsacnt0HzEEbK5dFFLebvGiLSWqraxGrrIqIj6fnICMgxGE3rOeG/kTWGRodaVGSijEuGm/aw==", "X-Received": "by 2002:a1c:f001:: with SMTP id a1mr5677327wmb.76.1584459588532;\n Tue, 17 Mar 2020 08:39:48 -0700 (PDT)", "From": "Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>", "To": "dev@dpdk.org", "Cc": "Kishore Padmanabha <kishore.padmanabha@broadcom.com>,\n Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>", "Date": "Tue, 17 Mar 2020 21:08:20 +0530", "Message-Id": "\n <1584459511-5353-23-git-send-email-venkatkumar.duvvuru@broadcom.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "\n <1584459511-5353-1-git-send-email-venkatkumar.duvvuru@broadcom.com>", "References": "\n <1584459511-5353-1-git-send-email-venkatkumar.duvvuru@broadcom.com>", "Subject": "[dpdk-dev] [PATCH 22/33] net/bnxt: match rte flow items with flow\n\ttemplate patterns", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>\n\nThis patch does the following\n1. Takes hdr_bitmap generated from the rte_flow_items\n2. Iterates through the static hdr_bitmap list\n3. Returns success if a match is found, otherwise an error\n\nSigned-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>\nSigned-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>\nReviewed-by: Lance Richardson <lance.richardson@broadcom.com>\nReviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/Makefile | 1 +\n drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 12 ++\n drivers/net/bnxt/tf_ulp/ulp_matcher.c | 152 ++++++++++++++++++++++++++\n drivers/net/bnxt/tf_ulp/ulp_matcher.h | 26 +++++\n drivers/net/bnxt/tf_ulp/ulp_template_db.c | 115 +++++++++++++++++++\n drivers/net/bnxt/tf_ulp/ulp_template_db.h | 40 +++++++\n drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 21 ++++\n 7 files changed, 367 insertions(+)\n create mode 100644 drivers/net/bnxt/tf_ulp/ulp_matcher.c\n create mode 100644 drivers/net/bnxt/tf_ulp/ulp_matcher.h", "diff": "diff --git a/drivers/net/bnxt/Makefile b/drivers/net/bnxt/Makefile\nindex 3a3dad4..9776987 100644\n--- a/drivers/net/bnxt/Makefile\n+++ b/drivers/net/bnxt/Makefile\n@@ -63,6 +63,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_BNXT_TRUFLOW) += tf_ulp/ulp_flow_db.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_TRUFLOW) += tf_ulp/ulp_template_db.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_TRUFLOW) += tf_ulp/ulp_utils.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_TRUFLOW) += tf_ulp/ulp_mapper.c\n+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_TRUFLOW) += tf_ulp/ulp_matcher.c\n #\n # Export include files\n #\ndiff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h\nindex 3516df4..e4ebfc5 100644\n--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h\n+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h\n@@ -25,6 +25,18 @@\n #define\tBNXT_ULP_TX_NUM_FLOWS\t\t\t32\n #define\tBNXT_ULP_TX_TBL_IF_ID\t\t\t0\n \n+enum bnxt_tf_rc {\n+\tBNXT_TF_RC_PARSE_ERR\t= -2,\n+\tBNXT_TF_RC_ERROR\t= -1,\n+\tBNXT_TF_RC_SUCCESS\t= 0\n+};\n+\n+/* ulp direction Type */\n+enum ulp_direction_type {\n+\tULP_DIR_INGRESS,\n+\tULP_DIR_EGRESS,\n+};\n+\n struct bnxt_ulp_mark_tbl *\n bnxt_ulp_cntxt_ptr2_mark_db_get(struct bnxt_ulp_context *ulp_ctx);\n \ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.c b/drivers/net/bnxt/tf_ulp/ulp_matcher.c\nnew file mode 100644\nindex 0000000..f367e4c\n--- /dev/null\n+++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.c\n@@ -0,0 +1,152 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2014-2020 Broadcom\n+ * All rights reserved.\n+ */\n+\n+#include \"ulp_matcher.h\"\n+#include \"ulp_utils.h\"\n+\n+/* Utility function to check if bitmap is zero */\n+static inline\n+int ulp_field_mask_is_zero(uint8_t *bitmap, uint32_t size)\n+{\n+\twhile (size-- > 0) {\n+\t\tif (*bitmap != 0)\n+\t\t\treturn 0;\n+\t\tbitmap++;\n+\t}\n+\treturn 1;\n+}\n+\n+/* Utility function to check if bitmap is all ones */\n+static inline int\n+ulp_field_mask_is_ones(uint8_t *bitmap, uint32_t size)\n+{\n+\twhile (size-- > 0) {\n+\t\tif (*bitmap != 0xFF)\n+\t\t\treturn 0;\n+\t\tbitmap++;\n+\t}\n+\treturn 1;\n+}\n+\n+/* Utility function to check if bitmap is non zero */\n+static inline int\n+ulp_field_mask_notzero(uint8_t *bitmap, uint32_t size)\n+{\n+\twhile (size-- > 0) {\n+\t\tif (*bitmap != 0)\n+\t\t\treturn 1;\n+\t\tbitmap++;\n+\t}\n+\treturn 0;\n+}\n+\n+/* Utility function to mask the computed and internal proto headers. */\n+static void\n+ulp_matcher_hdr_fields_normalize(struct ulp_rte_hdr_bitmap *hdr1,\n+\t\t\t\t struct ulp_rte_hdr_bitmap *hdr2)\n+{\n+\t/* copy the contents first */\n+\trte_memcpy(hdr2, hdr1, sizeof(struct ulp_rte_hdr_bitmap));\n+\n+\t/* reset the computed fields */\n+\tULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_SVIF);\n+\tULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_OO_VLAN);\n+\tULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_OI_VLAN);\n+\tULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_IO_VLAN);\n+\tULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_II_VLAN);\n+\tULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_O_L3);\n+\tULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_O_L4);\n+\tULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_I_L3);\n+\tULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_I_L4);\n+}\n+\n+/*\n+ * Function to handle the matching of RTE Flows and validating\n+ * the pattern masks against the flow templates.\n+ */\n+int32_t\n+ulp_matcher_pattern_match(enum ulp_direction_type dir,\n+\t\t\t struct ulp_rte_hdr_bitmap *hdr_bitmap,\n+\t\t\t struct ulp_rte_hdr_field *hdr_field,\n+\t\t\t struct ulp_rte_act_bitmap *act_bitmap,\n+\t\t\t uint32_t\t\t *class_id)\n+{\n+\tstruct bnxt_ulp_header_match_info\t*sel_hdr_match;\n+\tuint32_t\t\t\t\thdr_num, idx, jdx;\n+\tuint32_t\t\t\t\tmatch = 0;\n+\tstruct ulp_rte_hdr_bitmap\t\thdr_bitmap_masked;\n+\tuint32_t\t\t\t\tstart_idx;\n+\tstruct ulp_rte_hdr_field\t\t*m_field;\n+\tstruct bnxt_ulp_matcher_field_info\t*sf;\n+\n+\t/* Select the ingress or egress template to match against */\n+\tif (dir == ULP_DIR_INGRESS) {\n+\t\tsel_hdr_match = ulp_ingress_hdr_match_list;\n+\t\thdr_num = BNXT_ULP_INGRESS_HDR_MATCH_SZ;\n+\t} else {\n+\t\tsel_hdr_match = ulp_egress_hdr_match_list;\n+\t\thdr_num = BNXT_ULP_EGRESS_HDR_MATCH_SZ;\n+\t}\n+\n+\t/* Remove the hdr bit maps that are internal or computed */\n+\tulp_matcher_hdr_fields_normalize(hdr_bitmap, &hdr_bitmap_masked);\n+\n+\t/* Loop through the list of class templates to find the match */\n+\tfor (idx = 0; idx < hdr_num; idx++, sel_hdr_match++) {\n+\t\tif (ULP_BITSET_CMP(&sel_hdr_match->hdr_bitmap,\n+\t\t\t\t &hdr_bitmap_masked)) {\n+\t\t\t/* no match found */\n+\t\t\tBNXT_TF_DBG(DEBUG, \"Pattern Match failed template=%d\\n\",\n+\t\t\t\t idx);\n+\t\t\tcontinue;\n+\t\t}\n+\t\tmatch = ULP_BITMAP_ISSET(act_bitmap->bits,\n+\t\t\t\t\t BNXT_ULP_ACTION_BIT_VNIC);\n+\t\tif (match != sel_hdr_match->act_vnic) {\n+\t\t\t/* no match found */\n+\t\t\tBNXT_TF_DBG(DEBUG, \"Vnic Match failed template=%d\\n\",\n+\t\t\t\t idx);\n+\t\t\tcontinue;\n+\t\t} else {\n+\t\t\tmatch = 1;\n+\t\t}\n+\n+\t\t/* Found a matching hdr bitmap, match the fields next */\n+\t\tstart_idx = sel_hdr_match->start_idx;\n+\t\tfor (jdx = 0; jdx < sel_hdr_match->num_entries; jdx++) {\n+\t\t\tm_field = &hdr_field[jdx + BNXT_ULP_HDR_FIELD_LAST - 1];\n+\t\t\tsf = &ulp_field_match[start_idx + jdx];\n+\t\t\tswitch (sf->mask_opcode) {\n+\t\t\tcase BNXT_ULP_FMF_MASK_ANY:\n+\t\t\t\tmatch &= ulp_field_mask_is_zero(m_field->mask,\n+\t\t\t\t\t\t\t\tm_field->size);\n+\t\t\t\tbreak;\n+\t\t\tcase BNXT_ULP_FMF_MASK_EXACT:\n+\t\t\t\tmatch &= ulp_field_mask_is_ones(m_field->mask,\n+\t\t\t\t\t\t\t\tm_field->size);\n+\t\t\t\tbreak;\n+\t\t\tcase BNXT_ULP_FMF_MASK_WILDCARD:\n+\t\t\t\tmatch &= ulp_field_mask_notzero(m_field->mask,\n+\t\t\t\t\t\t\t\tm_field->size);\n+\t\t\t\tbreak;\n+\t\t\tcase BNXT_ULP_FMF_MASK_IGNORE:\n+\t\t\tdefault:\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (!match)\n+\t\t\t\tbreak;\n+\t\t}\n+\t\tif (match) {\n+\t\t\tBNXT_TF_DBG(DEBUG,\n+\t\t\t\t \"Found matching pattern template %d\\n\",\n+\t\t\t\t sel_hdr_match->class_tmpl_id);\n+\t\t\t*class_id = sel_hdr_match->class_tmpl_id;\n+\t\t\treturn BNXT_TF_RC_SUCCESS;\n+\t\t}\n+\t}\n+\tBNXT_TF_DBG(DEBUG, \"Did not find any matching template\\n\");\n+\t*class_id = 0;\n+\treturn BNXT_TF_RC_ERROR;\n+}\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.h b/drivers/net/bnxt/tf_ulp/ulp_matcher.h\nnew file mode 100644\nindex 0000000..57a161d\n--- /dev/null\n+++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.h\n@@ -0,0 +1,26 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2014-2020 Broadcom\n+ * All rights reserved.\n+ */\n+\n+#ifndef ULP_MATCHER_H_\n+#define ULP_MATCHER_H_\n+\n+#include <rte_log.h>\n+#include \"bnxt.h\"\n+#include \"ulp_template_db.h\"\n+#include \"ulp_template_struct.h\"\n+#include \"bnxt_tf_common.h\"\n+\n+/*\n+ * Function to handle the matching of RTE Flows and validating\n+ * the pattern masks against the flow templates.\n+ */\n+int32_t\n+ulp_matcher_pattern_match(enum ulp_direction_type\t dir,\n+\t\t\t struct ulp_rte_hdr_bitmap\t *hdr_bitmap,\n+\t\t\t struct ulp_rte_hdr_field\t *hdr_field,\n+\t\t\t struct ulp_rte_act_bitmap\t *act_bitmap,\n+\t\t\t uint32_t\t\t\t *class_id);\n+\n+#endif /* ULP_MATCHER_H_ */\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.c b/drivers/net/bnxt/tf_ulp/ulp_template_db.c\nindex 5ec7adc..68a2dc0 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.c\n@@ -796,6 +796,121 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {\n \t}\n };\n \n+struct bnxt_ulp_header_match_info ulp_ingress_hdr_match_list[] = {\n+\t{\n+\t.hdr_bitmap = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP },\n+\t.start_idx = 0,\n+\t.num_entries = 24,\n+\t.class_tmpl_id = 0,\n+\t.act_vnic = 0\n+\t}\n+};\n+\n+struct bnxt_ulp_header_match_info ulp_egress_hdr_match_list[] = {\n+};\n+\n+struct bnxt_ulp_matcher_field_info ulp_field_match[] = {\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_EXACT,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_EXACT,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_ANY,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_ANY,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_EXACT,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_EXACT,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_EXACT,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_EXACT,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t},\n+\t{\n+\t.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,\n+\t.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE\n+\t}\n+};\n+\n struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {\n \t{\n \t.field_bit_size = 10,\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h\nindex 957b21a..319500a 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h\n@@ -13,6 +13,8 @@\n \n #define BNXT_ULP_MAX_NUM_DEVICES 4\n #define BNXT_ULP_LOG2_MAX_NUM_DEV 2\n+#define BNXT_ULP_INGRESS_HDR_MATCH_SZ 2\n+#define BNXT_ULP_EGRESS_HDR_MATCH_SZ 1\n \n enum bnxt_ulp_action_bit {\n \tBNXT_ULP_ACTION_BIT_MARK = 0x0000000000000001,\n@@ -45,6 +47,31 @@ enum bnxt_ulp_action_bit {\n \tBNXT_ULP_ACTION_BIT_LAST = 0x0000000008000000\n };\n \n+enum bnxt_ulp_hdr_bit {\n+\tBNXT_ULP_HDR_BIT_SVIF = 0x0000000000000001,\n+\tBNXT_ULP_HDR_BIT_O_ETH = 0x0000000000000002,\n+\tBNXT_ULP_HDR_BIT_OO_VLAN = 0x0000000000000004,\n+\tBNXT_ULP_HDR_BIT_OI_VLAN = 0x0000000000000008,\n+\tBNXT_ULP_HDR_BIT_O_L3 = 0x0000000000000010,\n+\tBNXT_ULP_HDR_BIT_O_IPV4 = 0x0000000000000020,\n+\tBNXT_ULP_HDR_BIT_O_IPV6 = 0x0000000000000040,\n+\tBNXT_ULP_HDR_BIT_O_L4 = 0x0000000000000080,\n+\tBNXT_ULP_HDR_BIT_O_TCP = 0x0000000000000100,\n+\tBNXT_ULP_HDR_BIT_O_UDP = 0x0000000000000200,\n+\tBNXT_ULP_HDR_BIT_T_VXLAN = 0x0000000000000400,\n+\tBNXT_ULP_HDR_BIT_T_GRE = 0x0000000000000800,\n+\tBNXT_ULP_HDR_BIT_I_ETH = 0x0000000000001000,\n+\tBNXT_ULP_HDR_BIT_IO_VLAN = 0x0000000000002000,\n+\tBNXT_ULP_HDR_BIT_II_VLAN = 0x0000000000004000,\n+\tBNXT_ULP_HDR_BIT_I_L3 = 0x0000000000008000,\n+\tBNXT_ULP_HDR_BIT_I_IPV4 = 0x0000000000010000,\n+\tBNXT_ULP_HDR_BIT_I_IPV6 = 0x0000000000020000,\n+\tBNXT_ULP_HDR_BIT_I_L4 = 0x0000000000040000,\n+\tBNXT_ULP_HDR_BIT_I_TCP = 0x0000000000080000,\n+\tBNXT_ULP_HDR_BIT_I_UDP = 0x0000000000100000,\n+\tBNXT_ULP_HDR_BIT_LAST = 0x0000000000200000\n+};\n+\n enum bnxt_ulp_byte_order {\n \tBNXT_ULP_BYTE_ORDER_BE,\n \tBNXT_ULP_BYTE_ORDER_LE,\n@@ -67,12 +94,25 @@ enum bnxt_ulp_fmf_mask {\n \tBNXT_ULP_FMF_MASK_LAST\n };\n \n+enum bnxt_ulp_fmf_spec {\n+\tBNXT_ULP_FMF_SPEC_IGNORE = 0,\n+\tBNXT_ULP_FMF_SPEC_LAST = 1\n+};\n+\n enum bnxt_ulp_mark_enable {\n \tBNXT_ULP_MARK_ENABLE_NO = 0,\n \tBNXT_ULP_MARK_ENABLE_YES = 1,\n \tBNXT_ULP_MARK_ENABLE_LAST = 2\n };\n \n+enum bnxt_ulp_hdr_field {\n+\tBNXT_ULP_HDR_FIELD_MPLS_TAG_NUM = 0,\n+\tBNXT_ULP_HDR_FIELD_O_VTAG_NUM = 1,\n+\tBNXT_ULP_HDR_FIELD_I_VTAG_NUM = 2,\n+\tBNXT_ULP_HDR_FIELD_SVIF_INDEX = 3,\n+\tBNXT_ULP_HDR_FIELD_LAST = 4\n+};\n+\n enum bnxt_ulp_mask_opc {\n \tBNXT_ULP_MASK_OPC_SET_TO_CONSTANT = 0,\n \tBNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD = 1,\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h\nindex b7094c5..dd06fb1 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h\n@@ -29,6 +29,11 @@ struct ulp_rte_hdr_field {\n \tuint32_t\tsize;\n };\n \n+struct bnxt_ulp_matcher_field_info {\n+\tenum bnxt_ulp_fmf_mask\tmask_opcode;\n+\tenum bnxt_ulp_fmf_spec\tspec_opcode;\n+};\n+\n struct ulp_rte_act_bitmap {\n \tuint64_t\tbits;\n };\n@@ -41,6 +46,22 @@ struct ulp_rte_act_prop {\n \tuint8_t\tact_details[BNXT_ULP_ACT_PROP_IDX_LAST];\n };\n \n+/* Flow Matcher structures */\n+struct bnxt_ulp_header_match_info {\n+\tstruct ulp_rte_hdr_bitmap\t\thdr_bitmap;\n+\tuint32_t\t\t\t\tstart_idx;\n+\tuint32_t\t\t\t\tnum_entries;\n+\tuint32_t\t\t\t\tclass_tmpl_id;\n+\tuint32_t\t\t\t\tact_vnic;\n+};\n+\n+/* Flow Matcher templates Structure Array defined in template source*/\n+extern struct bnxt_ulp_header_match_info ulp_ingress_hdr_match_list[];\n+extern struct bnxt_ulp_header_match_info ulp_egress_hdr_match_list[];\n+\n+/* Flow field match Information Structure Array defined in template source*/\n+extern struct bnxt_ulp_matcher_field_info\tulp_field_match[];\n+\n /* Device specific parameters */\n struct bnxt_ulp_device_params {\n \tuint8_t\t\t\t\tdescription[16];\n", "prefixes": [ "22/33" ] }