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GET /api/patches/66790/?format=api
{ "id": 66790, "url": "http://patches.dpdk.org/api/patches/66790/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1584459511-5353-7-git-send-email-venkatkumar.duvvuru@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1584459511-5353-7-git-send-email-venkatkumar.duvvuru@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1584459511-5353-7-git-send-email-venkatkumar.duvvuru@broadcom.com", "date": "2020-03-17T15:38:04", "name": "[06/33] net/bnxt: add tf core session sram functions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "84f2de717ae34d54b6b7893b809117d92a2463c3", "submitter": { "id": 1635, "url": "http://patches.dpdk.org/api/people/1635/?format=api", "name": "Venkat Duvvuru", "email": "venkatkumar.duvvuru@broadcom.com" }, "delegate": { "id": 1766, "url": "http://patches.dpdk.org/api/users/1766/?format=api", "username": "ajitkhaparde", "first_name": "Ajit", "last_name": "Khaparde", "email": "ajit.khaparde@broadcom.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1584459511-5353-7-git-send-email-venkatkumar.duvvuru@broadcom.com/mbox/", "series": [ { "id": 8955, "url": "http://patches.dpdk.org/api/series/8955/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8955", "date": "2020-03-17T15:37:58", "name": "add support for host based flow table management", "version": 1, "mbox": "http://patches.dpdk.org/series/8955/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/66790/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/66790/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5A829A0565;\n\tTue, 17 Mar 2020 16:40:41 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 504891C0B7;\n\tTue, 17 Mar 2020 16:39:15 +0100 (CET)", "from mail-wm1-f68.google.com (mail-wm1-f68.google.com\n [209.85.128.68]) by dpdk.org (Postfix) with ESMTP id 83BE01C0AE\n for <dev@dpdk.org>; Tue, 17 Mar 2020 16:39:13 +0100 (CET)", "by mail-wm1-f68.google.com with SMTP id 25so21990832wmk.3\n for <dev@dpdk.org>; Tue, 17 Mar 2020 08:39:13 -0700 (PDT)", "from S60.dhcp.broadcom.net ([192.19.234.250])\n by smtp.gmail.com with ESMTPSA id q4sm5052142wro.56.2020.03.17.08.39.09\n (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n Tue, 17 Mar 2020 08:39:11 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com;\n s=google;\n h=from:to:cc:subject:date:message-id:in-reply-to:references;\n bh=UavrMQFB/ANrA2/e8SkN37+eCzkqv5AFDHjWeYOXIpM=;\n b=QhsW/s89MlnuhULPj5ZnWI0+jd9fDDlte3EBYvxhIciTP1Xe9/sn4hfimncHdH9ihf\n MhzCwf4qwccF6iD7khU6DGjEnNwkkRUL5HePxvEjZcZLJX60tInFB1Jcn3LsG1C3okCl\n 5U2BUlnJl7XfDQnwJR6Pv5tkMB+C3zkbkZDPA=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references;\n bh=UavrMQFB/ANrA2/e8SkN37+eCzkqv5AFDHjWeYOXIpM=;\n b=PfkSY/8X96EcIJwq6K6AkHaqLupWvVU7+FgXk6NbfWZjqnbf7wuDNUAqCxN4T+iQAw\n qNIY+y3G+kLkGXCMOiy2EgWxkv9nylKGyW4z0zHKVLOcQiK1blVqkdHFKPp7nwjGLjdH\n P2iwjsv6yt15i0Z5Jf0/J8SOMBIs+aCe1E1o9cqGwJX6ftA+VzqyLVma1q3XAVcvFk8b\n s+5d0Grw5AHJb4k5FumHcynCRmFwErhT5CGp1dwIrgKnYLSvLvDf6CUWR1Duyon508kI\n omSHzqwDNGdJDWieXkblHh2N2IDDPyd8d4rPgsQbHTDXqG7H7VTIkNuQ+XzrhgFmJvqj\n Ye3w==", "X-Gm-Message-State": "ANhLgQ3T8mClXaBf5MoNx1J/m2B55ZusVMRfT1kJYoHSxNcZTsz95Fbk\n Kp2mhOT2RS4E/ze+VxXHQn4rVWD6/GiUZaeOYbztwOKLN0dnsVRW6FLOMLNCnnQZfZcp/LT6TrC\n LhDooPttIpyJ5foDlm7X34X5LS5ypMbk1moCDhgGxVX2eiMctYJCYuRjH75KDPq0+yjT+", "X-Google-Smtp-Source": "\n ADFU+vv8giOTe7UHRVoECbUJZpG71Xe/8MCh4KHyduSQKczLWEQIvOannT0aX/7HNWmJZlsRvd68dg==", "X-Received": "by 2002:a1c:f001:: with SMTP id a1mr5674951wmb.76.1584459551532;\n Tue, 17 Mar 2020 08:39:11 -0700 (PDT)", "From": "Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>", "To": "dev@dpdk.org", "Cc": "Michael Wildt <michael.wildt@broadcom.com>", "Date": "Tue, 17 Mar 2020 21:08:04 +0530", "Message-Id": "\n <1584459511-5353-7-git-send-email-venkatkumar.duvvuru@broadcom.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "\n <1584459511-5353-1-git-send-email-venkatkumar.duvvuru@broadcom.com>", "References": "\n <1584459511-5353-1-git-send-email-venkatkumar.duvvuru@broadcom.com>", "Subject": "[dpdk-dev] [PATCH 06/33] net/bnxt: add tf core session sram\n\tfunctions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Michael Wildt <michael.wildt@broadcom.com>\n\n- Add TruFlow session resource support functionality\n- Add TruFlow session hw flush capability as well as\n sram support functions.\n- Add resource definitions for session pools.\n\nSigned-off-by: Michael Wildt <michael.wildt@broadcom.com>\nReviewed-by: Randy Schacher <stuart.schacher@broadcom.com>\nReviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/Makefile | 1 +\n drivers/net/bnxt/tf_core/rand.c | 47 ++++\n drivers/net/bnxt/tf_core/rand.h | 36 +++\n drivers/net/bnxt/tf_core/tf_core.c | 1 +\n drivers/net/bnxt/tf_core/tf_msg.c | 344 +++++++++++++++++++++++\n drivers/net/bnxt/tf_core/tf_msg.h | 37 +++\n drivers/net/bnxt/tf_core/tf_resources.h | 482 ++++++++++++++++++++++++++++++++\n 7 files changed, 948 insertions(+)\n create mode 100644 drivers/net/bnxt/tf_core/rand.c\n create mode 100644 drivers/net/bnxt/tf_core/rand.h", "diff": "diff --git a/drivers/net/bnxt/Makefile b/drivers/net/bnxt/Makefile\nindex 1b42c1f..d4c915a 100644\n--- a/drivers/net/bnxt/Makefile\n+++ b/drivers/net/bnxt/Makefile\n@@ -50,6 +50,7 @@ endif\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_TRUFLOW) += tf_core/tf_core.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_TRUFLOW) += tf_core/bitalloc.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_TRUFLOW) += tf_core/tf_msg.c\n+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_TRUFLOW) += tf_core/rand.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_TRUFLOW) += tf_core/tfp.c\n \n #\ndiff --git a/drivers/net/bnxt/tf_core/rand.c b/drivers/net/bnxt/tf_core/rand.c\nnew file mode 100644\nindex 0000000..32028df\n--- /dev/null\n+++ b/drivers/net/bnxt/tf_core/rand.c\n@@ -0,0 +1,47 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2019-2020 Broadcom\n+ * All rights reserved.\n+ */\n+\n+/* Random Number Functions */\n+\n+#include <stdio.h>\n+#include <stdint.h>\n+#include \"rand.h\"\n+\n+#define TF_RAND_LFSR_INIT_VALUE 0xACE1u\n+\n+uint16_t lfsr = TF_RAND_LFSR_INIT_VALUE;\n+uint32_t bit;\n+\n+/**\n+ * Generates a 16 bit pseudo random number\n+ *\n+ * Returns:\n+ * uint16_t number\n+ */\n+uint16_t rand16(void)\n+{\n+\tbit = ((lfsr >> 0) ^ (lfsr >> 2) ^ (lfsr >> 3) ^ (lfsr >> 5)) & 1;\n+\treturn lfsr = (lfsr >> 1) | (bit << 15);\n+}\n+\n+/**\n+ * Generates a 32 bit pseudo random number\n+ *\n+ * Returns:\n+ * uint32_t number\n+ */\n+uint32_t rand32(void)\n+{\n+\treturn (rand16() << 16) | rand16();\n+}\n+\n+/**\n+ * Resets the seed used by the pseudo random number generator\n+ */\n+void rand_init(void)\n+{\n+\tlfsr = TF_RAND_LFSR_INIT_VALUE;\n+\tbit = 0;\n+}\ndiff --git a/drivers/net/bnxt/tf_core/rand.h b/drivers/net/bnxt/tf_core/rand.h\nnew file mode 100644\nindex 0000000..31cd76e\n--- /dev/null\n+++ b/drivers/net/bnxt/tf_core/rand.h\n@@ -0,0 +1,36 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2019-2020 Broadcom\n+ * All rights reserved.\n+ */\n+\n+/* Random Number Functions */\n+#ifndef __RAND_H__\n+#define __RAND_H__\n+\n+/**\n+ * Generates a 16 bit pseudo random number\n+ *\n+ * Returns:\n+ * uint16_t number\n+ *\n+ */\n+uint16_t rand16(void);\n+\n+/**\n+ * Generates a 32 bit pseudo random number\n+ *\n+ * Returns:\n+ * uint32_t number\n+ *\n+ */\n+uint32_t rand32(void);\n+\n+/**\n+ * Resets the seed used by the pseudo random number generator\n+ *\n+ * Returns:\n+ *\n+ */\n+void rand_init(void);\n+\n+#endif /* __RAND_H__ */\ndiff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c\nindex 3c5d55d..d82f746 100644\n--- a/drivers/net/bnxt/tf_core/tf_core.c\n+++ b/drivers/net/bnxt/tf_core/tf_core.c\n@@ -12,6 +12,7 @@\n #include \"tfp.h\"\n #include \"bitalloc.h\"\n #include \"bnxt.h\"\n+#include \"rand.h\"\n \n static inline uint32_t SWAP_WORDS32(uint32_t val32)\n {\ndiff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c\nindex e05aea7..4ce2bc5 100644\n--- a/drivers/net/bnxt/tf_core/tf_msg.c\n+++ b/drivers/net/bnxt/tf_core/tf_msg.c\n@@ -478,3 +478,347 @@ tf_msg_session_hw_resc_free(struct tf *tfp,\n \n \treturn tfp_le_to_cpu_32(parms.tf_resp_code);\n }\n+\n+/**\n+ * Sends session HW resource flush request to TF Firmware\n+ */\n+int\n+tf_msg_session_hw_resc_flush(struct tf *tfp,\n+\t\t\t enum tf_dir dir,\n+\t\t\t struct tf_rm_entry *hw_entry)\n+{\n+\tint rc;\n+\tstruct tfp_send_msg_parms parms = { 0 };\n+\tstruct tf_session_hw_resc_free_input req = { 0 };\n+\tstruct tf_session *tfs = (struct tf_session *)(tfp->session->core_data);\n+\n+\t/* Populate the request */\n+\treq.fw_session_id =\n+\t\ttfp_cpu_to_le_32(tfs->session_id.internal.fw_session_id);\n+\treq.flags = tfp_cpu_to_le_16(dir);\n+\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_L2_CTXT_TCAM, req,\n+\t\t\t l2_ctx_tcam_entries);\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_PROF_FUNC, req,\n+\t\t\t prof_func);\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_PROF_TCAM, req,\n+\t\t\t prof_tcam_entries);\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_EM_PROF_ID, req,\n+\t\t\t em_prof_id);\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_EM_REC, req,\n+\t\t\t em_record_entries);\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_WC_TCAM_PROF_ID, req,\n+\t\t\t wc_tcam_prof_id);\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_WC_TCAM, req,\n+\t\t\t wc_tcam_entries);\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_METER_PROF, req,\n+\t\t\t meter_profiles);\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_METER_INST, req,\n+\t\t\t meter_inst);\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_MIRROR, req,\n+\t\t\t mirrors);\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_UPAR, req,\n+\t\t\t upar);\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_SP_TCAM, req,\n+\t\t\t sp_tcam_entries);\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_L2_FUNC, req,\n+\t\t\t l2_func);\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_FKB, req,\n+\t\t\t flex_key_templ);\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_TBL_SCOPE, req,\n+\t\t\t tbl_scope);\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_EPOCH0, req,\n+\t\t\t epoch0_entries);\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_EPOCH1, req,\n+\t\t\t epoch1_entries);\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_METADATA, req,\n+\t\t\t metadata);\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_CT_STATE, req,\n+\t\t\t ct_state);\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_RANGE_PROF, req,\n+\t\t\t range_prof);\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_RANGE_ENTRY, req,\n+\t\t\t range_entries);\n+\tTF_HW_FREE_TO_REQ(hw_entry, TF_RESC_TYPE_HW_LAG_ENTRY, req,\n+\t\t\t lag_tbl_entries);\n+\n+\tMSG_PREP_NO_RESP(parms,\n+\t\t\t TF_KONG_MB,\n+\t\t\t TF_TYPE_TRUFLOW,\n+\t\t\t HWRM_TFT_SESSION_HW_RESC_FLUSH,\n+\t\t\t req);\n+\n+\trc = tfp_send_msg_tunneled(tfp, &parms);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\treturn tfp_le_to_cpu_32(parms.tf_resp_code);\n+}\n+\n+/**\n+ * Sends session SRAM resource query capability request to TF Firmware\n+ */\n+int\n+tf_msg_session_sram_resc_qcaps(struct tf *tfp __rte_unused,\n+\t\t\t enum tf_dir dir,\n+\t\t\t struct tf_rm_sram_query *query __rte_unused)\n+{\n+\tint rc;\n+\tstruct tfp_send_msg_parms parms = { 0 };\n+\tstruct tf_session_sram_resc_qcaps_input req = { 0 };\n+\tstruct tf_session_sram_resc_qcaps_output resp = { 0 };\n+\tstruct tf_session *tfs = (struct tf_session *)(tfp->session->core_data);\n+\n+\t/* Populate the request */\n+\treq.fw_session_id =\n+\t\ttfp_cpu_to_le_32(tfs->session_id.internal.fw_session_id);\n+\treq.flags = tfp_cpu_to_le_16(dir);\n+\n+\tMSG_PREP(parms,\n+\t\t TF_KONG_MB,\n+\t\t HWRM_TF,\n+\t\t HWRM_TFT_SESSION_SRAM_RESC_QCAPS,\n+\t\t req,\n+\t\t resp);\n+\n+\trc = tfp_send_msg_tunneled(tfp, &parms);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\t/* Process the response */\n+\tTF_SRAM_RESP_TO_QUERY(query, TF_RESC_TYPE_SRAM_FULL_ACTION, resp,\n+\t\t\t full_action);\n+\tTF_SRAM_RESP_TO_QUERY(query, TF_RESC_TYPE_SRAM_MCG, resp,\n+\t\t\t mcg);\n+\tTF_SRAM_RESP_TO_QUERY(query, TF_RESC_TYPE_SRAM_ENCAP_8B, resp,\n+\t\t\t encap_8b);\n+\tTF_SRAM_RESP_TO_QUERY(query, TF_RESC_TYPE_SRAM_ENCAP_16B, resp,\n+\t\t\t encap_16b);\n+\tTF_SRAM_RESP_TO_QUERY(query, TF_RESC_TYPE_SRAM_ENCAP_64B, resp,\n+\t\t\t encap_64b);\n+\tTF_SRAM_RESP_TO_QUERY(query, TF_RESC_TYPE_SRAM_SP_SMAC, resp,\n+\t\t\t sp_smac);\n+\tTF_SRAM_RESP_TO_QUERY(query, TF_RESC_TYPE_SRAM_SP_SMAC_IPV4, resp,\n+\t\t\t sp_smac_ipv4);\n+\tTF_SRAM_RESP_TO_QUERY(query, TF_RESC_TYPE_SRAM_SP_SMAC_IPV6, resp,\n+\t\t\t sp_smac_ipv6);\n+\tTF_SRAM_RESP_TO_QUERY(query, TF_RESC_TYPE_SRAM_COUNTER_64B, resp,\n+\t\t\t counter_64b);\n+\tTF_SRAM_RESP_TO_QUERY(query, TF_RESC_TYPE_SRAM_NAT_SPORT, resp,\n+\t\t\t nat_sport);\n+\tTF_SRAM_RESP_TO_QUERY(query, TF_RESC_TYPE_SRAM_NAT_DPORT, resp,\n+\t\t\t nat_dport);\n+\tTF_SRAM_RESP_TO_QUERY(query, TF_RESC_TYPE_SRAM_NAT_S_IPV4, resp,\n+\t\t\t nat_s_ipv4);\n+\tTF_SRAM_RESP_TO_QUERY(query, TF_RESC_TYPE_SRAM_NAT_D_IPV4, resp,\n+\t\t\t nat_d_ipv4);\n+\n+\treturn tfp_le_to_cpu_32(parms.tf_resp_code);\n+}\n+\n+/**\n+ * Sends session SRAM resource allocation request to TF Firmware\n+ */\n+int\n+tf_msg_session_sram_resc_alloc(struct tf *tfp __rte_unused,\n+\t\t\t enum tf_dir dir,\n+\t\t\t struct tf_rm_sram_alloc *sram_alloc __rte_unused,\n+\t\t\t struct tf_rm_entry *sram_entry __rte_unused)\n+{\n+\tint rc;\n+\tstruct tfp_send_msg_parms parms = { 0 };\n+\tstruct tf_session_sram_resc_alloc_input req = { 0 };\n+\tstruct tf_session_sram_resc_alloc_output resp;\n+\tstruct tf_session *tfs = (struct tf_session *)(tfp->session->core_data);\n+\n+\tmemset(&resp, 0, sizeof(resp));\n+\n+\t/* Populate the request */\n+\treq.fw_session_id =\n+\t\ttfp_cpu_to_le_32(tfs->session_id.internal.fw_session_id);\n+\treq.flags = tfp_cpu_to_le_16(dir);\n+\n+\tTF_SRAM_ALLOC_TO_REQ(sram_alloc, TF_RESC_TYPE_SRAM_FULL_ACTION, req,\n+\t\t\t full_action);\n+\tTF_SRAM_ALLOC_TO_REQ(sram_alloc, TF_RESC_TYPE_SRAM_MCG, req,\n+\t\t\t mcg);\n+\tTF_SRAM_ALLOC_TO_REQ(sram_alloc, TF_RESC_TYPE_SRAM_ENCAP_8B, req,\n+\t\t\t encap_8b);\n+\tTF_SRAM_ALLOC_TO_REQ(sram_alloc, TF_RESC_TYPE_SRAM_ENCAP_16B, req,\n+\t\t\t encap_16b);\n+\tTF_SRAM_ALLOC_TO_REQ(sram_alloc, TF_RESC_TYPE_SRAM_ENCAP_64B, req,\n+\t\t\t encap_64b);\n+\tTF_SRAM_ALLOC_TO_REQ(sram_alloc, TF_RESC_TYPE_SRAM_SP_SMAC, req,\n+\t\t\t sp_smac);\n+\tTF_SRAM_ALLOC_TO_REQ(sram_alloc, TF_RESC_TYPE_SRAM_SP_SMAC_IPV4,\n+\t\t\t req, sp_smac_ipv4);\n+\tTF_SRAM_ALLOC_TO_REQ(sram_alloc, TF_RESC_TYPE_SRAM_SP_SMAC_IPV6,\n+\t\t\t req, sp_smac_ipv6);\n+\tTF_SRAM_ALLOC_TO_REQ(sram_alloc, TF_RESC_TYPE_SRAM_COUNTER_64B,\n+\t\t\t req, counter_64b);\n+\tTF_SRAM_ALLOC_TO_REQ(sram_alloc, TF_RESC_TYPE_SRAM_NAT_SPORT, req,\n+\t\t\t nat_sport);\n+\tTF_SRAM_ALLOC_TO_REQ(sram_alloc, TF_RESC_TYPE_SRAM_NAT_DPORT, req,\n+\t\t\t nat_dport);\n+\tTF_SRAM_ALLOC_TO_REQ(sram_alloc, TF_RESC_TYPE_SRAM_NAT_S_IPV4, req,\n+\t\t\t nat_s_ipv4);\n+\tTF_SRAM_ALLOC_TO_REQ(sram_alloc, TF_RESC_TYPE_SRAM_NAT_D_IPV4, req,\n+\t\t\t nat_d_ipv4);\n+\n+\tMSG_PREP(parms,\n+\t\t TF_KONG_MB,\n+\t\t HWRM_TF,\n+\t\t HWRM_TFT_SESSION_SRAM_RESC_ALLOC,\n+\t\t req,\n+\t\t resp);\n+\n+\trc = tfp_send_msg_tunneled(tfp, &parms);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\t/* Process the response */\n+\tTF_SRAM_RESP_TO_ALLOC(sram_entry, TF_RESC_TYPE_SRAM_FULL_ACTION,\n+\t\t\t resp, full_action);\n+\tTF_SRAM_RESP_TO_ALLOC(sram_entry, TF_RESC_TYPE_SRAM_MCG, resp,\n+\t\t\t mcg);\n+\tTF_SRAM_RESP_TO_ALLOC(sram_entry, TF_RESC_TYPE_SRAM_ENCAP_8B, resp,\n+\t\t\t encap_8b);\n+\tTF_SRAM_RESP_TO_ALLOC(sram_entry, TF_RESC_TYPE_SRAM_ENCAP_16B, resp,\n+\t\t\t encap_16b);\n+\tTF_SRAM_RESP_TO_ALLOC(sram_entry, TF_RESC_TYPE_SRAM_ENCAP_64B, resp,\n+\t\t\t encap_64b);\n+\tTF_SRAM_RESP_TO_ALLOC(sram_entry, TF_RESC_TYPE_SRAM_SP_SMAC, resp,\n+\t\t\t sp_smac);\n+\tTF_SRAM_RESP_TO_ALLOC(sram_entry, TF_RESC_TYPE_SRAM_SP_SMAC_IPV4,\n+\t\t\t resp, sp_smac_ipv4);\n+\tTF_SRAM_RESP_TO_ALLOC(sram_entry, TF_RESC_TYPE_SRAM_SP_SMAC_IPV6,\n+\t\t\t resp, sp_smac_ipv6);\n+\tTF_SRAM_RESP_TO_ALLOC(sram_entry, TF_RESC_TYPE_SRAM_COUNTER_64B, resp,\n+\t\t\t counter_64b);\n+\tTF_SRAM_RESP_TO_ALLOC(sram_entry, TF_RESC_TYPE_SRAM_NAT_SPORT, resp,\n+\t\t\t nat_sport);\n+\tTF_SRAM_RESP_TO_ALLOC(sram_entry, TF_RESC_TYPE_SRAM_NAT_DPORT, resp,\n+\t\t\t nat_dport);\n+\tTF_SRAM_RESP_TO_ALLOC(sram_entry, TF_RESC_TYPE_SRAM_NAT_S_IPV4, resp,\n+\t\t\t nat_s_ipv4);\n+\tTF_SRAM_RESP_TO_ALLOC(sram_entry, TF_RESC_TYPE_SRAM_NAT_D_IPV4, resp,\n+\t\t\t nat_d_ipv4);\n+\n+\treturn tfp_le_to_cpu_32(parms.tf_resp_code);\n+}\n+\n+/**\n+ * Sends session SRAM resource free request to TF Firmware\n+ */\n+int\n+tf_msg_session_sram_resc_free(struct tf *tfp __rte_unused,\n+\t\t\t enum tf_dir dir,\n+\t\t\t struct tf_rm_entry *sram_entry __rte_unused)\n+{\n+\tint rc;\n+\tstruct tfp_send_msg_parms parms = { 0 };\n+\tstruct tf_session_sram_resc_free_input req = { 0 };\n+\tstruct tf_session *tfs = (struct tf_session *)(tfp->session->core_data);\n+\n+\t/* Populate the request */\n+\treq.fw_session_id =\n+\t\ttfp_cpu_to_le_32(tfs->session_id.internal.fw_session_id);\n+\treq.flags = tfp_cpu_to_le_16(dir);\n+\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_FULL_ACTION, req,\n+\t\t\t full_action);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_MCG, req,\n+\t\t\t mcg);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_ENCAP_8B, req,\n+\t\t\t encap_8b);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_ENCAP_16B, req,\n+\t\t\t encap_16b);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_ENCAP_64B, req,\n+\t\t\t encap_64b);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_SP_SMAC, req,\n+\t\t\t sp_smac);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_SP_SMAC_IPV4, req,\n+\t\t\t sp_smac_ipv4);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_SP_SMAC_IPV6, req,\n+\t\t\t sp_smac_ipv6);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_COUNTER_64B, req,\n+\t\t\t counter_64b);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_NAT_SPORT, req,\n+\t\t\t nat_sport);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_NAT_DPORT, req,\n+\t\t\t nat_dport);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_NAT_S_IPV4, req,\n+\t\t\t nat_s_ipv4);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_NAT_D_IPV4, req,\n+\t\t\t nat_d_ipv4);\n+\n+\tMSG_PREP_NO_RESP(parms,\n+\t\t\t TF_KONG_MB,\n+\t\t\t HWRM_TF,\n+\t\t\t HWRM_TFT_SESSION_SRAM_RESC_FREE,\n+\t\t\t req);\n+\n+\trc = tfp_send_msg_tunneled(tfp, &parms);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\treturn tfp_le_to_cpu_32(parms.tf_resp_code);\n+}\n+\n+/**\n+ * Sends session SRAM resource flush request to TF Firmware\n+ */\n+int\n+tf_msg_session_sram_resc_flush(struct tf *tfp,\n+\t\t\t enum tf_dir dir,\n+\t\t\t struct tf_rm_entry *sram_entry)\n+{\n+\tint rc;\n+\tstruct tfp_send_msg_parms parms = { 0 };\n+\tstruct tf_session_sram_resc_free_input req = { 0 };\n+\tstruct tf_session *tfs = (struct tf_session *)(tfp->session->core_data);\n+\n+\t/* Populate the request */\n+\treq.fw_session_id =\n+\t\ttfp_cpu_to_le_32(tfs->session_id.internal.fw_session_id);\n+\treq.flags = tfp_cpu_to_le_16(dir);\n+\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_FULL_ACTION, req,\n+\t\t\t full_action);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_MCG, req,\n+\t\t\t mcg);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_ENCAP_8B, req,\n+\t\t\t encap_8b);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_ENCAP_16B, req,\n+\t\t\t encap_16b);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_ENCAP_64B, req,\n+\t\t\t encap_64b);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_SP_SMAC, req,\n+\t\t\t sp_smac);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_SP_SMAC_IPV4, req,\n+\t\t\t sp_smac_ipv4);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_SP_SMAC_IPV6, req,\n+\t\t\t sp_smac_ipv6);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_COUNTER_64B, req,\n+\t\t\t counter_64b);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_NAT_SPORT, req,\n+\t\t\t nat_sport);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_NAT_DPORT, req,\n+\t\t\t nat_dport);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_NAT_S_IPV4, req,\n+\t\t\t nat_s_ipv4);\n+\tTF_SRAM_FREE_TO_REQ(sram_entry, TF_RESC_TYPE_SRAM_NAT_D_IPV4, req,\n+\t\t\t nat_d_ipv4);\n+\n+\tMSG_PREP_NO_RESP(parms,\n+\t\t\t TF_KONG_MB,\n+\t\t\t TF_TYPE_TRUFLOW,\n+\t\t\t HWRM_TFT_SESSION_SRAM_RESC_FLUSH,\n+\t\t\t req);\n+\n+\trc = tfp_send_msg_tunneled(tfp, &parms);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\treturn tfp_le_to_cpu_32(parms.tf_resp_code);\n+}\ndiff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h\nindex da5ccf3..057de84 100644\n--- a/drivers/net/bnxt/tf_core/tf_msg.h\n+++ b/drivers/net/bnxt/tf_core/tf_msg.h\n@@ -83,4 +83,41 @@ int tf_msg_session_hw_resc_alloc(struct tf *tfp,\n int tf_msg_session_hw_resc_free(struct tf *tfp,\n \t\t\t\tenum tf_dir dir,\n \t\t\t\tstruct tf_rm_entry *hw_entry);\n+\n+/**\n+ * Sends session HW resource flush request to TF Firmware\n+ */\n+int tf_msg_session_hw_resc_flush(struct tf *tfp,\n+\t\t\t\t enum tf_dir dir,\n+\t\t\t\t struct tf_rm_entry *hw_entry);\n+\n+/**\n+ * Sends session SRAM resource query capability request to TF Firmware\n+ */\n+int tf_msg_session_sram_resc_qcaps(struct tf *tfp,\n+\t\t\t\t enum tf_dir dir,\n+\t\t\t\t struct tf_rm_sram_query *sram_query);\n+\n+/**\n+ * Sends session SRAM resource allocation request to TF Firmware\n+ */\n+int tf_msg_session_sram_resc_alloc(struct tf *tfp,\n+\t\t\t\t enum tf_dir dir,\n+\t\t\t\t struct tf_rm_sram_alloc *sram_alloc,\n+\t\t\t\t struct tf_rm_entry *sram_entry);\n+\n+/**\n+ * Sends session SRAM resource free request to TF Firmware\n+ */\n+int tf_msg_session_sram_resc_free(struct tf *tfp,\n+\t\t\t\t enum tf_dir dir,\n+\t\t\t\t struct tf_rm_entry *sram_entry);\n+\n+/**\n+ * Sends session SRAM resource flush request to TF Firmware\n+ */\n+int tf_msg_session_sram_resc_flush(struct tf *tfp,\n+\t\t\t\t enum tf_dir dir,\n+\t\t\t\t struct tf_rm_entry *sram_entry);\n+\n #endif /* _TF_MSG_H_ */\ndiff --git a/drivers/net/bnxt/tf_core/tf_resources.h b/drivers/net/bnxt/tf_core/tf_resources.h\nindex 8dbb2f9..05e131f 100644\n--- a/drivers/net/bnxt/tf_core/tf_resources.h\n+++ b/drivers/net/bnxt/tf_core/tf_resources.h\n@@ -6,6 +6,487 @@\n #ifndef _TF_RESOURCES_H_\n #define _TF_RESOURCES_H_\n \n+/*\n+ * Hardware specific MAX values\n+ * NOTE: Should really come from the chip_cfg.h in some MAX form or HCAPI\n+ */\n+\n+/* Common HW resources for all chip variants */\n+#define TF_NUM_L2_CTXT_TCAM 1024 /* < Number of L2 context TCAM\n+\t\t\t\t\t * entries\n+\t\t\t\t\t */\n+#define TF_NUM_PROF_FUNC 128 /* < Number prof_func ID */\n+#define TF_NUM_PROF_TCAM 1024 /* < Number entries in profile\n+\t\t\t\t\t * TCAM\n+\t\t\t\t\t */\n+#define TF_NUM_EM_PROF_ID 64 /* < Number software EM Profile\n+\t\t\t\t\t * IDs\n+\t\t\t\t\t */\n+#define TF_NUM_WC_PROF_ID 256 /* < Number WC profile IDs */\n+#define TF_NUM_WC_TCAM_ROW 256 /* Number slices per row in WC\n+\t\t\t\t\t * TCAM. A slices is a WC TCAM entry.\n+\t\t\t\t\t */\n+#define TF_NUM_METER_PROF 256 /* < Number of meter profiles */\n+#define TF_NUM_METER 1024 /* < Number of meter instances */\n+#define TF_NUM_MIRROR 2 /* < Number of mirror instances */\n+#define TF_NUM_UPAR 2 /* < Number of UPAR instances */\n+\n+/* Wh+/Brd2 specific HW resources */\n+#define TF_NUM_SP_TCAM 512 /* < Number of Source Property TCAM\n+\t\t\t\t\t * entries\n+\t\t\t\t\t */\n+\n+/* Brd2/Brd4 specific HW resources */\n+#define TF_NUM_L2_FUNC 256 /* < Number of L2 Func */\n+\n+\n+/* Brd3, Brd4 common HW resources */\n+#define TF_NUM_FKB 1 /* < Number of Flexible Key Builder\n+\t\t\t\t\t * templates\n+\t\t\t\t\t */\n+\n+/* Brd4 specific HW resources */\n+#define TF_NUM_TBL_SCOPE 16 /* < Number of TBL scopes */\n+#define TF_NUM_EPOCH0 1 /* < Number of Epoch0 */\n+#define TF_NUM_EPOCH1 1 /* < Number of Epoch1 */\n+#define TF_NUM_METADATA 8 /* < Number of MetaData Profiles */\n+#define TF_NUM_CT_STATE 32 /* < Number of Connection Tracking\n+\t\t\t\t\t * States\n+\t\t\t\t\t */\n+#define TF_NUM_RANGE_PROF 16 /* < Number of Range Profiles */\n+#define TF_NUM_RANGE_ENTRY (64 * 1024) /* < Number of Range Entries */\n+#define TF_NUM_LAG_ENTRY 256 /* < Number of LAG Entries */\n+\n+/*\n+ * Common for the Reserved Resource defines below:\n+ *\n+ * - HW Resources\n+ * For resources where a priority level plays a role, i.e. l2 ctx\n+ * tcam entries, both a number of resources and a begin/end pair is\n+ * required. The begin/end is used to assure TFLIB gets the correct\n+ * priority setting for that resource.\n+ *\n+ * For EM records there is no priority required thus a number of\n+ * resources is sufficient.\n+ *\n+ * Example, TCAM:\n+ * 64 L2 CTXT TCAM entries would in a max 1024 pool be entry\n+ * 0-63 as HW presents 0 as the highest priority entry.\n+ *\n+ * - SRAM Resources\n+ * Handled as regular resources as there is no priority required.\n+ *\n+ * Common for these resources is that they are handled per direction,\n+ * rx/tx.\n+ */\n+\n+/* HW Resources */\n+\n+/* L2 CTX */\n+#define TF_RSVD_L2_CTXT_TCAM_RX 64\n+#define TF_RSVD_L2_CTXT_TCAM_BEGIN_IDX_RX 0\n+#define TF_RSVD_L2_CTXT_TCAM_END_IDX_RX (TF_RSVD_L2_CTXT_RX - 1)\n+#define TF_RSVD_L2_CTXT_TCAM_TX 960\n+#define TF_RSVD_L2_CTXT_TCAM_BEGIN_IDX_TX 0\n+#define TF_RSVD_L2_CTXT_TCAM_END_IDX_TX (TF_RSVD_L2_CTXT_TX - 1)\n+\n+/* Profiler */\n+#define TF_RSVD_PROF_FUNC_RX 64\n+#define TF_RSVD_PROF_FUNC_BEGIN_IDX_RX 64\n+#define TF_RSVD_PROF_FUNC_END_IDX_RX 127\n+#define TF_RSVD_PROF_FUNC_TX 64\n+#define TF_RSVD_PROF_FUNC_BEGIN_IDX_TX 64\n+#define TF_RSVD_PROF_FUNC_END_IDX_TX 127\n+\n+#define TF_RSVD_PROF_TCAM_RX 64\n+#define TF_RSVD_PROF_TCAM_BEGIN_IDX_RX 960\n+#define TF_RSVD_PROF_TCAM_END_IDX_RX 1023\n+#define TF_RSVD_PROF_TCAM_TX 64\n+#define TF_RSVD_PROF_TCAM_BEGIN_IDX_TX 960\n+#define TF_RSVD_PROF_TCAM_END_IDX_TX 1023\n+\n+/* EM Profiles IDs */\n+#define TF_RSVD_EM_PROF_ID_RX 64\n+#define TF_RSVD_EM_PROF_ID_BEGIN_IDX_RX 0\n+#define TF_RSVD_EM_PROF_ID_END_IDX_RX 63 /* Less on CU+ then SR */\n+#define TF_RSVD_EM_PROF_ID_TX 64\n+#define TF_RSVD_EM_PROF_ID_BEGIN_IDX_TX 0\n+#define TF_RSVD_EM_PROF_ID_END_IDX_TX 63 /* Less on CU+ then SR */\n+\n+/* EM Records */\n+#define TF_RSVD_EM_REC_RX 16000\n+#define TF_RSVD_EM_REC_BEGIN_IDX_RX 0\n+#define TF_RSVD_EM_REC_TX 16000\n+#define TF_RSVD_EM_REC_BEGIN_IDX_TX 0\n+\n+/* Wildcard */\n+#define TF_RSVD_WC_TCAM_PROF_ID_RX 128\n+#define TF_RSVD_WC_TCAM_PROF_ID_BEGIN_IDX_RX 128\n+#define TF_RSVD_WC_TCAM_PROF_ID_END_IDX_RX 255\n+#define TF_RSVD_WC_TCAM_PROF_ID_TX 128\n+#define TF_RSVD_WC_TCAM_PROF_ID_BEGIN_IDX_TX 128\n+#define TF_RSVD_WC_TCAM_PROF_ID_END_IDX_TX 255\n+\n+#define TF_RSVD_WC_TCAM_RX 64\n+#define TF_RSVD_WC_TCAM_BEGIN_IDX_RX 0\n+#define TF_RSVD_WC_TCAM_END_IDX_RX 63\n+#define TF_RSVD_WC_TCAM_TX 64\n+#define TF_RSVD_WC_TCAM_BEGIN_IDX_TX 0\n+#define TF_RSVD_WC_TCAM_END_IDX_TX 63\n+\n+#define TF_RSVD_METER_PROF_RX 0\n+#define TF_RSVD_METER_PROF_BEGIN_IDX_RX 0\n+#define TF_RSVD_METER_PROF_END_IDX_RX 0\n+#define TF_RSVD_METER_PROF_TX 0\n+#define TF_RSVD_METER_PROF_BEGIN_IDX_TX 0\n+#define TF_RSVD_METER_PROF_END_IDX_TX 0\n+\n+#define TF_RSVD_METER_INST_RX 0\n+#define TF_RSVD_METER_INST_BEGIN_IDX_RX 0\n+#define TF_RSVD_METER_INST_END_IDX_RX 0\n+#define TF_RSVD_METER_INST_TX 0\n+#define TF_RSVD_METER_INST_BEGIN_IDX_TX 0\n+#define TF_RSVD_METER_INST_END_IDX_TX 0\n+\n+/* Mirror */\n+/* Not yet supported fully in the infra */\n+#define TF_RSVD_MIRROR_RX 0\n+#define TF_RSVD_MIRROR_BEGIN_IDX_RX 0\n+#define TF_RSVD_MIRROR_END_IDX_RX 0\n+#define TF_RSVD_MIRROR_TX 0\n+#define TF_RSVD_MIRROR_BEGIN_IDX_TX 0\n+#define TF_RSVD_MIRROR_END_IDX_TX 0\n+\n+/* UPAR */\n+/* Not yet supported fully in the infra */\n+#define TF_RSVD_UPAR_RX 0\n+#define TF_RSVD_UPAR_BEGIN_IDX_RX 0\n+#define TF_RSVD_UPAR_END_IDX_RX 0\n+#define TF_RSVD_UPAR_TX 0\n+#define TF_RSVD_UPAR_BEGIN_IDX_TX 0\n+#define TF_RSVD_UPAR_END_IDX_TX 0\n+\n+/* Source Properties */\n+/* Not yet supported fully in the infra */\n+#define TF_RSVD_SP_TCAM_RX 0\n+#define TF_RSVD_SP_TCAM_BEGIN_IDX_RX 0\n+#define TF_RSVD_SP_TCAM_END_IDX_RX 0\n+#define TF_RSVD_SP_TCAM_TX 0\n+#define TF_RSVD_SP_TCAM_BEGIN_IDX_TX 0\n+#define TF_RSVD_SP_TCAM_END_IDX_TX 0\n+\n+/* L2 Func */\n+#define TF_RSVD_L2_FUNC_RX 0\n+#define TF_RSVD_L2_FUNC_BEGIN_IDX_RX 0\n+#define TF_RSVD_L2_FUNC_END_IDX_RX 0\n+#define TF_RSVD_L2_FUNC_TX 0\n+#define TF_RSVD_L2_FUNC_BEGIN_IDX_TX 0\n+#define TF_RSVD_L2_FUNC_END_IDX_TX 0\n+\n+/* FKB */\n+#define TF_RSVD_FKB_RX 0\n+#define TF_RSVD_FKB_BEGIN_IDX_RX 0\n+#define TF_RSVD_FKB_END_IDX_RX 0\n+#define TF_RSVD_FKB_TX 0\n+#define TF_RSVD_FKB_BEGIN_IDX_TX 0\n+#define TF_RSVD_FKB_END_IDX_TX 0\n+\n+/* TBL Scope */\n+#define TF_RSVD_TBL_SCOPE_RX 1\n+#define TF_RSVD_TBL_SCOPE_BEGIN_IDX_RX 0\n+#define TF_RSVD_TBL_SCOPE_END_IDX_RX 1\n+#define TF_RSVD_TBL_SCOPE_TX 1\n+#define TF_RSVD_TBL_SCOPE_BEGIN_IDX_TX 0\n+#define TF_RSVD_TBL_SCOPE_END_IDX_TX 1\n+\n+/* EPOCH0 */\n+/* Not yet supported fully in the infra */\n+#define TF_RSVD_EPOCH0_RX 0\n+#define TF_RSVD_EPOCH0_BEGIN_IDX_RX 0\n+#define TF_RSVD_EPOCH0_END_IDX_RX 0\n+#define TF_RSVD_EPOCH0_TX 0\n+#define TF_RSVD_EPOCH0_BEGIN_IDX_TX 0\n+#define TF_RSVD_EPOCH0_END_IDX_TX 0\n+\n+/* EPOCH1 */\n+/* Not yet supported fully in the infra */\n+#define TF_RSVD_EPOCH1_RX 0\n+#define TF_RSVD_EPOCH1_BEGIN_IDX_RX 0\n+#define TF_RSVD_EPOCH1_END_IDX_RX 0\n+#define TF_RSVD_EPOCH1_TX 0\n+#define TF_RSVD_EPOCH1_BEGIN_IDX_TX 0\n+#define TF_RSVD_EPOCH1_END_IDX_TX 0\n+\n+/* METADATA */\n+/* Not yet supported fully in the infra */\n+#define TF_RSVD_METADATA_RX 0\n+#define TF_RSVD_METADATA_BEGIN_IDX_RX 0\n+#define TF_RSVD_METADATA_END_IDX_RX 0\n+#define TF_RSVD_METADATA_TX 0\n+#define TF_RSVD_METADATA_BEGIN_IDX_TX 0\n+#define TF_RSVD_METADATA_END_IDX_TX 0\n+\n+/* CT_STATE */\n+/* Not yet supported fully in the infra */\n+#define TF_RSVD_CT_STATE_RX 0\n+#define TF_RSVD_CT_STATE_BEGIN_IDX_RX 0\n+#define TF_RSVD_CT_STATE_END_IDX_RX 0\n+#define TF_RSVD_CT_STATE_TX 0\n+#define TF_RSVD_CT_STATE_BEGIN_IDX_TX 0\n+#define TF_RSVD_CT_STATE_END_IDX_TX 0\n+\n+/* RANGE_PROF */\n+/* Not yet supported fully in the infra */\n+#define TF_RSVD_RANGE_PROF_RX 0\n+#define TF_RSVD_RANGE_PROF_BEGIN_IDX_RX 0\n+#define TF_RSVD_RANGE_PROF_END_IDX_RX 0\n+#define TF_RSVD_RANGE_PROF_TX 0\n+#define TF_RSVD_RANGE_PROF_BEGIN_IDX_TX 0\n+#define TF_RSVD_RANGE_PROF_END_IDX_TX 0\n+\n+/* RANGE_ENTRY */\n+/* Not yet supported fully in the infra */\n+#define TF_RSVD_RANGE_ENTRY_RX 0\n+#define TF_RSVD_RANGE_ENTRY_BEGIN_IDX_RX 0\n+#define TF_RSVD_RANGE_ENTRY_END_IDX_RX 0\n+#define TF_RSVD_RANGE_ENTRY_TX 0\n+#define TF_RSVD_RANGE_ENTRY_BEGIN_IDX_TX 0\n+#define TF_RSVD_RANGE_ENTRY_END_IDX_TX 0\n+\n+/* LAG_ENTRY */\n+/* Not yet supported fully in the infra */\n+#define TF_RSVD_LAG_ENTRY_RX 0\n+#define TF_RSVD_LAG_ENTRY_BEGIN_IDX_RX 0\n+#define TF_RSVD_LAG_ENTRY_END_IDX_RX 0\n+#define TF_RSVD_LAG_ENTRY_TX 0\n+#define TF_RSVD_LAG_ENTRY_BEGIN_IDX_TX 0\n+#define TF_RSVD_LAG_ENTRY_END_IDX_TX 0\n+\n+\n+/* SRAM - Resources\n+ * Limited to the types that CFA provides.\n+ */\n+#define TF_RSVD_SRAM_FULL_ACTION_RX 8001\n+#define TF_RSVD_SRAM_FULL_ACTION_BEGIN_IDX_RX 0\n+#define TF_RSVD_SRAM_FULL_ACTION_TX 8001\n+#define TF_RSVD_SRAM_FULL_ACTION_BEGIN_IDX_TX 0\n+\n+/* Not yet supported fully in the infra */\n+#define TF_RSVD_SRAM_MCG_RX 0\n+#define TF_RSVD_SRAM_MCG_BEGIN_IDX_RX 0\n+/* Multicast Group on TX is not supported */\n+#define TF_RSVD_SRAM_MCG_TX 0\n+#define TF_RSVD_SRAM_MCG_BEGIN_IDX_TX 0\n+\n+/* First encap of 8B RX is reserved by CFA */\n+#define TF_RSVD_SRAM_ENCAP_8B_RX 32\n+#define TF_RSVD_SRAM_ENCAP_8B_BEGIN_IDX_RX 0\n+/* First encap of 8B TX is reserved by CFA */\n+#define TF_RSVD_SRAM_ENCAP_8B_TX 0\n+#define TF_RSVD_SRAM_ENCAP_8B_BEGIN_IDX_TX 0\n+\n+#define TF_RSVD_SRAM_ENCAP_16B_RX 16\n+#define TF_RSVD_SRAM_ENCAP_16B_BEGIN_IDX_RX 0\n+/* First encap of 16B TX is reserved by CFA */\n+#define TF_RSVD_SRAM_ENCAP_16B_TX 20\n+#define TF_RSVD_SRAM_ENCAP_16B_BEGIN_IDX_TX 0\n+\n+/* Encap of 64B on RX is not supported */\n+#define TF_RSVD_SRAM_ENCAP_64B_RX 0\n+#define TF_RSVD_SRAM_ENCAP_64B_BEGIN_IDX_RX 0\n+/* First encap of 64B TX is reserved by CFA */\n+#define TF_RSVD_SRAM_ENCAP_64B_TX 1007\n+#define TF_RSVD_SRAM_ENCAP_64B_BEGIN_IDX_TX 0\n+\n+#define TF_RSVD_SRAM_SP_SMAC_RX 0\n+#define TF_RSVD_SRAM_SP_SMAC_BEGIN_IDX_RX 0\n+#define TF_RSVD_SRAM_SP_SMAC_TX 0\n+#define TF_RSVD_SRAM_SP_SMAC_BEGIN_IDX_TX 0\n+\n+/* SRAM SP IPV4 on RX is not supported */\n+#define TF_RSVD_SRAM_SP_SMAC_IPV4_RX 0\n+#define TF_RSVD_SRAM_SP_SMAC_IPV4_BEGIN_IDX_RX 0\n+#define TF_RSVD_SRAM_SP_SMAC_IPV4_TX 511\n+#define TF_RSVD_SRAM_SP_SMAC_IPV4_BEGIN_IDX_TX 0\n+\n+/* SRAM SP IPV6 on RX is not supported */\n+#define TF_RSVD_SRAM_SP_SMAC_IPV6_RX 0\n+#define TF_RSVD_SRAM_SP_SMAC_IPV6_BEGIN_IDX_RX 0\n+/* Not yet supported fully in infra */\n+#define TF_RSVD_SRAM_SP_SMAC_IPV6_TX 0\n+#define TF_RSVD_SRAM_SP_SMAC_IPV6_BEGIN_IDX_TX 0\n+\n+#define TF_RSVD_SRAM_COUNTER_64B_RX 160\n+#define TF_RSVD_SRAM_COUNTER_64B_BEGIN_IDX_RX 0\n+#define TF_RSVD_SRAM_COUNTER_64B_TX 160\n+#define TF_RSVD_SRAM_COUNTER_64B_BEGIN_IDX_TX 0\n+\n+#define TF_RSVD_SRAM_NAT_SPORT_RX 0\n+#define TF_RSVD_SRAM_NAT_SPORT_BEGIN_IDX_RX 0\n+#define TF_RSVD_SRAM_NAT_SPORT_TX 0\n+#define TF_RSVD_SRAM_NAT_SPORT_BEGIN_IDX_TX 0\n+\n+#define TF_RSVD_SRAM_NAT_DPORT_RX 0\n+#define TF_RSVD_SRAM_NAT_DPORT_BEGIN_IDX_RX 0\n+#define TF_RSVD_SRAM_NAT_DPORT_TX 0\n+#define TF_RSVD_SRAM_NAT_DPORT_BEGIN_IDX_TX 0\n+\n+#define TF_RSVD_SRAM_NAT_S_IPV4_RX 0\n+#define TF_RSVD_SRAM_NAT_S_IPV4_BEGIN_IDX_RX 0\n+#define TF_RSVD_SRAM_NAT_S_IPV4_TX 0\n+#define TF_RSVD_SRAM_NAT_S_IPV4_BEGIN_IDX_TX 0\n+\n+#define TF_RSVD_SRAM_NAT_D_IPV4_RX 0\n+#define TF_RSVD_SRAM_NAT_D_IPV4_BEGIN_IDX_RX 0\n+#define TF_RSVD_SRAM_NAT_D_IPV4_TX 0\n+#define TF_RSVD_SRAM_NAT_D_IPV4_BEGIN_IDX_TX 0\n+\n+/* HW Resource Pool names */\n+\n+#define TF_L2_CTXT_TCAM_POOL_NAME l2_ctxt_tcam_pool\n+#define TF_L2_CTXT_TCAM_POOL_NAME_RX l2_ctxt_tcam_pool_rx\n+#define TF_L2_CTXT_TCAM_POOL_NAME_TX l2_ctxt_tcam_pool_tx\n+\n+#define TF_PROF_FUNC_POOL_NAME prof_func_pool\n+#define TF_PROF_FUNC_POOL_NAME_RX prof_func_pool_rx\n+#define TF_PROF_FUNC_POOL_NAME_TX prof_func_pool_tx\n+\n+#define TF_PROF_TCAM_POOL_NAME prof_tcam_pool\n+#define TF_PROF_TCAM_POOL_NAME_RX prof_tcam_pool_rx\n+#define TF_PROF_TCAM_POOL_NAME_TX prof_tcam_pool_tx\n+\n+#define TF_EM_PROF_ID_POOL_NAME em_prof_id_pool\n+#define TF_EM_PROF_ID_POOL_NAME_RX em_prof_id_pool_rx\n+#define TF_EM_PROF_ID_POOL_NAME_TX em_prof_id_pool_tx\n+\n+#define TF_WC_TCAM_PROF_ID_POOL_NAME wc_tcam_prof_id_pool\n+#define TF_WC_TCAM_PROF_ID_POOL_NAME_RX wc_tcam_prof_id_pool_rx\n+#define TF_WC_TCAM_PROF_ID_POOL_NAME_TX wc_tcam_prof_id_pool_tx\n+\n+#define TF_WC_TCAM_POOL_NAME wc_tcam_pool\n+#define TF_WC_TCAM_POOL_NAME_RX wc_tcam_pool_rx\n+#define TF_WC_TCAM_POOL_NAME_TX wc_tcam_pool_tx\n+\n+#define TF_METER_PROF_POOL_NAME meter_prof_pool\n+#define TF_METER_PROF_POOL_NAME_RX meter_prof_pool_rx\n+#define TF_METER_PROF_POOL_NAME_TX meter_prof_pool_tx\n+\n+#define TF_METER_INST_POOL_NAME meter_inst_pool\n+#define TF_METER_INST_POOL_NAME_RX meter_inst_pool_rx\n+#define TF_METER_INST_POOL_NAME_TX meter_inst_pool_tx\n+\n+#define TF_MIRROR_POOL_NAME mirror_pool\n+#define TF_MIRROR_POOL_NAME_RX mirror_pool_rx\n+#define TF_MIRROR_POOL_NAME_TX mirror_pool_tx\n+\n+#define TF_UPAR_POOL_NAME upar_pool\n+#define TF_UPAR_POOL_NAME_RX upar_pool_rx\n+#define TF_UPAR_POOL_NAME_TX upar_pool_tx\n+\n+#define TF_SP_TCAM_POOL_NAME sp_tcam_pool\n+#define TF_SP_TCAM_POOL_NAME_RX sp_tcam_pool_rx\n+#define TF_SP_TCAM_POOL_NAME_TX sp_tcam_pool_tx\n+\n+#define TF_FKB_POOL_NAME fkb_pool\n+#define TF_FKB_POOL_NAME_RX fkb_pool_rx\n+#define TF_FKB_POOL_NAME_TX fkb_pool_tx\n+\n+#define TF_TBL_SCOPE_POOL_NAME tbl_scope_pool\n+#define TF_TBL_SCOPE_POOL_NAME_RX tbl_scope_pool_rx\n+#define TF_TBL_SCOPE_POOL_NAME_TX tbl_scope_pool_tx\n+\n+#define TF_L2_FUNC_POOL_NAME l2_func_pool\n+#define TF_L2_FUNC_POOL_NAME_RX l2_func_pool_rx\n+#define TF_L2_FUNC_POOL_NAME_TX l2_func_pool_tx\n+\n+#define TF_EPOCH0_POOL_NAME epoch0_pool\n+#define TF_EPOCH0_POOL_NAME_RX epoch0_pool_rx\n+#define TF_EPOCH0_POOL_NAME_TX epoch0_pool_tx\n+\n+#define TF_EPOCH1_POOL_NAME epoch1_pool\n+#define TF_EPOCH1_POOL_NAME_RX epoch1_pool_rx\n+#define TF_EPOCH1_POOL_NAME_TX epoch1_pool_tx\n+\n+#define TF_METADATA_POOL_NAME metadata_pool\n+#define TF_METADATA_POOL_NAME_RX metadata_pool_rx\n+#define TF_METADATA_POOL_NAME_TX metadata_pool_tx\n+\n+#define TF_CT_STATE_POOL_NAME ct_state_pool\n+#define TF_CT_STATE_POOL_NAME_RX ct_state_pool_rx\n+#define TF_CT_STATE_POOL_NAME_TX ct_state_pool_tx\n+\n+#define TF_RANGE_PROF_POOL_NAME range_prof_pool\n+#define TF_RANGE_PROF_POOL_NAME_RX range_prof_pool_rx\n+#define TF_RANGE_PROF_POOL_NAME_TX range_prof_pool_tx\n+\n+#define TF_RANGE_ENTRY_POOL_NAME range_entry_pool\n+#define TF_RANGE_ENTRY_POOL_NAME_RX range_entry_pool_rx\n+#define TF_RANGE_ENTRY_POOL_NAME_TX range_entry_pool_tx\n+\n+#define TF_LAG_ENTRY_POOL_NAME lag_entry_pool\n+#define TF_LAG_ENTRY_POOL_NAME_RX lag_entry_pool_rx\n+#define TF_LAG_ENTRY_POOL_NAME_TX lag_entry_pool_tx\n+\n+/* SRAM Resource Pool names */\n+#define TF_SRAM_FULL_ACTION_POOL_NAME sram_full_action_pool\n+#define TF_SRAM_FULL_ACTION_POOL_NAME_RX sram_full_action_pool_rx\n+#define TF_SRAM_FULL_ACTION_POOL_NAME_TX sram_full_action_pool_tx\n+\n+#define TF_SRAM_MCG_POOL_NAME sram_mcg_pool\n+#define TF_SRAM_MCG_POOL_NAME_RX sram_mcg_pool_rx\n+#define TF_SRAM_MCG_POOL_NAME_TX sram_mcg_pool_tx\n+\n+#define TF_SRAM_ENCAP_8B_POOL_NAME sram_encap_8b_pool\n+#define TF_SRAM_ENCAP_8B_POOL_NAME_RX sram_encap_8b_pool_rx\n+#define TF_SRAM_ENCAP_8B_POOL_NAME_TX sram_encap_8b_pool_tx\n+\n+#define TF_SRAM_ENCAP_16B_POOL_NAME sram_encap_16b_pool\n+#define TF_SRAM_ENCAP_16B_POOL_NAME_RX sram_encap_16b_pool_rx\n+#define TF_SRAM_ENCAP_16B_POOL_NAME_TX sram_encap_16b_pool_tx\n+\n+#define TF_SRAM_ENCAP_64B_POOL_NAME sram_encap_64b_pool\n+#define TF_SRAM_ENCAP_64B_POOL_NAME_RX sram_encap_64b_pool_rx\n+#define TF_SRAM_ENCAP_64B_POOL_NAME_TX sram_encap_64b_pool_tx\n+\n+#define TF_SRAM_SP_SMAC_POOL_NAME sram_sp_smac_pool\n+#define TF_SRAM_SP_SMAC_POOL_NAME_RX sram_sp_smac_pool_rx\n+#define TF_SRAM_SP_SMAC_POOL_NAME_TX sram_sp_smac_pool_tx\n+\n+#define TF_SRAM_SP_SMAC_IPV4_POOL_NAME sram_sp_smac_ipv4_pool\n+#define TF_SRAM_SP_SMAC_IPV4_POOL_NAME_RX sram_sp_smac_ipv4_pool_rx\n+#define TF_SRAM_SP_SMAC_IPV4_POOL_NAME_TX sram_sp_smac_ipv4_pool_tx\n+\n+#define TF_SRAM_SP_SMAC_IPV6_POOL_NAME sram_sp_smac_ipv6_pool\n+#define TF_SRAM_SP_SMAC_IPV6_POOL_NAME_RX sram_sp_smac_ipv6_pool_rx\n+#define TF_SRAM_SP_SMAC_IPV6_POOL_NAME_TX sram_sp_smac_ipv6_pool_tx\n+\n+#define TF_SRAM_STATS_64B_POOL_NAME sram_stats_64b_pool\n+#define TF_SRAM_STATS_64B_POOL_NAME_RX sram_stats_64b_pool_rx\n+#define TF_SRAM_STATS_64B_POOL_NAME_TX sram_stats_64b_pool_tx\n+\n+#define TF_SRAM_NAT_SPORT_POOL_NAME sram_nat_sport_pool\n+#define TF_SRAM_NAT_SPORT_POOL_NAME_RX sram_nat_sport_pool_rx\n+#define TF_SRAM_NAT_SPORT_POOL_NAME_TX sram_nat_sport_pool_tx\n+\n+#define TF_SRAM_NAT_DPORT_POOL_NAME sram_nat_dport_pool\n+#define TF_SRAM_NAT_DPORT_POOL_NAME_RX sram_nat_dport_pool_rx\n+#define TF_SRAM_NAT_DPORT_POOL_NAME_TX sram_nat_dport_pool_tx\n+\n+#define TF_SRAM_NAT_S_IPV4_POOL_NAME sram_nat_s_ipv4_pool\n+#define TF_SRAM_NAT_S_IPV4_POOL_NAME_RX sram_nat_s_ipv4_pool_rx\n+#define TF_SRAM_NAT_S_IPV4_POOL_NAME_TX sram_nat_s_ipv4_pool_tx\n+\n+#define TF_SRAM_NAT_D_IPV4_POOL_NAME sram_nat_d_ipv4_pool\n+#define TF_SRAM_NAT_D_IPV4_POOL_NAME_RX sram_nat_d_ipv4_pool_rx\n+#define TF_SRAM_NAT_D_IPV4_POOL_NAME_TX sram_nat_d_ipv4_pool_tx\n+\n+/* Sw Resource Pool Names */\n+\n+#define TF_L2_CTXT_REMAP_POOL_NAME l2_ctxt_remap_pool\n+#define TF_L2_CTXT_REMAP_POOL_NAME_RX l2_ctxt_remap_pool_rx\n+#define TF_L2_CTXT_REMAP_POOL_NAME_TX l2_ctxt_remap_pool_tx\n+\n+\n /** HW Resource types\n */\n enum tf_resource_type_hw {\n@@ -57,4 +538,5 @@ enum tf_resource_type_sram {\n \tTF_RESC_TYPE_SRAM_NAT_D_IPV4,\n \tTF_RESC_TYPE_SRAM_MAX\n };\n+\n #endif /* _TF_RESOURCES_H_ */\n", "prefixes": [ "06/33" ] }