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GET /api/patches/66698/?format=api
{ "id": 66698, "url": "http://patches.dpdk.org/api/patches/66698/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1584351224-23500-8-git-send-email-hkalra@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1584351224-23500-8-git-send-email-hkalra@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1584351224-23500-8-git-send-email-hkalra@marvell.com", "date": "2020-03-16T09:33:43", "name": "[7/8] net/octeontx: add flow control support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "555bb8fbf4bee310f6460473a4cf2c56a249a13c", "submitter": { "id": 1182, "url": "http://patches.dpdk.org/api/people/1182/?format=api", "name": "Harman Kalra", "email": "hkalra@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1584351224-23500-8-git-send-email-hkalra@marvell.com/mbox/", "series": [ { "id": 8923, "url": "http://patches.dpdk.org/api/series/8923/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8923", "date": "2020-03-16T09:33:36", "name": "add new features to octeontx PMD", "version": 1, "mbox": "http://patches.dpdk.org/series/8923/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/66698/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/66698/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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"HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n 3FP7KP2ootXW7ggfgVgajOdvamOu3DyhcLvnu8DxA6Djqkt+5tfK7gmuE2YupM2MfCZA+AiAjR3q6sPCl2Cvqg==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR18MB3117", "X-OriginatorOrg": "marvell.com", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572\n definitions=2020-03-16_02:2020-03-12,\n 2020-03-16 signatures=0", "Subject": "[dpdk-dev] [PATCH 7/8] net/octeontx: add flow control support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Vamsi Attunuru <vattunuru@marvell.com>\n\nPatch adds ethdev flow control set/get callback ops,\npmd enables modifying flow control attributes like\nrx_pause, tx_pause, high & low water mark.\n\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\n---\n doc/guides/nics/features/octeontx.ini | 1 +\n drivers/net/octeontx/base/octeontx_bgx.c | 50 ++++++++\n drivers/net/octeontx/base/octeontx_bgx.h | 28 +++++\n drivers/net/octeontx/octeontx_ethdev.c | 20 ++++\n drivers/net/octeontx/octeontx_ethdev.h | 19 +++\n drivers/net/octeontx/octeontx_ethdev_ops.c | 128 +++++++++++++++++++++\n 6 files changed, 246 insertions(+)", "diff": "diff --git a/doc/guides/nics/features/octeontx.ini b/doc/guides/nics/features/octeontx.ini\nindex 377bb4d30..6049c1c43 100644\n--- a/doc/guides/nics/features/octeontx.ini\n+++ b/doc/guides/nics/features/octeontx.ini\n@@ -18,6 +18,7 @@ VLAN filter = Y\n VLAN offload = P\n CRC offload = Y\n Packet type parsing = Y\n+Flow control = Y\n Basic stats = Y\n Linux VFIO = Y\n ARMv8 = Y\ndiff --git a/drivers/net/octeontx/base/octeontx_bgx.c b/drivers/net/octeontx/base/octeontx_bgx.c\nindex d8611cb77..ac856ff86 100644\n--- a/drivers/net/octeontx/base/octeontx_bgx.c\n+++ b/drivers/net/octeontx/base/octeontx_bgx.c\n@@ -326,3 +326,53 @@ octeontx_bgx_port_mac_entries_get(int port)\n \n \treturn resp;\n }\n+\n+int octeontx_bgx_port_get_fifo_cfg(int port,\n+\t\t\t\t octeontx_mbox_bgx_port_fifo_cfg_t *cfg)\n+{\n+\tint len = sizeof(octeontx_mbox_bgx_port_fifo_cfg_t);\n+\tocteontx_mbox_bgx_port_fifo_cfg_t conf;\n+\tstruct octeontx_mbox_hdr hdr;\n+\n+\thdr.coproc = OCTEONTX_BGX_COPROC;\n+\thdr.msg = MBOX_BGX_PORT_GET_FIFO_CFG;\n+\thdr.vfid = port;\n+\n+\tif (octeontx_mbox_send(&hdr, NULL, 0, &conf, len) < 0)\n+\t\treturn -EACCES;\n+\n+\tcfg->rx_fifosz = conf.rx_fifosz;\n+\n+\treturn 0;\n+}\n+\n+int octeontx_bgx_port_flow_ctrl_cfg(int port,\n+\t\t\t\t octeontx_mbox_bgx_port_fc_cfg_t *cfg)\n+{\n+\tint len = sizeof(octeontx_mbox_bgx_port_fc_cfg_t);\n+\tocteontx_mbox_bgx_port_fc_cfg_t conf;\n+\tstruct octeontx_mbox_hdr hdr;\n+\n+\thdr.coproc = OCTEONTX_BGX_COPROC;\n+\thdr.msg = MBOX_BGX_PORT_FLOW_CTRL_CFG;\n+\thdr.vfid = port;\n+\n+\tif (cfg->fc_cfg == BGX_PORT_FC_CFG_SET)\n+\t\tmemcpy(&conf, cfg, len);\n+\telse\n+\t\tmemset(&conf, 0, len);\n+\n+\tif (octeontx_mbox_send(&hdr, &conf, len, &conf, len) < 0)\n+\t\treturn -EACCES;\n+\n+\tif (cfg->fc_cfg == BGX_PORT_FC_CFG_SET)\n+\t\tgoto done;\n+\n+\tcfg->rx_pause = conf.rx_pause;\n+\tcfg->tx_pause = conf.tx_pause;\n+\tcfg->low_water = conf.low_water;\n+\tcfg->high_water = conf.high_water;\n+\n+done:\n+\treturn 0;\n+}\ndiff --git a/drivers/net/octeontx/base/octeontx_bgx.h b/drivers/net/octeontx/base/octeontx_bgx.h\nindex 6b7476510..d126a0b7f 100644\n--- a/drivers/net/octeontx/base/octeontx_bgx.h\n+++ b/drivers/net/octeontx/base/octeontx_bgx.h\n@@ -11,6 +11,8 @@\n \n #include <octeontx_mbox.h>\n \n+#define OCTEONTX_BGX_RSVD_RX_FIFOBYTES\t0x40\n+\n #define OCTEONTX_BGX_COPROC\t 6\n \n /* BGX messages */\n@@ -32,6 +34,8 @@\n #define MBOX_BGX_PORT_ADD_MACADDR\t15\n #define MBOX_BGX_PORT_DEL_MACADDR\t16\n #define MBOX_BGX_PORT_GET_MACADDR_ENTRIES 17\n+#define MBOX_BGX_PORT_GET_FIFO_CFG\t18\n+#define MBOX_BGX_PORT_FLOW_CTRL_CFG\t19\n #define MBOX_BGX_PORT_SET_LINK_STATE\t20\n \n /* BGX port configuration parameters: */\n@@ -119,6 +123,26 @@ struct octeontx_mbox_bgx_port_mac_filter {\n \tint index;\n };\n \n+/* BGX port fifo config: */\n+typedef struct octeontx_mbox_bgx_port_fifo_cfg {\n+\tuint32_t rx_fifosz; /* in Bytes */\n+} octeontx_mbox_bgx_port_fifo_cfg_t;\n+\n+typedef enum {\n+\tBGX_PORT_FC_CFG_GET = 0,\n+\tBGX_PORT_FC_CFG_SET = 1\n+} bgx_port_fc_t;\n+\n+/* BGX port flow control config: */\n+typedef struct octeontx_mbox_bgx_port_fc_cfg {\n+\t/* BP on/off threshold levels in Bytes, must be a multiple of 16 */\n+\tuint16_t high_water;\n+\tuint16_t low_water;\n+\tuint8_t rx_pause; /* rx_pause = 1/0 to enable/disable fc on Tx */\n+\tuint8_t tx_pause; /* tx_pause = 1/0 to enable/disable fc on Rx */\n+\tbgx_port_fc_t fc_cfg;\n+} octeontx_mbox_bgx_port_fc_cfg_t;\n+\n int octeontx_bgx_port_open(int port, octeontx_mbox_bgx_port_conf_t *conf);\n int octeontx_bgx_port_close(int port);\n int octeontx_bgx_port_start(int port);\n@@ -135,6 +159,10 @@ int octeontx_bgx_port_mac_del(int port, uint32_t index);\n int octeontx_bgx_port_mac_entries_get(int port);\n int octeontx_bgx_port_mtu_set(int port, int mtu);\n int octeontx_bgx_port_set_link_state(int port, bool en);\n+int octeontx_bgx_port_get_fifo_cfg(int port,\n+\t\t\t\t octeontx_mbox_bgx_port_fifo_cfg_t *cfg);\n+int octeontx_bgx_port_flow_ctrl_cfg(int port,\n+\t\t\t\t octeontx_mbox_bgx_port_fc_cfg_t *cfg);\n \n #endif\t/* __OCTEONTX_BGX_H__ */\n \ndiff --git a/drivers/net/octeontx/octeontx_ethdev.c b/drivers/net/octeontx/octeontx_ethdev.c\nindex 08c621b4b..191869683 100644\n--- a/drivers/net/octeontx/octeontx_ethdev.c\n+++ b/drivers/net/octeontx/octeontx_ethdev.c\n@@ -122,6 +122,7 @@ static int\n octeontx_port_open(struct octeontx_nic *nic)\n {\n \tocteontx_mbox_bgx_port_conf_t bgx_port_conf;\n+\tocteontx_mbox_bgx_port_fifo_cfg_t fifo_cfg;\n \tint res;\n \n \tres = 0;\n@@ -147,6 +148,16 @@ octeontx_port_open(struct octeontx_nic *nic)\n \tnic->mcast_mode = bgx_port_conf.mcast_mode;\n \tnic->speed\t= bgx_port_conf.mode;\n \n+\tmemset(&fifo_cfg, 0x0, sizeof(fifo_cfg));\n+\n+\tres = octeontx_bgx_port_get_fifo_cfg(nic->port_id, &fifo_cfg);\n+\tif (res < 0) {\n+\t\tocteontx_log_err(\"failed to get port %d fifo cfg\", res);\n+\t\treturn res;\n+\t}\n+\n+\tnic->fc.rx_fifosz = fifo_cfg.rx_fifosz;\n+\n \tmemcpy(&nic->mac_addr[0], &bgx_port_conf.macaddr[0],\n \t\tRTE_ETHER_ADDR_LEN);\n \n@@ -482,6 +493,8 @@ octeontx_dev_close(struct rte_eth_dev *dev)\n \n \trte_event_dev_close(nic->evdev);\n \n+\tocteontx_dev_flow_ctrl_fini(dev);\n+\n \tocteontx_dev_vlan_offload_fini(dev);\n \n \tret = octeontx_pko_channel_close(nic->base_ochan);\n@@ -1208,6 +1221,7 @@ octeontx_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,\n \tocteontx_recheck_rx_offloads(rxq);\n \tdev->data->rx_queues[qidx] = rxq;\n \tdev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;\n+\n \treturn 0;\n }\n \n@@ -1276,6 +1290,8 @@ static const struct eth_dev_ops octeontx_dev_ops = {\n \t.dev_supported_ptypes_get = octeontx_dev_supported_ptypes_get,\n \t.mtu_set = octeontx_dev_mtu_set,\n \t.pool_ops_supported = octeontx_pool_ops,\n+\t.flow_ctrl_get = octeontx_dev_flow_ctrl_get,\n+\t.flow_ctrl_set = octeontx_dev_flow_ctrl_set,\n };\n \n /* Create Ethdev interface per BGX LMAC ports */\n@@ -1407,6 +1423,10 @@ octeontx_create(struct rte_vdev_device *dev, int port, uint8_t evdev,\n \t/* Update same mac address to BGX CAM table at index 0 */\n \tocteontx_bgx_port_mac_add(nic->port_id, nic->mac_addr, 0);\n \n+\tres = octeontx_dev_flow_ctrl_init(eth_dev);\n+\tif (res < 0)\n+\t\tgoto err;\n+\n \tPMD_INIT_LOG(DEBUG, \"ethdev info: \");\n \tPMD_INIT_LOG(DEBUG, \"port %d, port_ena %d ochan %d num_ochan %d tx_q %d\",\n \t\t\t\tnic->port_id, nic->port_ena,\ndiff --git a/drivers/net/octeontx/octeontx_ethdev.h b/drivers/net/octeontx/octeontx_ethdev.h\nindex 186a044f7..dc53b53be 100644\n--- a/drivers/net/octeontx/octeontx_ethdev.h\n+++ b/drivers/net/octeontx/octeontx_ethdev.h\n@@ -83,6 +83,16 @@ struct octeontx_vlan_info {\n \tuint8_t filter_on;\n };\n \n+struct octeontx_fc_info {\n+\tenum rte_eth_fc_mode mode; /**< Link flow control mode */\n+\tenum rte_eth_fc_mode def_mode;\n+\tuint16_t high_water;\n+\tuint16_t low_water;\n+\tuint16_t def_highmark;\n+\tuint16_t def_lowmark;\n+\tuint32_t rx_fifosz;\n+};\n+\n /* Octeontx ethdev nic */\n struct octeontx_nic {\n \tstruct rte_eth_dev *dev;\n@@ -122,6 +132,7 @@ struct octeontx_nic {\n \tuint16_t tx_offload_flags;\n \tstruct octeontx_vlan_info vlan_info;\n \tint print_flag;\n+\tstruct octeontx_fc_info fc;\n } __rte_cache_aligned;\n \n struct octeontx_txq {\n@@ -154,4 +165,12 @@ int octeontx_dev_vlan_filter_set(struct rte_eth_dev *dev,\n int octeontx_dev_set_link_up(struct rte_eth_dev *eth_dev);\n int octeontx_dev_set_link_down(struct rte_eth_dev *eth_dev);\n \n+/* Flow control */\n+int octeontx_dev_flow_ctrl_init(struct rte_eth_dev *dev);\n+int octeontx_dev_flow_ctrl_fini(struct rte_eth_dev *dev);\n+int octeontx_dev_flow_ctrl_get(struct rte_eth_dev *dev,\n+\t\t\t struct rte_eth_fc_conf *fc_conf);\n+int octeontx_dev_flow_ctrl_set(struct rte_eth_dev *dev,\n+\t\t\t struct rte_eth_fc_conf *fc_conf);\n+\n #endif /* __OCTEONTX_ETHDEV_H__ */\ndiff --git a/drivers/net/octeontx/octeontx_ethdev_ops.c b/drivers/net/octeontx/octeontx_ethdev_ops.c\nindex b5f0bfe8a..ff627a68e 100644\n--- a/drivers/net/octeontx/octeontx_ethdev_ops.c\n+++ b/drivers/net/octeontx/octeontx_ethdev_ops.c\n@@ -213,3 +213,131 @@ octeontx_dev_set_link_down(struct rte_eth_dev *eth_dev)\n \n \treturn octeontx_bgx_port_set_link_state(nic->port_id, false);\n }\n+\n+int\n+octeontx_dev_flow_ctrl_get(struct rte_eth_dev *dev,\n+\t\t\t struct rte_eth_fc_conf *fc_conf)\n+{\n+\tstruct octeontx_nic *nic = octeontx_pmd_priv(dev);\n+\tocteontx_mbox_bgx_port_fc_cfg_t conf;\n+\tint rc;\n+\n+\tmemset(&conf, 0, sizeof(octeontx_mbox_bgx_port_fc_cfg_t));\n+\n+\trc = octeontx_bgx_port_flow_ctrl_cfg(nic->port_id, &conf);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (conf.rx_pause && conf.tx_pause)\n+\t\tfc_conf->mode = RTE_FC_FULL;\n+\telse if (conf.rx_pause)\n+\t\tfc_conf->mode = RTE_FC_RX_PAUSE;\n+\telse if (conf.tx_pause)\n+\t\tfc_conf->mode = RTE_FC_TX_PAUSE;\n+\telse\n+\t\tfc_conf->mode = RTE_FC_NONE;\n+\n+\t/* low_water & high_water values are in Bytes */\n+\tfc_conf->low_water = conf.low_water;\n+\tfc_conf->high_water = conf.high_water;\n+\n+\treturn rc;\n+}\n+\n+int\n+octeontx_dev_flow_ctrl_set(struct rte_eth_dev *dev,\n+\t\t\t struct rte_eth_fc_conf *fc_conf)\n+{\n+\tstruct octeontx_nic *nic = octeontx_pmd_priv(dev);\n+\tstruct octeontx_fc_info *fc = &nic->fc;\n+\tocteontx_mbox_bgx_port_fc_cfg_t conf;\n+\tuint8_t tx_pause, rx_pause;\n+\tuint16_t max_high_water;\n+\tint rc;\n+\n+\tif (fc_conf->pause_time || fc_conf->mac_ctrl_frame_fwd ||\n+\t fc_conf->autoneg) {\n+\t\tocteontx_log_err(\"Below flowctrl parameters are not supported \"\n+\t\t\t\t \"pause_time, mac_ctrl_frame_fwd and autoneg\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (fc_conf->high_water == fc->high_water &&\n+\t fc_conf->low_water == fc->low_water &&\n+\t fc_conf->mode == fc->mode)\n+\t\treturn 0;\n+\n+\tmax_high_water = fc->rx_fifosz - OCTEONTX_BGX_RSVD_RX_FIFOBYTES;\n+\n+\tif (fc_conf->high_water > max_high_water ||\n+\t fc_conf->high_water < fc_conf->low_water) {\n+\t\tocteontx_log_err(\"Invalid high/low water values \"\n+\t\t\t\t \"High_water(in Bytes) must <= 0x%x \",\n+\t\t\t\t max_high_water);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (fc_conf->high_water % BIT(4) || fc_conf->low_water % BIT(4)) {\n+\t\tocteontx_log_err(\"High/low water value must be multiple of 16\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\trx_pause = (fc_conf->mode == RTE_FC_FULL) ||\n+\t\t\t(fc_conf->mode == RTE_FC_RX_PAUSE);\n+\ttx_pause = (fc_conf->mode == RTE_FC_FULL) ||\n+\t\t\t(fc_conf->mode == RTE_FC_TX_PAUSE);\n+\n+\tconf.high_water = fc_conf->high_water;\n+\tconf.low_water = fc_conf->low_water;\n+\tconf.fc_cfg = BGX_PORT_FC_CFG_SET;\n+\tconf.rx_pause = rx_pause;\n+\tconf.tx_pause = tx_pause;\n+\n+\trc = octeontx_bgx_port_flow_ctrl_cfg(nic->port_id, &conf);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tfc->high_water = fc_conf->high_water;\n+\tfc->low_water = fc_conf->low_water;\n+\tfc->mode = fc_conf->mode;\n+\n+\treturn rc;\n+}\n+\n+int\n+octeontx_dev_flow_ctrl_init(struct rte_eth_dev *dev)\n+{\n+\tstruct octeontx_nic *nic = octeontx_pmd_priv(dev);\n+\tstruct octeontx_fc_info *fc = &nic->fc;\n+\tstruct rte_eth_fc_conf fc_conf;\n+\tint rc;\n+\n+\trc = octeontx_dev_flow_ctrl_get(dev, &fc_conf);\n+\tif (rc) {\n+\t\tocteontx_log_err(\"Failed to get flow control info\");\n+\t\treturn rc;\n+\t}\n+\n+\tfc->def_highmark = fc_conf.high_water;\n+\tfc->def_lowmark = fc_conf.low_water;\n+\tfc->def_mode = fc_conf.mode;\n+\n+\treturn rc;\n+}\n+\n+int\n+octeontx_dev_flow_ctrl_fini(struct rte_eth_dev *dev)\n+{\n+\tstruct octeontx_nic *nic = octeontx_pmd_priv(dev);\n+\tstruct octeontx_fc_info *fc = &nic->fc;\n+\tstruct rte_eth_fc_conf fc_conf;\n+\n+\tmemset(&fc_conf, 0, sizeof(struct rte_eth_fc_conf));\n+\n+\t/* Restore flow control parameters with default values */\n+\tfc_conf.high_water = fc->def_highmark;\n+\tfc_conf.low_water = fc->def_lowmark;\n+\tfc_conf.mode = fc->def_mode;\n+\n+\treturn octeontx_dev_flow_ctrl_set(dev, &fc_conf);\n+}\n", "prefixes": [ "7/8" ] }