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GET /api/patches/66697/?format=api
{ "id": 66697, "url": "http://patches.dpdk.org/api/patches/66697/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1584351224-23500-9-git-send-email-hkalra@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1584351224-23500-9-git-send-email-hkalra@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1584351224-23500-9-git-send-email-hkalra@marvell.com", "date": "2020-03-16T09:33:44", "name": "[8/8] net/octeontx: support Rx Tx checksum offload", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "2a425224ce6461c5f19bb55e230f6280cfca56f8", "submitter": { "id": 1182, "url": "http://patches.dpdk.org/api/people/1182/?format=api", "name": "Harman Kalra", "email": "hkalra@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1584351224-23500-9-git-send-email-hkalra@marvell.com/mbox/", "series": [ { "id": 8923, "url": "http://patches.dpdk.org/api/series/8923/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8923", "date": "2020-03-16T09:33:36", "name": "add new features to octeontx PMD", "version": 1, "mbox": "http://patches.dpdk.org/series/8923/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/66697/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/66697/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 084A2A0559;\n\tMon, 16 Mar 2020 10:35:43 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 66BE71C0C2;\n\tMon, 16 Mar 2020 10:35:00 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 88AAC1C0B2\n for <dev@dpdk.org>; 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mx.microsoft.com 1; spf=pass\n smtp.mailfrom=marvell.com; dmarc=pass action=none header.from=marvell.com;\n dkim=pass header.d=marvell.com; arc=none", "From": "Harman Kalra <hkalra@marvell.com>", "To": "<jerinj@marvell.com>, <john.mcnamara@intel.com>,\n <marko.kovacevic@intel.com>", "CC": "<dev@dpdk.org>, <vattunuru@marvell.com>, Harman Kalra <hkalra@marvell.com>", "Date": "Mon, 16 Mar 2020 15:03:44 +0530", "Message-ID": "<1584351224-23500-9-git-send-email-hkalra@marvell.com>", "X-Mailer": [ "git-send-email 2.7.4", "git-send-email 2.7.4" ], "In-Reply-To": "<1584351224-23500-1-git-send-email-hkalra@marvell.com>", "References": "<1584351224-23500-1-git-send-email-hkalra@marvell.com>", "Content-Type": "text/plain", "X-ClientProxiedBy": "BMXPR01CA0006.INDPRD01.PROD.OUTLOOK.COM\n (2603:1096:b00:d::16) To MN2PR18MB2848.namprd18.prod.outlook.com\n (2603:10b6:208:38::19)", "MIME-Version": "1.0", "X-MS-Exchange-MessageSentRepresentingType": "1", "X-Originating-IP": "[115.113.156.2]", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "0f198454-e98a-404c-6c23-08d7c98d443e", "X-MS-TrafficTypeDiagnostic": "BYASPR01MB9:", "X-MS-Exchange-Transport-Forked": "True", "X-Microsoft-Antispam-PRVS": "\n <BYASPR01MB98F3CA6E61B26C80C99AFC5F90@BYASPR01MB9.namprd18.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:341;", "X-Forefront-PRVS": "03449D5DD1", "X-Forefront-Antispam-Report": "SFV:NSPM;\n SFS:(10009020)(4636009)(366004)(396003)(346002)(39860400002)(376002)(136003)(199004)(6486002)(4326008)(36756003)(2906002)(107886003)(30864003)(478600001)(186003)(16526019)(5660300002)(86362001)(2616005)(956004)(26005)(66946007)(81166006)(81156014)(8936002)(8676002)(66556008)(66476007)(55236004)(52116002)(316002)(7696005);\n DIR:OUT; SFP:1101; SCL:1; SRVR:BYASPR01MB9;\n H:MN2PR18MB2848.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en;\n PTR:InfoNoRecords; A:1;", "Received-SPF": "None (protection.outlook.com: marvell.com does not designate\n permitted sender hosts)", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n cd5jChQ7Jusnv94C3HZJSmzCFRqv9HRsIEcgcg1j1mfFsX3lSInyPOhlexxAzFEuV4mz91NYNItEgFUZLAKtLpT6ECNgssF4q4PYPx9WcPLuavZcehdGL3nu9TeZkV5Wxozl5oV1USHKq2DVTwrQRFiCp8aCk7I3QkBckT7izJXeKMkbgcbxOqsQa1PkCBsAdtXpS53GxSIL93jtQHgT+JksmrpT4XbMC4Ex3KeJsaaPITWbd9zBDov2jRYgBuAWozakE/y1/pNyITdr9yDx2hWQ1RCEmIxM6zH/Wt/8sbrOdqolQLIO4N++yIQ6UTTa95rzRkCc2l9uGBRfhjGwco+VDTdFKW3UePfoGdySfA3A6qBdSdxlrAud345cbCxv2aMw4JDHbhCJAbf+fqNVuK4QZyO5ibwohINBo2PIrwYVw8hIBb8hK56tL2piM/NR", "X-MS-Exchange-AntiSpam-MessageData": "\n a8moa4gj8T3kn6mvOVZQFw8uhS88Fed+/3gGyYegEdYpeZDCT/HQLuMJTMcLW3C+Og2/a29Y3VLh19QFo0OiTIE0Y6UMzaIgdg3Q3NY8LVcPn5C6+HwCI2wvYy0miNTlnRbOIomBbl3Ep6j6xwWNYQ==", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0f198454-e98a-404c-6c23-08d7c98d443e", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Mar 2020 09:34:47.0207 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "70e1fb47-1155-421d-87fc-2e58f638b6e0", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n KunwmFy3Ff61oAsVO6aMQUW31+sP/yuLTJEd98U/9LjhXrQKLZJwJcpK7c39y+P7Dk8mvevJeB48tYhIIX7t5Q==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYASPR01MB9", "X-OriginatorOrg": "marvell.com", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572\n definitions=2020-03-16_02:2020-03-12,\n 2020-03-16 signatures=0", "Subject": "[dpdk-dev] [PATCH 8/8] net/octeontx: support Rx Tx checksum offload", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch implements rx/tx checksum offload. In case of\nwrong checksum received (inner/outer l3/l4) it reports the\ncorresponding layer which has bad checksum and also corrects\nit if hw checksum is enabled on tx side.\n\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\n---\n doc/guides/nics/features/octeontx.ini | 4 +\n drivers/net/octeontx/octeontx_ethdev.c | 22 ++-\n drivers/net/octeontx/octeontx_ethdev.h | 21 ++-\n drivers/net/octeontx/octeontx_rxtx.c | 10 +-\n drivers/net/octeontx/octeontx_rxtx.h | 194 +++++++++++++++++++++++--\n 5 files changed, 227 insertions(+), 24 deletions(-)", "diff": "diff --git a/doc/guides/nics/features/octeontx.ini b/doc/guides/nics/features/octeontx.ini\nindex 6049c1c43..8a95c216c 100644\n--- a/doc/guides/nics/features/octeontx.ini\n+++ b/doc/guides/nics/features/octeontx.ini\n@@ -17,6 +17,10 @@ Unicast MAC filter = Y\n VLAN filter = Y\n VLAN offload = P\n CRC offload = Y\n+L3 checksum offload = Y\n+L4 checksum offload = Y\n+Inner L3 checksum = Y\n+Inner L4 checksum = Y\n Packet type parsing = Y\n Flow control = Y\n Basic stats = Y\ndiff --git a/drivers/net/octeontx/octeontx_ethdev.c b/drivers/net/octeontx/octeontx_ethdev.c\nindex 191869683..ea3b278a1 100644\n--- a/drivers/net/octeontx/octeontx_ethdev.c\n+++ b/drivers/net/octeontx/octeontx_ethdev.c\n@@ -370,6 +370,16 @@ octeontx_tx_offload_flags(struct rte_eth_dev *eth_dev)\n \tstruct octeontx_nic *nic = octeontx_pmd_priv(eth_dev);\n \tuint16_t flags = 0;\n \n+\tif (nic->tx_offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||\n+\t nic->tx_offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)\n+\t\tflags |= OCCTX_TX_OFFLOAD_OL3_OL4_CSUM_F;\n+\n+\tif (nic->tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||\n+\t nic->tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM ||\n+\t nic->tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||\n+\t nic->tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM)\n+\t\tflags |= OCCTX_TX_OFFLOAD_L3_L4_CSUM_F;\n+\n \tif (!(nic->tx_offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE))\n \t\tflags |= OCCTX_TX_OFFLOAD_MBUF_NOFF_F;\n \n@@ -383,13 +393,15 @@ static uint16_t\n octeontx_rx_offload_flags(struct rte_eth_dev *eth_dev)\n {\n \tstruct octeontx_nic *nic = octeontx_pmd_priv(eth_dev);\n-\tstruct rte_eth_dev_data *data = eth_dev->data;\n-\tstruct rte_eth_conf *conf = &data->dev_conf;\n-\tstruct rte_eth_rxmode *rxmode = &conf->rxmode;\n \tuint16_t flags = 0;\n \n-\tif (rxmode->mq_mode == ETH_MQ_RX_RSS)\n-\t\tflags |= OCCTX_RX_OFFLOAD_RSS_F;\n+\tif (nic->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |\n+\t\t\t DEV_RX_OFFLOAD_UDP_CKSUM))\n+\t\tflags |= OCCTX_RX_OFFLOAD_CSUM_F;\n+\n+\tif (nic->rx_offloads & (DEV_RX_OFFLOAD_IPV4_CKSUM |\n+\t\t\t\tDEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))\n+\t\tflags |= OCCTX_RX_OFFLOAD_CSUM_F;\n \n \tif (nic->rx_offloads & DEV_RX_OFFLOAD_SCATTER) {\n \t\tflags |= OCCTX_RX_MULTI_SEG_F;\ndiff --git a/drivers/net/octeontx/octeontx_ethdev.h b/drivers/net/octeontx/octeontx_ethdev.h\nindex dc53b53be..7246fb6d1 100644\n--- a/drivers/net/octeontx/octeontx_ethdev.h\n+++ b/drivers/net/octeontx/octeontx_ethdev.h\n@@ -53,13 +53,24 @@\n \n #define OCCTX_MAX_MTU\t\t(OCCTX_MAX_FRS - OCCTX_L2_OVERHEAD)\n \n-#define OCTEONTX_RX_OFFLOADS\t\t(DEV_RX_OFFLOAD_CHECKSUM | \\\n-\t\t\t\t\t DEV_RX_OFFLOAD_SCATTER\t | \\\n-\t\t\t\t\t DEV_RX_OFFLOAD_JUMBO_FRAME | \\\n+#define OCTEONTX_RX_OFFLOADS\t\t(\t\t\t\t \\\n+\t\t\t\t\t DEV_RX_OFFLOAD_CHECKSUM\t | \\\n+\t\t\t\t\t DEV_RX_OFFLOAD_SCTP_CKSUM | \\\n+\t\t\t\t\t DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \\\n+\t\t\t\t\t DEV_RX_OFFLOAD_SCATTER\t | \\\n+\t\t\t\t\t DEV_RX_OFFLOAD_SCATTER\t\t | \\\n+\t\t\t\t\t DEV_RX_OFFLOAD_JUMBO_FRAME\t | \\\n \t\t\t\t\t DEV_RX_OFFLOAD_VLAN_FILTER)\n \n-#define OCTEONTX_TX_OFFLOADS\t\t(DEV_TX_OFFLOAD_MT_LOCKFREE | \\\n-\t\t\t\t\t DEV_TX_OFFLOAD_MBUF_FAST_FREE | \\\n+#define OCTEONTX_TX_OFFLOADS\t\t(\t\t\t\t \\\n+\t\t\t\t\t DEV_TX_OFFLOAD_MBUF_FAST_FREE\t | \\\n+\t\t\t\t\t DEV_TX_OFFLOAD_MT_LOCKFREE\t | \\\n+\t\t\t\t\t DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \\\n+\t\t\t\t\t DEV_TX_OFFLOAD_OUTER_UDP_CKSUM\t | \\\n+\t\t\t\t\t DEV_TX_OFFLOAD_IPV4_CKSUM\t | \\\n+\t\t\t\t\t DEV_TX_OFFLOAD_TCP_CKSUM\t | \\\n+\t\t\t\t\t DEV_TX_OFFLOAD_UDP_CKSUM\t | \\\n+\t\t\t\t\t DEV_TX_OFFLOAD_SCTP_CKSUM\t | \\\n \t\t\t\t\t DEV_TX_OFFLOAD_MULTI_SEGS)\n \n static inline struct octeontx_nic *\ndiff --git a/drivers/net/octeontx/octeontx_rxtx.c b/drivers/net/octeontx/octeontx_rxtx.c\nindex c817f7179..d2453ba26 100644\n--- a/drivers/net/octeontx/octeontx_rxtx.c\n+++ b/drivers/net/octeontx/octeontx_rxtx.c\n@@ -41,7 +41,7 @@ octeontx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \treturn count; /* return number of pkts received */\n }\n \n-#define T(name, f1, f0, sz, flags)\t\t\t\t\t\\\n+#define T(name, f3, f2, f1, f0, sz, flags)\t\t\t\t\\\n static uint16_t __rte_noinline\t__hot\t\t\t\t\t\\\n octeontx_xmit_pkts_ ##name(void *tx_queue,\t\t\t\t\\\n \t\t\tstruct rte_mbuf **tx_pkts, uint16_t pkts)\t\\\n@@ -60,9 +60,9 @@ octeontx_set_tx_function(struct rte_eth_dev *dev)\n {\n \tstruct octeontx_nic *nic = octeontx_pmd_priv(dev);\n \n-\tconst eth_tx_burst_t tx_burst_func[2][2] = {\n-#define T(name, f1, f0, sz, flags)\t\t\t\\\n-\t[f1][f0] = octeontx_xmit_pkts_ ##name,\n+\tconst eth_tx_burst_t tx_burst_func[2][2][2][2] = {\n+#define T(name, f3, f2, f1, f0, sz, flags)\t\t\t\\\n+\t[f3][f2][f1][f0] = octeontx_xmit_pkts_ ##name,\n \n OCCTX_TX_FASTPATH_MODES\n #undef T\n@@ -70,5 +70,7 @@ OCCTX_TX_FASTPATH_MODES\n \n \tdev->tx_pkt_burst = tx_burst_func\n \t\t[!!(nic->tx_offload_flags & OCCTX_TX_OFFLOAD_MBUF_NOFF_F)]\n+\t\t[!!(nic->tx_offload_flags & OCCTX_TX_OFFLOAD_OL3_OL4_CSUM_F)]\n+\t\t[!!(nic->tx_offload_flags & OCCTX_TX_OFFLOAD_L3_L4_CSUM_F)]\n \t\t[!!(nic->tx_offload_flags & OCCTX_TX_MULTI_SEG_F)];\n }\ndiff --git a/drivers/net/octeontx/octeontx_rxtx.h b/drivers/net/octeontx/octeontx_rxtx.h\nindex cc044dd79..acc1f5cb8 100644\n--- a/drivers/net/octeontx/octeontx_rxtx.h\n+++ b/drivers/net/octeontx/octeontx_rxtx.h\n@@ -18,17 +18,65 @@\n #define BIT(nr) (1UL << (nr))\n \n #define OCCTX_RX_OFFLOAD_NONE\t\t(0)\n-#define OCCTX_RX_OFFLOAD_RSS_F BIT(0)\n-#define OCCTX_RX_VLAN_FLTR_F BIT(1)\n-#define OCCTX_RX_MULTI_SEG_F\t\tBIT(15)\n+#define OCCTX_RX_MULTI_SEG_F\t\tBIT(0)\n+#define OCCTX_RX_OFFLOAD_CSUM_F BIT(1)\n+#define OCCTX_RX_VLAN_FLTR_F BIT(2)\n \n #define OCCTX_TX_OFFLOAD_NONE\t\t(0)\n+#define OCCTX_TX_MULTI_SEG_F\t\tBIT(0)\n+#define OCCTX_TX_OFFLOAD_L3_L4_CSUM_F\tBIT(1)\n+#define OCCTX_TX_OFFLOAD_OL3_OL4_CSUM_F\tBIT(2)\n #define OCCTX_TX_OFFLOAD_MBUF_NOFF_F\tBIT(3)\n \n-#define OCCTX_TX_MULTI_SEG_F\t\tBIT(15)\n /* Packet type table */\n #define PTYPE_SIZE\tOCCTX_PKI_LTYPE_LAST\n \n+/* octeontx send header sub descriptor structure */\n+RTE_STD_C11\n+union octeontx_send_hdr_w0_u {\n+\tuint64_t u;\n+\tstruct {\n+\t\tuint64_t total : 16;\n+\t\tuint64_t markptr : 8;\n+\t\tuint64_t l3ptr : 8;\n+\t\tuint64_t l4ptr : 8;\n+\t\tuint64_t ii\t : 1;\n+\t\tuint64_t shp_dis : 1;\n+\t\tuint64_t ckle : 1;\n+\t\tuint64_t cklf : 2;\n+\t\tuint64_t ckl3 : 1;\n+\t\tuint64_t ckl4 : 2;\n+\t\tuint64_t p\t : 1;\n+\t\tuint64_t format\t : 7;\n+\t\tuint64_t tstamp : 1;\n+\t\tuint64_t tso_eom : 1;\n+\t\tuint64_t df\t : 1;\n+\t\tuint64_t tso\t : 1;\n+\t\tuint64_t n2\t : 1;\n+\t\tuint64_t scntn1\t : 3;\n+\t};\n+};\n+\n+RTE_STD_C11\n+union octeontx_send_hdr_w1_u {\n+\tuint64_t u;\n+\tstruct {\n+\t\tuint64_t tso_mss : 14;\n+\t\tuint64_t shp_ra : 2;\n+\t\tuint64_t tso_sb : 8;\n+\t\tuint64_t leptr : 8;\n+\t\tuint64_t lfptr : 8;\n+\t\tuint64_t shp_chg : 9;\n+\t\tuint64_t tso_fn : 7;\n+\t\tuint64_t l2len : 8;\n+\t};\n+};\n+\n+struct octeontx_send_hdr_s {\n+\tunion octeontx_send_hdr_w0_u w0;\n+\tunion octeontx_send_hdr_w1_u w1;\n+};\n+\n static const uint32_t __rte_cache_aligned\n ptype_table[PTYPE_SIZE][PTYPE_SIZE][PTYPE_SIZE] = {\n \t[LC_NONE][LE_NONE][LF_NONE] = RTE_PTYPE_UNKNOWN,\n@@ -182,6 +230,90 @@ octeontx_prefree_seg(struct rte_mbuf *m)\n \treturn 1;\n }\n \n+static __rte_always_inline void\n+octeontx_tx_checksum_offload(uint64_t *cmd_buf, const uint16_t flags,\n+\t\t\t struct rte_mbuf *m)\n+{\n+\tstruct octeontx_send_hdr_s *send_hdr =\n+\t\t\t\t(struct octeontx_send_hdr_s *)cmd_buf;\n+\tuint64_t ol_flags = m->ol_flags;\n+\n+\t/* PKO Checksum L4 Algorithm Enumeration\n+\t * 0x0 - No checksum\n+\t * 0x1 - UDP L4 checksum\n+\t * 0x2 - TCP L4 checksum\n+\t * 0x3 - SCTP L4 checksum\n+\t */\n+\tconst uint8_t csum = (!(((ol_flags ^ PKT_TX_UDP_CKSUM) >> 52) & 0x3) +\n+\t\t (!(((ol_flags ^ PKT_TX_TCP_CKSUM) >> 52) & 0x3) * 2) +\n+\t\t (!(((ol_flags ^ PKT_TX_SCTP_CKSUM) >> 52) & 0x3) * 3));\n+\n+\tconst uint8_t is_tunnel_parsed = (!!(ol_flags & PKT_TX_TUNNEL_GTP) ||\n+\t\t\t\t !!(ol_flags & PKT_TX_TUNNEL_VXLAN_GPE) ||\n+\t\t\t\t !!(ol_flags & PKT_TX_TUNNEL_VXLAN) ||\n+\t\t\t\t !!(ol_flags & PKT_TX_TUNNEL_GRE) ||\n+\t\t\t\t !!(ol_flags & PKT_TX_TUNNEL_GENEVE) ||\n+\t\t\t\t !!(ol_flags & PKT_TX_TUNNEL_IP) ||\n+\t\t\t\t !!(ol_flags & PKT_TX_TUNNEL_IPIP));\n+\n+\tconst uint8_t csum_outer = (!!(ol_flags & PKT_TX_OUTER_UDP_CKSUM) ||\n+\t\t\t\t !!(ol_flags & PKT_TX_TUNNEL_UDP));\n+\tconst uint8_t outer_l2_len = m->outer_l2_len;\n+\tconst uint8_t l2_len = m->l2_len;\n+\n+\tif ((flags & OCCTX_TX_OFFLOAD_OL3_OL4_CSUM_F) &&\n+\t (flags & OCCTX_TX_OFFLOAD_L3_L4_CSUM_F)) {\n+\t\tif (is_tunnel_parsed) {\n+\t\t\t/* Outer L3 */\n+\t\t\tsend_hdr->w0.l3ptr = outer_l2_len;\n+\t\t\tsend_hdr->w0.l4ptr = outer_l2_len + m->outer_l3_len;\n+\t\t\t/* Set clk3 for PKO to calculate IPV4 header checksum */\n+\t\t\tsend_hdr->w0.ckl3 = !!(ol_flags & PKT_TX_OUTER_IPV4);\n+\n+\t\t\t/* Outer L4 */\n+\t\t\tsend_hdr->w0.ckl4 = csum_outer;\n+\n+\t\t\t/* Inner L3 */\n+\t\t\tsend_hdr->w1.leptr = send_hdr->w0.l4ptr + l2_len;\n+\t\t\tsend_hdr->w1.lfptr = send_hdr->w1.leptr + m->l3_len;\n+\t\t\t/* Set clke for PKO to calculate inner IPV4 header\n+\t\t\t * checksum.\n+\t\t\t */\n+\t\t\tsend_hdr->w0.ckle = !!(ol_flags & PKT_TX_IPV4);\n+\n+\t\t\t/* Inner L4 */\n+\t\t\tsend_hdr->w0.cklf = csum;\n+\t\t} else {\n+\t\t\t/* Inner L3 */\n+\t\t\tsend_hdr->w0.l3ptr = l2_len;\n+\t\t\tsend_hdr->w0.l4ptr = l2_len + m->l3_len;\n+\t\t\t/* Set clk3 for PKO to calculate IPV4 header checksum */\n+\t\t\tsend_hdr->w0.ckl3 = !!(ol_flags & PKT_TX_IPV4);\n+\n+\t\t\t/* Inner L4 */\n+\t\t\tsend_hdr->w0.ckl4 = csum;\n+\t\t}\n+\t} else if (flags & OCCTX_TX_OFFLOAD_OL3_OL4_CSUM_F) {\n+\t\t/* Outer L3 */\n+\t\tsend_hdr->w0.l3ptr = outer_l2_len;\n+\t\tsend_hdr->w0.l4ptr = outer_l2_len + m->outer_l3_len;\n+\t\t/* Set clk3 for PKO to calculate IPV4 header checksum */\n+\t\tsend_hdr->w0.ckl3 = !!(ol_flags & PKT_TX_OUTER_IPV4);\n+\n+\t\t/* Outer L4 */\n+\t\tsend_hdr->w0.ckl4 = csum_outer;\n+\t} else if (flags & OCCTX_TX_OFFLOAD_L3_L4_CSUM_F) {\n+\t\t/* Inner L3 */\n+\t\tsend_hdr->w0.l3ptr = l2_len;\n+\t\tsend_hdr->w0.l4ptr = l2_len + m->l3_len;\n+\t\t/* Set clk3 for PKO to calculate IPV4 header checksum */\n+\t\tsend_hdr->w0.ckl3 = !!(ol_flags & PKT_TX_IPV4);\n+\n+\t\t/* Inner L4 */\n+\t\tsend_hdr->w0.ckl4 = csum;\n+\t}\n+}\n+\n static __rte_always_inline uint16_t\n __octeontx_xmit_prepare(struct rte_mbuf *tx_pkt, uint64_t *cmd_buf,\n \t\t\tconst uint16_t flag)\n@@ -192,6 +324,11 @@ __octeontx_xmit_prepare(struct rte_mbuf *tx_pkt, uint64_t *cmd_buf,\n \tcmd_buf[nb_desc++] = tx_pkt->data_len & 0xffff;\n \tcmd_buf[nb_desc++] = 0x0;\n \n+\t/* Enable tx checksum offload */\n+\tif ((flag & OCCTX_TX_OFFLOAD_OL3_OL4_CSUM_F) ||\n+\t (flag & OCCTX_TX_OFFLOAD_L3_L4_CSUM_F))\n+\t\tocteontx_tx_checksum_offload(cmd_buf, flag, tx_pkt);\n+\n \t/* SEND_HDR[DF] bit controls if buffer is to be freed or\n \t * not, as SG_DESC[I] and SEND_HDR[II] are clear.\n \t */\n@@ -230,6 +367,11 @@ __octeontx_xmit_mseg_prepare(struct rte_mbuf *tx_pkt, uint64_t *cmd_buf,\n \tcmd_buf[nb_desc++] = tx_pkt->pkt_len & 0xffff;\n \tcmd_buf[nb_desc++] = 0x0;\n \n+\t/* Enable tx checksum offload */\n+\tif ((flag & OCCTX_TX_OFFLOAD_OL3_OL4_CSUM_F) ||\n+\t (flag & OCCTX_TX_OFFLOAD_L3_L4_CSUM_F))\n+\t\tocteontx_tx_checksum_offload(cmd_buf, flag, tx_pkt);\n+\n \tdo {\n \t\tm_next = tx_pkt->next;\n \t\t/* To handle case where mbufs belong to diff pools, like\n@@ -305,13 +447,45 @@ __octeontx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n uint16_t\n octeontx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts);\n \n+#define L3L4CSUM_F OCCTX_TX_OFFLOAD_L3_L4_CSUM_F\n+#define OL3OL4CSUM_F OCCTX_TX_OFFLOAD_OL3_OL4_CSUM_F\n #define NOFF_F OCCTX_TX_OFFLOAD_MBUF_NOFF_F\n #define MULT_F OCCTX_TX_MULTI_SEG_F\n-/* [NOFF] [MULTI_SEG] */\n-#define OCCTX_TX_FASTPATH_MODES\t\t\t\t\t\t \\\n-T(no_offload,\t\t\t\t0, 0,\t4, OCCTX_TX_OFFLOAD_NONE) \\\n-T(mseg,\t\t\t\t\t0, 1,\t14, MULT_F)\t\t \\\n-T(noff,\t\t\t\t\t1, 0,\t4, NOFF_F)\t\t \\\n-T(noff_mseg,\t\t\t\t1, 1,\t14, NOFF_F | MULT_F)\n+\n+/* [L3L4CSUM_F] [OL3OL4CSUM_F] [NOFF] [MULTI_SEG] */\n+#define OCCTX_TX_FASTPATH_MODES\t\t\t\t\t\t \\\n+T(no_offload,\t\t\t\t0, 0, 0, 0,\t4,\t\t \\\n+\t\t\t\t\tOCCTX_TX_OFFLOAD_NONE)\t\t \\\n+T(mseg,\t\t\t\t\t0, 0, 0, 1,\t14,\t\t \\\n+\t\t\t\t\tMULT_F)\t\t\t \\\n+T(l3l4csum,\t\t\t\t0, 0, 1, 0, 4,\t\t \\\n+\t\t\t\t\tL3L4CSUM_F)\t\t\t \\\n+T(l3l4csum_mseg,\t\t\t0, 0, 1, 1,\t14,\t\t \\\n+\t\t\t\t\tL3L4CSUM_F | MULT_F)\t\t \\\n+T(ol3ol4csum,\t\t\t\t0, 1, 0, 0,\t4,\t\t \\\n+\t\t\t\t\tOL3OL4CSUM_F)\t\t\t \\\n+T(ol3l4csum_mseg,\t\t\t0, 1, 0, 1,\t14,\t\t \\\n+\t\t\t\t\tOL3OL4CSUM_F | MULT_F)\t \\\n+T(ol3l4csum_l3l4csum,\t\t\t0, 1, 1, 0, 4,\t\t \\\n+\t\t\t\t\tOL3OL4CSUM_F | L3L4CSUM_F)\t \\\n+T(ol3l4csum_l3l4csum_mseg,\t\t0, 1, 1, 1,\t14,\t\t \\\n+\t\t\t\t\tOL3OL4CSUM_F | L3L4CSUM_F | MULT_F) \\\n+T(noff,\t\t\t\t\t1, 0, 0, 0, 4,\t\t \\\n+\t\t\t\t\tNOFF_F)\t\t\t\t \\\n+T(noff_mseg,\t\t\t\t1, 0, 0, 1,\t14,\t\t \\\n+\t\t\t\t\tNOFF_F | MULT_F)\t \\\n+T(noff_l3l4csum,\t\t\t1, 0, 1, 0, 4,\t\t \\\n+\t\t\t\t\tNOFF_F | L3L4CSUM_F)\t\t \\\n+T(noff_l3l4csum_mseg,\t\t\t1, 0, 1, 1,\t14,\t\t \\\n+\t\t\t\t\tNOFF_F | L3L4CSUM_F | MULT_F)\t \\\n+T(noff_ol3ol4csum,\t\t\t1, 1, 0, 0,\t4,\t\t \\\n+\t\t\t\t\tNOFF_F | OL3OL4CSUM_F)\t\t \\\n+T(noff_ol3ol4csum_mseg,\t\t\t1, 1, 0, 1,\t14,\t\t \\\n+\t\t\t\t\tNOFF_F | OL3OL4CSUM_F | MULT_F)\t \\\n+T(noff_ol3ol4csum_l3l4csum,\t\t1, 1, 1, 0, 4,\t\t \\\n+\t\t\t\t\tNOFF_F | OL3OL4CSUM_F | L3L4CSUM_F) \\\n+T(noff_ol3ol4csum_l3l4csum_mseg,\t1, 1, 1, 1,\t14,\t\t \\\n+\t\t\t\t\tNOFF_F | OL3OL4CSUM_F | L3L4CSUM_F | \\\n+\t\t\t\t\tMULT_F)\n \n #endif /* __OCTEONTX_RXTX_H__ */\n", "prefixes": [ "8/8" ] }