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GET /api/patches/66692/?format=api
{ "id": 66692, "url": "http://patches.dpdk.org/api/patches/66692/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1584351224-23500-2-git-send-email-hkalra@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1584351224-23500-2-git-send-email-hkalra@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1584351224-23500-2-git-send-email-hkalra@marvell.com", "date": "2020-03-16T09:33:37", "name": "[1/8] net/octeontx: add multi segment support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "fe0e847899a09f4d3bb48212b055306c2b078cfc", "submitter": { "id": 1182, "url": "http://patches.dpdk.org/api/people/1182/?format=api", "name": "Harman Kalra", "email": "hkalra@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1584351224-23500-2-git-send-email-hkalra@marvell.com/mbox/", "series": [ { "id": 8923, "url": "http://patches.dpdk.org/api/series/8923/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8923", "date": "2020-03-16T09:33:36", "name": "add new features to octeontx PMD", "version": 1, "mbox": "http://patches.dpdk.org/series/8923/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/66692/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/66692/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1B20BA0559;\n\tMon, 16 Mar 2020 10:34:33 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 107E91C07B;\n\tMon, 16 Mar 2020 10:34:29 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 8B5F91C067\n for <dev@dpdk.org>; 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mx.microsoft.com 1; spf=pass\n smtp.mailfrom=marvell.com; dmarc=pass action=none header.from=marvell.com;\n dkim=pass header.d=marvell.com; arc=none", "From": "Harman Kalra <hkalra@marvell.com>", "To": "<jerinj@marvell.com>, <john.mcnamara@intel.com>,\n <marko.kovacevic@intel.com>", "CC": "<dev@dpdk.org>, <vattunuru@marvell.com>, Harman Kalra <hkalra@marvell.com>", "Date": "Mon, 16 Mar 2020 15:03:37 +0530", "Message-ID": "<1584351224-23500-2-git-send-email-hkalra@marvell.com>", "X-Mailer": [ "git-send-email 2.7.4", "git-send-email 2.7.4" ], "In-Reply-To": "<1584351224-23500-1-git-send-email-hkalra@marvell.com>", "References": "<1584351224-23500-1-git-send-email-hkalra@marvell.com>", "Content-Type": "text/plain", "X-ClientProxiedBy": "BMXPR01CA0006.INDPRD01.PROD.OUTLOOK.COM\n (2603:1096:b00:d::16) To MN2PR18MB2848.namprd18.prod.outlook.com\n (2603:10b6:208:38::19)", "MIME-Version": "1.0", "X-MS-Exchange-MessageSentRepresentingType": "1", "X-Originating-IP": "[115.113.156.2]", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "8445be8e-a56c-45ff-c8f0-08d7c98d355e", "X-MS-TrafficTypeDiagnostic": "MN2PR18MB3117:", "X-MS-Exchange-Transport-Forked": "True", "X-Microsoft-Antispam-PRVS": "\n <MN2PR18MB311793DC2B4A5CE9382F2095C5F90@MN2PR18MB3117.namprd18.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:142;", "X-Forefront-PRVS": "03449D5DD1", "X-Forefront-Antispam-Report": "SFV:NSPM;\n SFS:(10009020)(4636009)(366004)(136003)(376002)(39860400002)(346002)(396003)(199004)(52116002)(7696005)(478600001)(4326008)(8676002)(8936002)(107886003)(26005)(66556008)(30864003)(2906002)(86362001)(5660300002)(36756003)(55236004)(16526019)(2616005)(956004)(66946007)(6486002)(66476007)(81156014)(81166006)(6666004)(186003)(316002);\n DIR:OUT; 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Also\nadding the logic to share rx/tx ofloads with the eventdev\ncode.\n\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\n---\n doc/guides/nics/features/octeontx.ini | 1 +\n doc/guides/nics/octeontx.rst | 1 +\n drivers/event/octeontx/ssovf_worker.c | 2 +-\n drivers/net/octeontx/base/octeontx_pki_var.h | 32 ++++++\n drivers/net/octeontx/base/octeontx_pkovf.h | 5 +-\n drivers/net/octeontx/octeontx_ethdev.c | 98 +++++++++++++++++-\n drivers/net/octeontx/octeontx_ethdev.h | 13 ++-\n drivers/net/octeontx/octeontx_rxtx.c | 30 +++++-\n drivers/net/octeontx/octeontx_rxtx.h | 102 +++++++++++++++----\n 9 files changed, 253 insertions(+), 31 deletions(-)", "diff": "diff --git a/doc/guides/nics/features/octeontx.ini b/doc/guides/nics/features/octeontx.ini\nindex 323befe59..19caee61b 100644\n--- a/doc/guides/nics/features/octeontx.ini\n+++ b/doc/guides/nics/features/octeontx.ini\n@@ -9,6 +9,7 @@ Link status = Y\n Lock-free Tx queue = Y\n Queue start/stop = P\n Jumbo frame = Y\n+Scattered Rx = Y\n Promiscuous mode = Y\n Unicast MAC filter = Y\n CRC offload = Y\ndiff --git a/doc/guides/nics/octeontx.rst b/doc/guides/nics/octeontx.rst\nindex 8fc53810b..0c36e10cb 100644\n--- a/doc/guides/nics/octeontx.rst\n+++ b/doc/guides/nics/octeontx.rst\n@@ -20,6 +20,7 @@ Features of the OCTEON TX Ethdev PMD are:\n - Promiscuous mode\n - Port hardware statistics\n - Jumbo frames\n+- Scatter-Gather IO support\n - Link state information\n - SR-IOV VF\n - Multiple queues for TX\ndiff --git a/drivers/event/octeontx/ssovf_worker.c b/drivers/event/octeontx/ssovf_worker.c\nindex d940b5dd6..f11b9d8c4 100644\n--- a/drivers/event/octeontx/ssovf_worker.c\n+++ b/drivers/event/octeontx/ssovf_worker.c\n@@ -300,7 +300,7 @@ sso_event_tx_adapter_enqueue(void *port,\n \tdq = &txq->dq;\n \n \tif (__octeontx_xmit_pkts(dq->lmtline_va, dq->ioreg_va, dq->fc_status_va,\n-\t\t\t\tm) < 0)\n+\t\t\t\tm, OCCTX_TX_OFFLOAD_NONE) < 0)\n \t\treturn 0;\n \n \treturn 1;\ndiff --git a/drivers/net/octeontx/base/octeontx_pki_var.h b/drivers/net/octeontx/base/octeontx_pki_var.h\nindex f4661d24e..4445369ce 100644\n--- a/drivers/net/octeontx/base/octeontx_pki_var.h\n+++ b/drivers/net/octeontx/base/octeontx_pki_var.h\n@@ -215,4 +215,36 @@ enum lf_type_e {\n \tLF_UDP_VXLAN\t= OCCTX_PKI_LTYPE_UDP_VXLAN,\n \tLF_NVGRE\t= OCCTX_PKI_LTYPE_NVGRE,\n };\n+\n+/* Word 0 of HW segment buflink structure */\n+typedef union octtx_pki_buflink_w0_u {\n+\tuint64_t v;\n+\tstruct {\n+\t\tuint64_t size:16;\n+\t\tuint64_t rsvd1:15;\n+\t\tuint64_t invfree:1;\n+\t\t/** Aura number of the next segment */\n+\t\tuint64_t aura:16;\n+\t\tuint64_t sw:9;\n+\t\tuint64_t later_invfree:1;\n+\t\tuint64_t rsvd2:5;\n+\t\t/** 1 if aura number is set */\n+\t\tuint64_t has_aura:1;\n+\t} s;\n+} octtx_pki_buflink_w0_t;\n+\n+/* Word 1 of HW segment buflink structure */\n+typedef union octtx_pki_buflink_w1_u {\n+\tuint64_t v;\n+\tstruct {\n+\t\tuint64_t addr;\n+\t} s;\n+} octtx_pki_buflink_w1_t;\n+\n+/* HW structure linking packet segments into singly linked list */\n+typedef struct octtx_pki_buflink_s {\n+\tocttx_pki_buflink_w0_t w0; /* Word 0 of the buflink */\n+\tocttx_pki_buflink_w1_t w1; /* Word 1 of the buflink */\n+} octtx_pki_buflink_t;\n+\n #endif /* __OCTEONTX_PKI_VAR_H__ */\ndiff --git a/drivers/net/octeontx/base/octeontx_pkovf.h b/drivers/net/octeontx/base/octeontx_pkovf.h\nindex 4208ef880..4e0bb7c2e 100644\n--- a/drivers/net/octeontx/base/octeontx_pkovf.h\n+++ b/drivers/net/octeontx/base/octeontx_pkovf.h\n@@ -36,7 +36,10 @@\n \n /* pko_send_hdr_s + pko_send_link */\n #define PKO_CMD_SZ\t\t\t(2 << 1)\n-#define PKO_SEND_GATHER_SUBDC\t\t(0x0ull << 60)\n+#define PKO_SEND_BUFLINK_SUBDC\t\t(0x0ull << 60)\n+#define PKO_SEND_BUFLINK_LDTYPE(x)\t((x) << 58)\n+#define PKO_SEND_BUFLINK_GAUAR(x)\t((x) << 24)\n+#define PKO_SEND_GATHER_SUBDC\t\t(0x2ull << 60)\n #define PKO_SEND_GATHER_LDTYPE(x)\t((x) << 58)\n #define PKO_SEND_GATHER_GAUAR(x)\t((x) << 24)\n \ndiff --git a/drivers/net/octeontx/octeontx_ethdev.c b/drivers/net/octeontx/octeontx_ethdev.c\nindex e8aa4ec78..24c4e83a9 100644\n--- a/drivers/net/octeontx/octeontx_ethdev.c\n+++ b/drivers/net/octeontx/octeontx_ethdev.c\n@@ -24,6 +24,10 @@\n #include \"octeontx_rxtx.h\"\n #include \"octeontx_logs.h\"\n \n+struct evdev_priv_data {\n+\tOFFLOAD_FLAGS; /*Sequence should not be changed */\n+} __rte_cache_aligned;\n+\n struct octeontx_vdev_init_params {\n \tuint8_t\tnr_port;\n };\n@@ -257,6 +261,43 @@ devconf_set_default_sane_values(struct rte_event_dev_config *dev_conf,\n \t\t\tinfo->max_num_events;\n }\n \n+static uint16_t\n+octeontx_tx_offload_flags(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct octeontx_nic *nic = octeontx_pmd_priv(eth_dev);\n+\tuint16_t flags = 0;\n+\n+\t/* Created function for supoorting future offloads */\n+\tif (nic->tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS)\n+\t\tflags |= OCCTX_TX_MULTI_SEG_F;\n+\n+\treturn flags;\n+}\n+\n+static uint16_t\n+octeontx_rx_offload_flags(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct octeontx_nic *nic = octeontx_pmd_priv(eth_dev);\n+\tstruct rte_eth_dev_data *data = eth_dev->data;\n+\tstruct rte_eth_conf *conf = &data->dev_conf;\n+\tstruct rte_eth_rxmode *rxmode = &conf->rxmode;\n+\tuint16_t flags = 0;\n+\n+\tif (rxmode->mq_mode == ETH_MQ_RX_RSS)\n+\t\tflags |= OCCTX_RX_OFFLOAD_RSS_F;\n+\n+\tif (nic->rx_offloads & DEV_RX_OFFLOAD_SCATTER) {\n+\t\tflags |= OCCTX_RX_MULTI_SEG_F;\n+\t\teth_dev->data->scattered_rx = 1;\n+\t\t/* If scatter mode is enabled, TX should also be in multi\n+\t\t * seg mode, else memory leak will occur\n+\t\t */\n+\t\tnic->tx_offloads |= DEV_TX_OFFLOAD_MULTI_SEGS;\n+\t}\n+\n+\treturn flags;\n+}\n+\n static int\n octeontx_dev_configure(struct rte_eth_dev *dev)\n {\n@@ -321,6 +362,11 @@ octeontx_dev_configure(struct rte_eth_dev *dev)\n \tnic->pki.hash_enable = true;\n \tnic->pki.initialized = false;\n \n+\tnic->rx_offloads |= rxmode->offloads;\n+\tnic->tx_offloads |= txmode->offloads;\n+\tnic->rx_offload_flags |= octeontx_rx_offload_flags(dev);\n+\tnic->tx_offload_flags |= octeontx_tx_offload_flags(dev);\n+\n \treturn 0;\n }\n \n@@ -359,6 +405,51 @@ octeontx_dev_close(struct rte_eth_dev *dev)\n \tdev->rx_pkt_burst = NULL;\n }\n \n+static int\n+octeontx_recheck_rx_offloads(struct octeontx_rxq *rxq)\n+{\n+\tstruct rte_eth_dev *eth_dev = rxq->eth_dev;\n+\tstruct octeontx_nic *nic = octeontx_pmd_priv(eth_dev);\n+\tstruct rte_eth_dev_data *data = eth_dev->data;\n+\tstruct rte_pktmbuf_pool_private *mbp_priv;\n+\tstruct evdev_priv_data *evdev_priv;\n+\tstruct rte_eventdev *dev;\n+\tuint32_t buffsz;\n+\n+\t/* Get rx buffer size */\n+\tmbp_priv = rte_mempool_get_priv(rxq->pool);\n+\tbuffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;\n+\n+\t/* Setup scatter mode if needed by jumbo */\n+\tif (data->dev_conf.rxmode.max_rx_pkt_len > buffsz) {\n+\t\tnic->rx_offloads |= DEV_RX_OFFLOAD_SCATTER;\n+\t\tnic->rx_offload_flags |= octeontx_rx_offload_flags(eth_dev);\n+\t\tnic->tx_offload_flags |= octeontx_tx_offload_flags(eth_dev);\n+\t}\n+\n+\t/* Sharing offload flags via eventdev priv region */\n+\tdev = &rte_eventdevs[rxq->evdev];\n+\tevdev_priv = dev->data->dev_private;\n+\tevdev_priv->rx_offload_flags = nic->rx_offload_flags;\n+\tevdev_priv->tx_offload_flags = nic->tx_offload_flags;\n+\n+\treturn 0;\n+}\n+\n+static void\n+octeontx_set_tx_function(struct rte_eth_dev *dev)\n+{\n+\tstruct octeontx_nic *nic = octeontx_pmd_priv(dev);\n+\n+\tconst eth_tx_burst_t tx_burst_func[2] = {\n+\t\t[0] = octeontx_xmit_pkts,\n+\t\t[1] = octeontx_xmit_pkts_mseg,\n+\t};\n+\n+\tdev->tx_pkt_burst =\n+\t\ttx_burst_func[!!(nic->tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS)];\n+}\n+\n static int\n octeontx_dev_start(struct rte_eth_dev *dev)\n {\n@@ -371,7 +462,7 @@ octeontx_dev_start(struct rte_eth_dev *dev)\n \t/*\n \t * Tx start\n \t */\n-\tdev->tx_pkt_burst = octeontx_xmit_pkts;\n+\tocteontx_set_tx_function(dev);\n \tret = octeontx_pko_channel_start(nic->base_ochan);\n \tif (ret < 0) {\n \t\tocteontx_log_err(\"fail to conf VF%d no. txq %d chan %d ret %d\",\n@@ -599,10 +690,8 @@ octeontx_dev_default_mac_addr_set(struct rte_eth_dev *dev,\n \t\t\t\t\tstruct rte_ether_addr *addr)\n {\n \tstruct octeontx_nic *nic = octeontx_pmd_priv(dev);\n-\tuint8_t prom_mode = dev->data->promiscuous;\n \tint ret;\n \n-\tdev->data->promiscuous = 0;\n \tret = octeontx_bgx_port_mac_set(nic->port_id, addr->addr_bytes);\n \tif (ret == 0) {\n \t\t/* Update same mac address to BGX CAM table */\n@@ -610,7 +699,6 @@ octeontx_dev_default_mac_addr_set(struct rte_eth_dev *dev,\n \t\t\t\t\t\t0);\n \t}\n \tif (ret < 0) {\n-\t\tdev->data->promiscuous = prom_mode;\n \t\tocteontx_log_err(\"failed to set MAC address on port %d\",\n \t\t\t\t nic->port_id);\n \t}\n@@ -977,7 +1065,9 @@ octeontx_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,\n \trxq->evdev = nic->evdev;\n \trxq->ev_queues = ev_queues;\n \trxq->ev_ports = ev_ports;\n+\trxq->pool = mb_pool;\n \n+\tocteontx_recheck_rx_offloads(rxq);\n \tdev->data->rx_queues[qidx] = rxq;\n \tdev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;\n \treturn 0;\ndiff --git a/drivers/net/octeontx/octeontx_ethdev.h b/drivers/net/octeontx/octeontx_ethdev.h\nindex 50fae35d9..10da6a2a0 100644\n--- a/drivers/net/octeontx/octeontx_ethdev.h\n+++ b/drivers/net/octeontx/octeontx_ethdev.h\n@@ -29,8 +29,12 @@\n #define OCTEONTX_MAX_BGX_PORTS\t\t\t4\n #define OCTEONTX_MAX_LMAC_PER_BGX\t\t4\n \n-#define OCTEONTX_RX_OFFLOADS\t\t\tDEV_RX_OFFLOAD_CHECKSUM\n-#define OCTEONTX_TX_OFFLOADS\t\t\tDEV_TX_OFFLOAD_MT_LOCKFREE\n+#define OCTEONTX_RX_OFFLOADS\t\t\t(DEV_RX_OFFLOAD_CHECKSUM | \\\n+\t\t\t\t\t\t DEV_RX_OFFLOAD_SCATTER\t | \\\n+\t\t\t\t\t\t DEV_RX_OFFLOAD_JUMBO_FRAME)\n+\n+#define OCTEONTX_TX_OFFLOADS\t\t\t(DEV_TX_OFFLOAD_MT_LOCKFREE | \\\n+\t\t\t\t\t\t DEV_TX_OFFLOAD_MULTI_SEGS)\n \n static inline struct octeontx_nic *\n octeontx_pmd_priv(struct rte_eth_dev *dev)\n@@ -73,6 +77,10 @@ struct octeontx_nic {\n \n \tuint16_t ev_queues;\n \tuint16_t ev_ports;\n+\tuint64_t rx_offloads;\n+\tuint16_t rx_offload_flags;\n+\tuint64_t tx_offloads;\n+\tuint16_t tx_offload_flags;\n } __rte_cache_aligned;\n \n struct octeontx_txq {\n@@ -88,6 +96,7 @@ struct octeontx_rxq {\n \tstruct rte_eth_dev *eth_dev;\n \tuint16_t ev_queues;\n \tuint16_t ev_ports;\n+\tstruct rte_mempool *pool;\n } __rte_cache_aligned;\n \n #endif /* __OCTEONTX_ETHDEV_H__ */\ndiff --git a/drivers/net/octeontx/octeontx_rxtx.c b/drivers/net/octeontx/octeontx_rxtx.c\nindex 1e201f322..8f6d14b5f 100644\n--- a/drivers/net/octeontx/octeontx_rxtx.c\n+++ b/drivers/net/octeontx/octeontx_rxtx.c\n@@ -32,8 +32,34 @@ octeontx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \trte_cio_wmb();\n \twhile (count < nb_pkts) {\n \t\tres = __octeontx_xmit_pkts(dq->lmtline_va, dq->ioreg_va,\n-\t\t\t\t\t dq->fc_status_va,\n-\t\t\t\t\t tx_pkts[count]);\n+\t\t\t\t\t dq->fc_status_va, tx_pkts[count],\n+\t\t\t\t\t OCCTX_TX_OFFLOAD_NONE);\n+\t\tif (res < 0)\n+\t\t\tbreak;\n+\n+\t\tcount++;\n+\t}\n+\n+\treturn count; /* return number of pkts transmitted */\n+}\n+\n+uint16_t __hot\n+octeontx_xmit_pkts_mseg(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\tuint16_t nb_pkts)\n+{\n+\tint count;\n+\tstruct octeontx_txq *txq = tx_queue;\n+\tocteontx_dq_t *dq = &txq->dq;\n+\tint res;\n+\n+\tcount = 0;\n+\n+\trte_cio_wmb();\n+\twhile (count < nb_pkts) {\n+\t\tres = __octeontx_xmit_pkts(dq->lmtline_va, dq->ioreg_va,\n+\t\t\t\t\t dq->fc_status_va, tx_pkts[count],\n+\t\t\t\t\t OCCTX_TX_OFFLOAD_NONE |\n+\t\t\t\t\t OCCTX_TX_MULTI_SEG_F);\n \t\tif (res < 0)\n \t\t\tbreak;\n \ndiff --git a/drivers/net/octeontx/octeontx_rxtx.h b/drivers/net/octeontx/octeontx_rxtx.h\nindex d0d73b304..562268f16 100644\n--- a/drivers/net/octeontx/octeontx_rxtx.h\n+++ b/drivers/net/octeontx/octeontx_rxtx.h\n@@ -11,6 +11,19 @@\n #define __hot\t__attribute__((hot))\n #endif\n \n+#define OFFLOAD_FLAGS\t\t\t\t\t\\\n+\tuint16_t rx_offload_flags;\t\t\t\\\n+\tuint16_t tx_offload_flags\n+\n+#define BIT(nr) (1UL << (nr))\n+\n+#define OCCTX_RX_OFFLOAD_NONE\t\t(0)\n+#define OCCTX_RX_OFFLOAD_RSS_F BIT(0)\n+#define OCCTX_RX_MULTI_SEG_F\t\tBIT(15)\n+\n+#define OCCTX_TX_OFFLOAD_NONE\t\t(0)\n+\n+#define OCCTX_TX_MULTI_SEG_F\t\tBIT(15)\n /* Packet type table */\n #define PTYPE_SIZE\tOCCTX_PKI_LTYPE_LAST\n \n@@ -102,33 +115,76 @@ ptype_table[PTYPE_SIZE][PTYPE_SIZE][PTYPE_SIZE] = {\n \n static __rte_always_inline int\n __octeontx_xmit_pkts(void *lmtline_va, void *ioreg_va, int64_t *fc_status_va,\n-\t\t\tstruct rte_mbuf *tx_pkt)\n+\t\t\tstruct rte_mbuf *tx_pkt, const uint16_t flag)\n {\n-\tuint64_t cmd_buf[4] __rte_cache_aligned;\n-\tuint16_t gaura_id;\n+\tuint8_t sz = (4 + (!!(flag & OCCTX_TX_MULTI_SEG_F) * 10));\n+\t/* Max size of PKO SEND desc is 112 bytes*/\n+\tuint64_t cmd_buf[sz] __rte_cache_aligned;\n+\tuint8_t nb_segs, nb_desc = 0;\n+\tuint16_t gaura_id, len = 0;\n+\tstruct rte_mbuf *m_next = NULL;\n \n \tif (unlikely(*((volatile int64_t *)fc_status_va) < 0))\n \t\treturn -ENOSPC;\n \n-\t/* Get the gaura Id */\n-\tgaura_id = octeontx_fpa_bufpool_gpool((uintptr_t)tx_pkt->pool->pool_id);\n-\n-\t/* Setup PKO_SEND_HDR_S */\n-\tcmd_buf[0] = tx_pkt->data_len & 0xffff;\n-\tcmd_buf[1] = 0x0;\n \n-\t/* Set don't free bit if reference count > 1 */\n-\tif (rte_mbuf_refcnt_read(tx_pkt) > 1)\n-\t\tcmd_buf[0] |= (1ULL << 58); /* SET DF */\n-\n-\t/* Setup PKO_SEND_GATHER_S */\n-\tcmd_buf[(1 << 1) | 1] = rte_mbuf_data_iova(tx_pkt);\n-\tcmd_buf[(1 << 1) | 0] = PKO_SEND_GATHER_SUBDC |\n-\t\t\t\tPKO_SEND_GATHER_LDTYPE(0x1ull) |\n-\t\t\t\tPKO_SEND_GATHER_GAUAR((long)gaura_id) |\n-\t\t\t\ttx_pkt->data_len;\n-\n-\tocteontx_reg_lmtst(lmtline_va, ioreg_va, cmd_buf, PKO_CMD_SZ);\n+\tif (flag & OCCTX_TX_MULTI_SEG_F) {\n+\t\tnb_segs = tx_pkt->nb_segs;\n+\t\t/* Setup PKO_SEND_HDR_S */\n+\t\tcmd_buf[nb_desc++] = tx_pkt->pkt_len & 0xffff;\n+\t\tcmd_buf[nb_desc++] = 0x0;\n+\n+\t\tdo {\n+\t\t\tm_next = tx_pkt->next;\n+\t\t\t/* To handle case where mbufs belong to diff pools, like\n+\t\t\t * fragmentation\n+\t\t\t */\n+\t\t\tgaura_id = octeontx_fpa_bufpool_gpool((uintptr_t)\n+\t\t\t\t\t\t\ttx_pkt->pool->pool_id);\n+\n+\t\t\t/* Setup PKO_SEND_GATHER_S */\n+\t\t\tcmd_buf[nb_desc] = PKO_SEND_GATHER_SUBDC |\n+\t\t\t\t\t PKO_SEND_GATHER_LDTYPE(0x1ull) |\n+\t\t\t\t\t PKO_SEND_GATHER_GAUAR((long)\n+\t\t\t\t\t\t\t\t gaura_id) |\n+\t\t\t\t\t tx_pkt->data_len;\n+\t\t\t/* Mark mempool object as \"put\" since it is freed by\n+\t\t\t * PKO.\n+\t\t\t */\n+\t\t\tif (!(cmd_buf[nb_desc] & (1ULL << 57))) {\n+\t\t\t\ttx_pkt->next = NULL;\n+\t\t\t\t__mempool_check_cookies(tx_pkt->pool,\n+\t\t\t\t\t\t\t(void **)&tx_pkt, 1, 0);\n+\t\t\t}\n+\t\t\tnb_desc++;\n+\n+\t\t\tcmd_buf[nb_desc++] = rte_mbuf_data_iova(tx_pkt);\n+\n+\t\t\tnb_segs--;\n+\t\t\tlen += tx_pkt->data_len;\n+\t\t\ttx_pkt = m_next;\n+\t\t} while (nb_segs);\n+\t} else {\n+\t\t/* Setup PKO_SEND_HDR_S */\n+\t\tcmd_buf[nb_desc++] = tx_pkt->data_len & 0xffff;\n+\t\tcmd_buf[nb_desc++] = 0x0;\n+\n+\t\t/* Mark mempool object as \"put\" since it is freed by PKO */\n+\t\tif (!(cmd_buf[0] & (1ULL << 58)))\n+\t\t\t__mempool_check_cookies(tx_pkt->pool, (void **)&tx_pkt,\n+\t\t\t\t\t\t1, 0);\n+\t\t/* Get the gaura Id */\n+\t\tgaura_id = octeontx_fpa_bufpool_gpool((uintptr_t)\n+\t\t\t\t\t\t tx_pkt->pool->pool_id);\n+\n+\t\t/* Setup PKO_SEND_BUFLINK_S */\n+\t\tcmd_buf[nb_desc++] = PKO_SEND_BUFLINK_SUBDC |\n+\t\t\t\t PKO_SEND_BUFLINK_LDTYPE(0x1ull) |\n+\t\t\t\t PKO_SEND_BUFLINK_GAUAR((long)gaura_id) |\n+\t\t\t\t tx_pkt->data_len;\n+\t\tcmd_buf[nb_desc++] = rte_mbuf_data_iova(tx_pkt);\n+\t}\n+\tocteontx_reg_lmtst(lmtline_va, ioreg_va, cmd_buf, nb_desc);\n \n \treturn 0;\n }\n@@ -136,6 +192,10 @@ __octeontx_xmit_pkts(void *lmtline_va, void *ioreg_va, int64_t *fc_status_va,\n uint16_t\n octeontx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts);\n \n+uint16_t\n+octeontx_xmit_pkts_mseg(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\tuint16_t nb_pkts);\n+\n uint16_t\n octeontx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts);\n \n", "prefixes": [ "1/8" ] }