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GET /api/patches/66680/?format=api
{ "id": 66680, "url": "http://patches.dpdk.org/api/patches/66680/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200316074603.10998-6-leyi.rong@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200316074603.10998-6-leyi.rong@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200316074603.10998-6-leyi.rong@intel.com", "date": "2020-03-16T07:45:56", "name": "[05/12] net/iavf: flexible Rx descriptor support in AVX path", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1c05b82690c63660159101e7184cb7e49f354649", "submitter": { "id": 1204, "url": "http://patches.dpdk.org/api/people/1204/?format=api", "name": "Leyi Rong", "email": "leyi.rong@intel.com" }, "delegate": { "id": 31221, "url": "http://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200316074603.10998-6-leyi.rong@intel.com/mbox/", "series": [ { "id": 8918, "url": "http://patches.dpdk.org/api/series/8918/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8918", "date": "2020-03-16T07:45:51", "name": "framework for advanced iAVF PMD", "version": 1, "mbox": "http://patches.dpdk.org/series/8918/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/66680/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/66680/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 23196A0559;\n\tMon, 16 Mar 2020 08:58:26 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 63D001C0BE;\n\tMon, 16 Mar 2020 08:57:35 +0100 (CET)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by dpdk.org (Postfix) with ESMTP id C67071C0AC\n for <dev@dpdk.org>; Mon, 16 Mar 2020 08:57:31 +0100 (CET)", "from orsmga004.jf.intel.com ([10.7.209.38])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 16 Mar 2020 00:57:30 -0700", "from dpdk-lrong-srv-04.sh.intel.com ([10.67.119.221])\n by orsmga004.jf.intel.com with ESMTP; 16 Mar 2020 00:57:29 -0700" ], "IronPort-SDR": [ "\n FqdXICpMS6q+KDKgUf3dt3umKkOnXIhZdZs7dB0Qjsgy5L+uLzu7bEn1wTq2qxej4+xxZP5dDe\n 7IcDi9Cf8Dbw==", "\n 2CW8XQY0SPa9B7HbERKuRtZQ/84sH5K2UysdUV4PfZRfKi9JBS2SZk0eaYqEQcpeR/iZxs0Vp2\n Us3gHiZF9eFQ==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.70,559,1574150400\"; d=\"scan'208\";a=\"390622514\"", "From": "Leyi Rong <leyi.rong@intel.com>", "To": "qi.z.zhang@intel.com,\n\txiaolong.ye@intel.com", "Cc": "dev@dpdk.org,\n\tLeyi Rong <leyi.rong@intel.com>", "Date": "Mon, 16 Mar 2020 15:45:56 +0800", "Message-Id": "<20200316074603.10998-6-leyi.rong@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200316074603.10998-1-leyi.rong@intel.com>", "References": "<20200316074603.10998-1-leyi.rong@intel.com>", "Subject": "[dpdk-dev] [PATCH 05/12] net/iavf: flexible Rx descriptor support\n\tin AVX path", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Support flexible Rx descriptor format in AVX\npath of iAVF PMD.\n\nSigned-off-by: Leyi Rong <leyi.rong@intel.com>\n---\n drivers/net/iavf/iavf_rxtx.c | 24 +-\n drivers/net/iavf/iavf_rxtx.h | 6 +\n drivers/net/iavf/iavf_rxtx_vec_avx2.c | 550 +++++++++++++++++++++++++-\n 3 files changed, 570 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c\nindex b9b35bdbb..57fffece9 100644\n--- a/drivers/net/iavf/iavf_rxtx.c\n+++ b/drivers/net/iavf/iavf_rxtx.c\n@@ -2115,16 +2115,28 @@ iavf_set_rx_function(struct rte_eth_dev *dev)\n \t\t\t\t \"Using %sVector Scattered Rx (port %d).\",\n \t\t\t\t use_avx2 ? \"avx2 \" : \"\",\n \t\t\t\t dev->data->port_id);\n-\t\t\tdev->rx_pkt_burst = use_avx2 ?\n-\t\t\t\t\t iavf_recv_scattered_pkts_vec_avx2 :\n-\t\t\t\t\t iavf_recv_scattered_pkts_vec;\n+\t\t\tif (vf->vf_res->vf_cap_flags &\n+\t\t\t\tVIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)\n+\t\t\t\tdev->rx_pkt_burst = use_avx2 ?\n+\t\t\t\t\tiavf_recv_scattered_pkts_vec_avx2_flex_rxd :\n+\t\t\t\t\tiavf_recv_scattered_pkts_vec;\n+\t\t\telse\n+\t\t\t\tdev->rx_pkt_burst = use_avx2 ?\n+\t\t\t\t\tiavf_recv_scattered_pkts_vec_avx2 :\n+\t\t\t\t\tiavf_recv_scattered_pkts_vec;\n \t\t} else {\n \t\t\tPMD_DRV_LOG(DEBUG, \"Using %sVector Rx (port %d).\",\n \t\t\t\t use_avx2 ? \"avx2 \" : \"\",\n \t\t\t\t dev->data->port_id);\n-\t\t\tdev->rx_pkt_burst = use_avx2 ?\n-\t\t\t\t\t iavf_recv_pkts_vec_avx2 :\n-\t\t\t\t\t iavf_recv_pkts_vec;\n+\t\t\tif (vf->vf_res->vf_cap_flags &\n+\t\t\t\tVIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)\n+\t\t\t\tdev->rx_pkt_burst = use_avx2 ?\n+\t\t\t\t\tiavf_recv_pkts_vec_avx2_flex_rxd :\n+\t\t\t\t\tiavf_recv_pkts_vec;\n+\t\t\telse\n+\t\t\t\tdev->rx_pkt_burst = use_avx2 ?\n+\t\t\t\t\tiavf_recv_pkts_vec_avx2 :\n+\t\t\t\t\tiavf_recv_pkts_vec;\n \t\t}\n \n \t\treturn;\ndiff --git a/drivers/net/iavf/iavf_rxtx.h b/drivers/net/iavf/iavf_rxtx.h\nindex ee306d400..de13fd516 100644\n--- a/drivers/net/iavf/iavf_rxtx.h\n+++ b/drivers/net/iavf/iavf_rxtx.h\n@@ -212,9 +212,15 @@ uint16_t iavf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\t\t uint16_t nb_pkts);\n uint16_t iavf_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\t\t uint16_t nb_pkts);\n+uint16_t iavf_recv_pkts_vec_avx2_flex_rxd(void *rx_queue,\n+\t\t\t\t\t struct rte_mbuf **rx_pkts,\n+\t\t\t\t\t uint16_t nb_pkts);\n uint16_t iavf_recv_scattered_pkts_vec_avx2(void *rx_queue,\n \t\t\t\t\t struct rte_mbuf **rx_pkts,\n \t\t\t\t\t uint16_t nb_pkts);\n+uint16_t iavf_recv_scattered_pkts_vec_avx2_flex_rxd(void *rx_queue,\n+\t\t\t\t\t\t struct rte_mbuf **rx_pkts,\n+\t\t\t\t\t\t uint16_t nb_pkts);\n uint16_t iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\t uint16_t nb_pkts);\n uint16_t iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,\ndiff --git a/drivers/net/iavf/iavf_rxtx_vec_avx2.c b/drivers/net/iavf/iavf_rxtx_vec_avx2.c\nindex 4e1231162..74f672c7e 100644\n--- a/drivers/net/iavf/iavf_rxtx_vec_avx2.c\n+++ b/drivers/net/iavf/iavf_rxtx_vec_avx2.c\n@@ -11,14 +11,16 @@\n #endif\n \n static inline void\n-iavf_rxq_rearm(struct iavf_rx_queue *rxq)\n+iavf_rxq_rearm(struct iavf_rx_queue *rxq, volatile union iavf_rx_desc *rxdp)\n {\n \tint i;\n \tuint16_t rx_id;\n-\tvolatile union iavf_rx_desc *rxdp;\n \tstruct rte_mbuf **rxp = &rxq->sw_ring[rxq->rxrearm_start];\n \n-\trxdp = rxq->rx_ring + rxq->rxrearm_start;\n+\tif (rxq->rxdid == IAVF_RXDID_COMMS_OVS_1) {\n+\t\tvolatile union iavf_rx_flex_desc *rxdp =\n+\t\t\t(union iavf_rx_flex_desc *)rxdp;\n+\t}\n \n \t/* Pull 'n' more MBUFs into the software ring */\n \tif (rte_mempool_get_bulk(rxq->mp,\n@@ -110,7 +112,7 @@ _iavf_recv_raw_pkts_vec_avx2(struct iavf_rx_queue *rxq,\n \t * of time to act\n \t */\n \tif (rxq->rxrearm_nb > IAVF_RXQ_REARM_THRESH)\n-\t\tiavf_rxq_rearm(rxq);\n+\t\tiavf_rxq_rearm(rxq, rxq->rx_ring + rxq->rxrearm_start);\n \n \t/* Before we start moving massive data around, check to see if\n \t * there is actually a packet available\n@@ -548,6 +550,465 @@ _iavf_recv_raw_pkts_vec_avx2(struct iavf_rx_queue *rxq,\n \treturn received;\n }\n \n+static inline uint16_t\n+_iavf_recv_raw_pkts_vec_avx2_flex_rxd(struct iavf_rx_queue *rxq,\n+\t\t\t\t struct rte_mbuf **rx_pkts,\n+\t\t\t\t uint16_t nb_pkts, uint8_t *split_packet)\n+{\n+#define IAVF_DESCS_PER_LOOP_AVX 8\n+\n+\tconst uint32_t *type_table = rxq->vsi->adapter->ptype_tbl;\n+\n+\tconst __m256i mbuf_init = _mm256_set_epi64x(0, 0,\n+\t\t\t0, rxq->mbuf_initializer);\n+\tstruct rte_mbuf **sw_ring = &rxq->sw_ring[rxq->rx_tail];\n+\tvolatile union iavf_rx_flex_desc *rxdp =\n+\t\t(union iavf_rx_flex_desc *)rxq->rx_ring + rxq->rx_tail;\n+\n+\trte_prefetch0(rxdp);\n+\n+\t/* nb_pkts has to be floor-aligned to IAVF_DESCS_PER_LOOP_AVX */\n+\tnb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_DESCS_PER_LOOP_AVX);\n+\n+\t/* See if we need to rearm the RX queue - gives the prefetch a bit\n+\t * of time to act\n+\t */\n+\tif (rxq->rxrearm_nb > IAVF_RXQ_REARM_THRESH)\n+\t\t/* iavf_rxq_rearm(rxq); */\n+\t\tiavf_rxq_rearm(rxq, rxq->rx_ring + rxq->rxrearm_start);\n+\n+\t/* Before we start moving massive data around, check to see if\n+\t * there is actually a packet available\n+\t */\n+\tif (!(rxdp->wb.status_error0 &\n+\t\t\trte_cpu_to_le_32(1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))\n+\t\treturn 0;\n+\n+\t/* constants used in processing loop */\n+\tconst __m256i crc_adjust =\n+\t\t_mm256_set_epi16\n+\t\t\t(/* first descriptor */\n+\t\t\t 0, 0, 0, /* ignore non-length fields */\n+\t\t\t -rxq->crc_len, /* sub crc on data_len */\n+\t\t\t 0, /* ignore high-16bits of pkt_len */\n+\t\t\t -rxq->crc_len, /* sub crc on pkt_len */\n+\t\t\t 0, 0, /* ignore pkt_type field */\n+\t\t\t /* second descriptor */\n+\t\t\t 0, 0, 0, /* ignore non-length fields */\n+\t\t\t -rxq->crc_len, /* sub crc on data_len */\n+\t\t\t 0, /* ignore high-16bits of pkt_len */\n+\t\t\t -rxq->crc_len, /* sub crc on pkt_len */\n+\t\t\t 0, 0 /* ignore pkt_type field */\n+\t\t\t);\n+\n+\t/* 8 packets DD mask, LSB in each 32-bit value */\n+\tconst __m256i dd_check = _mm256_set1_epi32(1);\n+\n+\t/* 8 packets EOP mask, second-LSB in each 32-bit value */\n+\tconst __m256i eop_check = _mm256_slli_epi32(dd_check,\n+\t\t\tIAVF_RX_FLEX_DESC_STATUS0_EOF_S);\n+\n+\t/* mask to shuffle from desc. to mbuf (2 descriptors)*/\n+\tconst __m256i shuf_msk =\n+\t\t_mm256_set_epi8\n+\t\t\t(/* first descriptor */\n+\t\t\t 15, 14,\n+\t\t\t 13, 12,\t/* octet 12~15, 32 bits rss */\n+\t\t\t 11, 10,\t/* octet 10~11, 16 bits vlan_macip */\n+\t\t\t 5, 4,\t\t/* octet 4~5, 16 bits data_len */\n+\t\t\t 0xFF, 0xFF,\t/* skip hi 16 bits pkt_len, zero out */\n+\t\t\t 5, 4,\t\t/* octet 4~5, 16 bits pkt_len */\n+\t\t\t 0xFF, 0xFF,\t/* pkt_type set as unknown */\n+\t\t\t 0xFF, 0xFF,\t/*pkt_type set as unknown */\n+\t\t\t /* second descriptor */\n+\t\t\t 15, 14,\n+\t\t\t 13, 12,\t/* octet 12~15, 32 bits rss */\n+\t\t\t 11, 10,\t/* octet 10~11, 16 bits vlan_macip */\n+\t\t\t 5, 4,\t\t/* octet 4~5, 16 bits data_len */\n+\t\t\t 0xFF, 0xFF,\t/* skip hi 16 bits pkt_len, zero out */\n+\t\t\t 5, 4,\t\t/* octet 4~5, 16 bits pkt_len */\n+\t\t\t 0xFF, 0xFF,\t/* pkt_type set as unknown */\n+\t\t\t 0xFF, 0xFF\t/*pkt_type set as unknown */\n+\t\t\t);\n+\t/**\n+\t * compile-time check the above crc and shuffle layout is correct.\n+\t * NOTE: the first field (lowest address) is given last in set_epi\n+\t * calls above.\n+\t */\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=\n+\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=\n+\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=\n+\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=\n+\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);\n+\n+\t/* Status/Error flag masks */\n+\t/**\n+\t * mask everything except Checksum Reports, RSS indication\n+\t * and VLAN indication.\n+\t * bit6:4 for IP/L4 checksum errors.\n+\t * bit12 is for RSS indication.\n+\t * bit13 is for VLAN indication.\n+\t */\n+\tconst __m256i flags_mask =\n+\t\t _mm256_set1_epi32((7 << 4) | (1 << 12) | (1 << 13));\n+\t/**\n+\t * data to be shuffled by the result of the flags mask shifted by 4\n+\t * bits. This gives use the l3_l4 flags.\n+\t */\n+\tconst __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t\t/* shift right 1 bit to make sure it not exceed 255 */\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |\n+\t\t\t PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |\n+\t\t\t PKT_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |\n+\t\t\t PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |\n+\t\t\t PKT_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t\t(PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t\t(PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t\t/* second 128-bits */\n+\t\t\t0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |\n+\t\t\t PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |\n+\t\t\t PKT_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |\n+\t\t\t PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |\n+\t\t\t PKT_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t\t(PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t\t(PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1);\n+\tconst __m256i cksum_mask =\n+\t\t _mm256_set1_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |\n+\t\t\t\t PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |\n+\t\t\t\t PKT_RX_EIP_CKSUM_BAD);\n+\t/**\n+\t * data to be shuffled by result of flag mask, shifted down 12.\n+\t * If RSS(bit12)/VLAN(bit13) are set,\n+\t * shuffle moves appropriate flags in place.\n+\t */\n+\tconst __m256i rss_vlan_flags_shuf = _mm256_set_epi8(0, 0, 0, 0,\n+\t\t\t0, 0, 0, 0,\n+\t\t\t0, 0, 0, 0,\n+\t\t\tPKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,\n+\t\t\tPKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,\n+\t\t\tPKT_RX_RSS_HASH, 0,\n+\t\t\t/* end up 128-bits */\n+\t\t\t0, 0, 0, 0,\n+\t\t\t0, 0, 0, 0,\n+\t\t\t0, 0, 0, 0,\n+\t\t\tPKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,\n+\t\t\tPKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,\n+\t\t\tPKT_RX_RSS_HASH, 0);\n+\n+\tuint16_t i, received;\n+\n+\tfor (i = 0, received = 0; i < nb_pkts;\n+\t i += IAVF_DESCS_PER_LOOP_AVX,\n+\t rxdp += IAVF_DESCS_PER_LOOP_AVX) {\n+\t\t/* step 1, copy over 8 mbuf pointers to rx_pkts array */\n+\t\t_mm256_storeu_si256((void *)&rx_pkts[i],\n+\t\t\t\t _mm256_loadu_si256((void *)&sw_ring[i]));\n+#ifdef RTE_ARCH_X86_64\n+\t\t_mm256_storeu_si256\n+\t\t\t((void *)&rx_pkts[i + 4],\n+\t\t\t _mm256_loadu_si256((void *)&sw_ring[i + 4]));\n+#endif\n+\n+\t\t__m256i raw_desc0_1, raw_desc2_3, raw_desc4_5, raw_desc6_7;\n+\n+\t\tconst __m128i raw_desc7 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 7));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc6 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 6));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc5 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 5));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc4 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 4));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc3 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 3));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc2 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 2));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc1 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 1));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc0 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 0));\n+\n+\t\traw_desc6_7 =\n+\t\t\t_mm256_inserti128_si256\n+\t\t\t\t(_mm256_castsi128_si256(raw_desc6),\n+\t\t\t\t raw_desc7, 1);\n+\t\traw_desc4_5 =\n+\t\t\t_mm256_inserti128_si256\n+\t\t\t\t(_mm256_castsi128_si256(raw_desc4),\n+\t\t\t\t raw_desc5, 1);\n+\t\traw_desc2_3 =\n+\t\t\t_mm256_inserti128_si256\n+\t\t\t\t(_mm256_castsi128_si256(raw_desc2),\n+\t\t\t\t raw_desc3, 1);\n+\t\traw_desc0_1 =\n+\t\t\t_mm256_inserti128_si256\n+\t\t\t\t(_mm256_castsi128_si256(raw_desc0),\n+\t\t\t\t raw_desc1, 1);\n+\n+\t\tif (split_packet) {\n+\t\t\tint j;\n+\n+\t\t\tfor (j = 0; j < IAVF_DESCS_PER_LOOP_AVX; j++)\n+\t\t\t\trte_mbuf_prefetch_part2(rx_pkts[i + j]);\n+\t\t}\n+\n+\t\t/**\n+\t\t * convert descriptors 4-7 into mbufs, re-arrange fields.\n+\t\t * Then write into the mbuf.\n+\t\t */\n+\t\t__m256i mb6_7 = _mm256_shuffle_epi8(raw_desc6_7, shuf_msk);\n+\t\t__m256i mb4_5 = _mm256_shuffle_epi8(raw_desc4_5, shuf_msk);\n+\n+\t\tmb6_7 = _mm256_add_epi16(mb6_7, crc_adjust);\n+\t\tmb4_5 = _mm256_add_epi16(mb4_5, crc_adjust);\n+\t\t/**\n+\t\t * to get packet types, ptype is located in bit16-25\n+\t\t * of each 128bits\n+\t\t */\n+\t\tconst __m256i ptype_mask =\n+\t\t\t_mm256_set1_epi16(IAVF_RX_FLEX_DESC_PTYPE_M);\n+\t\tconst __m256i ptypes6_7 =\n+\t\t\t_mm256_and_si256(raw_desc6_7, ptype_mask);\n+\t\tconst __m256i ptypes4_5 =\n+\t\t\t_mm256_and_si256(raw_desc4_5, ptype_mask);\n+\t\tconst uint16_t ptype7 = _mm256_extract_epi16(ptypes6_7, 9);\n+\t\tconst uint16_t ptype6 = _mm256_extract_epi16(ptypes6_7, 1);\n+\t\tconst uint16_t ptype5 = _mm256_extract_epi16(ptypes4_5, 9);\n+\t\tconst uint16_t ptype4 = _mm256_extract_epi16(ptypes4_5, 1);\n+\n+\t\tmb6_7 = _mm256_insert_epi32(mb6_7, type_table[ptype7], 4);\n+\t\tmb6_7 = _mm256_insert_epi32(mb6_7, type_table[ptype6], 0);\n+\t\tmb4_5 = _mm256_insert_epi32(mb4_5, type_table[ptype5], 4);\n+\t\tmb4_5 = _mm256_insert_epi32(mb4_5, type_table[ptype4], 0);\n+\t\t/* merge the status bits into one register */\n+\t\tconst __m256i status4_7 = _mm256_unpackhi_epi32(raw_desc6_7,\n+\t\t\t\traw_desc4_5);\n+\n+\t\t/**\n+\t\t * convert descriptors 0-3 into mbufs, re-arrange fields.\n+\t\t * Then write into the mbuf.\n+\t\t */\n+\t\t__m256i mb2_3 = _mm256_shuffle_epi8(raw_desc2_3, shuf_msk);\n+\t\t__m256i mb0_1 = _mm256_shuffle_epi8(raw_desc0_1, shuf_msk);\n+\n+\t\tmb2_3 = _mm256_add_epi16(mb2_3, crc_adjust);\n+\t\tmb0_1 = _mm256_add_epi16(mb0_1, crc_adjust);\n+\t\t/**\n+\t\t * to get packet types, ptype is located in bit16-25\n+\t\t * of each 128bits\n+\t\t */\n+\t\tconst __m256i ptypes2_3 =\n+\t\t\t_mm256_and_si256(raw_desc2_3, ptype_mask);\n+\t\tconst __m256i ptypes0_1 =\n+\t\t\t_mm256_and_si256(raw_desc0_1, ptype_mask);\n+\t\tconst uint16_t ptype3 = _mm256_extract_epi16(ptypes2_3, 9);\n+\t\tconst uint16_t ptype2 = _mm256_extract_epi16(ptypes2_3, 1);\n+\t\tconst uint16_t ptype1 = _mm256_extract_epi16(ptypes0_1, 9);\n+\t\tconst uint16_t ptype0 = _mm256_extract_epi16(ptypes0_1, 1);\n+\n+\t\tmb2_3 = _mm256_insert_epi32(mb2_3, type_table[ptype3], 4);\n+\t\tmb2_3 = _mm256_insert_epi32(mb2_3, type_table[ptype2], 0);\n+\t\tmb0_1 = _mm256_insert_epi32(mb0_1, type_table[ptype1], 4);\n+\t\tmb0_1 = _mm256_insert_epi32(mb0_1, type_table[ptype0], 0);\n+\t\t/* merge the status bits into one register */\n+\t\tconst __m256i status0_3 = _mm256_unpackhi_epi32(raw_desc2_3,\n+\t\t\t\t\t\t\t\traw_desc0_1);\n+\n+\t\t/**\n+\t\t * take the two sets of status bits and merge to one\n+\t\t * After merge, the packets status flags are in the\n+\t\t * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]\n+\t\t */\n+\t\t__m256i status0_7 = _mm256_unpacklo_epi64(status4_7,\n+\t\t\t\t\t\t\t status0_3);\n+\n+\t\t/* now do flag manipulation */\n+\n+\t\t/* get only flag/error bits we want */\n+\t\tconst __m256i flag_bits =\n+\t\t\t_mm256_and_si256(status0_7, flags_mask);\n+\t\t/**\n+\t\t * l3_l4_error flags, shuffle, then shift to correct adjustment\n+\t\t * of flags in flags_shuf, and finally mask out extra bits\n+\t\t */\n+\t\t__m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,\n+\t\t\t\t_mm256_srli_epi32(flag_bits, 4));\n+\t\tl3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);\n+\t\tl3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);\n+\t\t/* set rss and vlan flags */\n+\t\tconst __m256i rss_vlan_flag_bits =\n+\t\t\t_mm256_srli_epi32(flag_bits, 12);\n+\t\tconst __m256i rss_vlan_flags =\n+\t\t\t_mm256_shuffle_epi8(rss_vlan_flags_shuf,\n+\t\t\t\t\t rss_vlan_flag_bits);\n+\n+\t\t/* merge flags */\n+\t\tconst __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,\n+\t\t\t\trss_vlan_flags);\n+\t\t/**\n+\t\t * At this point, we have the 8 sets of flags in the low 16-bits\n+\t\t * of each 32-bit value in vlan0.\n+\t\t * We want to extract these, and merge them with the mbuf init\n+\t\t * data so we can do a single write to the mbuf to set the flags\n+\t\t * and all the other initialization fields. Extracting the\n+\t\t * appropriate flags means that we have to do a shift and blend\n+\t\t * for each mbuf before we do the write. However, we can also\n+\t\t * add in the previously computed rx_descriptor fields to\n+\t\t * make a single 256-bit write per mbuf\n+\t\t */\n+\t\t/* check the structure matches expectations */\n+\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=\n+\t\t\t\t offsetof(struct rte_mbuf, rearm_data) + 8);\n+\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=\n+\t\t\t\t RTE_ALIGN(offsetof(struct rte_mbuf,\n+\t\t\t\t\t\t rearm_data),\n+\t\t\t\t\t 16));\n+\t\t/* build up data and do writes */\n+\t\t__m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,\n+\t\t\trearm6, rearm7;\n+\t\trearm6 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t _mm256_slli_si256(mbuf_flags, 8),\n+\t\t\t\t\t 0x04);\n+\t\trearm4 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t _mm256_slli_si256(mbuf_flags, 4),\n+\t\t\t\t\t 0x04);\n+\t\trearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);\n+\t\trearm0 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t _mm256_srli_si256(mbuf_flags, 4),\n+\t\t\t\t\t 0x04);\n+\t\t/* permute to add in the rx_descriptor e.g. rss fields */\n+\t\trearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);\n+\t\trearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);\n+\t\trearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);\n+\t\trearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);\n+\t\t/* write to mbuf */\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,\n+\t\t\t\t rearm6);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,\n+\t\t\t\t rearm4);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,\n+\t\t\t\t rearm2);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,\n+\t\t\t\t rearm0);\n+\n+\t\t/* repeat for the odd mbufs */\n+\t\tconst __m256i odd_flags =\n+\t\t\t_mm256_castsi128_si256\n+\t\t\t\t(_mm256_extracti128_si256(mbuf_flags, 1));\n+\t\trearm7 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t _mm256_slli_si256(odd_flags, 8),\n+\t\t\t\t\t 0x04);\n+\t\trearm5 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t _mm256_slli_si256(odd_flags, 4),\n+\t\t\t\t\t 0x04);\n+\t\trearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);\n+\t\trearm1 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t _mm256_srli_si256(odd_flags, 4),\n+\t\t\t\t\t 0x04);\n+\t\t/* since odd mbufs are already in hi 128-bits use blend */\n+\t\trearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);\n+\t\trearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);\n+\t\trearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);\n+\t\trearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);\n+\t\t/* again write to mbufs */\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,\n+\t\t\t\t rearm7);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,\n+\t\t\t\t rearm5);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,\n+\t\t\t\t rearm3);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,\n+\t\t\t\t rearm1);\n+\n+\t\t/* extract and record EOP bit */\n+\t\tif (split_packet) {\n+\t\t\tconst __m128i eop_mask =\n+\t\t\t\t_mm_set1_epi16(1 <<\n+\t\t\t\t\t IAVF_RX_FLEX_DESC_STATUS0_EOF_S);\n+\t\t\tconst __m256i eop_bits256 = _mm256_and_si256(status0_7,\n+\t\t\t\t\t\t\t\t eop_check);\n+\t\t\t/* pack status bits into a single 128-bit register */\n+\t\t\tconst __m128i eop_bits =\n+\t\t\t\t_mm_packus_epi32\n+\t\t\t\t\t(_mm256_castsi256_si128(eop_bits256),\n+\t\t\t\t\t _mm256_extractf128_si256(eop_bits256,\n+\t\t\t\t\t\t\t\t 1));\n+\t\t\t/**\n+\t\t\t * flip bits, and mask out the EOP bit, which is now\n+\t\t\t * a split-packet bit i.e. !EOP, rather than EOP one.\n+\t\t\t */\n+\t\t\t__m128i split_bits = _mm_andnot_si128(eop_bits,\n+\t\t\t\t\teop_mask);\n+\t\t\t/**\n+\t\t\t * eop bits are out of order, so we need to shuffle them\n+\t\t\t * back into order again. In doing so, only use low 8\n+\t\t\t * bits, which acts like another pack instruction\n+\t\t\t * The original order is (hi->lo): 1,3,5,7,0,2,4,6\n+\t\t\t * [Since we use epi8, the 16-bit positions are\n+\t\t\t * multiplied by 2 in the eop_shuffle value.]\n+\t\t\t */\n+\t\t\t__m128i eop_shuffle =\n+\t\t\t\t_mm_set_epi8(/* zero hi 64b */\n+\t\t\t\t\t 0xFF, 0xFF, 0xFF, 0xFF,\n+\t\t\t\t\t 0xFF, 0xFF, 0xFF, 0xFF,\n+\t\t\t\t\t /* move values to lo 64b */\n+\t\t\t\t\t 8, 0, 10, 2,\n+\t\t\t\t\t 12, 4, 14, 6);\n+\t\t\tsplit_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);\n+\t\t\t*(uint64_t *)split_packet =\n+\t\t\t\t_mm_cvtsi128_si64(split_bits);\n+\t\t\tsplit_packet += IAVF_DESCS_PER_LOOP_AVX;\n+\t\t}\n+\n+\t\t/* perform dd_check */\n+\t\tstatus0_7 = _mm256_and_si256(status0_7, dd_check);\n+\t\tstatus0_7 = _mm256_packs_epi32(status0_7,\n+\t\t\t\t\t _mm256_setzero_si256());\n+\n+\t\tuint64_t burst = __builtin_popcountll\n+\t\t\t\t\t(_mm_cvtsi128_si64\n+\t\t\t\t\t\t(_mm256_extracti128_si256\n+\t\t\t\t\t\t\t(status0_7, 1)));\n+\t\tburst += __builtin_popcountll\n+\t\t\t\t(_mm_cvtsi128_si64\n+\t\t\t\t\t(_mm256_castsi256_si128(status0_7)));\n+\t\treceived += burst;\n+\t\tif (burst != IAVF_DESCS_PER_LOOP_AVX)\n+\t\t\tbreak;\n+\t}\n+\n+\t/* update tail pointers */\n+\trxq->rx_tail += received;\n+\trxq->rx_tail &= (rxq->nb_rx_desc - 1);\n+\tif ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep avx2 aligned */\n+\t\trxq->rx_tail--;\n+\t\treceived--;\n+\t}\n+\trxq->rxrearm_nb += received;\n+\treturn received;\n+}\n+\n /**\n * Notice:\n * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet\n@@ -559,6 +1020,18 @@ iavf_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,\n \treturn _iavf_recv_raw_pkts_vec_avx2(rx_queue, rx_pkts, nb_pkts, NULL);\n }\n \n+/**\n+ * Notice:\n+ * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet\n+ */\n+uint16_t\n+iavf_recv_pkts_vec_avx2_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t\t\t uint16_t nb_pkts)\n+{\n+\treturn _iavf_recv_raw_pkts_vec_avx2_flex_rxd(rx_queue, rx_pkts,\n+\t\t\t\t\t\t nb_pkts, NULL);\n+}\n+\n /**\n * vPMD receive routine that reassembles single burst of 32 scattered packets\n * Notice:\n@@ -624,6 +1097,75 @@ iavf_recv_scattered_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\t\trx_pkts + retval, nb_pkts);\n }\n \n+/**\n+ * vPMD receive routine that reassembles single burst of\n+ * 32 scattered packets for flex RxD\n+ * Notice:\n+ * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet\n+ */\n+static uint16_t\n+iavf_recv_scattered_burst_vec_avx2_flex_rxd(void *rx_queue,\n+\t\t\t\t\t struct rte_mbuf **rx_pkts,\n+\t\t\t\t\t uint16_t nb_pkts)\n+{\n+\tstruct iavf_rx_queue *rxq = rx_queue;\n+\tuint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};\n+\n+\t/* get some new buffers */\n+\tuint16_t nb_bufs = _iavf_recv_raw_pkts_vec_avx2_flex_rxd(rxq,\n+\t\t\t\t\trx_pkts, nb_pkts, split_flags);\n+\tif (nb_bufs == 0)\n+\t\treturn 0;\n+\n+\t/* happy day case, full burst + no packets to be joined */\n+\tconst uint64_t *split_fl64 = (uint64_t *)split_flags;\n+\n+\tif (!rxq->pkt_first_seg &&\n+\t split_fl64[0] == 0 && split_fl64[1] == 0 &&\n+\t split_fl64[2] == 0 && split_fl64[3] == 0)\n+\t\treturn nb_bufs;\n+\n+\t/* reassemble any packets that need reassembly*/\n+\tunsigned int i = 0;\n+\n+\tif (!rxq->pkt_first_seg) {\n+\t\t/* find the first split flag, and only reassemble then*/\n+\t\twhile (i < nb_bufs && !split_flags[i])\n+\t\t\ti++;\n+\t\tif (i == nb_bufs)\n+\t\t\treturn nb_bufs;\n+\t\trxq->pkt_first_seg = rx_pkts[i];\n+\t}\n+\treturn i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,\n+\t\t\t\t\t &split_flags[i]);\n+}\n+\n+/**\n+ * vPMD receive routine that reassembles scattered packets for flex RxD.\n+ * Main receive routine that can handle arbitrary burst sizes\n+ * Notice:\n+ * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet\n+ */\n+uint16_t\n+iavf_recv_scattered_pkts_vec_avx2_flex_rxd(void *rx_queue,\n+\t\t\t\t\t struct rte_mbuf **rx_pkts,\n+\t\t\t\t\t uint16_t nb_pkts)\n+{\n+\tuint16_t retval = 0;\n+\n+\twhile (nb_pkts > IAVF_VPMD_RX_MAX_BURST) {\n+\t\tuint16_t burst =\n+\t\t\tiavf_recv_scattered_burst_vec_avx2_flex_rxd\n+\t\t\t(rx_queue, rx_pkts + retval, IAVF_VPMD_RX_MAX_BURST);\n+\t\tretval += burst;\n+\t\tnb_pkts -= burst;\n+\t\tif (burst < IAVF_VPMD_RX_MAX_BURST)\n+\t\t\treturn retval;\n+\t}\n+\treturn retval + iavf_recv_scattered_burst_vec_avx2_flex_rxd(rx_queue,\n+\t\t\t\trx_pkts + retval, nb_pkts);\n+}\n+\n static inline void\n iavf_vtx1(volatile struct iavf_tx_desc *txdp,\n \t struct rte_mbuf *pkt, uint64_t flags)\n", "prefixes": [ "05/12" ] }