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GET /api/patches/66654/?format=api
{ "id": 66654, "url": "http://patches.dpdk.org/api/patches/66654/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200313152423.23498-3-adamx.dybkowski@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200313152423.23498-3-adamx.dybkowski@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200313152423.23498-3-adamx.dybkowski@intel.com", "date": "2020-03-13T15:24:23", "name": "[v2,2/2] crypto/qat: handle mixed hash-cipher crypto on GEN2 QAT", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "58b0df5d0df573b8fe6fd65b22f242606e2a3071", "submitter": { "id": 1322, "url": "http://patches.dpdk.org/api/people/1322/?format=api", "name": "Dybkowski, AdamX", "email": "adamx.dybkowski@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200313152423.23498-3-adamx.dybkowski@intel.com/mbox/", "series": [ { "id": 8907, "url": "http://patches.dpdk.org/api/series/8907/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8907", "date": "2020-03-13T15:24:21", "name": "crypto/qat: handle mixed hash-cipher crypto on GEN2 QAT", "version": 2, "mbox": "http://patches.dpdk.org/series/8907/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/66654/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/66654/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2BA67A0567;\n\tFri, 13 Mar 2020 16:24:52 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5B6EC1C02D;\n\tFri, 13 Mar 2020 16:24:35 +0100 (CET)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by dpdk.org (Postfix) with ESMTP id ECF221C012\n for <dev@dpdk.org>; Fri, 13 Mar 2020 16:24:32 +0100 (CET)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 13 Mar 2020 08:24:31 -0700", "from adamdybx-mobl.ger.corp.intel.com (HELO\n addy-VirtualBox.ger.corp.intel.com) ([10.104.121.37])\n by fmsmga002.fm.intel.com with ESMTP; 13 Mar 2020 08:24:29 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.70,549,1574150400\"; d=\"scan'208\";a=\"278260334\"", "From": "Adam Dybkowski <adamx.dybkowski@intel.com>", "To": "dev@dpdk.org,\n\tfiona.trahe@intel.com,\n\takhil.goyal@nxp.com", "Cc": "Adam Dybkowski <adamx.dybkowski@intel.com>", "Date": "Fri, 13 Mar 2020 16:24:23 +0100", "Message-Id": "<20200313152423.23498-3-adamx.dybkowski@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200313152423.23498-1-adamx.dybkowski@intel.com>", "References": "<20200312141335.13392-1-adamx.dybkowski@intel.com>\n <20200313152423.23498-1-adamx.dybkowski@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 2/2] crypto/qat: handle mixed hash-cipher\n\tcrypto on GEN2 QAT", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds handling of mixed hash-cipher algorithms\navailable on GEN2 QAT in particular firmware versions.\nAlso the documentation is updated to show the mixed crypto\nalgorithms are supported on QAT GEN2.\n\nSigned-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>\n---\n doc/guides/cryptodevs/qat.rst | 9 ++++-----\n doc/guides/rel_notes/release_20_05.rst | 7 +++++++\n drivers/crypto/qat/qat_sym_pmd.c | 27 ++++++++++++++++++++++++++\n drivers/crypto/qat/qat_sym_pmd.h | 5 +++++\n drivers/crypto/qat/qat_sym_session.c | 17 ++++++++++------\n 5 files changed, 54 insertions(+), 11 deletions(-)", "diff": "diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst\nindex 06985e319..2e0dc1b00 100644\n--- a/doc/guides/cryptodevs/qat.rst\n+++ b/doc/guides/cryptodevs/qat.rst\n@@ -82,18 +82,17 @@ All the usual chains are supported and also some mixed chains:\n +------------------+-----------+-------------+----------+----------+\n | Cipher algorithm | NULL AUTH | SNOW3G UIA2 | ZUC EIA3 | AES CMAC |\n +==================+===========+=============+==========+==========+\n- | NULL CIPHER | Y | 3 | 3 | Y |\n+ | NULL CIPHER | Y | 2&3 | 2&3 | Y |\n +------------------+-----------+-------------+----------+----------+\n- | SNOW3G UEA2 | 3 | Y | 3 | 3 |\n+ | SNOW3G UEA2 | 2&3 | Y | 2&3 | 2&3 |\n +------------------+-----------+-------------+----------+----------+\n- | ZUC EEA3 | 3 | 3 | 2&3 | 3 |\n+ | ZUC EEA3 | 2&3 | 2&3 | 2&3 | 2&3 |\n +------------------+-----------+-------------+----------+----------+\n- | AES CTR | Y | 3 | 3 | Y |\n+ | AES CTR | Y | 2&3 | 2&3 | Y |\n +------------------+-----------+-------------+----------+----------+\n \n * The combinations marked as \"Y\" are supported on all QAT hardware versions.\n * The combinations marked as \"2&3\" are supported on GEN2/GEN3 QAT hardware only.\n-* The combinations marked as \"3\" are supported on GEN3 QAT hardware only.\n \n \n Limitations\ndiff --git a/doc/guides/rel_notes/release_20_05.rst b/doc/guides/rel_notes/release_20_05.rst\nindex 2190eaf85..bdfa64973 100644\n--- a/doc/guides/rel_notes/release_20_05.rst\n+++ b/doc/guides/rel_notes/release_20_05.rst\n@@ -56,6 +56,13 @@ New Features\n Also, make sure to start the actual text at the margin.\n =========================================================\n \n+* **Added handling of mixed crypto algorithms in QAT PMD for GEN2.**\n+\n+ Enabled handling of mixed algorithms in encrypted digest hash-cipher\n+ (generation) and cipher-hash (verification) requests in QAT PMD\n+ when running on GEN2 QAT hardware with particular firmware versions\n+ (GEN3 support was added in DPDK 20.02).\n+\n \n Removed Items\n -------------\ndiff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c\nindex 666ede726..41305ea56 100644\n--- a/drivers/crypto/qat/qat_sym_pmd.c\n+++ b/drivers/crypto/qat/qat_sym_pmd.c\n@@ -14,6 +14,8 @@\n #include \"qat_sym_session.h\"\n #include \"qat_sym_pmd.h\"\n \n+#define MIXED_CRYPTO_MIN_FW_VER 0x04090000\n+\n uint8_t cryptodev_qat_driver_id;\n \n static const struct rte_cryptodev_capabilities qat_gen1_sym_capabilities[] = {\n@@ -187,6 +189,31 @@ static int qat_sym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \t\t\t\tqat_sgl_dst);\n \t}\n \n+\t/* Get fw version from QAT (GEN2), skip if we've got it already */\n+\tif (qp->qat_dev_gen == QAT_GEN2 && !(qat_private->internal_capabilities\n+\t\t\t& QAT_SYM_CAP_VALID)) {\n+\t\tret = qat_cq_get_fw_version(qp);\n+\n+\t\tif (ret < 0) {\n+\t\t\tqat_sym_qp_release(dev, qp_id);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tif (ret != 0)\n+\t\t\tQAT_LOG(DEBUG, \"QAT firmware version: %d.%d.%d\",\n+\t\t\t\t\t(ret >> 24) & 0xff,\n+\t\t\t\t\t(ret >> 16) & 0xff,\n+\t\t\t\t\t(ret >> 8) & 0xff);\n+\t\telse\n+\t\t\tQAT_LOG(DEBUG, \"unknown QAT firmware version\");\n+\n+\t\t/* set capabilities based on the fw version */\n+\t\tqat_private->internal_capabilities = QAT_SYM_CAP_VALID |\n+\t\t\t\t((ret >= MIXED_CRYPTO_MIN_FW_VER) ?\n+\t\t\t\t\t\tQAT_SYM_CAP_MIXED_CRYPTO : 0);\n+\t\tret = 0;\n+\t}\n+\n \treturn ret;\n }\n \ndiff --git a/drivers/crypto/qat/qat_sym_pmd.h b/drivers/crypto/qat/qat_sym_pmd.h\nindex a32c25abc..a5a31e512 100644\n--- a/drivers/crypto/qat/qat_sym_pmd.h\n+++ b/drivers/crypto/qat/qat_sym_pmd.h\n@@ -15,6 +15,10 @@\n /** Intel(R) QAT Symmetric Crypto PMD driver name */\n #define CRYPTODEV_NAME_QAT_SYM_PMD\tcrypto_qat\n \n+/* Internal capabilities */\n+#define QAT_SYM_CAP_MIXED_CRYPTO\t(1 << 0)\n+#define QAT_SYM_CAP_VALID\t\t(1 << 31)\n+\n extern uint8_t cryptodev_qat_driver_id;\n \n /** private data structure for a QAT device.\n@@ -29,6 +33,7 @@ struct qat_sym_dev_private {\n \tconst struct rte_cryptodev_capabilities *qat_dev_capabilities;\n \t/* QAT device symmetric crypto capabilities */\n \tuint16_t min_enq_burst_threshold;\n+\tuint32_t internal_capabilities; /* see flags QAT_SYM_CAP_xxx */\n };\n \n int\ndiff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c\nindex 4359f2f0b..bf6af60aa 100644\n--- a/drivers/crypto/qat/qat_sym_session.c\n+++ b/drivers/crypto/qat/qat_sym_session.c\n@@ -459,18 +459,23 @@ qat_sym_session_set_ext_hash_flags(struct qat_sym_session *session,\n }\n \n static void\n-qat_sym_session_handle_mixed(struct qat_sym_session *session)\n+qat_sym_session_handle_mixed(const struct rte_cryptodev *dev,\n+\t\tstruct qat_sym_session *session)\n {\n+\tconst struct qat_sym_dev_private *qat_private = dev->data->dev_private;\n+\tenum qat_device_gen min_dev_gen = (qat_private->internal_capabilities &\n+\t\t\tQAT_SYM_CAP_MIXED_CRYPTO) ? QAT_GEN2 : QAT_GEN3;\n+\n \tif (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 &&\n \t\t\tsession->qat_cipher_alg !=\n \t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {\n-\t\tsession->min_qat_dev_gen = QAT_GEN3;\n+\t\tsession->min_qat_dev_gen = min_dev_gen;\n \t\tqat_sym_session_set_ext_hash_flags(session,\n \t\t\t1 << ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS);\n \t} else if (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 &&\n \t\t\tsession->qat_cipher_alg !=\n \t\t\tICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {\n-\t\tsession->min_qat_dev_gen = QAT_GEN3;\n+\t\tsession->min_qat_dev_gen = min_dev_gen;\n \t\tqat_sym_session_set_ext_hash_flags(session,\n \t\t\t1 << ICP_QAT_FW_AUTH_HDR_FLAG_SNOW3G_UIA2_BITPOS);\n \t} else if ((session->aes_cmac ||\n@@ -479,7 +484,7 @@ qat_sym_session_handle_mixed(struct qat_sym_session *session)\n \t\t\tICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||\n \t\t\tsession->qat_cipher_alg ==\n \t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)) {\n-\t\tsession->min_qat_dev_gen = QAT_GEN3;\n+\t\tsession->min_qat_dev_gen = min_dev_gen;\n \t\tqat_sym_session_set_ext_hash_flags(session, 0);\n \t}\n }\n@@ -532,7 +537,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \t\t\tif (ret < 0)\n \t\t\t\treturn ret;\n \t\t\t/* Special handling of mixed hash+cipher algorithms */\n-\t\t\tqat_sym_session_handle_mixed(session);\n+\t\t\tqat_sym_session_handle_mixed(dev, session);\n \t\t}\n \t\tbreak;\n \tcase ICP_QAT_FW_LA_CMD_HASH_CIPHER:\n@@ -551,7 +556,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \t\t\tif (ret < 0)\n \t\t\t\treturn ret;\n \t\t\t/* Special handling of mixed hash+cipher algorithms */\n-\t\t\tqat_sym_session_handle_mixed(session);\n+\t\t\tqat_sym_session_handle_mixed(dev, session);\n \t\t}\n \t\tbreak;\n \tcase ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:\n", "prefixes": [ "v2", "2/2" ] }