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GET /api/patches/66586/?format=api
{ "id": 66586, "url": "http://patches.dpdk.org/api/patches/66586/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200312111907.31555-12-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200312111907.31555-12-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200312111907.31555-12-ndabilpuram@marvell.com", "date": "2020-03-12T11:19:07", "name": "[11/11] net/octeontx2: add tm capability callbacks", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "aa614d94bb0daae75ed1d226537d3875cadd301b", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200312111907.31555-12-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 8894, "url": "http://patches.dpdk.org/api/series/8894/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8894", "date": "2020-03-12T11:18:56", "name": "net/octeontx2: add traffic manager support", "version": 1, "mbox": "http://patches.dpdk.org/series/8894/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/66586/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/66586/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 959D3A056B;\n\tThu, 12 Mar 2020 12:22:09 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D892B1C0D2;\n\tThu, 12 Mar 2020 12:19:44 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 7BB781C0C2\n for <dev@dpdk.org>; Thu, 12 Mar 2020 12:19:42 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n 02CBG0KY017747 for <dev@dpdk.org>; Thu, 12 Mar 2020 04:19:42 -0700", "from sc-exch04.marvell.com ([199.233.58.184])\n by mx0b-0016f401.pphosted.com with ESMTP id 2yqfggs6g4-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 12 Mar 2020 04:19:41 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH04.marvell.com\n (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Mar\n 2020 04:19:39 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n (10.93.176.83) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 12 Mar 2020 04:19:39 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 45D3E3F703F;\n Thu, 12 Mar 2020 04:19:38 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0818; bh=W48c9oH6ehI9ukQn3x9faEAEzN4aKHpNn74vm6qTSmA=;\n b=n4ASozH8pMUU0q8xHFqiyb40PGdtcXARu62NTgp/+6HtiXjgMoGwZ9t55YqdRgLHmWPO\n BSHLeaZg/Y3SsrUytR61/hIQCw9mLZgMDg/ZKnvd/tBQ7vugPXrusVz+crz3afy7Wijp\n IfoNx7JAsuFd1RizlaMx7OqODpfYHpzfHCopp/6D/KQSwUcizeu8F/PSY3iKQ93bh4Lp\n M3tLBsKBdGuRkmSugqZqeUpLxZ155BmqS3ELvDQaLe2t4WtiDV/X4F0uUjcAutpwUU5B\n 5FtktCtcTdWRyfRwwWngCYOwg1FqBVT1NJ8tUDwKp/t7+nsc06F2FC+OYSny99Rpf+fv Pw==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n <ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>", "CC": "Krzysztof Kanas <kkanas@marvell.com>, <dev@dpdk.org>", "Date": "Thu, 12 Mar 2020 16:49:07 +0530", "Message-ID": "<20200312111907.31555-12-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20200312111907.31555-1-ndabilpuram@marvell.com>", "References": "<20200312111907.31555-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572\n definitions=2020-03-12_03:2020-03-11,\n 2020-03-12 signatures=0", "Subject": "[dpdk-dev] [PATCH 11/11] net/octeontx2: add tm capability callbacks", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Krzysztof Kanas <kkanas@marvell.com>\n\nAdd Traffic Management capability callbacks to provide\nglobal, level and node capabilities. This patch also\nadds documentation on Traffic Management Support.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Krzysztof Kanas <kkanas@marvell.com>\n---\n doc/guides/nics/features/octeontx2.ini | 1 +\n doc/guides/nics/octeontx2.rst | 15 +++\n drivers/net/octeontx2/otx2_ethdev.c | 1 +\n drivers/net/octeontx2/otx2_tm.c | 232 +++++++++++++++++++++++++++++++++\n drivers/net/octeontx2/otx2_tm.h | 1 +\n 5 files changed, 250 insertions(+)", "diff": "diff --git a/doc/guides/nics/features/octeontx2.ini b/doc/guides/nics/features/octeontx2.ini\nindex 473fe56..fb13517 100644\n--- a/doc/guides/nics/features/octeontx2.ini\n+++ b/doc/guides/nics/features/octeontx2.ini\n@@ -31,6 +31,7 @@ Inline protocol = Y\n VLAN filter = Y\n Flow control = Y\n Flow API = Y\n+Rate limitation = Y\n Jumbo frame = Y\n Scattered Rx = Y\n VLAN offload = Y\ndiff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst\nindex 60187ec..6b885d6 100644\n--- a/doc/guides/nics/octeontx2.rst\n+++ b/doc/guides/nics/octeontx2.rst\n@@ -39,6 +39,7 @@ Features of the OCTEON TX2 Ethdev PMD are:\n - HW offloaded `ethdev Rx queue` to `eventdev event queue` packet injection\n - Support Rx interrupt\n - Inline IPsec processing support\n+- :ref:`Traffic Management API <tmapi>`\n \n Prerequisites\n -------------\n@@ -213,6 +214,20 @@ Runtime Config Options\n parameters to all the PCIe devices if application requires to configure on\n all the ethdev ports.\n \n+Traffic Management API\n+----------------------\n+\n+OCTEON TX2 PMD supports generic DPDK Traffic Management API which allows to\n+configure the following features:\n+\n+1. Hierarchical scheduling\n+2. Single rate - two color, Two rate - three color shaping\n+\n+Both DWRR and Static Priority(SP) hierarchial scheduling is supported.\n+Every parent can have atmost 10 SP Children and unlimited DWRR children.\n+Both PF & VF supports traffic management API with PF supporting 6 levels\n+and VF supporting 5 levels of topology.\n+\n Limitations\n -----------\n \ndiff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex 78b7f3a..599a14c 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -2026,6 +2026,7 @@ static const struct eth_dev_ops otx2_eth_dev_ops = {\n \t.link_update = otx2_nix_link_update,\n \t.tx_queue_setup = otx2_nix_tx_queue_setup,\n \t.tx_queue_release = otx2_nix_tx_queue_release,\n+\t.tm_ops_get = otx2_nix_tm_ops_get,\n \t.rx_queue_setup = otx2_nix_rx_queue_setup,\n \t.rx_queue_release = otx2_nix_rx_queue_release,\n \t.dev_start = otx2_nix_dev_start,\ndiff --git a/drivers/net/octeontx2/otx2_tm.c b/drivers/net/octeontx2/otx2_tm.c\nindex bafb9aa..1ccb441 100644\n--- a/drivers/net/octeontx2/otx2_tm.c\n+++ b/drivers/net/octeontx2/otx2_tm.c\n@@ -1825,7 +1825,217 @@ nix_tm_node_type_get(struct rte_eth_dev *eth_dev, uint32_t node_id,\n \t\t*is_leaf = true;\n \telse\n \t\t*is_leaf = false;\n+\treturn 0;\n+}\n \n+static int\n+nix_tm_capabilities_get(struct rte_eth_dev *eth_dev,\n+\t\t\tstruct rte_tm_capabilities *cap,\n+\t\t\tstruct rte_tm_error *error)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tint rc, max_nr_nodes = 0, i;\n+\tstruct free_rsrcs_rsp *rsp;\n+\n+\tmemset(cap, 0, sizeof(*cap));\n+\n+\totx2_mbox_alloc_msg_free_rsrc_cnt(mbox);\n+\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc) {\n+\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n+\t\terror->message = \"unexpected fatal error\";\n+\t\treturn rc;\n+\t}\n+\n+\tfor (i = 0; i < NIX_TXSCH_LVL_TL1; i++)\n+\t\tmax_nr_nodes += rsp->schq[i];\n+\n+\tcap->n_nodes_max = max_nr_nodes + dev->tm_leaf_cnt;\n+\t/* TL1 level is reserved for PF */\n+\tcap->n_levels_max = nix_tm_have_tl1_access(dev) ?\n+\t\t\t\tOTX2_TM_LVL_MAX : OTX2_TM_LVL_MAX - 1;\n+\tcap->non_leaf_nodes_identical = 1;\n+\tcap->leaf_nodes_identical = 1;\n+\n+\t/* Shaper Capabilities */\n+\tcap->shaper_private_n_max = max_nr_nodes;\n+\tcap->shaper_n_max = max_nr_nodes;\n+\tcap->shaper_private_dual_rate_n_max = max_nr_nodes;\n+\tcap->shaper_private_rate_min = MIN_SHAPER_RATE / 8;\n+\tcap->shaper_private_rate_max = MAX_SHAPER_RATE / 8;\n+\tcap->shaper_pkt_length_adjust_min = 0;\n+\tcap->shaper_pkt_length_adjust_max = 0;\n+\n+\t/* Schedule Capabilites */\n+\tcap->sched_n_children_max = rsp->schq[NIX_TXSCH_LVL_MDQ];\n+\tcap->sched_sp_n_priorities_max = TXSCH_TLX_SP_PRIO_MAX;\n+\tcap->sched_wfq_n_children_per_group_max = cap->sched_n_children_max;\n+\tcap->sched_wfq_n_groups_max = 1;\n+\tcap->sched_wfq_weight_max = MAX_SCHED_WEIGHT;\n+\n+\tcap->dynamic_update_mask =\n+\t\tRTE_TM_UPDATE_NODE_PARENT_KEEP_LEVEL |\n+\t\tRTE_TM_UPDATE_NODE_SUSPEND_RESUME;\n+\tcap->stats_mask =\n+\t\tRTE_TM_STATS_N_PKTS |\n+\t\tRTE_TM_STATS_N_BYTES |\n+\t\tRTE_TM_STATS_N_PKTS_RED_DROPPED |\n+\t\tRTE_TM_STATS_N_BYTES_RED_DROPPED;\n+\n+\tfor (i = 0; i < RTE_COLORS; i++) {\n+\t\tcap->mark_vlan_dei_supported[i] = false;\n+\t\tcap->mark_ip_ecn_tcp_supported[i] = false;\n+\t\tcap->mark_ip_dscp_supported[i] = false;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+nix_tm_level_capabilities_get(struct rte_eth_dev *eth_dev, uint32_t lvl,\n+\t\t\t struct rte_tm_level_capabilities *cap,\n+\t\t\t struct rte_tm_error *error)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct free_rsrcs_rsp *rsp;\n+\tuint16_t hw_lvl;\n+\tint rc;\n+\n+\tmemset(cap, 0, sizeof(*cap));\n+\n+\totx2_mbox_alloc_msg_free_rsrc_cnt(mbox);\n+\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc) {\n+\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n+\t\terror->message = \"unexpected fatal error\";\n+\t\treturn rc;\n+\t}\n+\n+\thw_lvl = nix_tm_lvl2nix(dev, lvl);\n+\n+\tif (nix_tm_is_leaf(dev, lvl)) {\n+\t\t/* Leaf */\n+\t\tcap->n_nodes_max = dev->tm_leaf_cnt;\n+\t\tcap->n_nodes_leaf_max = dev->tm_leaf_cnt;\n+\t\tcap->leaf_nodes_identical = 1;\n+\t\tcap->leaf.stats_mask =\n+\t\t\tRTE_TM_STATS_N_PKTS |\n+\t\t\tRTE_TM_STATS_N_BYTES;\n+\n+\t} else if (lvl == OTX2_TM_LVL_ROOT) {\n+\t\t/* Root node, aka TL2(vf)/TL1(pf) */\n+\t\tcap->n_nodes_max = 1;\n+\t\tcap->n_nodes_nonleaf_max = 1;\n+\t\tcap->non_leaf_nodes_identical = 1;\n+\n+\t\tcap->nonleaf.shaper_private_supported = true;\n+\t\tcap->nonleaf.shaper_private_dual_rate_supported =\n+\t\t\tnix_tm_have_tl1_access(dev) ? false : true;\n+\t\tcap->nonleaf.shaper_private_rate_min = MIN_SHAPER_RATE / 8;\n+\t\tcap->nonleaf.shaper_private_rate_max = MAX_SHAPER_RATE / 8;\n+\n+\t\tcap->nonleaf.sched_n_children_max = rsp->schq[hw_lvl - 1];\n+\t\tcap->nonleaf.sched_sp_n_priorities_max =\n+\t\t\t\t\tnix_max_prio(dev, hw_lvl) + 1;\n+\t\tcap->nonleaf.sched_wfq_n_groups_max = 1;\n+\t\tcap->nonleaf.sched_wfq_weight_max = MAX_SCHED_WEIGHT;\n+\n+\t\tif (nix_tm_have_tl1_access(dev))\n+\t\t\tcap->nonleaf.stats_mask =\n+\t\t\t\tRTE_TM_STATS_N_PKTS_RED_DROPPED |\n+\t\t\t\tRTE_TM_STATS_N_BYTES_RED_DROPPED;\n+\t} else if ((lvl < OTX2_TM_LVL_MAX) &&\n+\t\t (hw_lvl < NIX_TXSCH_LVL_CNT)) {\n+\t\t/* TL2, TL3, TL4, MDQ */\n+\t\tcap->n_nodes_max = rsp->schq[hw_lvl];\n+\t\tcap->n_nodes_nonleaf_max = cap->n_nodes_max;\n+\t\tcap->non_leaf_nodes_identical = 1;\n+\n+\t\tcap->nonleaf.shaper_private_supported = true;\n+\t\tcap->nonleaf.shaper_private_dual_rate_supported = true;\n+\t\tcap->nonleaf.shaper_private_rate_min = MIN_SHAPER_RATE / 8;\n+\t\tcap->nonleaf.shaper_private_rate_max = MAX_SHAPER_RATE / 8;\n+\n+\t\t/* MDQ doesn't support Strict Priority */\n+\t\tif (hw_lvl == NIX_TXSCH_LVL_MDQ)\n+\t\t\tcap->nonleaf.sched_n_children_max = dev->tm_leaf_cnt;\n+\t\telse\n+\t\t\tcap->nonleaf.sched_n_children_max =\n+\t\t\t\trsp->schq[hw_lvl - 1];\n+\t\tcap->nonleaf.sched_sp_n_priorities_max =\n+\t\t\tnix_max_prio(dev, hw_lvl) + 1;\n+\t\tcap->nonleaf.sched_wfq_n_groups_max = 1;\n+\t\tcap->nonleaf.sched_wfq_weight_max = MAX_SCHED_WEIGHT;\n+\t} else {\n+\t\t/* unsupported level */\n+\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n+\t\treturn rc;\n+\t}\n+\treturn 0;\n+}\n+\n+static int\n+nix_tm_node_capabilities_get(struct rte_eth_dev *eth_dev, uint32_t node_id,\n+\t\t\t struct rte_tm_node_capabilities *cap,\n+\t\t\t struct rte_tm_error *error)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct otx2_nix_tm_node *tm_node;\n+\tstruct free_rsrcs_rsp *rsp;\n+\tint rc, hw_lvl, lvl;\n+\n+\tmemset(cap, 0, sizeof(*cap));\n+\n+\ttm_node = nix_tm_node_search(dev, node_id, true);\n+\tif (!tm_node) {\n+\t\terror->type = RTE_TM_ERROR_TYPE_NODE_ID;\n+\t\terror->message = \"no such node\";\n+\t\treturn -EINVAL;\n+\t}\n+\n+\thw_lvl = tm_node->hw_lvl;\n+\tlvl = tm_node->lvl;\n+\n+\t/* Leaf node */\n+\tif (nix_tm_is_leaf(dev, lvl)) {\n+\t\tcap->stats_mask = RTE_TM_STATS_N_PKTS |\n+\t\t\t\t\tRTE_TM_STATS_N_BYTES;\n+\t\treturn 0;\n+\t}\n+\n+\totx2_mbox_alloc_msg_free_rsrc_cnt(mbox);\n+\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc) {\n+\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n+\t\terror->message = \"unexpected fatal error\";\n+\t\treturn rc;\n+\t}\n+\n+\t/* Non Leaf Shaper */\n+\tcap->shaper_private_supported = true;\n+\tcap->shaper_private_dual_rate_supported =\n+\t\t(hw_lvl == NIX_TXSCH_LVL_TL1) ? false : true;\n+\tcap->shaper_private_rate_min = MIN_SHAPER_RATE / 8;\n+\tcap->shaper_private_rate_max = MAX_SHAPER_RATE / 8;\n+\n+\t/* Non Leaf Scheduler */\n+\tif (hw_lvl == NIX_TXSCH_LVL_MDQ)\n+\t\tcap->nonleaf.sched_n_children_max = dev->tm_leaf_cnt;\n+\telse\n+\t\tcap->nonleaf.sched_n_children_max = rsp->schq[hw_lvl - 1];\n+\n+\tcap->nonleaf.sched_sp_n_priorities_max = nix_max_prio(dev, hw_lvl) + 1;\n+\tcap->nonleaf.sched_wfq_n_children_per_group_max =\n+\t\tcap->nonleaf.sched_n_children_max;\n+\tcap->nonleaf.sched_wfq_n_groups_max = 1;\n+\tcap->nonleaf.sched_wfq_weight_max = MAX_SCHED_WEIGHT;\n+\n+\tif (hw_lvl == NIX_TXSCH_LVL_TL1)\n+\t\tcap->stats_mask = RTE_TM_STATS_N_PKTS_RED_DROPPED |\n+\t\t\tRTE_TM_STATS_N_BYTES_RED_DROPPED;\n \treturn 0;\n }\n \n@@ -2505,6 +2715,10 @@ nix_tm_node_stats_read(struct rte_eth_dev *eth_dev, uint32_t node_id,\n const struct rte_tm_ops otx2_tm_ops = {\n \t.node_type_get = nix_tm_node_type_get,\n \n+\t.capabilities_get = nix_tm_capabilities_get,\n+\t.level_capabilities_get = nix_tm_level_capabilities_get,\n+\t.node_capabilities_get = nix_tm_node_capabilities_get,\n+\n \t.shaper_profile_add = nix_tm_shaper_profile_add,\n \t.shaper_profile_delete = nix_tm_shaper_profile_delete,\n \n@@ -2901,6 +3115,24 @@ otx2_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev,\n }\n \n int\n+otx2_nix_tm_ops_get(struct rte_eth_dev *eth_dev, void *arg)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\n+\tif (!arg)\n+\t\treturn -EINVAL;\n+\n+\t/* Check for supported revisions */\n+\tif (otx2_dev_is_95xx_Ax(dev) ||\n+\t otx2_dev_is_96xx_Ax(dev))\n+\t\treturn -EINVAL;\n+\n+\t*(const void **)arg = &otx2_tm_ops;\n+\n+\treturn 0;\n+}\n+\n+int\n otx2_nix_tm_fini(struct rte_eth_dev *eth_dev)\n {\n \tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\ndiff --git a/drivers/net/octeontx2/otx2_tm.h b/drivers/net/octeontx2/otx2_tm.h\nindex 7b1672e..9675182 100644\n--- a/drivers/net/octeontx2/otx2_tm.h\n+++ b/drivers/net/octeontx2/otx2_tm.h\n@@ -19,6 +19,7 @@ struct otx2_eth_dev;\n void otx2_nix_tm_conf_init(struct rte_eth_dev *eth_dev);\n int otx2_nix_tm_init_default(struct rte_eth_dev *eth_dev);\n int otx2_nix_tm_fini(struct rte_eth_dev *eth_dev);\n+int otx2_nix_tm_ops_get(struct rte_eth_dev *eth_dev, void *ops);\n int otx2_nix_tm_get_leaf_data(struct otx2_eth_dev *dev, uint16_t sq,\n \t\t\t uint32_t *rr_quantum, uint16_t *smq);\n int otx2_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev,\n", "prefixes": [ "11/11" ] }