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{
    "id": 66577,
    "url": "http://patches.dpdk.org/api/patches/66577/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200312111907.31555-3-ndabilpuram@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20200312111907.31555-3-ndabilpuram@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20200312111907.31555-3-ndabilpuram@marvell.com",
    "date": "2020-03-12T11:18:58",
    "name": "[02/11] net/octeontx2: restructure tm helper functions",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "e9c9bda2dfa9770adda4cf5c992470b5ed59cf34",
    "submitter": {
        "id": 1202,
        "url": "http://patches.dpdk.org/api/people/1202/?format=api",
        "name": "Nithin Dabilpuram",
        "email": "ndabilpuram@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200312111907.31555-3-ndabilpuram@marvell.com/mbox/",
    "series": [
        {
            "id": 8894,
            "url": "http://patches.dpdk.org/api/series/8894/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8894",
            "date": "2020-03-12T11:18:56",
            "name": "net/octeontx2: add traffic manager support",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/8894/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/66577/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/66577/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
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        "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>",
        "To": "Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n <ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>",
        "CC": "Krzysztof Kanas <kkanas@marvell.com>, <dev@dpdk.org>",
        "Date": "Thu, 12 Mar 2020 16:48:58 +0530",
        "Message-ID": "<20200312111907.31555-3-ndabilpuram@marvell.com>",
        "X-Mailer": "git-send-email 2.8.4",
        "In-Reply-To": "<20200312111907.31555-1-ndabilpuram@marvell.com>",
        "References": "<20200312111907.31555-1-ndabilpuram@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
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        "Subject": "[dpdk-dev] [PATCH 02/11] net/octeontx2: restructure tm helper\n\tfunctions",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Restructure traffic manager helper function by splitting to\nmultiple sets of register configurations like shaping, scheduling\nand topology config.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Krzysztof Kanas <kkanas@marvell.com>\n---\n drivers/net/octeontx2/otx2_tm.c | 689 ++++++++++++++++++++++------------------\n drivers/net/octeontx2/otx2_tm.h |  85 ++---\n 2 files changed, 417 insertions(+), 357 deletions(-)",
    "diff": "diff --git a/drivers/net/octeontx2/otx2_tm.c b/drivers/net/octeontx2/otx2_tm.c\nindex 2364e03..057297a 100644\n--- a/drivers/net/octeontx2/otx2_tm.c\n+++ b/drivers/net/octeontx2/otx2_tm.c\n@@ -94,52 +94,50 @@ nix_tm_shaper_profile_search(struct otx2_eth_dev *dev, uint32_t shaper_id)\n }\n \n static inline uint64_t\n-shaper_rate_to_nix(uint64_t cclk_hz, uint64_t cclk_ticks,\n-\t\t   uint64_t value, uint64_t *exponent_p,\n+shaper_rate_to_nix(uint64_t value, uint64_t *exponent_p,\n \t\t   uint64_t *mantissa_p, uint64_t *div_exp_p)\n {\n \tuint64_t div_exp, exponent, mantissa;\n \n \t/* Boundary checks */\n-\tif (value < MIN_SHAPER_RATE(cclk_hz, cclk_ticks) ||\n-\t    value > MAX_SHAPER_RATE(cclk_hz, cclk_ticks))\n+\tif (value < MIN_SHAPER_RATE ||\n+\t    value > MAX_SHAPER_RATE)\n \t\treturn 0;\n \n-\tif (value <= SHAPER_RATE(cclk_hz, cclk_ticks, 0, 0, 0)) {\n+\tif (value <= SHAPER_RATE(0, 0, 0)) {\n \t\t/* Calculate rate div_exp and mantissa using\n \t\t * the following formula:\n \t\t *\n-\t\t * value = (cclk_hz * (256 + mantissa)\n-\t\t *              / ((cclk_ticks << div_exp) * 256)\n+\t\t * value = (2E6 * (256 + mantissa)\n+\t\t *              / ((1 << div_exp) * 256))\n \t\t */\n \t\tdiv_exp = 0;\n \t\texponent = 0;\n \t\tmantissa = MAX_RATE_MANTISSA;\n \n-\t\twhile (value < (cclk_hz / (cclk_ticks << div_exp)))\n+\t\twhile (value < (NIX_SHAPER_RATE_CONST / (1 << div_exp)))\n \t\t\tdiv_exp += 1;\n \n \t\twhile (value <\n-\t\t       ((cclk_hz * (256 + mantissa)) /\n-\t\t\t((cclk_ticks << div_exp) * 256)))\n+\t\t       ((NIX_SHAPER_RATE_CONST * (256 + mantissa)) /\n+\t\t\t((1 << div_exp) * 256)))\n \t\t\tmantissa -= 1;\n \t} else {\n \t\t/* Calculate rate exponent and mantissa using\n \t\t * the following formula:\n \t\t *\n-\t\t * value = (cclk_hz * ((256 + mantissa) << exponent)\n-\t\t *              / (cclk_ticks * 256)\n+\t\t * value = (2E6 * ((256 + mantissa) << exponent)) / 256\n \t\t *\n \t\t */\n \t\tdiv_exp = 0;\n \t\texponent = MAX_RATE_EXPONENT;\n \t\tmantissa = MAX_RATE_MANTISSA;\n \n-\t\twhile (value < (cclk_hz * (1 << exponent)) / cclk_ticks)\n+\t\twhile (value < (NIX_SHAPER_RATE_CONST * (1 << exponent)))\n \t\t\texponent -= 1;\n \n-\t\twhile (value < (cclk_hz * ((256 + mantissa) << exponent)) /\n-\t\t       (cclk_ticks * 256))\n+\t\twhile (value < ((NIX_SHAPER_RATE_CONST *\n+\t\t\t\t((256 + mantissa) << exponent)) / 256))\n \t\t\tmantissa -= 1;\n \t}\n \n@@ -155,20 +153,7 @@ shaper_rate_to_nix(uint64_t cclk_hz, uint64_t cclk_ticks,\n \t\t*mantissa_p = mantissa;\n \n \t/* Calculate real rate value */\n-\treturn SHAPER_RATE(cclk_hz, cclk_ticks, exponent, mantissa, div_exp);\n-}\n-\n-static inline uint64_t\n-lx_shaper_rate_to_nix(uint64_t cclk_hz, uint32_t hw_lvl,\n-\t\t      uint64_t value, uint64_t *exponent,\n-\t\t      uint64_t *mantissa, uint64_t *div_exp)\n-{\n-\tif (hw_lvl == NIX_TXSCH_LVL_TL1)\n-\t\treturn shaper_rate_to_nix(cclk_hz, L1_TIME_WHEEL_CCLK_TICKS,\n-\t\t\t\t\t  value, exponent, mantissa, div_exp);\n-\telse\n-\t\treturn shaper_rate_to_nix(cclk_hz, LX_TIME_WHEEL_CCLK_TICKS,\n-\t\t\t\t\t  value, exponent, mantissa, div_exp);\n+\treturn SHAPER_RATE(exponent, mantissa, div_exp);\n }\n \n static inline uint64_t\n@@ -207,329 +192,394 @@ shaper_burst_to_nix(uint64_t value, uint64_t *exponent_p,\n \treturn SHAPER_BURST(exponent, mantissa);\n }\n \n-static int\n-configure_shaper_cir_pir_reg(struct otx2_eth_dev *dev,\n-\t\t\t     struct otx2_nix_tm_node *tm_node,\n-\t\t\t     struct shaper_params *cir,\n-\t\t\t     struct shaper_params *pir)\n-{\n-\tuint32_t shaper_profile_id = RTE_TM_SHAPER_PROFILE_ID_NONE;\n-\tstruct otx2_nix_tm_shaper_profile *shaper_profile = NULL;\n-\tstruct rte_tm_shaper_params *param;\n-\n-\tshaper_profile_id = tm_node->params.shaper_profile_id;\n-\n-\tshaper_profile = nix_tm_shaper_profile_search(dev, shaper_profile_id);\n-\tif (shaper_profile) {\n-\t\tparam = &shaper_profile->profile;\n-\t\t/* Calculate CIR exponent and mantissa */\n-\t\tif (param->committed.rate)\n-\t\t\tcir->rate = lx_shaper_rate_to_nix(CCLK_HZ,\n-\t\t\t\t\t\t\t  tm_node->hw_lvl_id,\n-\t\t\t\t\t\t\t  param->committed.rate,\n-\t\t\t\t\t\t\t  &cir->exponent,\n-\t\t\t\t\t\t\t  &cir->mantissa,\n-\t\t\t\t\t\t\t  &cir->div_exp);\n-\n-\t\t/* Calculate PIR exponent and mantissa */\n-\t\tif (param->peak.rate)\n-\t\t\tpir->rate = lx_shaper_rate_to_nix(CCLK_HZ,\n-\t\t\t\t\t\t\t  tm_node->hw_lvl_id,\n-\t\t\t\t\t\t\t  param->peak.rate,\n-\t\t\t\t\t\t\t  &pir->exponent,\n-\t\t\t\t\t\t\t  &pir->mantissa,\n-\t\t\t\t\t\t\t  &pir->div_exp);\n-\n-\t\t/* Calculate CIR burst exponent and mantissa */\n-\t\tif (param->committed.size)\n-\t\t\tcir->burst = shaper_burst_to_nix(param->committed.size,\n-\t\t\t\t\t\t\t &cir->burst_exponent,\n-\t\t\t\t\t\t\t &cir->burst_mantissa);\n-\n-\t\t/* Calculate PIR burst exponent and mantissa */\n-\t\tif (param->peak.size)\n-\t\t\tpir->burst = shaper_burst_to_nix(param->peak.size,\n-\t\t\t\t\t\t\t &pir->burst_exponent,\n-\t\t\t\t\t\t\t &pir->burst_mantissa);\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-send_tm_reqval(struct otx2_mbox *mbox, struct nix_txschq_config *req)\n+static void\n+shaper_config_to_nix(struct otx2_nix_tm_shaper_profile *profile,\n+\t\t     struct shaper_params *cir,\n+\t\t     struct shaper_params *pir)\n {\n-\tint rc;\n-\n-\tif (req->num_regs > MAX_REGS_PER_MBOX_MSG)\n-\t\treturn -ERANGE;\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\treq->num_regs = 0;\n-\treturn 0;\n+\tstruct rte_tm_shaper_params *param = &profile->params;\n+\n+\tif (!profile)\n+\t\treturn;\n+\n+\t/* Calculate CIR exponent and mantissa */\n+\tif (param->committed.rate)\n+\t\tcir->rate = shaper_rate_to_nix(param->committed.rate,\n+\t\t\t\t\t       &cir->exponent,\n+\t\t\t\t\t       &cir->mantissa,\n+\t\t\t\t\t       &cir->div_exp);\n+\n+\t/* Calculate PIR exponent and mantissa */\n+\tif (param->peak.rate)\n+\t\tpir->rate = shaper_rate_to_nix(param->peak.rate,\n+\t\t\t\t\t       &pir->exponent,\n+\t\t\t\t\t       &pir->mantissa,\n+\t\t\t\t\t       &pir->div_exp);\n+\n+\t/* Calculate CIR burst exponent and mantissa */\n+\tif (param->committed.size)\n+\t\tcir->burst = shaper_burst_to_nix(param->committed.size,\n+\t\t\t\t\t\t &cir->burst_exponent,\n+\t\t\t\t\t\t &cir->burst_mantissa);\n+\n+\t/* Calculate PIR burst exponent and mantissa */\n+\tif (param->peak.size)\n+\t\tpir->burst = shaper_burst_to_nix(param->peak.size,\n+\t\t\t\t\t\t &pir->burst_exponent,\n+\t\t\t\t\t\t &pir->burst_mantissa);\n }\n \n static int\n-populate_tm_registers(struct otx2_eth_dev *dev,\n-\t\t      struct otx2_nix_tm_node *tm_node)\n+populate_tm_tl1_default(struct otx2_eth_dev *dev, uint32_t schq)\n {\n-\tuint64_t strict_schedul_prio, rr_prio;\n \tstruct otx2_mbox *mbox = dev->mbox;\n-\tvolatile uint64_t *reg, *regval;\n-\tuint64_t parent = 0, child = 0;\n-\tstruct shaper_params cir, pir;\n \tstruct nix_txschq_config *req;\n+\n+\t/*\n+\t * Default config for TL1.\n+\t * For VF this is always ignored.\n+\t */\n+\n+\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\treq->lvl = NIX_TXSCH_LVL_TL1;\n+\n+\t/* Set DWRR quantum */\n+\treq->reg[0] = NIX_AF_TL1X_SCHEDULE(schq);\n+\treq->regval[0] = TXSCH_TL1_DFLT_RR_QTM;\n+\treq->num_regs++;\n+\n+\treq->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq);\n+\treq->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1);\n+\treq->num_regs++;\n+\n+\treq->reg[2] = NIX_AF_TL1X_CIR(schq);\n+\treq->regval[2] = 0;\n+\treq->num_regs++;\n+\n+\treturn otx2_mbox_process(mbox);\n+}\n+\n+static uint8_t\n+prepare_tm_sched_reg(struct otx2_eth_dev *dev,\n+\t\t     struct otx2_nix_tm_node *tm_node,\n+\t\t     volatile uint64_t *reg, volatile uint64_t *regval)\n+{\n+\tuint64_t strict_prio = tm_node->priority;\n+\tuint32_t hw_lvl = tm_node->hw_lvl;\n+\tuint32_t schq = tm_node->hw_id;\n \tuint64_t rr_quantum;\n-\tuint32_t hw_lvl;\n-\tuint32_t schq;\n-\tint rc;\n+\tuint8_t k = 0;\n+\n+\trr_quantum = NIX_TM_WEIGHT_TO_RR_QUANTUM(tm_node->weight);\n+\n+\t/* For children to root, strict prio is default if either\n+\t * device root is TL2 or TL1 Static Priority is disabled.\n+\t */\n+\tif (hw_lvl == NIX_TXSCH_LVL_TL2 &&\n+\t    (dev->otx2_tm_root_lvl == NIX_TXSCH_LVL_TL2 ||\n+\t     dev->tm_flags & NIX_TM_TL1_NO_SP))\n+\t\tstrict_prio = TXSCH_TL1_DFLT_RR_PRIO;\n+\n+\totx2_tm_dbg(\"Schedule config node %s(%u) lvl %u id %u, \"\n+\t\t     \"prio 0x%\" PRIx64 \", rr_quantum 0x%\" PRIx64 \" (%p)\",\n+\t\t     nix_hwlvl2str(tm_node->hw_lvl), schq, tm_node->lvl,\n+\t\t     tm_node->id, strict_prio, rr_quantum, tm_node);\n+\n+\tswitch (hw_lvl) {\n+\tcase NIX_TXSCH_LVL_SMQ:\n+\t\treg[k] = NIX_AF_MDQX_SCHEDULE(schq);\n+\t\tregval[k] = (strict_prio << 24) | rr_quantum;\n+\t\tk++;\n+\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL4:\n+\t\treg[k] = NIX_AF_TL4X_SCHEDULE(schq);\n+\t\tregval[k] = (strict_prio << 24) | rr_quantum;\n+\t\tk++;\n+\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL3:\n+\t\treg[k] = NIX_AF_TL3X_SCHEDULE(schq);\n+\t\tregval[k] = (strict_prio << 24) | rr_quantum;\n+\t\tk++;\n+\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL2:\n+\t\treg[k] = NIX_AF_TL2X_SCHEDULE(schq);\n+\t\tregval[k] = (strict_prio << 24) | rr_quantum;\n+\t\tk++;\n+\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL1:\n+\t\treg[k] = NIX_AF_TL1X_SCHEDULE(schq);\n+\t\tregval[k] = rr_quantum;\n+\t\tk++;\n+\n+\t\tbreak;\n+\t}\n+\n+\treturn k;\n+}\n+\n+static uint8_t\n+prepare_tm_shaper_reg(struct otx2_nix_tm_node *tm_node,\n+\t\t      struct otx2_nix_tm_shaper_profile *profile,\n+\t\t      volatile uint64_t *reg, volatile uint64_t *regval)\n+{\n+\tstruct shaper_params cir, pir;\n+\tuint32_t schq = tm_node->hw_id;\n+\tuint8_t k = 0;\n \n \tmemset(&cir, 0, sizeof(cir));\n \tmemset(&pir, 0, sizeof(pir));\n+\tshaper_config_to_nix(profile, &cir, &pir);\n \n-\t/* Skip leaf nodes */\n-\tif (tm_node->hw_lvl_id == NIX_TXSCH_LVL_CNT)\n-\t\treturn 0;\n+\totx2_tm_dbg(\"Shaper config node %s(%u) lvl %u id %u, \"\n+\t\t    \"pir %\" PRIu64 \"(%\" PRIu64 \"B),\"\n+\t\t     \" cir %\" PRIu64 \"(%\" PRIu64 \"B) (%p)\",\n+\t\t     nix_hwlvl2str(tm_node->hw_lvl), schq, tm_node->lvl,\n+\t\t     tm_node->id, pir.rate, pir.burst,\n+\t\t     cir.rate, cir.burst, tm_node);\n+\n+\tswitch (tm_node->hw_lvl) {\n+\tcase NIX_TXSCH_LVL_SMQ:\n+\t\t/* Configure PIR, CIR */\n+\t\treg[k] = NIX_AF_MDQX_PIR(schq);\n+\t\tregval[k] = (pir.rate && pir.burst) ?\n+\t\t\t\t(shaper2regval(&pir) | 1) : 0;\n+\t\tk++;\n+\n+\t\treg[k] = NIX_AF_MDQX_CIR(schq);\n+\t\tregval[k] = (cir.rate && cir.burst) ?\n+\t\t\t\t(shaper2regval(&cir) | 1) : 0;\n+\t\tk++;\n+\n+\t\t/* Configure RED ALG */\n+\t\treg[k] = NIX_AF_MDQX_SHAPE(schq);\n+\t\tregval[k] = ((uint64_t)tm_node->red_algo << 9);\n+\t\tk++;\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL4:\n+\t\t/* Configure PIR, CIR */\n+\t\treg[k] = NIX_AF_TL4X_PIR(schq);\n+\t\tregval[k] = (pir.rate && pir.burst) ?\n+\t\t\t\t(shaper2regval(&pir) | 1) : 0;\n+\t\tk++;\n+\n+\t\treg[k] = NIX_AF_TL4X_CIR(schq);\n+\t\tregval[k] = (cir.rate && cir.burst) ?\n+\t\t\t\t(shaper2regval(&cir) | 1) : 0;\n+\t\tk++;\n+\n+\t\t/* Configure RED algo */\n+\t\treg[k] = NIX_AF_TL4X_SHAPE(schq);\n+\t\tregval[k] = ((uint64_t)tm_node->red_algo << 9);\n+\t\tk++;\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL3:\n+\t\t/* Configure PIR, CIR */\n+\t\treg[k] = NIX_AF_TL3X_PIR(schq);\n+\t\tregval[k] = (pir.rate && pir.burst) ?\n+\t\t\t\t(shaper2regval(&pir) | 1) : 0;\n+\t\tk++;\n+\n+\t\treg[k] = NIX_AF_TL3X_CIR(schq);\n+\t\tregval[k] = (cir.rate && cir.burst) ?\n+\t\t\t\t(shaper2regval(&cir) | 1) : 0;\n+\t\tk++;\n+\n+\t\t/* Configure RED algo */\n+\t\treg[k] = NIX_AF_TL3X_SHAPE(schq);\n+\t\tregval[k] = ((uint64_t)tm_node->red_algo << 9);\n+\t\tk++;\n+\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL2:\n+\t\t/* Configure PIR, CIR */\n+\t\treg[k] = NIX_AF_TL2X_PIR(schq);\n+\t\tregval[k] = (pir.rate && pir.burst) ?\n+\t\t\t\t(shaper2regval(&pir) | 1) : 0;\n+\t\tk++;\n+\n+\t\treg[k] = NIX_AF_TL2X_CIR(schq);\n+\t\tregval[k] = (cir.rate && cir.burst) ?\n+\t\t\t\t(shaper2regval(&cir) | 1) : 0;\n+\t\tk++;\n+\n+\t\t/* Configure RED algo */\n+\t\treg[k] = NIX_AF_TL2X_SHAPE(schq);\n+\t\tregval[k] = ((uint64_t)tm_node->red_algo << 9);\n+\t\tk++;\n+\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL1:\n+\t\t/* Configure CIR */\n+\t\treg[k] = NIX_AF_TL1X_CIR(schq);\n+\t\tregval[k] = (cir.rate && cir.burst) ?\n+\t\t\t\t(shaper2regval(&cir) | 1) : 0;\n+\t\tk++;\n+\t\tbreak;\n+\t}\n+\n+\treturn k;\n+}\n+\n+static int\n+populate_tm_reg(struct otx2_eth_dev *dev,\n+\t\tstruct otx2_nix_tm_node *tm_node)\n+{\n+\tstruct otx2_nix_tm_shaper_profile *profile;\n+\tuint64_t regval_mask[MAX_REGS_PER_MBOX_MSG];\n+\tuint64_t regval[MAX_REGS_PER_MBOX_MSG];\n+\tuint64_t reg[MAX_REGS_PER_MBOX_MSG];\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tuint64_t parent = 0, child = 0;\n+\tuint32_t hw_lvl, rr_prio, schq;\n+\tstruct nix_txschq_config *req;\n+\tint rc = -EFAULT;\n+\tuint8_t k = 0;\n+\n+\tmemset(regval_mask, 0, sizeof(regval_mask));\n+\tprofile = nix_tm_shaper_profile_search(dev,\n+\t\t\t\t\ttm_node->params.shaper_profile_id);\n+\trr_prio = tm_node->rr_prio;\n+\thw_lvl = tm_node->hw_lvl;\n+\tschq = tm_node->hw_id;\n \n \t/* Root node will not have a parent node */\n-\tif (tm_node->hw_lvl_id == dev->otx2_tm_root_lvl)\n+\tif (hw_lvl == dev->otx2_tm_root_lvl)\n \t\tparent = tm_node->parent_hw_id;\n \telse\n \t\tparent = tm_node->parent->hw_id;\n \n \t/* Do we need this trigger to configure TL1 */\n \tif (dev->otx2_tm_root_lvl == NIX_TXSCH_LVL_TL2 &&\n-\t    tm_node->hw_lvl_id == dev->otx2_tm_root_lvl) {\n-\t\tschq = parent;\n-\t\t/*\n-\t\t * Default config for TL1.\n-\t\t * For VF this is always ignored.\n-\t\t */\n-\n-\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n-\t\treq->lvl = NIX_TXSCH_LVL_TL1;\n-\n-\t\t/* Set DWRR quantum */\n-\t\treq->reg[0] = NIX_AF_TL1X_SCHEDULE(schq);\n-\t\treq->regval[0] = TXSCH_TL1_DFLT_RR_QTM;\n-\t\treq->num_regs++;\n-\n-\t\treq->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq);\n-\t\treq->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1);\n-\t\treq->num_regs++;\n-\n-\t\treq->reg[2] = NIX_AF_TL1X_CIR(schq);\n-\t\treq->regval[2] = 0;\n-\t\treq->num_regs++;\n-\n-\t\trc = send_tm_reqval(mbox, req);\n+\t    hw_lvl == dev->otx2_tm_root_lvl) {\n+\t\trc = populate_tm_tl1_default(dev, parent);\n \t\tif (rc)\n \t\t\tgoto error;\n \t}\n \n-\tif (tm_node->hw_lvl_id != NIX_TXSCH_LVL_SMQ)\n+\tif (hw_lvl != NIX_TXSCH_LVL_SMQ)\n \t\tchild = find_prio_anchor(dev, tm_node->id);\n \n-\trr_prio = tm_node->rr_prio;\n-\thw_lvl = tm_node->hw_lvl_id;\n-\tstrict_schedul_prio = tm_node->priority;\n-\tschq = tm_node->hw_id;\n-\trr_quantum = (tm_node->weight * NIX_TM_RR_QUANTUM_MAX) /\n-\t\tMAX_SCHED_WEIGHT;\n-\n-\tconfigure_shaper_cir_pir_reg(dev, tm_node, &cir, &pir);\n-\n-\totx2_tm_dbg(\"Configure node %p, lvl %u hw_lvl %u, id %u, hw_id %u,\"\n-\t\t     \"parent_hw_id %\" PRIx64 \", pir %\" PRIx64 \", cir %\" PRIx64,\n-\t\t     tm_node, tm_node->level_id, hw_lvl,\n-\t\t     tm_node->id, schq, parent, pir.rate, cir.rate);\n-\n-\trc = -EFAULT;\n-\n+\t/* Override default rr_prio when TL1\n+\t * Static Priority is disabled\n+\t */\n+\tif (hw_lvl == NIX_TXSCH_LVL_TL1 &&\n+\t    dev->tm_flags & NIX_TM_TL1_NO_SP) {\n+\t\trr_prio = TXSCH_TL1_DFLT_RR_PRIO;\n+\t\tchild = 0;\n+\t}\n+\n+\totx2_tm_dbg(\"Topology config node %s(%u)->%s(%lu) lvl %u, id %u\"\n+\t\t    \" prio_anchor %lu rr_prio %u (%p)\", nix_hwlvl2str(hw_lvl),\n+\t\t    schq, nix_hwlvl2str(hw_lvl + 1), parent, tm_node->lvl,\n+\t\t    tm_node->id, child, rr_prio, tm_node);\n+\n+\t/* Prepare Topology and Link config */\n \tswitch (hw_lvl) {\n \tcase NIX_TXSCH_LVL_SMQ:\n-\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n-\t\treq->lvl = hw_lvl;\n-\t\treg = req->reg;\n-\t\tregval = req->regval;\n-\t\treq->num_regs = 0;\n \n \t\t/* Set xoff which will be cleared later */\n-\t\t*reg++ = NIX_AF_SMQX_CFG(schq);\n-\t\t*regval++ = BIT_ULL(50) | ((uint64_t)NIX_MAX_VTAG_INS << 36) |\n-\t\t\t\t(NIX_MAX_HW_FRS << 8) | NIX_MIN_HW_FRS;\n-\t\treq->num_regs++;\n-\t\t*reg++ = NIX_AF_MDQX_PARENT(schq);\n-\t\t*regval++ = parent << 16;\n-\t\treq->num_regs++;\n-\t\t*reg++ = NIX_AF_MDQX_SCHEDULE(schq);\n-\t\t*regval++ = (strict_schedul_prio << 24) | rr_quantum;\n-\t\treq->num_regs++;\n-\t\tif (pir.rate && pir.burst) {\n-\t\t\t*reg++ = NIX_AF_MDQX_PIR(schq);\n-\t\t\t*regval++ = shaper2regval(&pir) | 1;\n-\t\t\treq->num_regs++;\n-\t\t}\n+\t\treg[k] = NIX_AF_SMQX_CFG(schq);\n+\t\tregval[k] = BIT_ULL(50);\n+\t\tregval_mask[k] = ~BIT_ULL(50);\n+\t\tk++;\n \n-\t\tif (cir.rate && cir.burst) {\n-\t\t\t*reg++ = NIX_AF_MDQX_CIR(schq);\n-\t\t\t*regval++ = shaper2regval(&cir) | 1;\n-\t\t\treq->num_regs++;\n-\t\t}\n+\t\t/* Parent and schedule conf */\n+\t\treg[k] = NIX_AF_MDQX_PARENT(schq);\n+\t\tregval[k] = parent << 16;\n+\t\tk++;\n \n-\t\trc = send_tm_reqval(mbox, req);\n-\t\tif (rc)\n-\t\t\tgoto error;\n \t\tbreak;\n \tcase NIX_TXSCH_LVL_TL4:\n-\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n-\t\treq->lvl = hw_lvl;\n-\t\treq->num_regs = 0;\n-\t\treg = req->reg;\n-\t\tregval = req->regval;\n+\t\t/* Parent and schedule conf */\n+\t\treg[k] = NIX_AF_TL4X_PARENT(schq);\n+\t\tregval[k] = parent << 16;\n+\t\tk++;\n+\n+\t\treg[k] = NIX_AF_TL4X_TOPOLOGY(schq);\n+\t\tregval[k] = (child << 32) | (rr_prio << 1);\n+\t\tk++;\n \n-\t\t*reg++ = NIX_AF_TL4X_PARENT(schq);\n-\t\t*regval++ = parent << 16;\n-\t\treq->num_regs++;\n-\t\t*reg++ = NIX_AF_TL4X_TOPOLOGY(schq);\n-\t\t*regval++ = (child << 32) | (rr_prio << 1);\n-\t\treq->num_regs++;\n-\t\t*reg++ = NIX_AF_TL4X_SCHEDULE(schq);\n-\t\t*regval++ = (strict_schedul_prio << 24) | rr_quantum;\n-\t\treq->num_regs++;\n-\t\tif (pir.rate && pir.burst) {\n-\t\t\t*reg++ = NIX_AF_TL4X_PIR(schq);\n-\t\t\t*regval++ = shaper2regval(&pir) | 1;\n-\t\t\treq->num_regs++;\n-\t\t}\n-\t\tif (cir.rate && cir.burst) {\n-\t\t\t*reg++ = NIX_AF_TL4X_CIR(schq);\n-\t\t\t*regval++ = shaper2regval(&cir) | 1;\n-\t\t\treq->num_regs++;\n-\t\t}\n \t\t/* Configure TL4 to send to SDP channel instead of CGX/LBK */\n \t\tif (otx2_dev_is_sdp(dev)) {\n-\t\t\t*reg++ = NIX_AF_TL4X_SDP_LINK_CFG(schq);\n-\t\t\t*regval++ = BIT_ULL(12);\n-\t\t\treq->num_regs++;\n+\t\t\treg[k] = NIX_AF_TL4X_SDP_LINK_CFG(schq);\n+\t\t\tregval[k] = BIT_ULL(12);\n+\t\t\tk++;\n \t\t}\n-\n-\t\trc = send_tm_reqval(mbox, req);\n-\t\tif (rc)\n-\t\t\tgoto error;\n \t\tbreak;\n \tcase NIX_TXSCH_LVL_TL3:\n-\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n-\t\treq->lvl = hw_lvl;\n-\t\treq->num_regs = 0;\n-\t\treg = req->reg;\n-\t\tregval = req->regval;\n+\t\t/* Parent and schedule conf */\n+\t\treg[k] = NIX_AF_TL3X_PARENT(schq);\n+\t\tregval[k] = parent << 16;\n+\t\tk++;\n \n-\t\t*reg++ = NIX_AF_TL3X_PARENT(schq);\n-\t\t*regval++ = parent << 16;\n-\t\treq->num_regs++;\n-\t\t*reg++ = NIX_AF_TL3X_TOPOLOGY(schq);\n-\t\t*regval++ = (child << 32) | (rr_prio << 1);\n-\t\treq->num_regs++;\n-\t\t*reg++ = NIX_AF_TL3X_SCHEDULE(schq);\n-\t\t*regval++ = (strict_schedul_prio << 24) | rr_quantum;\n-\t\treq->num_regs++;\n+\t\treg[k] = NIX_AF_TL3X_TOPOLOGY(schq);\n+\t\tregval[k] = (child << 32) | (rr_prio << 1);\n+\t\tk++;\n \n \t\t/* Link configuration */\n \t\tif (!otx2_dev_is_sdp(dev) &&\n \t\t    dev->link_cfg_lvl == NIX_TXSCH_LVL_TL3) {\n-\t\t\t*reg++ = NIX_AF_TL3_TL2X_LINKX_CFG(schq,\n+\t\t\treg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq,\n \t\t\t\t\t\tnix_get_link(dev));\n-\t\t\t*regval++ = BIT_ULL(12) | nix_get_relchan(dev);\n-\t\t\treq->num_regs++;\n+\t\t\tregval[k] = BIT_ULL(12) | nix_get_relchan(dev);\n+\t\t\tk++;\n \t\t}\n \n-\t\tif (pir.rate && pir.burst) {\n-\t\t\t*reg++ = NIX_AF_TL3X_PIR(schq);\n-\t\t\t*regval++ = shaper2regval(&pir) | 1;\n-\t\t\treq->num_regs++;\n-\t\t}\n-\t\tif (cir.rate && cir.burst) {\n-\t\t\t*reg++ = NIX_AF_TL3X_CIR(schq);\n-\t\t\t*regval++ = shaper2regval(&cir) | 1;\n-\t\t\treq->num_regs++;\n-\t\t}\n-\n-\t\trc = send_tm_reqval(mbox, req);\n-\t\tif (rc)\n-\t\t\tgoto error;\n \t\tbreak;\n \tcase NIX_TXSCH_LVL_TL2:\n-\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n-\t\treq->lvl = hw_lvl;\n-\t\treq->num_regs = 0;\n-\t\treg = req->reg;\n-\t\tregval = req->regval;\n+\t\t/* Parent and schedule conf */\n+\t\treg[k] = NIX_AF_TL2X_PARENT(schq);\n+\t\tregval[k] = parent << 16;\n+\t\tk++;\n \n-\t\t*reg++ = NIX_AF_TL2X_PARENT(schq);\n-\t\t*regval++ = parent << 16;\n-\t\treq->num_regs++;\n-\t\t*reg++ = NIX_AF_TL2X_TOPOLOGY(schq);\n-\t\t*regval++ = (child << 32) | (rr_prio << 1);\n-\t\treq->num_regs++;\n-\t\t*reg++ = NIX_AF_TL2X_SCHEDULE(schq);\n-\t\tif (dev->otx2_tm_root_lvl == NIX_TXSCH_LVL_TL2)\n-\t\t\t*regval++ = (1 << 24) | rr_quantum;\n-\t\telse\n-\t\t\t*regval++ = (strict_schedul_prio << 24) | rr_quantum;\n-\t\treq->num_regs++;\n+\t\treg[k] = NIX_AF_TL2X_TOPOLOGY(schq);\n+\t\tregval[k] = (child << 32) | (rr_prio << 1);\n+\t\tk++;\n \n \t\t/* Link configuration */\n \t\tif (!otx2_dev_is_sdp(dev) &&\n \t\t    dev->link_cfg_lvl == NIX_TXSCH_LVL_TL2) {\n-\t\t\t*reg++ = NIX_AF_TL3_TL2X_LINKX_CFG(schq,\n+\t\t\treg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq,\n \t\t\t\t\t\tnix_get_link(dev));\n-\t\t\t*regval++ = BIT_ULL(12) | nix_get_relchan(dev);\n-\t\t\treq->num_regs++;\n-\t\t}\n-\t\tif (pir.rate && pir.burst) {\n-\t\t\t*reg++ = NIX_AF_TL2X_PIR(schq);\n-\t\t\t*regval++ = shaper2regval(&pir) | 1;\n-\t\t\treq->num_regs++;\n-\t\t}\n-\t\tif (cir.rate && cir.burst) {\n-\t\t\t*reg++ = NIX_AF_TL2X_CIR(schq);\n-\t\t\t*regval++ = shaper2regval(&cir) | 1;\n-\t\t\treq->num_regs++;\n+\t\t\tregval[k] = BIT_ULL(12) | nix_get_relchan(dev);\n+\t\t\tk++;\n \t\t}\n \n-\t\trc = send_tm_reqval(mbox, req);\n-\t\tif (rc)\n-\t\t\tgoto error;\n \t\tbreak;\n \tcase NIX_TXSCH_LVL_TL1:\n-\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n-\t\treq->lvl = hw_lvl;\n-\t\treq->num_regs = 0;\n-\t\treg = req->reg;\n-\t\tregval = req->regval;\n+\t\treg[k] = NIX_AF_TL1X_TOPOLOGY(schq);\n+\t\tregval[k] = (child << 32) | (rr_prio << 1 /*RR_PRIO*/);\n+\t\tk++;\n \n-\t\t*reg++ = NIX_AF_TL1X_SCHEDULE(schq);\n-\t\t*regval++ = rr_quantum;\n-\t\treq->num_regs++;\n-\t\t*reg++ = NIX_AF_TL1X_TOPOLOGY(schq);\n-\t\t*regval++ = (child << 32) | (rr_prio << 1 /*RR_PRIO*/);\n-\t\treq->num_regs++;\n-\t\tif (cir.rate && cir.burst) {\n-\t\t\t*reg++ = NIX_AF_TL1X_CIR(schq);\n-\t\t\t*regval++ = shaper2regval(&cir) | 1;\n-\t\t\treq->num_regs++;\n-\t\t}\n-\n-\t\trc = send_tm_reqval(mbox, req);\n-\t\tif (rc)\n-\t\t\tgoto error;\n \t\tbreak;\n \t}\n \n+\t/* Prepare schedule config */\n+\tk += prepare_tm_sched_reg(dev, tm_node, &reg[k], &regval[k]);\n+\n+\t/* Prepare shaping config */\n+\tk += prepare_tm_shaper_reg(tm_node, profile, &reg[k], &regval[k]);\n+\n+\tif (!k)\n+\t\treturn 0;\n+\n+\t/* Copy and send config mbox */\n+\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\treq->lvl = hw_lvl;\n+\treq->num_regs = k;\n+\n+\totx2_mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);\n+\totx2_mbox_memcpy(req->regval, regval, sizeof(uint64_t) * k);\n+\totx2_mbox_memcpy(req->regval_mask, regval_mask, sizeof(uint64_t) * k);\n+\n+\trc = otx2_mbox_process(mbox);\n+\tif (rc)\n+\t\tgoto error;\n+\n \treturn 0;\n error:\n \totx2_err(\"Txschq cfg request failed for node %p, rc=%d\", tm_node, rc);\n@@ -541,13 +591,14 @@ static int\n nix_tm_txsch_reg_config(struct otx2_eth_dev *dev)\n {\n \tstruct otx2_nix_tm_node *tm_node;\n-\tuint32_t lvl;\n+\tuint32_t hw_lvl;\n \tint rc = 0;\n \n-\tfor (lvl = 0; lvl < (uint32_t)dev->otx2_tm_root_lvl + 1; lvl++) {\n+\tfor (hw_lvl = 0; hw_lvl <= dev->otx2_tm_root_lvl; hw_lvl++) {\n \t\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n-\t\t\tif (tm_node->hw_lvl_id == lvl) {\n-\t\t\t\trc = populate_tm_registers(dev, tm_node);\n+\t\t\tif (tm_node->hw_lvl == hw_lvl &&\n+\t\t\t    tm_node->hw_lvl != NIX_TXSCH_LVL_CNT) {\n+\t\t\t\trc = populate_tm_reg(dev, tm_node);\n \t\t\t\tif (rc)\n \t\t\t\t\tgoto exit;\n \t\t\t}\n@@ -637,8 +688,8 @@ nix_tm_update_parent_info(struct otx2_eth_dev *dev)\n static int\n nix_tm_node_add_to_list(struct otx2_eth_dev *dev, uint32_t node_id,\n \t\t\tuint32_t parent_node_id, uint32_t priority,\n-\t\t\tuint32_t weight, uint16_t hw_lvl_id,\n-\t\t\tuint16_t level_id, bool user,\n+\t\t\tuint32_t weight, uint16_t hw_lvl,\n+\t\t\tuint16_t lvl, bool user,\n \t\t\tstruct rte_tm_node_params *params)\n {\n \tstruct otx2_nix_tm_shaper_profile *shaper_profile;\n@@ -655,8 +706,8 @@ nix_tm_node_add_to_list(struct otx2_eth_dev *dev, uint32_t node_id,\n \tif (!tm_node)\n \t\treturn -ENOMEM;\n \n-\ttm_node->level_id = level_id;\n-\ttm_node->hw_lvl_id = hw_lvl_id;\n+\ttm_node->lvl = lvl;\n+\ttm_node->hw_lvl = hw_lvl;\n \n \ttm_node->id = node_id;\n \ttm_node->priority = priority;\n@@ -935,18 +986,18 @@ nix_tm_free_resources(struct otx2_eth_dev *dev, uint32_t flags_mask,\n \t\t\tcontinue;\n \n \t\tif (nix_tm_have_tl1_access(dev) &&\n-\t\t    tm_node->hw_lvl_id ==  NIX_TXSCH_LVL_TL1)\n+\t\t    tm_node->hw_lvl ==  NIX_TXSCH_LVL_TL1)\n \t\t\tskip_node = true;\n \n \t\totx2_tm_dbg(\"Free hwres for node %u, hwlvl %u, hw_id %u (%p)\",\n-\t\t\t    tm_node->id,  tm_node->hw_lvl_id,\n+\t\t\t    tm_node->id,  tm_node->hw_lvl,\n \t\t\t    tm_node->hw_id, tm_node);\n \t\t/* Free specific HW resource if requested */\n \t\tif (!skip_node && flags_mask &&\n \t\t    tm_node->flags & NIX_TM_NODE_HWRES) {\n \t\t\treq = otx2_mbox_alloc_msg_nix_txsch_free(mbox);\n \t\t\treq->flags = 0;\n-\t\t\treq->schq_lvl = tm_node->hw_lvl_id;\n+\t\t\treq->schq_lvl = tm_node->hw_lvl;\n \t\t\treq->schq = tm_node->hw_id;\n \t\t\trc = otx2_mbox_process(mbox);\n \t\t\tif (rc)\n@@ -1010,17 +1061,17 @@ nix_tm_assign_id_to_node(struct otx2_eth_dev *dev,\n \tuint32_t l_id, schq_index;\n \n \totx2_tm_dbg(\"Assign hw id for child node %u, lvl %u, hw_lvl %u (%p)\",\n-\t\t    child->id, child->level_id, child->hw_lvl_id, child);\n+\t\t    child->id, child->lvl, child->hw_lvl, child);\n \n \tchild->flags |= NIX_TM_NODE_HWRES;\n \n \t/* Process root nodes */\n \tif (dev->otx2_tm_root_lvl == NIX_TXSCH_LVL_TL2 &&\n-\t    child->hw_lvl_id == dev->otx2_tm_root_lvl && !parent) {\n+\t    child->hw_lvl == dev->otx2_tm_root_lvl && !parent) {\n \t\tint idx = 0;\n \t\tuint32_t tschq_con_index;\n \n-\t\tl_id = child->hw_lvl_id;\n+\t\tl_id = child->hw_lvl;\n \t\ttschq_con_index = dev->txschq_contig_index[l_id];\n \t\thw_id = dev->txschq_contig_list[l_id][tschq_con_index];\n \t\tchild->hw_id = hw_id;\n@@ -1032,10 +1083,10 @@ nix_tm_assign_id_to_node(struct otx2_eth_dev *dev,\n \t\treturn 0;\n \t}\n \tif (dev->otx2_tm_root_lvl == NIX_TXSCH_LVL_TL1 &&\n-\t    child->hw_lvl_id == dev->otx2_tm_root_lvl && !parent) {\n+\t    child->hw_lvl == dev->otx2_tm_root_lvl && !parent) {\n \t\tuint32_t tschq_con_index;\n \n-\t\tl_id = child->hw_lvl_id;\n+\t\tl_id = child->hw_lvl;\n \t\ttschq_con_index = dev->txschq_index[l_id];\n \t\thw_id = dev->txschq_list[l_id][tschq_con_index];\n \t\tchild->hw_id = hw_id;\n@@ -1044,7 +1095,7 @@ nix_tm_assign_id_to_node(struct otx2_eth_dev *dev,\n \t}\n \n \t/* Process children with parents */\n-\tl_id = child->hw_lvl_id;\n+\tl_id = child->hw_lvl;\n \tschq_index = dev->txschq_index[l_id];\n \tschq_con_index = dev->txschq_contig_index[l_id];\n \n@@ -1069,8 +1120,8 @@ nix_tm_assign_hw_id(struct otx2_eth_dev *dev)\n \n \tfor (i = NIX_TXSCH_LVL_TL1; i > 0; i--) {\n \t\tTAILQ_FOREACH(parent, &dev->node_list, node) {\n-\t\t\tchild_hw_lvl = parent->hw_lvl_id - 1;\n-\t\t\tif (parent->hw_lvl_id != i)\n+\t\t\tchild_hw_lvl = parent->hw_lvl - 1;\n+\t\t\tif (parent->hw_lvl != i)\n \t\t\t\tcontinue;\n \t\t\tTAILQ_FOREACH(child, &dev->node_list, node) {\n \t\t\t\tif (!child->parent)\n@@ -1087,7 +1138,7 @@ nix_tm_assign_hw_id(struct otx2_eth_dev *dev)\n \t\t\t * Explicitly assign id to parent node if it\n \t\t\t * doesn't have a parent\n \t\t\t */\n-\t\t\tif (parent->hw_lvl_id == dev->otx2_tm_root_lvl)\n+\t\t\tif (parent->hw_lvl == dev->otx2_tm_root_lvl)\n \t\t\t\tnix_tm_assign_id_to_node(dev, parent, NULL);\n \t\t}\n \t}\n@@ -1102,7 +1153,7 @@ nix_tm_count_req_schq(struct otx2_eth_dev *dev,\n \tuint8_t contig_count;\n \n \tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n-\t\tif (lvl == tm_node->hw_lvl_id) {\n+\t\tif (lvl == tm_node->hw_lvl) {\n \t\t\treq->schq[lvl - 1] += tm_node->rr_num;\n \t\t\tif (tm_node->max_prio != UINT32_MAX) {\n \t\t\t\tcontig_count = tm_node->max_prio + 1;\n@@ -1111,7 +1162,7 @@ nix_tm_count_req_schq(struct otx2_eth_dev *dev,\n \t\t}\n \t\tif (lvl == dev->otx2_tm_root_lvl &&\n \t\t    dev->otx2_tm_root_lvl && lvl == NIX_TXSCH_LVL_TL2 &&\n-\t\t    tm_node->hw_lvl_id == dev->otx2_tm_root_lvl) {\n+\t\t    tm_node->hw_lvl == dev->otx2_tm_root_lvl) {\n \t\t\treq->schq_contig[dev->otx2_tm_root_lvl]++;\n \t\t}\n \t}\n@@ -1192,7 +1243,7 @@ nix_tm_alloc_resources(struct rte_eth_dev *eth_dev, bool xmit_enable)\n \t\t\tcontinue;\n \n \t\t/* Enable xmit on sq */\n-\t\tif (tm_node->level_id != OTX2_TM_LVL_QUEUE) {\n+\t\tif (tm_node->lvl != OTX2_TM_LVL_QUEUE) {\n \t\t\ttm_node->flags |= NIX_TM_NODE_ENABLED;\n \t\t\tcontinue;\n \t\t}\n@@ -1210,8 +1261,7 @@ nix_tm_alloc_resources(struct rte_eth_dev *eth_dev, bool xmit_enable)\n \t\ttxq = eth_dev->data->tx_queues[sq];\n \n \t\tsmq = tm_node->parent->hw_id;\n-\t\trr_quantum = (tm_node->weight *\n-\t\t\t      NIX_TM_RR_QUANTUM_MAX) / MAX_SCHED_WEIGHT;\n+\t\trr_quantum = NIX_TM_WEIGHT_TO_RR_QUANTUM(tm_node->weight);\n \n \t\trc = nix_tm_sw_xon(txq, smq, rr_quantum);\n \t\tif (rc)\n@@ -1332,6 +1382,7 @@ void otx2_nix_tm_conf_init(struct rte_eth_dev *eth_dev)\n \n int otx2_nix_tm_init_default(struct rte_eth_dev *eth_dev)\n {\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n \tstruct otx2_eth_dev  *dev = otx2_eth_pmd_priv(eth_dev);\n \tuint16_t sq_cnt = eth_dev->data->nb_tx_queues;\n \tint rc;\n@@ -1347,6 +1398,13 @@ int otx2_nix_tm_init_default(struct rte_eth_dev *eth_dev)\n \tnix_tm_clear_shaper_profiles(dev);\n \tdev->tm_flags = NIX_TM_DEFAULT_TREE;\n \n+\t/* Disable TL1 Static Priority when VF's are enabled\n+\t * as otherwise VF's TL2 reallocation will be needed\n+\t * runtime to support a specific topology of PF.\n+\t */\n+\tif (pci_dev->max_vfs)\n+\t\tdev->tm_flags |= NIX_TM_TL1_NO_SP;\n+\n \trc = nix_tm_prepare_default_tree(eth_dev);\n \tif (rc != 0)\n \t\treturn rc;\n@@ -1397,15 +1455,14 @@ otx2_nix_tm_get_leaf_data(struct otx2_eth_dev *dev, uint16_t sq,\n \t\ttm_node = nix_tm_node_search(dev, sq, true);\n \n \t/* Check if we found a valid leaf node */\n-\tif (!tm_node || tm_node->level_id != OTX2_TM_LVL_QUEUE ||\n+\tif (!tm_node || tm_node->lvl != OTX2_TM_LVL_QUEUE ||\n \t    !tm_node->parent || tm_node->parent->hw_id == UINT32_MAX) {\n \t\treturn -EIO;\n \t}\n \n \t/* Get SMQ Id of leaf node's parent */\n \t*smq = tm_node->parent->hw_id;\n-\t*rr_quantum = (tm_node->weight * NIX_TM_RR_QUANTUM_MAX)\n-\t\t/ MAX_SCHED_WEIGHT;\n+\t*rr_quantum = NIX_TM_WEIGHT_TO_RR_QUANTUM(tm_node->weight);\n \n \trc = nix_smq_xoff(dev, *smq, false);\n \tif (rc)\ndiff --git a/drivers/net/octeontx2/otx2_tm.h b/drivers/net/octeontx2/otx2_tm.h\nindex 4712b09..ad7727e 100644\n--- a/drivers/net/octeontx2/otx2_tm.h\n+++ b/drivers/net/octeontx2/otx2_tm.h\n@@ -10,6 +10,7 @@\n #include <rte_tm_driver.h>\n \n #define NIX_TM_DEFAULT_TREE\tBIT_ULL(0)\n+#define NIX_TM_TL1_NO_SP\tBIT_ULL(3)\n \n struct otx2_eth_dev;\n \n@@ -27,16 +28,18 @@ struct otx2_nix_tm_node {\n \tuint32_t hw_id;\n \tuint32_t priority;\n \tuint32_t weight;\n-\tuint16_t level_id;\n-\tuint16_t hw_lvl_id;\n+\tuint16_t lvl;\n+\tuint16_t hw_lvl;\n \tuint32_t rr_prio;\n \tuint32_t rr_num;\n \tuint32_t max_prio;\n \tuint32_t parent_hw_id;\n-\tuint32_t flags;\n+\tuint32_t flags:16;\n #define NIX_TM_NODE_HWRES\tBIT_ULL(0)\n #define NIX_TM_NODE_ENABLED\tBIT_ULL(1)\n #define NIX_TM_NODE_USER\tBIT_ULL(2)\n+\t/* Shaper algorithm for RED state @NIX_REDALG_E */\n+\tuint32_t red_algo:2;\n \tstruct otx2_nix_tm_node *parent;\n \tstruct rte_tm_node_params params;\n };\n@@ -45,7 +48,7 @@ struct otx2_nix_tm_shaper_profile {\n \tTAILQ_ENTRY(otx2_nix_tm_shaper_profile) shaper;\n \tuint32_t shaper_profile_id;\n \tuint32_t reference_count;\n-\tstruct rte_tm_shaper_params profile;\n+\tstruct rte_tm_shaper_params params; /* Rate in bits/sec */\n };\n \n struct shaper_params {\n@@ -63,6 +66,10 @@ TAILQ_HEAD(otx2_nix_tm_shaper_profile_list, otx2_nix_tm_shaper_profile);\n \n #define MAX_SCHED_WEIGHT ((uint8_t)~0)\n #define NIX_TM_RR_QUANTUM_MAX (BIT_ULL(24) - 1)\n+#define NIX_TM_WEIGHT_TO_RR_QUANTUM(__weight)\t\t\t\\\n+\t\t((((__weight) & MAX_SCHED_WEIGHT) *             \\\n+\t\t  NIX_TM_RR_QUANTUM_MAX) / MAX_SCHED_WEIGHT)\n+\n \n /* DEFAULT_RR_WEIGHT * NIX_TM_RR_QUANTUM_MAX / MAX_SCHED_WEIGHT  */\n /* = NIX_MAX_HW_MTU */\n@@ -73,52 +80,27 @@ TAILQ_HEAD(otx2_nix_tm_shaper_profile_list, otx2_nix_tm_shaper_profile);\n #define MAX_RATE_EXPONENT 0xf\n #define MAX_RATE_MANTISSA 0xff\n \n-/** NIX rate limiter time-wheel resolution */\n-#define L1_TIME_WHEEL_CCLK_TICKS 240\n-#define LX_TIME_WHEEL_CCLK_TICKS 860\n+#define NIX_SHAPER_RATE_CONST ((uint64_t)2E6)\n \n-#define CCLK_HZ 1000000000\n-\n-/* NIX rate calculation\n- *\tCCLK = coprocessor-clock frequency in MHz\n- *\tCCLK_TICKS = rate limiter time-wheel resolution\n- *\n+/* NIX rate calculation in Bits/Sec\n  *\tPIR_ADD = ((256 + NIX_*_PIR[RATE_MANTISSA])\n  *\t\t<< NIX_*_PIR[RATE_EXPONENT]) / 256\n- *\tPIR = (CCLK / (CCLK_TICKS << NIX_*_PIR[RATE_DIVIDER_EXPONENT]))\n- *\t\t* PIR_ADD\n+ *\tPIR = (2E6 * PIR_ADD / (1 << NIX_*_PIR[RATE_DIVIDER_EXPONENT]))\n  *\n  *\tCIR_ADD = ((256 + NIX_*_CIR[RATE_MANTISSA])\n  *\t\t<< NIX_*_CIR[RATE_EXPONENT]) / 256\n- *\tCIR = (CCLK / (CCLK_TICKS << NIX_*_CIR[RATE_DIVIDER_EXPONENT]))\n- *\t\t* CIR_ADD\n+ *\tCIR = (2E6 * CIR_ADD / (CCLK_TICKS << NIX_*_CIR[RATE_DIVIDER_EXPONENT]))\n  */\n-#define SHAPER_RATE(cclk_hz, cclk_ticks, \\\n-\t\t\texponent, mantissa, div_exp) \\\n-\t(((uint64_t)(cclk_hz) * ((256 + (mantissa)) << (exponent))) \\\n-\t\t/ (((cclk_ticks) << (div_exp)) * 256))\n+#define SHAPER_RATE(exponent, mantissa, div_exp) \\\n+\t((NIX_SHAPER_RATE_CONST * ((256 + (mantissa)) << (exponent)))\\\n+\t\t/ (((1ull << (div_exp)) * 256)))\n \n-#define L1_SHAPER_RATE(cclk_hz, exponent, mantissa, div_exp) \\\n-\tSHAPER_RATE(cclk_hz, L1_TIME_WHEEL_CCLK_TICKS, \\\n-\t\t\texponent, mantissa, div_exp)\n+/* 96xx rate limits in Bits/Sec */\n+#define MIN_SHAPER_RATE \\\n+\tSHAPER_RATE(0, 0, MAX_RATE_DIV_EXP)\n \n-#define LX_SHAPER_RATE(cclk_hz, exponent, mantissa, div_exp) \\\n-\tSHAPER_RATE(cclk_hz, LX_TIME_WHEEL_CCLK_TICKS, \\\n-\t\t\texponent, mantissa, div_exp)\n-\n-/* Shaper rate limits */\n-#define MIN_SHAPER_RATE(cclk_hz, cclk_ticks) \\\n-\tSHAPER_RATE(cclk_hz, cclk_ticks, 0, 0, MAX_RATE_DIV_EXP)\n-\n-#define MAX_SHAPER_RATE(cclk_hz, cclk_ticks) \\\n-\tSHAPER_RATE(cclk_hz, cclk_ticks, MAX_RATE_EXPONENT, \\\n-\t\t\tMAX_RATE_MANTISSA, 0)\n-\n-#define MIN_L1_SHAPER_RATE(cclk_hz) \\\n-\tMIN_SHAPER_RATE(cclk_hz, L1_TIME_WHEEL_CCLK_TICKS)\n-\n-#define MAX_L1_SHAPER_RATE(cclk_hz) \\\n-\tMAX_SHAPER_RATE(cclk_hz, L1_TIME_WHEEL_CCLK_TICKS)\n+#define MAX_SHAPER_RATE \\\n+\tSHAPER_RATE(MAX_RATE_EXPONENT, MAX_RATE_MANTISSA, 0)\n \n /** TM Shaper - low level operations */\n \n@@ -150,4 +132,25 @@ TAILQ_HEAD(otx2_nix_tm_shaper_profile_list, otx2_nix_tm_shaper_profile);\n #define TXSCH_TL1_DFLT_RR_QTM  ((1 << 24) - 1)\n #define TXSCH_TL1_DFLT_RR_PRIO 1\n \n+static inline const char *\n+nix_hwlvl2str(uint32_t hw_lvl)\n+{\n+\tswitch (hw_lvl) {\n+\tcase NIX_TXSCH_LVL_MDQ:\n+\t\treturn \"SMQ/MDQ\";\n+\tcase NIX_TXSCH_LVL_TL4:\n+\t\treturn \"TL4\";\n+\tcase NIX_TXSCH_LVL_TL3:\n+\t\treturn \"TL3\";\n+\tcase NIX_TXSCH_LVL_TL2:\n+\t\treturn \"TL2\";\n+\tcase NIX_TXSCH_LVL_TL1:\n+\t\treturn \"TL1\";\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn \"???\";\n+}\n+\n #endif /* __OTX2_TM_H__ */\n",
    "prefixes": [
        "02/11"
    ]
}