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GET /api/patches/66538/?format=api
{ "id": 66538, "url": "http://patches.dpdk.org/api/patches/66538/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/e5393f0c369b95b40af2f58ecc34a4b6fda70feb.1583906144.git.kaara.satwik@chelsio.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<e5393f0c369b95b40af2f58ecc34a4b6fda70feb.1583906144.git.kaara.satwik@chelsio.com>", "list_archive_url": "https://inbox.dpdk.org/dev/e5393f0c369b95b40af2f58ecc34a4b6fda70feb.1583906144.git.kaara.satwik@chelsio.com", "date": "2020-03-11T09:05:51", "name": "[9/9] net/cxgbe: add devargs to control filtermode and filtermask values", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "dc83b632c48cdfd1275370fbe834e3ba8cdbbb35", "submitter": { "id": 241, "url": "http://patches.dpdk.org/api/people/241/?format=api", "name": "Rahul Lakkireddy", "email": "rahul.lakkireddy@chelsio.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/e5393f0c369b95b40af2f58ecc34a4b6fda70feb.1583906144.git.kaara.satwik@chelsio.com/mbox/", "series": [ { "id": 8880, "url": "http://patches.dpdk.org/api/series/8880/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8880", "date": "2020-03-11T09:05:42", "name": "net/cxgbe: updates for rte_flow support", "version": 1, "mbox": "http://patches.dpdk.org/series/8880/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/66538/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/66538/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5C057A0567;\n\tWed, 11 Mar 2020 10:18:24 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 2CEDC1C07C;\n\tWed, 11 Mar 2020 10:17:06 +0100 (CET)", "from stargate.chelsio.com (stargate.chelsio.com [12.32.117.8])\n by dpdk.org (Postfix) with ESMTP id 78A881C07C\n for <dev@dpdk.org>; Wed, 11 Mar 2020 10:17:04 +0100 (CET)", "from localhost (scalar.blr.asicdesigners.com [10.193.185.94])\n by stargate.chelsio.com (8.13.8/8.13.8) with ESMTP id 02B9H278014348;\n Wed, 11 Mar 2020 02:17:02 -0700" ], "From": "Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>", "To": "dev@dpdk.org", "Cc": "nirranjan@chelsio.com, kaara.satwik@chelsio.com", "Date": "Wed, 11 Mar 2020 14:35:51 +0530", "Message-Id": "\n <e5393f0c369b95b40af2f58ecc34a4b6fda70feb.1583906144.git.kaara.satwik@chelsio.com>", "X-Mailer": "git-send-email 2.5.3", "In-Reply-To": [ "<cover.1583906144.git.kaara.satwik@chelsio.com>", "<cover.1583906144.git.kaara.satwik@chelsio.com>" ], "References": [ "<cover.1583906144.git.kaara.satwik@chelsio.com>", "<cover.1583906144.git.kaara.satwik@chelsio.com>" ], "Subject": "[dpdk-dev] [PATCH 9/9] net/cxgbe: add devargs to control filtermode\n\tand filtermask values", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Karra Satwik <kaara.satwik@chelsio.com>\n\nApart from the 4-tuple (IP src/dst addresses and TCP/UDP src/dst\nport addresses), there are only 40-bits available to match other\nfields in packet headers. Not all combinations of packet header\nfields can fit in the 40-bit tuple.\n\nCurrently, the combination of packet header fields to match are\nconfigured via filterMode for LETCAM filters and filterMask for\nHASH filters in firmware config files (t5/t6-config.txt). So, add\ndevargs to allow User to dynamically select the filterMode and\nfilterMask combination during runtime, without having to modify the\nfirmware config files and reflashing them onto the adapter. A table\nof supported combinations is maintained by the driver to internally\ntranslate the User specified devargs combination to hardware's internal\nformat before writing the requested combination to hardware\n\nSigned-off-by: Karra Satwik <kaara.satwik@chelsio.com>\nSigned-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>\n---\n doc/guides/nics/cxgbe.rst | 219 +++++++++++++++++++++-\n drivers/net/cxgbe/base/adapter.h | 2 +\n drivers/net/cxgbe/base/t4fw_interface.h | 5 +\n drivers/net/cxgbe/cxgbe.h | 23 +++\n drivers/net/cxgbe/cxgbe_ethdev.c | 4 +-\n drivers/net/cxgbe/cxgbe_main.c | 237 ++++++++++++++++++++++++\n 6 files changed, 482 insertions(+), 8 deletions(-)", "diff": "diff --git a/doc/guides/nics/cxgbe.rst b/doc/guides/nics/cxgbe.rst\nindex cae78a34c..54a4c1389 100644\n--- a/doc/guides/nics/cxgbe.rst\n+++ b/doc/guides/nics/cxgbe.rst\n@@ -70,7 +70,7 @@ in :ref:`t5-nics` and :ref:`t6-nics`.\n Prerequisites\n -------------\n \n-- Requires firmware version **1.23.4.0** and higher. Visit\n+- Requires firmware version **1.24.11.0** and higher. Visit\n `Chelsio Download Center <http://service.chelsio.com>`_ to get latest firmware\n bundled with the latest Chelsio Unified Wire package.\n \n@@ -141,6 +141,211 @@ CXGBE VF Only Runtime Options\n underlying Chelsio NICs. This enables multiple VFs on the same NIC\n to send traffic to each other even when the physical link is down.\n \n+CXGBE PF Only Runtime Options\n+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n+\n+- ``filtermode`` (default **0**)\n+\n+ Apart from the 4-tuple (IP src/dst addresses and TCP/UDP src/dst port\n+ addresses), there are only 40-bits available to match other fields in\n+ packet headers. So, ``filtermode`` devarg allows user to dynamically\n+ select a 40-bit supported match field combination for LETCAM (wildcard)\n+ filters.\n+\n+ Default value of **0** makes driver pick the combination configured in\n+ the firmware configuration file on the adapter.\n+\n+ The supported flags and their corresponding values are shown in table below.\n+ These flags can be OR'd to create 1 of the multiple supported combinations\n+ for LETCAM filters.\n+\n+ ================== ======\n+ FLAG VALUE\n+ ================== ======\n+ Physical Port 0x1\n+ PFVF 0x2\n+ Destination MAC 0x4\n+ Ethertype 0x8\n+ Inner VLAN 0x10\n+ Outer VLAN 0x20\n+ IP TOS 0x40\n+ IP Protocol 0x80\n+ ================== ======\n+\n+ The supported ``filtermode`` combinations and their corresponding OR'd\n+ values are shown in table below.\n+\n+ +-----------------------------------+-----------+\n+ | FILTERMODE COMBINATIONS | VALUE |\n+ +===================================+===========+\n+ | Protocol, TOS, Outer VLAN, Port | 0xE1 |\n+ +-----------------------------------+-----------+\n+ | Protocol, TOS, Outer VLAN | 0xE0 |\n+ +-----------------------------------+-----------+\n+ | Protocol, TOS, Inner VLAN, Port | 0xD1 |\n+ +-----------------------------------+-----------+\n+ | Protocol, TOS, Inner VLAN | 0xD0 |\n+ +-----------------------------------+-----------+\n+ | Protocol, TOS, PFVF, Port | 0xC3 |\n+ +-----------------------------------+-----------+\n+ | Protocol, TOS, PFVF | 0xC2 |\n+ +-----------------------------------+-----------+\n+ | Protocol, TOS, Port | 0xC1 |\n+ +-----------------------------------+-----------+\n+ | Protocol, TOS | 0xC0 |\n+ +-----------------------------------+-----------+\n+ | Protocol, Outer VLAN, Port | 0xA1 |\n+ +-----------------------------------+-----------+\n+ | Protocol, Outer VLAN | 0xA0 |\n+ +-----------------------------------+-----------+\n+ | Protocol, Inner VLAN, Port | 0x91 |\n+ +-----------------------------------+-----------+\n+ | Protocol, Inner VLAN | 0x90 |\n+ +-----------------------------------+-----------+\n+ | Protocol, Ethertype, DstMAC, Port | 0x8D |\n+ +-----------------------------------+-----------+\n+ | Protocol, Ethertype, DstMAC | 0x8C |\n+ +-----------------------------------+-----------+\n+ | Protocol, Ethertype, Port | 0x89 |\n+ +-----------------------------------+-----------+\n+ | Protocol, Ethertype | 0x88 |\n+ +-----------------------------------+-----------+\n+ | Protocol, DstMAC, PFVF, Port | 0x87 |\n+ +-----------------------------------+-----------+\n+ | Protocol, DstMAC, PFVF | 0x86 |\n+ +-----------------------------------+-----------+\n+ | Protocol, DstMAC, Port | 0x85 |\n+ +-----------------------------------+-----------+\n+ | Protocol, DstMAC | 0x84 |\n+ +-----------------------------------+-----------+\n+ | Protocol, PFVF, Port | 0x83 |\n+ +-----------------------------------+-----------+\n+ | Protocol, PFVF | 0x82 |\n+ +-----------------------------------+-----------+\n+ | Protocol, Port | 0x81 |\n+ +-----------------------------------+-----------+\n+ | Protocol | 0x80 |\n+ +-----------------------------------+-----------+\n+ | TOS, Outer VLAN, Port | 0x61 |\n+ +-----------------------------------+-----------+\n+ | TOS, Outer VLAN | 0x60 |\n+ +-----------------------------------+-----------+\n+ | TOS, Inner VLAN, Port | 0x51 |\n+ +-----------------------------------+-----------+\n+ | TOS, Inner VLAN | 0x50 |\n+ +-----------------------------------+-----------+\n+ | TOS, Ethertype, DstMAC, Port | 0x4D |\n+ +-----------------------------------+-----------+\n+ | TOS, Ethertype, DstMAC | 0x4C |\n+ +-----------------------------------+-----------+\n+ | TOS, Ethertype, Port | 0x49 |\n+ +-----------------------------------+-----------+\n+ | TOS, Ethertype | 0x48 |\n+ +-----------------------------------+-----------+\n+ | TOS, DstMAC, PFVF, Port | 0x47 |\n+ +-----------------------------------+-----------+\n+ | TOS, DstMAC, PFVF | 0x46 |\n+ +-----------------------------------+-----------+\n+ | TOS, DstMAC, Port | 0x45 |\n+ +-----------------------------------+-----------+\n+ | TOS, DstMAC | 0x44 |\n+ +-----------------------------------+-----------+\n+ | TOS, PFVF, Port | 0x43 |\n+ +-----------------------------------+-----------+\n+ | TOS, PFVF | 0x42 |\n+ +-----------------------------------+-----------+\n+ | TOS, Port | 0x41 |\n+ +-----------------------------------+-----------+\n+ | TOS | 0x40 |\n+ +-----------------------------------+-----------+\n+ | Outer VLAN, Inner VLAN, Port | 0x31 |\n+ +-----------------------------------+-----------+\n+ | Outer VLAN, Ethertype, Port | 0x29 |\n+ +-----------------------------------+-----------+\n+ | Outer VLAN, Ethertype | 0x28 |\n+ +-----------------------------------+-----------+\n+ | Outer VLAN, DstMAC, Port | 0x25 |\n+ +-----------------------------------+-----------+\n+ | Outer VLAN, DstMAC | 0x24 |\n+ +-----------------------------------+-----------+\n+ | Outer VLAN, Port | 0x21 |\n+ +-----------------------------------+-----------+\n+ | Outer VLAN | 0x20 |\n+ +-----------------------------------+-----------+\n+ | Inner VLAN, Ethertype, Port | 0x19 |\n+ +-----------------------------------+-----------+\n+ | Inner VLAN, Ethertype | 0x18 |\n+ +-----------------------------------+-----------+\n+ | Inner VLAN, DstMAC, Port | 0x15 |\n+ +-----------------------------------+-----------+\n+ | Inner VLAN, DstMAC | 0x14 |\n+ +-----------------------------------+-----------+\n+ | Inner VLAN, Port | 0x11 |\n+ +-----------------------------------+-----------+\n+ | Inner VLAN | 0x10 |\n+ +-----------------------------------+-----------+\n+ | Ethertype, DstMAC, Port | 0xD |\n+ +-----------------------------------+-----------+\n+ | Ethertype, DstMAC | 0xC |\n+ +-----------------------------------+-----------+\n+ | Ethertype, PFVF, Port | 0xB |\n+ +-----------------------------------+-----------+\n+ | Ethertype, PFVF | 0xA |\n+ +-----------------------------------+-----------+\n+ | Ethertype, Port | 0x9 |\n+ +-----------------------------------+-----------+\n+ | Ethertype | 0x8 |\n+ +-----------------------------------+-----------+\n+ | DstMAC, PFVF, Port | 0x7 |\n+ +-----------------------------------+-----------+\n+ | DstMAC, PFVF | 0x6 |\n+ +-----------------------------------+-----------+\n+ | DstMAC, Port | 0x5 |\n+ +-----------------------------------+-----------+\n+ | Destination MAC | 0x4 |\n+ +-----------------------------------+-----------+\n+ | PFVF, Port | 0x3 |\n+ +-----------------------------------+-----------+\n+ | PFVF | 0x2 |\n+ +-----------------------------------+-----------+\n+ | Physical Port | 0x1 +\n+ +-----------------------------------+-----------+\n+\n+ For example, to enable matching ``ethertype`` field in Ethernet\n+ header, and ``protocol`` field in IPv4 header, the ``filtermode``\n+ combination must be given as:\n+\n+ .. code-block:: console\n+\n+ testpmd -w 02:00.4,filtermode=0x88 -- -i\n+\n+- ``filtermask`` (default **0**)\n+\n+ ``filtermask`` devarg works similar to ``filtermode``, but is used\n+ to configure a filter mode combination for HASH (exact-match) filters.\n+\n+ .. note::\n+\n+ The combination chosen for ``filtermask`` devarg **must be a subset** of\n+ the combination chosen for ``filtermode`` devarg.\n+\n+ Default value of **0** makes driver pick the combination configured in\n+ the firmware configuration file on the adapter.\n+\n+ Note that the filter rule will only be inserted in HASH region, if the\n+ rule contains **all** the fields specified in the ``filtermask`` combination.\n+ Otherwise, the filter rule will get inserted in LETCAM region.\n+\n+ The same combination list explained in the tables in ``filtermode`` devarg\n+ section earlier applies for ``filtermask`` devarg, as well.\n+\n+ For example, to enable matching only protocol field in IPv4 header, the\n+ ``filtermask`` combination must be given as:\n+\n+ .. code-block:: console\n+\n+ testpmd -w 02:00.4,filtermode=0x88,filtermask=0x80 -- -i\n+\n .. _driver-compilation:\n \n Driver compilation and testing\n@@ -215,7 +420,7 @@ Unified Wire package for Linux operating system are as follows:\n \n .. code-block:: console\n \n- firmware-version: 1.23.4.0, TP 0.1.23.2\n+ firmware-version: 1.24.11.0, TP 0.1.23.2\n \n Running testpmd\n ~~~~~~~~~~~~~~~\n@@ -273,7 +478,7 @@ devices managed by librte_pmd_cxgbe in Linux operating system.\n EAL: PCI memory mapped at 0x7fd7c0200000\n EAL: PCI memory mapped at 0x7fd77cdfd000\n EAL: PCI memory mapped at 0x7fd7c10b7000\n- PMD: rte_cxgbe_pmd: fw: 1.23.4.0, TP: 0.1.23.2\n+ PMD: rte_cxgbe_pmd: fw: 1.24.11.0, TP: 0.1.23.2\n PMD: rte_cxgbe_pmd: Coming up as MASTER: Initializing adapter\n Interactive-mode selected\n Configuring Port 0 (socket 0)\n@@ -379,7 +584,7 @@ virtual functions.\n [...]\n EAL: PCI device 0000:02:01.0 on NUMA socket 0\n EAL: probe driver: 1425:5803 net_cxgbevf\n- PMD: rte_cxgbe_pmd: Firmware version: 1.23.4.0\n+ PMD: rte_cxgbe_pmd: Firmware version: 1.24.11.0\n PMD: rte_cxgbe_pmd: TP Microcode version: 0.1.23.2\n PMD: rte_cxgbe_pmd: Chelsio rev 0\n PMD: rte_cxgbe_pmd: No bootstrap loaded\n@@ -387,7 +592,7 @@ virtual functions.\n PMD: rte_cxgbe_pmd: 0000:02:01.0 Chelsio rev 0 1G/10GBASE-SFP\n EAL: PCI device 0000:02:01.1 on NUMA socket 0\n EAL: probe driver: 1425:5803 net_cxgbevf\n- PMD: rte_cxgbe_pmd: Firmware version: 1.23.4.0\n+ PMD: rte_cxgbe_pmd: Firmware version: 1.24.11.0\n PMD: rte_cxgbe_pmd: TP Microcode version: 0.1.23.2\n PMD: rte_cxgbe_pmd: Chelsio rev 0\n PMD: rte_cxgbe_pmd: No bootstrap loaded\n@@ -465,7 +670,7 @@ Unified Wire package for FreeBSD operating system are as follows:\n \n .. code-block:: console\n \n- dev.t5nex.0.firmware_version: 1.23.4.0\n+ dev.t5nex.0.firmware_version: 1.24.11.0\n \n Running testpmd\n ~~~~~~~~~~~~~~~\n@@ -583,7 +788,7 @@ devices managed by librte_pmd_cxgbe in FreeBSD operating system.\n EAL: PCI memory mapped at 0x8007ec000\n EAL: PCI memory mapped at 0x842800000\n EAL: PCI memory mapped at 0x80086c000\n- PMD: rte_cxgbe_pmd: fw: 1.23.4.0, TP: 0.1.23.2\n+ PMD: rte_cxgbe_pmd: fw: 1.24.11.0, TP: 0.1.23.2\n PMD: rte_cxgbe_pmd: Coming up as MASTER: Initializing adapter\n Interactive-mode selected\n Configuring Port 0 (socket 0)\ndiff --git a/drivers/net/cxgbe/base/adapter.h b/drivers/net/cxgbe/base/adapter.h\nindex ae318ccf5..62de35c7c 100644\n--- a/drivers/net/cxgbe/base/adapter.h\n+++ b/drivers/net/cxgbe/base/adapter.h\n@@ -309,6 +309,8 @@ struct adapter_devargs {\n \tbool keep_ovlan;\n \tbool force_link_up;\n \tbool tx_mode_latency;\n+\tu32 filtermode;\n+\tu32 filtermask;\n };\n \n struct adapter {\ndiff --git a/drivers/net/cxgbe/base/t4fw_interface.h b/drivers/net/cxgbe/base/t4fw_interface.h\nindex 46d087a09..0032178d0 100644\n--- a/drivers/net/cxgbe/base/t4fw_interface.h\n+++ b/drivers/net/cxgbe/base/t4fw_interface.h\n@@ -674,12 +674,16 @@ enum fw_params_mnem {\n \n #define S_FW_PARAMS_PARAM_FILTER_MODE 16\n #define M_FW_PARAMS_PARAM_FILTER_MODE 0xffff\n+#define V_FW_PARAMS_PARAM_FILTER_MODE(x) \\\n+\t((x) << S_FW_PARAMS_PARAM_FILTER_MODE)\n #define G_FW_PARAMS_PARAM_FILTER_MODE(x) \\\n \t(((x) >> S_FW_PARAMS_PARAM_FILTER_MODE) & \\\n \tM_FW_PARAMS_PARAM_FILTER_MODE)\n \n #define S_FW_PARAMS_PARAM_FILTER_MASK 0\n #define M_FW_PARAMS_PARAM_FILTER_MASK 0xffff\n+#define V_FW_PARAMS_PARAM_FILTER_MASK(x) \\\n+\t((x) << S_FW_PARAMS_PARAM_FILTER_MASK)\n #define G_FW_PARAMS_PARAM_FILTER_MASK(x) \\\n \t(((x) >> S_FW_PARAMS_PARAM_FILTER_MASK) & \\\n \tM_FW_PARAMS_PARAM_FILTER_MASK)\n@@ -725,6 +729,7 @@ enum fw_params_param_dmaq {\n };\n \n enum fw_params_param_dev_filter {\n+\tFW_PARAM_DEV_FILTER_VNIC_MODE = 0x00,\n \tFW_PARAM_DEV_FILTER_MODE_MASK = 0x01,\n };\n \ndiff --git a/drivers/net/cxgbe/cxgbe.h b/drivers/net/cxgbe/cxgbe.h\nindex 75a2e9931..0bf6061c0 100644\n--- a/drivers/net/cxgbe/cxgbe.h\n+++ b/drivers/net/cxgbe/cxgbe.h\n@@ -51,6 +51,25 @@\n \t\t\t DEV_RX_OFFLOAD_SCATTER | \\\n \t\t\t DEV_RX_OFFLOAD_RSS_HASH)\n \n+/* Devargs filtermode and filtermask representation */\n+enum cxgbe_devargs_filter_mode_flags {\n+\tCXGBE_DEVARGS_FILTER_MODE_PHYSICAL_PORT = (1 << 0),\n+\tCXGBE_DEVARGS_FILTER_MODE_PF_VF = (1 << 1),\n+\n+\tCXGBE_DEVARGS_FILTER_MODE_ETHERNET_DSTMAC = (1 << 2),\n+\tCXGBE_DEVARGS_FILTER_MODE_ETHERNET_ETHTYPE = (1 << 3),\n+\tCXGBE_DEVARGS_FILTER_MODE_VLAN_INNER = (1 << 4),\n+\tCXGBE_DEVARGS_FILTER_MODE_VLAN_OUTER = (1 << 5),\n+\tCXGBE_DEVARGS_FILTER_MODE_IP_TOS = (1 << 6),\n+\tCXGBE_DEVARGS_FILTER_MODE_IP_PROTOCOL = (1 << 7),\n+\tCXGBE_DEVARGS_FILTER_MODE_MAX = (1 << 8),\n+};\n+\n+enum cxgbe_filter_vnic_mode {\n+\tCXGBE_FILTER_VNIC_MODE_NONE,\n+\tCXGBE_FILTER_VNIC_MODE_PFVF,\n+\tCXGBE_FILTER_VNIC_MODE_OVLAN,\n+};\n \n /* Common PF and VF devargs */\n #define CXGBE_DEVARG_CMN_KEEP_OVLAN \"keep_ovlan\"\n@@ -59,6 +78,10 @@\n /* VF only devargs */\n #define CXGBE_DEVARG_VF_FORCE_LINK_UP \"force_link_up\"\n \n+/* Filter Mode/Mask devargs */\n+#define CXGBE_DEVARG_PF_FILTER_MODE \"filtermode\"\n+#define CXGBE_DEVARG_PF_FILTER_MASK \"filtermask\"\n+\n bool cxgbe_force_linkup(struct adapter *adap);\n int cxgbe_probe(struct adapter *adapter);\n int cxgbevf_probe(struct adapter *adapter);\ndiff --git a/drivers/net/cxgbe/cxgbe_ethdev.c b/drivers/net/cxgbe/cxgbe_ethdev.c\nindex 51b63ef57..1deee2f5c 100644\n--- a/drivers/net/cxgbe/cxgbe_ethdev.c\n+++ b/drivers/net/cxgbe/cxgbe_ethdev.c\n@@ -1244,7 +1244,9 @@ RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);\n RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, \"* igb_uio | uio_pci_generic | vfio-pci\");\n RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe,\n \t\t\t CXGBE_DEVARG_CMN_KEEP_OVLAN \"=<0|1> \"\n-\t\t\t CXGBE_DEVARG_CMN_TX_MODE_LATENCY \"=<0|1> \");\n+\t\t\t CXGBE_DEVARG_CMN_TX_MODE_LATENCY \"=<0|1> \"\n+\t\t\t CXGBE_DEVARG_PF_FILTER_MODE \"=<uint32> \"\n+\t\t\t CXGBE_DEVARG_PF_FILTER_MASK \"=<uint32> \");\n \n RTE_INIT(cxgbe_init_log)\n {\ndiff --git a/drivers/net/cxgbe/cxgbe_main.c b/drivers/net/cxgbe/cxgbe_main.c\nindex df54e54f5..a541d95cc 100644\n--- a/drivers/net/cxgbe/cxgbe_main.c\n+++ b/drivers/net/cxgbe/cxgbe_main.c\n@@ -43,6 +43,77 @@\n #include \"smt.h\"\n #include \"mps_tcam.h\"\n \n+static const u16 cxgbe_filter_mode_features[] = {\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE |\n+\t F_PROTOCOL | F_PORT),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE |\n+\t F_PROTOCOL | F_FCOE),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_TOS |\n+\t F_PORT),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_TOS |\n+\t F_FCOE),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_PORT |\n+\t F_FCOE),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_TOS |\n+\t F_PORT | F_FCOE),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_VLAN |\n+\t F_FCOE),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_VNIC_ID |\n+\t F_FCOE),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_TOS | F_VLAN |\n+\t F_FCOE),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_TOS | F_VNIC_ID |\n+\t F_FCOE),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_VLAN | F_PORT |\n+\t F_FCOE),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_VNIC_ID | F_PORT |\n+\t F_FCOE),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_PROTOCOL | F_TOS |\n+\t F_PORT | F_FCOE),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_VLAN | F_PORT),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_VLAN | F_FCOE),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_VNIC_ID | F_PORT),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_VNIC_ID | F_FCOE),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VLAN | F_PORT),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VLAN | F_FCOE),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VNIC_ID |\n+\t F_PORT),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VNIC_ID |\n+\t F_FCOE),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_VLAN | F_PORT |\n+\t F_FCOE),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_VNIC_ID | F_PORT |\n+\t F_FCOE),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_TOS | F_VLAN | F_PORT | F_FCOE),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_TOS | F_VNIC_ID | F_PORT | F_FCOE),\n+\t(F_FRAGMENTATION | F_MPSHITTYPE | F_VLAN | F_VNIC_ID | F_FCOE),\n+\t(F_FRAGMENTATION | F_MACMATCH | F_ETHERTYPE | F_PROTOCOL | F_PORT |\n+\t F_FCOE),\n+\t(F_FRAGMENTATION | F_MACMATCH | F_ETHERTYPE | F_TOS | F_PORT | F_FCOE),\n+\t(F_FRAGMENTATION | F_MACMATCH | F_PROTOCOL | F_VLAN | F_PORT | F_FCOE),\n+\t(F_FRAGMENTATION | F_MACMATCH | F_PROTOCOL | F_VNIC_ID | F_PORT |\n+\t F_FCOE),\n+\t(F_FRAGMENTATION | F_MACMATCH | F_TOS | F_VLAN | F_PORT | F_FCOE),\n+\t(F_FRAGMENTATION | F_MACMATCH | F_TOS | F_VNIC_ID | F_PORT | F_FCOE),\n+\t(F_FRAGMENTATION | F_ETHERTYPE | F_VLAN | F_PORT | F_FCOE),\n+\t(F_FRAGMENTATION | F_ETHERTYPE | F_VNIC_ID | F_PORT | F_FCOE),\n+\t(F_FRAGMENTATION | F_PROTOCOL | F_TOS | F_VLAN | F_FCOE),\n+\t(F_FRAGMENTATION | F_PROTOCOL | F_TOS | F_VNIC_ID | F_FCOE),\n+\t(F_FRAGMENTATION | F_VLAN | F_VNIC_ID | F_PORT | F_FCOE),\n+\t(F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_PROTOCOL | F_PORT |\n+\t F_FCOE),\n+\t(F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_TOS | F_PORT | F_FCOE),\n+\t(F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_VLAN | F_PORT),\n+\t(F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_VNIC_ID | F_PORT),\n+\t(F_MPSHITTYPE | F_MACMATCH | F_TOS | F_VLAN | F_PORT),\n+\t(F_MPSHITTYPE | F_MACMATCH | F_TOS | F_VNIC_ID | F_PORT),\n+\t(F_MPSHITTYPE | F_ETHERTYPE | F_VLAN | F_PORT | F_FCOE),\n+\t(F_MPSHITTYPE | F_ETHERTYPE | F_VNIC_ID | F_PORT | F_FCOE),\n+\t(F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VLAN | F_PORT | F_FCOE),\n+\t(F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VNIC_ID | F_PORT | F_FCOE),\n+\t(F_MPSHITTYPE | F_VLAN | F_VNIC_ID | F_PORT),\n+};\n+\n /**\n * Allocate a chunk of memory. The allocated memory is cleared.\n */\n@@ -687,6 +758,19 @@ static int check_devargs_handler(const char *key, const char *value, void *p)\n \t\t}\n \t}\n \n+\tif (!strncmp(key, CXGBE_DEVARG_PF_FILTER_MODE, strlen(key)) ||\n+\t !strncmp(key, CXGBE_DEVARG_PF_FILTER_MASK, strlen(key))) {\n+\t\tu32 *dst_val = (u32 *)p;\n+\t\tchar *endptr = NULL;\n+\t\tu32 arg_val;\n+\n+\t\targ_val = strtoul(value, &endptr, 16);\n+\t\tif (errno || endptr == value)\n+\t\t\treturn -EINVAL;\n+\n+\t\t*dst_val = arg_val;\n+\t}\n+\n \treturn 0;\n }\n \n@@ -732,6 +816,24 @@ static void cxgbe_get_devargs_int(struct adapter *adap, bool *dst,\n \t*dst = devarg_value;\n }\n \n+static void cxgbe_get_devargs_u32(struct adapter *adap, u32 *dst,\n+\t\t\t\t const char *key, u32 default_value)\n+{\n+\tstruct rte_pci_device *pdev = adap->pdev;\n+\tu32 devarg_value = default_value;\n+\tint ret;\n+\n+\t*dst = default_value;\n+\tif (!pdev)\n+\t\treturn;\n+\n+\tret = cxgbe_get_devargs(pdev->device.devargs, key, &devarg_value);\n+\tif (ret)\n+\t\treturn;\n+\n+\t*dst = devarg_value;\n+}\n+\n void cxgbe_process_devargs(struct adapter *adap)\n {\n \tcxgbe_get_devargs_int(adap, &adap->devargs.keep_ovlan,\n@@ -740,6 +842,10 @@ void cxgbe_process_devargs(struct adapter *adap)\n \t\t\t CXGBE_DEVARG_CMN_TX_MODE_LATENCY, false);\n \tcxgbe_get_devargs_int(adap, &adap->devargs.force_link_up,\n \t\t\t CXGBE_DEVARG_VF_FORCE_LINK_UP, false);\n+\tcxgbe_get_devargs_u32(adap, &adap->devargs.filtermode,\n+\t\t\t CXGBE_DEVARG_PF_FILTER_MODE, 0);\n+\tcxgbe_get_devargs_u32(adap, &adap->devargs.filtermask,\n+\t\t\t CXGBE_DEVARG_PF_FILTER_MASK, 0);\n }\n \n static void configure_vlan_types(struct adapter *adapter)\n@@ -776,6 +882,134 @@ static void configure_vlan_types(struct adapter *adapter)\n \t\t\t V_RM_OVLAN(!adapter->devargs.keep_ovlan));\n }\n \n+static int cxgbe_get_filter_vnic_mode_from_devargs(u32 val)\n+{\n+\tu32 vnic_mode;\n+\n+\tvnic_mode = val & (CXGBE_DEVARGS_FILTER_MODE_PF_VF |\n+\t\t\t CXGBE_DEVARGS_FILTER_MODE_VLAN_OUTER);\n+\tif (vnic_mode) {\n+\t\tswitch (vnic_mode) {\n+\t\tcase CXGBE_DEVARGS_FILTER_MODE_VLAN_OUTER:\n+\t\t\treturn CXGBE_FILTER_VNIC_MODE_OVLAN;\n+\t\tcase CXGBE_DEVARGS_FILTER_MODE_PF_VF:\n+\t\t\treturn CXGBE_FILTER_VNIC_MODE_PFVF;\n+\t\tdefault:\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\treturn CXGBE_FILTER_VNIC_MODE_NONE;\n+}\n+\n+static int cxgbe_get_filter_mode_from_devargs(u32 val, bool closest_match)\n+{\n+\tint vnic_mode, fmode = 0;\n+\tbool found = false;\n+\tu8 i;\n+\n+\tif (val >= CXGBE_DEVARGS_FILTER_MODE_MAX) {\n+\t\tpr_err(\"Unsupported flags set in filter mode. Must be < 0x%x\\n\",\n+\t\t CXGBE_DEVARGS_FILTER_MODE_MAX);\n+\t\treturn -ERANGE;\n+\t}\n+\n+\tvnic_mode = cxgbe_get_filter_vnic_mode_from_devargs(val);\n+\tif (vnic_mode < 0) {\n+\t\tpr_err(\"Unsupported Vnic-mode, more than 1 Vnic-mode selected\\n\");\n+\t\treturn vnic_mode;\n+\t}\n+\n+\tif (vnic_mode)\n+\t\tfmode |= F_VNIC_ID;\n+\tif (val & CXGBE_DEVARGS_FILTER_MODE_PHYSICAL_PORT)\n+\t\tfmode |= F_PORT;\n+\tif (val & CXGBE_DEVARGS_FILTER_MODE_ETHERNET_DSTMAC)\n+\t\tfmode |= F_MACMATCH;\n+\tif (val & CXGBE_DEVARGS_FILTER_MODE_ETHERNET_ETHTYPE)\n+\t\tfmode |= F_ETHERTYPE;\n+\tif (val & CXGBE_DEVARGS_FILTER_MODE_VLAN_INNER)\n+\t\tfmode |= F_VLAN;\n+\tif (val & CXGBE_DEVARGS_FILTER_MODE_IP_TOS)\n+\t\tfmode |= F_TOS;\n+\tif (val & CXGBE_DEVARGS_FILTER_MODE_IP_PROTOCOL)\n+\t\tfmode |= F_PROTOCOL;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(cxgbe_filter_mode_features); i++) {\n+\t\tif ((cxgbe_filter_mode_features[i] & fmode) == fmode) {\n+\t\t\tfound = true;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (!found)\n+\t\treturn -EINVAL;\n+\n+\treturn closest_match ? cxgbe_filter_mode_features[i] : fmode;\n+}\n+\n+static int configure_filter_mode_mask(struct adapter *adap)\n+{\n+\tu32 params[2], val[2], nparams = 0;\n+\tint ret;\n+\n+\tif (!adap->devargs.filtermode && !adap->devargs.filtermask)\n+\t\treturn 0;\n+\n+\tif (!adap->devargs.filtermode || !adap->devargs.filtermask) {\n+\t\tpr_err(\"Unsupported, Provide both filtermode and filtermask devargs\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (adap->devargs.filtermask & ~adap->devargs.filtermode) {\n+\t\tpr_err(\"Unsupported, filtermask (0x%x) must be subset of filtermode (0x%x)\\n\",\n+\t\t adap->devargs.filtermask, adap->devargs.filtermode);\n+\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tparams[0] = CXGBE_FW_PARAM_DEV(FILTER) |\n+\t\t V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK);\n+\n+\tret = cxgbe_get_filter_mode_from_devargs(adap->devargs.filtermode,\n+\t\t\t\t\t\t true);\n+\tif (ret < 0) {\n+\t\tpr_err(\"Unsupported filtermode devargs combination:0x%x\\n\",\n+\t\t adap->devargs.filtermode);\n+\t\treturn ret;\n+\t}\n+\n+\tval[0] = V_FW_PARAMS_PARAM_FILTER_MODE(ret);\n+\n+\tret = cxgbe_get_filter_mode_from_devargs(adap->devargs.filtermask,\n+\t\t\t\t\t\t false);\n+\tif (ret < 0) {\n+\t\tpr_err(\"Unsupported filtermask devargs combination:0x%x\\n\",\n+\t\t adap->devargs.filtermask);\n+\t\treturn ret;\n+\t}\n+\n+\tval[0] |= V_FW_PARAMS_PARAM_FILTER_MASK(ret);\n+\n+\tnparams++;\n+\n+\tret = cxgbe_get_filter_vnic_mode_from_devargs(adap->devargs.filtermode);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tif (ret) {\n+\t\tparams[1] = CXGBE_FW_PARAM_DEV(FILTER) |\n+\t\t\t V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE);\n+\n+\t\tval[1] = ret - 1;\n+\n+\t\tnparams++;\n+\t}\n+\n+\treturn t4_set_params(adap, adap->mbox, adap->pf, 0, nparams,\n+\t\t\t params, val);\n+}\n+\n static void configure_pcie_ext_tag(struct adapter *adapter)\n {\n \tu16 v;\n@@ -1300,6 +1534,9 @@ static int adap_init0(struct adapter *adap)\n \t\t\t adap->params.b_wnd);\n \t}\n \tt4_init_sge_params(adap);\n+\tret = configure_filter_mode_mask(adap);\n+\tif (ret < 0)\n+\t\tgoto bye;\n \tt4_init_tp_params(adap);\n \tconfigure_pcie_ext_tag(adap);\n \tconfigure_vlan_types(adap);\n", "prefixes": [ "9/9" ] }