Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/66439/?format=api
{ "id": 66439, "url": "http://patches.dpdk.org/api/patches/66439/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200309114357.31800-23-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200309114357.31800-23-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200309114357.31800-23-qi.z.zhang@intel.com", "date": "2020-03-09T11:43:51", "name": "[22/28] net/ice/base: couple casting issue fixes", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0a3ba19edb261e426d3294b5d43ff84c95b3743b", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 31221, "url": "http://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200309114357.31800-23-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 8843, "url": "http://patches.dpdk.org/api/series/8843/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8843", "date": "2020-03-09T11:43:29", "name": "update ice base code", "version": 1, "mbox": "http://patches.dpdk.org/series/8843/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/66439/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/66439/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 72E91A054E;\n\tMon, 9 Mar 2020 12:44:05 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 36B3A1C1B6;\n\tMon, 9 Mar 2020 12:41:16 +0100 (CET)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by dpdk.org (Postfix) with ESMTP id 5DC891C1AF\n for <dev@dpdk.org>; Mon, 9 Mar 2020 12:41:14 +0100 (CET)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 09 Mar 2020 04:41:13 -0700", "from dpdk51.sh.intel.com ([10.67.110.245])\n by fmsmga002.fm.intel.com with ESMTP; 09 Mar 2020 04:41:12 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.70,533,1574150400\"; d=\"scan'208\";a=\"276483637\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com,\n\tbeilei.xing@intel.com", "Cc": "xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 9 Mar 2020 19:43:51 +0800", "Message-Id": "<20200309114357.31800-23-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20200309114357.31800-1-qi.z.zhang@intel.com>", "References": "<20200309114357.31800-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 22/28] net/ice/base: couple casting issue fixes", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Adjust variable size between u8 and u16 to fix casting issues\nAlso fix couple coding style issues\n\nKarol Kolacinski <karol.kolacinski@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h | 9 ++++----\n drivers/net/ice/base/ice_common.c | 4 ++--\n drivers/net/ice/base/ice_common.h | 2 +-\n drivers/net/ice/base/ice_controlq.c | 18 +++++++--------\n drivers/net/ice/base/ice_flex_pipe.c | 22 ++++++++++---------\n drivers/net/ice/base/ice_flex_pipe.h | 4 ++--\n drivers/net/ice/base/ice_switch.c | 41 +++++++++++++++++------------------\n drivers/net/ice/base/ice_type.h | 4 ++--\n 8 files changed, 52 insertions(+), 52 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex 3ab76a3fd..73f5e7090 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -682,7 +682,7 @@ struct ice_aqc_recipe_content {\n #define ICE_AQ_RECIPE_ID_S\t\t0\n #define ICE_AQ_RECIPE_ID_M\t\t(0x3F << ICE_AQ_RECIPE_ID_S)\n #define ICE_AQ_RECIPE_ID_IS_ROOT\tBIT(7)\n-#define ICE_AQ_SW_ID_LKUP_IDX\t\t0\n+#define\tICE_AQ_SW_ID_LKUP_IDX\t\t0\n \tu8 lkup_indx[5];\n #define ICE_AQ_RECIPE_LKUP_DATA_S\t0\n #define ICE_AQ_RECIPE_LKUP_DATA_M\t(0x3F << ICE_AQ_RECIPE_LKUP_DATA_S)\n@@ -813,7 +813,7 @@ struct ice_sw_rule_lkup_rx_tx {\n #define ICE_SINGLE_ACT_OTHER_ACTS\t\t0x3\n #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S\t17\n #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M\t\\\n-\t\t\t\t(0x3 << \\ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)\n+\t\t\t\t(0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)\n \n \t/* Bit 17:18 - Defines other actions */\n \t/* Other action = 0 - Mirror VSI */\n@@ -2118,9 +2118,7 @@ struct ice_aqc_move_txqs {\n \t__le32 addr_low;\n };\n \n-/* This is the descriptor of each queue entry for the move Tx LAN Queues\n- * command (0x0C32).\n- */\n+/* Per-queue data buffer for the Move Tx LAN Queues command/response */\n struct ice_aqc_move_txqs_elem {\n \t__le16 txq_id;\n \tu8 q_cgd;\n@@ -2128,6 +2126,7 @@ struct ice_aqc_move_txqs_elem {\n \t__le32 q_teid;\n };\n \n+/* Indirect data buffer for the Move Tx LAN Queues command/response */\n struct ice_aqc_move_txqs_data {\n \t__le32 src_teid;\n \t__le32 dest_teid;\ndiff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex 99f696211..25e205944 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -4004,7 +4004,7 @@ ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,\n * This function adds/updates the VSI queues per TC.\n */\n static enum ice_status\n-ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,\n+ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,\n \t u16 *maxqs, u8 owner)\n {\n \tenum ice_status status = ICE_SUCCESS;\n@@ -4043,7 +4043,7 @@ ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,\n * This function adds/updates the VSI LAN queues per TC.\n */\n enum ice_status\n-ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,\n+ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,\n \t\tu16 *max_lanqs)\n {\n \treturn ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,\ndiff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h\nindex bbff17536..4e2e25744 100644\n--- a/drivers/net/ice/base/ice_common.h\n+++ b/drivers/net/ice/base/ice_common.h\n@@ -188,7 +188,7 @@ ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,\n \t\tenum ice_disq_rst_src rst_src, u16 vmvf_num,\n \t\tstruct ice_sq_cd *cd);\n enum ice_status\n-ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,\n+ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,\n \t\tu16 *max_lanqs);\n enum ice_status\n ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,\ndiff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c\nindex 8a65fae40..e7752fca2 100644\n--- a/drivers/net/ice/base/ice_controlq.c\n+++ b/drivers/net/ice/base/ice_controlq.c\n@@ -624,18 +624,18 @@ static enum ice_status ice_init_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type)\n */\n enum ice_status ice_init_all_ctrlq(struct ice_hw *hw)\n {\n-\tenum ice_status ret_code;\n+\tenum ice_status status;\n \n \tice_debug(hw, ICE_DBG_TRACE, \"%s\\n\", __func__);\n \n \t/* Init FW admin queue */\n-\tret_code = ice_init_ctrlq(hw, ICE_CTL_Q_ADMIN);\n-\tif (ret_code)\n-\t\treturn ret_code;\n+\tstatus = ice_init_ctrlq(hw, ICE_CTL_Q_ADMIN);\n+\tif (status)\n+\t\treturn status;\n \n-\tret_code = ice_init_check_adminq(hw);\n-\tif (ret_code)\n-\t\treturn ret_code;\n+\tstatus = ice_init_check_adminq(hw);\n+\tif (status)\n+\t\treturn status;\n \t/* Init Mailbox queue */\n \treturn ice_init_ctrlq(hw, ICE_CTL_Q_MAILBOX);\n }\n@@ -832,7 +832,7 @@ static void ice_debug_cq(struct ice_hw *hw, void *desc, void *buf, u16 buf_len)\n \t flags & ICE_AQ_FLAG_RD)) {\n \t\tice_debug(hw, ICE_DBG_AQ_DESC_BUF, \"Buffer:\\n\");\n \t\tice_debug_array(hw, ICE_DBG_AQ_DESC_BUF, 16, 1, (u8 *)buf,\n-\t\t\t\tmin(buf_len, datalen));\n+\t\t\t\tMIN_T(u16, buf_len, datalen));\n \t}\n }\n \n@@ -1140,7 +1140,7 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n \t}\n \tice_memcpy(&e->desc, desc, sizeof(e->desc), ICE_DMA_TO_NONDMA);\n \tdatalen = LE16_TO_CPU(desc->datalen);\n-\te->msg_len = min(datalen, e->buf_len);\n+\te->msg_len = MIN_T(u16, datalen, e->buf_len);\n \tif (e->msg_buf && e->msg_len)\n \t\tice_memcpy(e->msg_buf, cq->rq.r.rq_bi[desc_idx].va,\n \t\t\t e->msg_len, ICE_DMA_TO_NONDMA);\ndiff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c\nindex 2e64adbe4..1ad7026c7 100644\n--- a/drivers/net/ice/base/ice_flex_pipe.c\n+++ b/drivers/net/ice/base/ice_flex_pipe.c\n@@ -1562,7 +1562,7 @@ ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type req_profs,\n * allocated for every list entry.\n */\n enum ice_status\n-ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt,\n+ice_get_sw_fv_list(struct ice_hw *hw, u8 *prot_ids, u8 ids_cnt,\n \t\t ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list)\n {\n \tstruct ice_sw_fv_list_entry *fvl;\n@@ -1961,7 +1961,7 @@ ice_create_tunnel(struct ice_hw *hw, enum ice_tunnel_type type, u16 port)\n \t */\n \tice_set_key((u8 *)§_rx->tcam[0].key, sizeof(sect_rx->tcam[0].key),\n \t\t (u8 *)&port, NULL, NULL, NULL,\n-\t\t offsetof(struct ice_boost_key_value, hv_dst_port_key),\n+\t\t (u16)offsetof(struct ice_boost_key_value, hv_dst_port_key),\n \t\t sizeof(sect_rx->tcam[0].key.key.hv_dst_port_key));\n \n \t/* exact copy of entry to Tx section entry */\n@@ -2009,7 +2009,7 @@ enum ice_status ice_destroy_tunnel(struct ice_hw *hw, u16 port, bool all)\n \t\treturn ICE_ERR_PARAM;\n \n \t/* size of section - there is at least one entry */\n-\tsize = (count - 1) * sizeof(*sect_rx->tcam) + sizeof(*sect_rx);\n+\tsize = ice_struct_size(sect_rx, tcam, count - 1);\n \n \tbld = ice_pkg_buf_alloc(hw);\n \tif (!bld)\n@@ -2076,7 +2076,7 @@ enum ice_status ice_destroy_tunnel(struct ice_hw *hw, u16 port, bool all)\n * @off: variable to receive the protocol offset\n */\n enum ice_status\n-ice_find_prot_off(struct ice_hw *hw, enum ice_block blk, u8 prof, u8 fv_idx,\n+ice_find_prot_off(struct ice_hw *hw, enum ice_block blk, u8 prof, u16 fv_idx,\n \t\t u8 *prot, u16 *off)\n {\n \tstruct ice_fv_word *fv_ext;\n@@ -2678,9 +2678,9 @@ ice_find_prof_id_with_mask(struct ice_hw *hw, enum ice_block blk,\n \t\t\t struct ice_fv_word *fv, u16 *masks, u8 *prof_id)\n {\n \tstruct ice_es *es = &hw->blk[blk].es;\n-\tu16 i;\n+\tu8 i;\n \n-\tfor (i = 0; i < es->count; i++) {\n+\tfor (i = 0; i < (u8)es->count; i++) {\n \t\tu16 off = i * es->fvw;\n \n \t\tif (memcmp(&es->t[off], fv, es->fvw * sizeof(*fv)))\n@@ -4462,7 +4462,7 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],\n \tice_declare_bitmap(ptgs_used, ICE_XLT1_CNT);\n \tstruct ice_prof_map *prof;\n \tenum ice_status status;\n-\tu32 byte = 0;\n+\tu8 byte = 0;\n \tu8 prof_id;\n \n \tice_zero_bitmap(ptgs_used, ICE_XLT1_CNT);\n@@ -4511,7 +4511,7 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],\n \n \t/* build list of ptgs */\n \twhile (bytes && prof->ptg_cnt < ICE_MAX_PTG_PER_PROFILE) {\n-\t\tu32 bit;\n+\t\tu8 bit;\n \n \t\tif (!ptypes[byte]) {\n \t\t\tbytes--;\n@@ -4560,7 +4560,7 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],\n \t\t\t\t}\n \n \t\t\t\t/* nothing left in byte, then exit */\n-\t\t\t\tm = ~((1 << (bit + 1)) - 1);\n+\t\t\t\tm = ~(u8)((1 << (bit + 1)) - 1);\n \t\t\t\tif (!(ptypes[byte] & m))\n \t\t\t\t\tbreak;\n \t\t\t}\n@@ -5333,8 +5333,10 @@ ice_add_prof_id_vsig(struct ice_hw *hw, enum ice_block blk, u16 vsig, u64 hdl,\n \t\t\t\t\t t->tcam[i].ptg, vsig, 0,\n \t\t\t\t\t t->tcam[i].attr.flags, vl_msk,\n \t\t\t\t\t dc_msk, nm_msk);\n-\t\tif (status)\n+\t\tif (status) {\n+\t\t\tice_free(hw, p);\n \t\t\tgoto err_ice_add_prof_id_vsig;\n+\t\t}\n \n \t\t/* log change */\n \t\tLIST_ADD(&p->list_entry, chg);\ndiff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h\nindex fa72e386d..107f7e498 100644\n--- a/drivers/net/ice/base/ice_flex_pipe.h\n+++ b/drivers/net/ice/base/ice_flex_pipe.h\n@@ -25,7 +25,7 @@ enum ice_status\n ice_acquire_change_lock(struct ice_hw *hw, enum ice_aq_res_access_type access);\n void ice_release_change_lock(struct ice_hw *hw);\n enum ice_status\n-ice_find_prot_off(struct ice_hw *hw, enum ice_block blk, u8 prof, u8 fv_idx,\n+ice_find_prot_off(struct ice_hw *hw, enum ice_block blk, u8 prof, u16 fv_idx,\n \t\t u8 *prot, u16 *off);\n enum ice_status\n ice_find_label_value(struct ice_seg *ice_seg, char const *name, u32 type,\n@@ -36,7 +36,7 @@ ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type type,\n void\n ice_init_prof_result_bm(struct ice_hw *hw);\n enum ice_status\n-ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt,\n+ice_get_sw_fv_list(struct ice_hw *hw, u8 *prot_ids, u8 ids_cnt,\n \t\t ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list);\n bool\n ice_get_open_tunnel_port(struct ice_hw *hw, enum ice_tunnel_type type,\ndiff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c\nindex 225842dc1..935c6954e 100644\n--- a/drivers/net/ice/base/ice_switch.c\n+++ b/drivers/net/ice/base/ice_switch.c\n@@ -623,8 +623,9 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,\n \tstruct ice_aqc_recipe_data_elem *tmp;\n \tu16 num_recps = ICE_MAX_NUM_RECIPES;\n \tstruct ice_prot_lkup_ext *lkup_exts;\n-\tu16 i, sub_recps, fv_word_idx = 0;\n \tenum ice_status status;\n+\tu8 fv_word_idx = 0;\n+\tu16 sub_recps;\n \n \tice_zero_bitmap(result_bm, ICE_MAX_FV_WORDS);\n \n@@ -662,7 +663,7 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,\n \tfor (sub_recps = 0; sub_recps < num_recps; sub_recps++) {\n \t\tstruct ice_aqc_recipe_data_elem root_bufs = tmp[sub_recps];\n \t\tstruct ice_recp_grp_entry *rg_entry;\n-\t\tu8 prof, idx, prot = 0;\n+\t\tu8 i, prof, idx, prot = 0;\n \t\tbool is_root;\n \t\tu16 off = 0;\n \n@@ -718,7 +719,7 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,\n \t\tLIST_ADD(&rg_entry->l_entry, &recps[rid].rg_list);\n \n \t\t/* Propagate some data to the recipe database */\n-\t\trecps[idx].is_root = is_root;\n+\t\trecps[idx].is_root = !!is_root;\n \t\trecps[idx].priority = root_bufs.content.act_ctrl_fwd_priority;\n \t\tice_zero_bitmap(recps[idx].res_idxs, ICE_MAX_FV_WORDS);\n \t\tif (root_bufs.content.result_indx & ICE_AQ_RECIPE_RESULT_EN) {\n@@ -1842,10 +1843,10 @@ enum ice_status ice_get_initial_sw_cfg(struct ice_hw *hw)\n {\n \tstruct ice_aqc_get_sw_cfg_resp *rbuf;\n \tenum ice_status status;\n-\tu16 num_total_ports;\n+\tu8 num_total_ports;\n \tu16 req_desc = 0;\n \tu16 num_elems;\n-\tu16 j = 0;\n+\tu8 j = 0;\n \tu16 i;\n \n \tnum_total_ports = 1;\n@@ -3124,11 +3125,11 @@ ice_add_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list,\n \tstruct ice_aqc_sw_rules_elem *s_rule, *r_iter;\n \tstruct ice_fltr_list_entry *m_list_itr;\n \tstruct LIST_HEAD_TYPE *rule_head;\n-\tu16 elem_sent, total_elem_left;\n+\tu16 total_elem_left, s_rule_size;\n \tstruct ice_lock *rule_lock; /* Lock to protect filter rule list */\n \tenum ice_status status = ICE_SUCCESS;\n \tu16 num_unicast = 0;\n-\tu16 s_rule_size;\n+\tu8 elem_sent;\n \n \ts_rule = NULL;\n \trule_lock = &recp_list->filt_rule_lock;\n@@ -3210,8 +3211,8 @@ ice_add_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list,\n \t total_elem_left -= elem_sent) {\n \t\tstruct ice_aqc_sw_rules_elem *entry = r_iter;\n \n-\t\telem_sent = min(total_elem_left,\n-\t\t\t\t(u16)(ICE_AQ_MAX_BUF_LEN / s_rule_size));\n+\t\telem_sent = MIN_T(u8, total_elem_left,\n+\t\t\t\t (ICE_AQ_MAX_BUF_LEN / s_rule_size));\n \t\tstatus = ice_aq_sw_rules(hw, entry, elem_sent * s_rule_size,\n \t\t\t\t\t elem_sent, ice_aqc_opc_add_sw_rules,\n \t\t\t\t\t NULL);\n@@ -4943,7 +4944,7 @@ static u16 ice_find_recp(struct ice_hw *hw, struct ice_prot_lkup_ext *lkup_exts)\n {\n \tbool refresh_required = true;\n \tstruct ice_sw_recipe *recp;\n-\tu16 i;\n+\tu8 i;\n \n \t/* Walk through existing recipes to find a match */\n \trecp = hw->switch_info->recp_list;\n@@ -5009,9 +5010,9 @@ static u16 ice_find_recp(struct ice_hw *hw, struct ice_prot_lkup_ext *lkup_exts)\n *\n * Returns true if found, false otherwise\n */\n-static bool ice_prot_type_to_id(enum ice_protocol_type type, u16 *id)\n+static bool ice_prot_type_to_id(enum ice_protocol_type type, u8 *id)\n {\n-\tu16 i;\n+\tu8 i;\n \n \tfor (i = 0; i < ARRAY_SIZE(ice_prot_id_tbl); i++)\n \t\tif (ice_prot_id_tbl[i].type == type) {\n@@ -5028,13 +5029,11 @@ static bool ice_prot_type_to_id(enum ice_protocol_type type, u16 *id)\n *\n * calculate valid words in a lookup rule using mask value\n */\n-static u16\n+static u8\n ice_fill_valid_words(struct ice_adv_lkup_elem *rule,\n \t\t struct ice_prot_lkup_ext *lkup_exts)\n {\n-\tu16 j, word = 0;\n-\tu16 prot_id;\n-\tu16 ret_val;\n+\tu8 j, word, prot_id, ret_val;\n \n \tif (!ice_prot_type_to_id(rule->type, &prot_id))\n \t\treturn 0;\n@@ -5043,7 +5042,7 @@ ice_fill_valid_words(struct ice_adv_lkup_elem *rule,\n \n \tfor (j = 0; j < sizeof(rule->m_u) / sizeof(u16); j++)\n \t\tif (((u16 *)&rule->m_u)[j] &&\n-\t\t (unsigned long)rule->type < ARRAY_SIZE(ice_prot_ext)) {\n+\t\t rule->type < ARRAY_SIZE(ice_prot_ext)) {\n \t\t\t/* No more space to accommodate */\n \t\t\tif (word >= ICE_MAX_CHAIN_WORDS)\n \t\t\t\treturn 0;\n@@ -5612,10 +5611,10 @@ ice_get_fv(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,\n \t ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list)\n {\n \tenum ice_status status;\n-\tu16 *prot_ids;\n+\tu8 *prot_ids;\n \tu16 i;\n \n-\tprot_ids = (u16 *)ice_calloc(hw, lkups_cnt, sizeof(*prot_ids));\n+\tprot_ids = (u8 *)ice_calloc(hw, lkups_cnt, sizeof(*prot_ids));\n \tif (!prot_ids)\n \t\treturn ICE_ERR_NO_MEMORY;\n \n@@ -5791,7 +5790,7 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,\n \t\tmatch_tun = true;\n \n \t/* set the recipe priority if specified */\n-\trm->priority = rinfo->priority ? rinfo->priority : 0;\n+\trm->priority = (u8)rinfo->priority;\n \n \t/* Find offsets from the field vector. Pick the first one for all the\n \t * recipes.\n@@ -6197,7 +6196,7 @@ ice_fill_adv_packet_tun(struct ice_hw *hw, enum ice_sw_tunnel_type tun_type,\n */\n static struct ice_adv_fltr_mgmt_list_entry *\n ice_find_adv_rule_entry(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,\n-\t\t\tu16 lkups_cnt, u8 recp_id,\n+\t\t\tu16 lkups_cnt, u16 recp_id,\n \t\t\tstruct ice_adv_rule_info *rinfo)\n {\n \tstruct ice_adv_fltr_mgmt_list_entry *list_itr;\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex 4979580ec..00459bcc8 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -786,8 +786,8 @@ struct ice_hw {\n \tu16 max_burst_size;\t/* driver sets this value */\n \n \t/* Tx Scheduler values */\n-\tu16 num_tx_sched_layers;\n-\tu16 num_tx_sched_phys_layers;\n+\tu8 num_tx_sched_layers;\n+\tu8 num_tx_sched_phys_layers;\n \tu8 flattened_layers;\n \tu8 max_cgds;\n \tu8 sw_entry_point_layer;\n", "prefixes": [ "22/28" ] }