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GET /api/patches/66430/?format=api
{ "id": 66430, "url": "http://patches.dpdk.org/api/patches/66430/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200309114357.31800-14-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200309114357.31800-14-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200309114357.31800-14-qi.z.zhang@intel.com", "date": "2020-03-09T11:43:42", "name": "[13/28] net/ice/base: add link default override support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c051a36ae31c41c2d54889ad3858196ccb9e7c90", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 31221, "url": "http://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200309114357.31800-14-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 8843, "url": "http://patches.dpdk.org/api/series/8843/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8843", "date": "2020-03-09T11:43:29", "name": "update ice base code", "version": 1, "mbox": "http://patches.dpdk.org/series/8843/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/66430/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/66430/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1375FA052E;\n\tMon, 9 Mar 2020 12:42:44 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 4051F1C120;\n\tMon, 9 Mar 2020 12:40:58 +0100 (CET)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by dpdk.org (Postfix) with ESMTP id F06C51C11B\n for <dev@dpdk.org>; Mon, 9 Mar 2020 12:40:56 +0100 (CET)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 09 Mar 2020 04:40:56 -0700", "from dpdk51.sh.intel.com ([10.67.110.245])\n by fmsmga002.fm.intel.com with ESMTP; 09 Mar 2020 04:40:54 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.70,533,1574150400\"; d=\"scan'208\";a=\"276483573\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com,\n\tbeilei.xing@intel.com", "Cc": "xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Evan Swanson <evan.swanson@intel.com>,\n Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 9 Mar 2020 19:43:42 +0800", "Message-Id": "<20200309114357.31800-14-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20200309114357.31800-1-qi.z.zhang@intel.com>", "References": "<20200309114357.31800-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 13/28] net/ice/base: add link default override\n\tsupport", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Adds functions to check for link override firmware support and get\nthe override settings for a port. Link override allows a user to force\nlink settings that are not normally supported.\n\nFirmware support is version dependent so a function to check support has\nbeen added.\n\nThe link FC settings will use the override if available.\n\nSigned-off-by: Evan Swanson <evan.swanson@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h | 5 +-\n drivers/net/ice/base/ice_common.c | 113 +++++++++++++++++++++++++++++++++-\n drivers/net/ice/base/ice_common.h | 5 ++\n drivers/net/ice/base/ice_type.h | 34 ++++++++++\n 4 files changed, 154 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex bcb2dd783..34c05815f 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -1363,7 +1363,8 @@ struct ice_aqc_get_phy_caps_data {\n #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN\t\tBIT(6)\n #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN\t\tBIT(7)\n #define ICE_AQC_PHY_FEC_MASK\t\t\t\tMAKEMASK(0xdf, 0)\n-\tu8 rsvd1;\t/* Byte 35 reserved */\n+\tu8 module_compliance_enforcement;\n+#define ICE_AQC_MOD_ENFORCE_STRICT_MODE\t\t\tBIT(0)\n \tu8 extended_compliance_code;\n #define ICE_MODULE_TYPE_TOTAL_BYTE\t\t\t3\n \tu8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];\n@@ -1416,7 +1417,7 @@ struct ice_aqc_set_phy_cfg_data {\n \t__le16 eee_cap; /* Value from ice_aqc_get_phy_caps */\n \t__le16 eeer_value;\n \tu8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */\n-\tu8 rsvd1;\n+\tu8 module_compliance_enforcement;\n };\n \n /* Set MAC Config command data structure (direct 0x0603) */\ndiff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex 4b1b31066..3fae6e731 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -2526,6 +2526,7 @@ ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)\n {\n \tstruct ice_aqc_set_phy_cfg_data cfg = { 0 };\n \tstruct ice_phy_cache_mode_data cache_data;\n+\tstruct ice_link_default_override_tlv tlv;\n \tstruct ice_aqc_get_phy_caps_data *pcaps;\n \tenum ice_status status;\n \tu8 pause_mask = 0x0;\n@@ -2573,7 +2574,18 @@ ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)\n \t\t\t\t ICE_AQC_PHY_EN_RX_LINK_PAUSE);\n \n \t/* set the new capabilities */\n-\tcfg.caps |= pause_mask;\n+\tif (pi->fc.req_mode == ICE_FC_AUTO &&\n+\t ice_fw_supports_link_override(hw)) {\n+\t\tstatus = ice_get_link_default_override(&tlv, pi);\n+\t\tif (status)\n+\t\t\treturn status;\n+\n+\t\tif (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&\n+\t\t (tlv.options & ICE_LINK_OVERRIDE_EN))\n+\t\t\tcfg.caps |= tlv.phy_config & ICE_LINK_OVERRIDE_PAUSE_M;\n+\t} else {\n+\t\tcfg.caps |= pause_mask;\n+\t}\n \n \t/* If the capabilities have changed, then set the new config */\n \tif (cfg.caps != pcaps->caps) {\n@@ -4269,3 +4281,102 @@ enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)\n \telse\n \t\treturn ICE_FW_MODE_NORMAL;\n }\n+\n+/**\n+ * ice_fw_supports_link_override\n+ * @hw: pointer to the hardware structure\n+ *\n+ * Checks if the firmware supports link override\n+ */\n+bool ice_fw_supports_link_override(struct ice_hw *hw)\n+{\n+\tif (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) {\n+\t\tif (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN)\n+\t\t\treturn true;\n+\t\tif (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN &&\n+\t\t hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH)\n+\t\t\treturn true;\n+\t} else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) {\n+\t\treturn true;\n+\t}\n+\n+\treturn false;\n+}\n+\n+/**\n+ * ice_get_link_default_override\n+ * @ldo: pointer to the link default override struct\n+ * @pi: pointer to the port info struct\n+ *\n+ * Gets the link default override for a port\n+ */\n+enum ice_status\n+ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,\n+\t\t\t struct ice_port_info *pi)\n+{\n+\tu16 i, tlv, tlv_len, tlv_start, buf, offset;\n+\tstruct ice_hw *hw = pi->hw;\n+\tenum ice_status status;\n+\n+\tstatus = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len,\n+\t\t\t\t\tICE_SR_LINK_DEFAULT_OVERRIDE_PTR);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"Failed to read link override TLV.\\n\");\n+\t\treturn status;\n+\t}\n+\n+\t/* Each port has its own config; calculate for our port */\n+\ttlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS +\n+\t\tICE_SR_PFA_LINK_OVERRIDE_OFFSET;\n+\n+\t/* link options first */\n+\tstatus = ice_read_sr_word(hw, tlv_start, &buf);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"Failed to read override link options.\\n\");\n+\t\treturn status;\n+\t}\n+\tldo->options = buf & ICE_LINK_OVERRIDE_OPT_M;\n+\tldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>\n+\t\tICE_LINK_OVERRIDE_PHY_CFG_S;\n+\n+\t/* link PHY config */\n+\toffset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;\n+\tstatus = ice_read_sr_word(hw, offset, &buf);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"Failed to read override phy config.\\n\");\n+\t\treturn status;\n+\t}\n+\tldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;\n+\n+\t/* PHY types low */\n+\toffset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET;\n+\tfor (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {\n+\t\tstatus = ice_read_sr_word(hw, (offset + i), &buf);\n+\t\tif (status) {\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t \"Failed to read override link options.\\n\");\n+\t\t\treturn status;\n+\t\t}\n+\t\t/* shift 16 bits at a time to fill 64 bits */\n+\t\tldo->phy_type_low |= ((u64)buf << (i * 16));\n+\t}\n+\n+\t/* PHY types high */\n+\toffset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET +\n+\t\tICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS;\n+\tfor (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {\n+\t\tstatus = ice_read_sr_word(hw, (offset + i), &buf);\n+\t\tif (status) {\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t \"Failed to read override link options.\\n\");\n+\t\t\treturn status;\n+\t\t}\n+\t\t/* shift 16 bits at a time to fill 64 bits */\n+\t\tldo->phy_type_high |= ((u64)buf << (i * 16));\n+\t}\n+\n+\treturn status;\n+}\ndiff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h\nindex c73184499..bbff17536 100644\n--- a/drivers/net/ice/base/ice_common.h\n+++ b/drivers/net/ice/base/ice_common.h\n@@ -140,6 +140,11 @@ enum ice_status ice_clear_pf_cfg(struct ice_hw *hw);\n enum ice_status\n ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,\n \t\t struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);\n+bool ice_fw_supports_link_override(struct ice_hw *hw);\n+enum ice_status\n+ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,\n+\t\t\t struct ice_port_info *pi);\n+\n enum ice_fc_mode ice_caps_to_fc_mode(u8 caps);\n enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options);\n enum ice_status\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex 59dce32fa..29fa34fc0 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -168,6 +168,7 @@ enum ice_fc_mode {\n \tICE_FC_RX_PAUSE,\n \tICE_FC_TX_PAUSE,\n \tICE_FC_FULL,\n+\tICE_FC_AUTO,\n \tICE_FC_PFC,\n \tICE_FC_DFLT\n };\n@@ -483,6 +484,28 @@ struct ice_nvm_info {\n \tu8 blank_nvm_mode;\t\t/* is NVM empty (no FW present)*/\n };\n \n+struct ice_link_default_override_tlv {\n+\tu8 options;\n+#define ICE_LINK_OVERRIDE_OPT_M\t\t0x3F\n+#define ICE_LINK_OVERRIDE_STRICT_MODE\tBIT(0)\n+#define ICE_LINK_OVERRIDE_EPCT_DIS\tBIT(1)\n+#define ICE_LINK_OVERRIDE_PORT_DIS\tBIT(2)\n+#define ICE_LINK_OVERRIDE_EN\t\tBIT(3)\n+#define ICE_LINK_OVERRIDE_AUTO_LINK_DIS\tBIT(4)\n+#define ICE_LINK_OVERRIDE_EEE_EN\tBIT(5)\n+\tu8 phy_config;\n+#define ICE_LINK_OVERRIDE_PHY_CFG_S\t8\n+#define ICE_LINK_OVERRIDE_PHY_CFG_M\t(0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)\n+#define ICE_LINK_OVERRIDE_PAUSE_M\t0x3\n+#define ICE_LINK_OVERRIDE_LESM_EN\tBIT(6)\n+#define ICE_LINK_OVERRIDE_AUTO_FEC_EN\tBIT(7)\n+\tu8 fec_options;\n+#define ICE_LINK_OVERRIDE_FEC_OPT_M\t0xFF\n+\tu8 rsvd1;\n+\tu64 phy_type_low;\n+\tu64 phy_type_high;\n+};\n+\n #define ICE_NVM_VER_LEN\t32\n \n /* Max number of port to queue branches w.r.t topology */\n@@ -1003,6 +1026,7 @@ enum ice_sw_fwd_act_type {\n #define ICE_SR_EMP_SR_SETTINGS_PTR\t\t0x48\n #define ICE_SR_CONFIGURATION_METADATA_PTR\t0x4D\n #define ICE_SR_IMMEDIATE_VALUES_PTR\t\t0x4E\n+#define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR\t0x134\n #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR\t0x118\n \n /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */\n@@ -1020,6 +1044,16 @@ enum ice_sw_fwd_act_type {\n */\n #define ICE_SR_SW_CHECKSUM_BASE\t\t0xBABA\n \n+/* Link override related */\n+#define ICE_SR_PFA_LINK_OVERRIDE_WORDS\t\t10\n+#define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS\t4\n+#define ICE_SR_PFA_LINK_OVERRIDE_OFFSET\t\t2\n+#define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET\t1\n+#define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET\t2\n+#define ICE_FW_API_LINK_OVERRIDE_MAJ\t\t1\n+#define ICE_FW_API_LINK_OVERRIDE_MIN\t\t5\n+#define ICE_FW_API_LINK_OVERRIDE_PATCH\t\t2\n+\n #define ICE_PBA_FLAG_DFLT\t\t0xFAFA\n /* Hash redirection LUT for VSI - maximum array size */\n #define ICE_VSIQF_HLUT_ARRAY_SIZE\t((VSIQF_HLUT_MAX_INDEX + 1) * 4)\n", "prefixes": [ "13/28" ] }