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GET /api/patches/66429/?format=api
{ "id": 66429, "url": "http://patches.dpdk.org/api/patches/66429/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200309114357.31800-13-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200309114357.31800-13-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200309114357.31800-13-qi.z.zhang@intel.com", "date": "2020-03-09T11:43:41", "name": "[12/28] net/ice/base: support GTPU uplink and downlink", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "65cc373faf722821e0bc7ff75c1bccaafb4fdd71", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 31221, "url": "http://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200309114357.31800-13-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 8843, "url": "http://patches.dpdk.org/api/series/8843/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8843", "date": "2020-03-09T11:43:29", "name": "update ice base code", "version": 1, "mbox": "http://patches.dpdk.org/series/8843/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/66429/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/66429/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0C1B0A052E;\n\tMon, 9 Mar 2020 12:42:33 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 80E631C117;\n\tMon, 9 Mar 2020 12:40:56 +0100 (CET)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by dpdk.org (Postfix) with ESMTP id E079D1C116\n for <dev@dpdk.org>; Mon, 9 Mar 2020 12:40:54 +0100 (CET)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 09 Mar 2020 04:40:54 -0700", "from dpdk51.sh.intel.com ([10.67.110.245])\n by fmsmga002.fm.intel.com with ESMTP; 09 Mar 2020 04:40:52 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.70,533,1574150400\"; d=\"scan'208\";a=\"276483568\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com,\n\tbeilei.xing@intel.com", "Cc": "xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Dan Nowlin <dan.nowlin@intel.com>,\n Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 9 Mar 2020 19:43:41 +0800", "Message-Id": "<20200309114357.31800-13-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20200309114357.31800-1-qi.z.zhang@intel.com>", "References": "<20200309114357.31800-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 12/28] net/ice/base: support GTPU uplink and\n\tdownlink", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Enable GTPU uplink and downlink flag usage.\nTCAM with different GTPU extend header flag can be saperated.\n\nSigned-off-by: Dan Nowlin <dan.nowlin@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_flex_pipe.c | 68 +++++++++++++++++++++++++++-------\n drivers/net/ice/base/ice_flow.c | 71 ++++++++++++++++++++++++++++++++++--\n 2 files changed, 122 insertions(+), 17 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c\nindex 21b7c2efd..8a27637f8 100644\n--- a/drivers/net/ice/base/ice_flex_pipe.c\n+++ b/drivers/net/ice/base/ice_flex_pipe.c\n@@ -1435,8 +1435,8 @@ static struct ice_buf_build *ice_pkg_buf_alloc(struct ice_hw *hw)\n \t\treturn NULL;\n \n \tbuf = (struct ice_buf_hdr *)bld;\n-\tbuf->data_end = CPU_TO_LE16(sizeof(*buf) -\n-\t\t\t\t sizeof(buf->section_entry[0]));\n+\tbuf->data_end = CPU_TO_LE16(offsetof(struct ice_buf_hdr,\n+\t\t\t\t\t section_entry));\n \treturn bld;\n }\n \n@@ -3832,7 +3832,7 @@ ice_prof_gen_key(struct ice_hw *hw, enum ice_block blk, u8 ptg, u16 vsig,\n \tdefault:\n \t\tice_debug(hw, ICE_DBG_PKG, \"Error in profile config\\n\");\n \t\tbreak;\n-\t};\n+\t}\n \n \treturn ice_set_key(key, ICE_TCAM_KEY_SZ, (u8 *)&inkey, vl_msk, dc_msk,\n \t\t\t nm_msk, 0, ICE_TCAM_KEY_SZ / 2);\n@@ -4861,8 +4861,6 @@ enum ice_status ice_rem_prof(struct ice_hw *hw, enum ice_block blk, u64 id)\n \tLIST_DEL(&pmap->list);\n \tice_free(hw, pmap);\n \n-\tstatus = ICE_SUCCESS;\n-\n err_ice_rem_prof:\n \tice_release_lock(&hw->blk[blk].es.prof_map_lock);\n \treturn status;\n@@ -5144,6 +5142,32 @@ ice_prof_tcam_ena_dis(struct ice_hw *hw, enum ice_block blk, bool enable,\n }\n \n /**\n+ * ice_ptg_attr_in_use - determine if PTG and attribute pair is in use\n+ * @ptg_attr: pointer to the PTG and attribute pair to check\n+ * @ptgs_used: bitmap that denotes which PTGs are in use\n+ * @attr_used: array of PTG and attributes pairs already used\n+ * @attr_cnt: count of entries in the attr_used array\n+ */\n+static bool\n+ice_ptg_attr_in_use(struct ice_tcam_inf *ptg_attr, ice_bitmap_t *ptgs_used,\n+\t\t struct ice_tcam_inf *attr_used[], u16 attr_cnt)\n+{\n+\tu16 i;\n+\n+\tif (!ice_is_bit_set(ptgs_used, ptg_attr->ptg))\n+\t\treturn false;\n+\n+\t/* the PTG is used, so now look for correct attributes */\n+\tfor (i = 0; i < attr_cnt; i++)\n+\t\tif (attr_used[i]->ptg == ptg_attr->ptg &&\n+\t\t attr_used[i]->attr.flags == ptg_attr->attr.flags &&\n+\t\t attr_used[i]->attr.mask == ptg_attr->attr.mask)\n+\t\t\treturn true;\n+\n+\treturn false;\n+}\n+\n+/**\n * ice_adj_prof_priorities - adjust profile based on priorities\n * @hw: pointer to the HW struct\n * @blk: hardware block\n@@ -5155,10 +5179,18 @@ ice_adj_prof_priorities(struct ice_hw *hw, enum ice_block blk, u16 vsig,\n \t\t\tstruct LIST_HEAD_TYPE *chg)\n {\n \tice_declare_bitmap(ptgs_used, ICE_XLT1_CNT);\n+\tstruct ice_tcam_inf **attr_used;\n+\tenum ice_status status = ICE_SUCCESS;\n \tstruct ice_vsig_prof *t;\n-\tenum ice_status status;\n+\tu16 attr_used_cnt = 0;\n \tu16 idx;\n \n+#define ICE_MAX_PTG_ATTRS\t1024\n+\tattr_used = (struct ice_tcam_inf **)ice_calloc(hw, ICE_MAX_PTG_ATTRS,\n+\t\t\t\t\t\t sizeof(*attr_used));\n+\tif (!attr_used)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n \tice_zero_bitmap(ptgs_used, ICE_XLT1_CNT);\n \tidx = vsig & ICE_VSIG_IDX_M;\n \n@@ -5176,11 +5208,15 @@ ice_adj_prof_priorities(struct ice_hw *hw, enum ice_block blk, u16 vsig,\n \t\tu16 i;\n \n \t\tfor (i = 0; i < t->tcam_count; i++) {\n+\t\t\tbool used;\n+\n \t\t\t/* Scan the priorities from newest to oldest.\n \t\t\t * Make sure that the newest profiles take priority.\n \t\t\t */\n-\t\t\tif (ice_is_bit_set(ptgs_used, t->tcam[i].ptg) &&\n-\t\t\t t->tcam[i].in_use) {\n+\t\t\tused = ice_ptg_attr_in_use(&t->tcam[i], ptgs_used,\n+\t\t\t\t\t\t attr_used, attr_used_cnt);\n+\n+\t\t\tif (used && t->tcam[i].in_use) {\n \t\t\t\t/* need to mark this PTG as never match, as it\n \t\t\t\t * was already in use and therefore duplicate\n \t\t\t\t * (and lower priority)\n@@ -5190,9 +5226,8 @@ ice_adj_prof_priorities(struct ice_hw *hw, enum ice_block blk, u16 vsig,\n \t\t\t\t\t\t\t &t->tcam[i],\n \t\t\t\t\t\t\t chg);\n \t\t\t\tif (status)\n-\t\t\t\t\treturn status;\n-\t\t\t} else if (!ice_is_bit_set(ptgs_used, t->tcam[i].ptg) &&\n-\t\t\t\t !t->tcam[i].in_use) {\n+\t\t\t\t\tgoto err_ice_adj_prof_priorities;\n+\t\t\t} else if (!used && !t->tcam[i].in_use) {\n \t\t\t\t/* need to enable this PTG, as it in not in use\n \t\t\t\t * and not enabled (highest priority)\n \t\t\t\t */\n@@ -5201,15 +5236,22 @@ ice_adj_prof_priorities(struct ice_hw *hw, enum ice_block blk, u16 vsig,\n \t\t\t\t\t\t\t &t->tcam[i],\n \t\t\t\t\t\t\t chg);\n \t\t\t\tif (status)\n-\t\t\t\t\treturn status;\n+\t\t\t\t\tgoto err_ice_adj_prof_priorities;\n \t\t\t}\n \n \t\t\t/* keep track of used ptgs */\n \t\t\tice_set_bit(t->tcam[i].ptg, ptgs_used);\n+\t\t\tif (attr_used_cnt < ICE_MAX_PTG_ATTRS)\n+\t\t\t\tattr_used[attr_used_cnt++] = &t->tcam[i];\n+\t\t\telse\n+\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t\t \"Warn: ICE_MAX_PTG_ATTRS exceeded\\n\");\n \t\t}\n \t}\n \n-\treturn ICE_SUCCESS;\n+err_ice_adj_prof_priorities:\n+\tice_free(hw, attr_used);\n+\treturn status;\n }\n \n /**\ndiff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c\nindex 0838b3bd2..17fd2423e 100644\n--- a/drivers/net/ice/base/ice_flow.c\n+++ b/drivers/net/ice/base/ice_flow.c\n@@ -152,7 +152,7 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = {\n static const u32 ice_ptypes_mac_ofos[] = {\n \t0xFDC00846, 0xBFBF7F7E, 0xF70001DF, 0xFEFDFDFB,\n \t0x0000077E, 0x00000000, 0x00000000, 0x00000000,\n-\t0x00000000, 0x00003000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x03FFF000, 0x7FFFFFE0, 0x00000000,\n \t0x00000000, 0x00000000, 0x00000000, 0x00000000,\n \t0x00000000, 0x00000000, 0x00000000, 0x00000000,\n \t0x00000000, 0x00000000, 0x00000000, 0x00000000,\n@@ -366,6 +366,52 @@ static const struct ice_ptype_attributes ice_attr_gtpu_eh[] = {\n \t{ ICE_MAC_IPV6_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_PDU_EH },\n };\n \n+static const struct ice_ptype_attributes ice_attr_gtpu_down[] = {\n+\t{ ICE_MAC_IPV4_GTPU_IPV4_FRAG,\t ICE_PTYPE_ATTR_GTP_DOWNLINK },\n+\t{ ICE_MAC_IPV4_GTPU_IPV4_PAY,\t ICE_PTYPE_ATTR_GTP_DOWNLINK },\n+\t{ ICE_MAC_IPV4_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_DOWNLINK },\n+\t{ ICE_MAC_IPV4_GTPU_IPV4_TCP,\t ICE_PTYPE_ATTR_GTP_DOWNLINK },\n+\t{ ICE_MAC_IPV4_GTPU_IPV4_ICMP,\t ICE_PTYPE_ATTR_GTP_DOWNLINK },\n+\t{ ICE_MAC_IPV6_GTPU_IPV4_FRAG,\t ICE_PTYPE_ATTR_GTP_DOWNLINK },\n+\t{ ICE_MAC_IPV6_GTPU_IPV4_PAY,\t ICE_PTYPE_ATTR_GTP_DOWNLINK },\n+\t{ ICE_MAC_IPV6_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_DOWNLINK },\n+\t{ ICE_MAC_IPV6_GTPU_IPV4_TCP,\t ICE_PTYPE_ATTR_GTP_DOWNLINK },\n+\t{ ICE_MAC_IPV6_GTPU_IPV4_ICMP,\t ICE_PTYPE_ATTR_GTP_DOWNLINK },\n+\t{ ICE_MAC_IPV4_GTPU_IPV6_FRAG,\t ICE_PTYPE_ATTR_GTP_DOWNLINK },\n+\t{ ICE_MAC_IPV4_GTPU_IPV6_PAY,\t ICE_PTYPE_ATTR_GTP_DOWNLINK },\n+\t{ ICE_MAC_IPV4_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_DOWNLINK },\n+\t{ ICE_MAC_IPV4_GTPU_IPV6_TCP,\t ICE_PTYPE_ATTR_GTP_DOWNLINK },\n+\t{ ICE_MAC_IPV4_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_DOWNLINK },\n+\t{ ICE_MAC_IPV6_GTPU_IPV6_FRAG,\t ICE_PTYPE_ATTR_GTP_DOWNLINK },\n+\t{ ICE_MAC_IPV6_GTPU_IPV6_PAY,\t ICE_PTYPE_ATTR_GTP_DOWNLINK },\n+\t{ ICE_MAC_IPV6_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_DOWNLINK },\n+\t{ ICE_MAC_IPV6_GTPU_IPV6_TCP,\t ICE_PTYPE_ATTR_GTP_DOWNLINK },\n+\t{ ICE_MAC_IPV6_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_DOWNLINK },\n+};\n+\n+static const struct ice_ptype_attributes ice_attr_gtpu_up[] = {\n+\t{ ICE_MAC_IPV4_GTPU_IPV4_FRAG,\t ICE_PTYPE_ATTR_GTP_UPLINK },\n+\t{ ICE_MAC_IPV4_GTPU_IPV4_PAY,\t ICE_PTYPE_ATTR_GTP_UPLINK },\n+\t{ ICE_MAC_IPV4_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_UPLINK },\n+\t{ ICE_MAC_IPV4_GTPU_IPV4_TCP,\t ICE_PTYPE_ATTR_GTP_UPLINK },\n+\t{ ICE_MAC_IPV4_GTPU_IPV4_ICMP,\t ICE_PTYPE_ATTR_GTP_UPLINK },\n+\t{ ICE_MAC_IPV6_GTPU_IPV4_FRAG,\t ICE_PTYPE_ATTR_GTP_UPLINK },\n+\t{ ICE_MAC_IPV6_GTPU_IPV4_PAY,\t ICE_PTYPE_ATTR_GTP_UPLINK },\n+\t{ ICE_MAC_IPV6_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_UPLINK },\n+\t{ ICE_MAC_IPV6_GTPU_IPV4_TCP,\t ICE_PTYPE_ATTR_GTP_UPLINK },\n+\t{ ICE_MAC_IPV6_GTPU_IPV4_ICMP,\t ICE_PTYPE_ATTR_GTP_UPLINK },\n+\t{ ICE_MAC_IPV4_GTPU_IPV6_FRAG,\t ICE_PTYPE_ATTR_GTP_UPLINK },\n+\t{ ICE_MAC_IPV4_GTPU_IPV6_PAY,\t ICE_PTYPE_ATTR_GTP_UPLINK },\n+\t{ ICE_MAC_IPV4_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_UPLINK },\n+\t{ ICE_MAC_IPV4_GTPU_IPV6_TCP,\t ICE_PTYPE_ATTR_GTP_UPLINK },\n+\t{ ICE_MAC_IPV4_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_UPLINK },\n+\t{ ICE_MAC_IPV6_GTPU_IPV6_FRAG,\t ICE_PTYPE_ATTR_GTP_UPLINK },\n+\t{ ICE_MAC_IPV6_GTPU_IPV6_PAY,\t ICE_PTYPE_ATTR_GTP_UPLINK },\n+\t{ ICE_MAC_IPV6_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_UPLINK },\n+\t{ ICE_MAC_IPV6_GTPU_IPV6_TCP,\t ICE_PTYPE_ATTR_GTP_UPLINK },\n+\t{ ICE_MAC_IPV6_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_UPLINK },\n+};\n+\n static const u32 ice_ptypes_gtpu[] = {\n \t0x00000000, 0x00000000, 0x00000000, 0x00000000,\n \t0x00000000, 0x00000000, 0x00000000, 0x00000000,\n@@ -586,6 +632,22 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params)\n \t\t\tsrc = (const ice_bitmap_t *)ice_ptypes_gtpc_tid;\n \t\t\tice_and_bitmap(params->ptypes, params->ptypes,\n \t\t\t\t src, ICE_FLOW_PTYPE_MAX);\n+\t\t} else if (hdrs & ICE_FLOW_SEG_HDR_GTPU_DWN) {\n+\t\t\tsrc = (const ice_bitmap_t *)ice_ptypes_gtpu;\n+\t\t\tice_and_bitmap(params->ptypes, params->ptypes,\n+\t\t\t\t src, ICE_FLOW_PTYPE_MAX);\n+\n+\t\t\t/* Attributes for GTP packet with downlink */\n+\t\t\tparams->attr = ice_attr_gtpu_down;\n+\t\t\tparams->attr_cnt = ARRAY_SIZE(ice_attr_gtpu_down);\n+\t\t} else if (hdrs & ICE_FLOW_SEG_HDR_GTPU_UP) {\n+\t\t\tsrc = (const ice_bitmap_t *)ice_ptypes_gtpu;\n+\t\t\tice_and_bitmap(params->ptypes, params->ptypes,\n+\t\t\t\t src, ICE_FLOW_PTYPE_MAX);\n+\n+\t\t\t/* Attributes for GTP packet with uplink */\n+\t\t\tparams->attr = ice_attr_gtpu_up;\n+\t\t\tparams->attr_cnt = ARRAY_SIZE(ice_attr_gtpu_up);\n \t\t} else if (hdrs & ICE_FLOW_SEG_HDR_GTPU_EH) {\n \t\t\tsrc = (const ice_bitmap_t *)ice_ptypes_gtpu;\n \t\t\tice_and_bitmap(params->ptypes, params->ptypes,\n@@ -594,7 +656,8 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params)\n \t\t\t/* Attributes for GTP packet with Extension Header */\n \t\t\tparams->attr = ice_attr_gtpu_eh;\n \t\t\tparams->attr_cnt = ARRAY_SIZE(ice_attr_gtpu_eh);\n-\t\t} else if (hdrs & ICE_FLOW_SEG_HDR_GTPU_IP) {\n+\t\t} else if ((hdrs & ICE_FLOW_SEG_HDR_GTPU) ==\n+\t\t\t ICE_FLOW_SEG_HDR_GTPU) {\n \t\t\tsrc = (const ice_bitmap_t *)ice_ptypes_gtpu;\n \t\t\tice_and_bitmap(params->ptypes, params->ptypes,\n \t\t\t\t src, ICE_FLOW_PTYPE_MAX);\n@@ -1238,7 +1301,7 @@ static enum ice_status\n ice_flow_rem_prof_sync(struct ice_hw *hw, enum ice_block blk,\n \t\t struct ice_flow_prof *prof)\n {\n-\tenum ice_status status = ICE_SUCCESS;\n+\tenum ice_status status;\n \n \t/* Remove all remaining flow entries before removing the flow profile */\n \tif (!LIST_EMPTY(&prof->entries)) {\n@@ -2080,7 +2143,7 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,\n \tconst enum ice_block blk = ICE_BLK_RSS;\n \tstruct ice_flow_prof *prof = NULL;\n \tstruct ice_flow_seg_info *segs;\n-\tenum ice_status status = ICE_SUCCESS;\n+\tenum ice_status status;\n \n \tif (!segs_cnt || segs_cnt > ICE_FLOW_SEG_MAX)\n \t\treturn ICE_ERR_PARAM;\n", "prefixes": [ "12/28" ] }