Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/66428/?format=api
{ "id": 66428, "url": "http://patches.dpdk.org/api/patches/66428/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200309114357.31800-12-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200309114357.31800-12-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200309114357.31800-12-qi.z.zhang@intel.com", "date": "2020-03-09T11:43:40", "name": "[11/28] net/ice/base: minor fixes", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7a9863b57c80cc9b2f84f9329345ae8e8db1bc95", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 31221, "url": "http://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200309114357.31800-12-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 8843, "url": "http://patches.dpdk.org/api/series/8843/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8843", "date": "2020-03-09T11:43:29", "name": "update ice base code", "version": 1, "mbox": "http://patches.dpdk.org/series/8843/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/66428/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/66428/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9D90BA052E;\n\tMon, 9 Mar 2020 12:42:24 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id F02921C113;\n\tMon, 9 Mar 2020 12:40:53 +0100 (CET)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by dpdk.org (Postfix) with ESMTP id B62E11C10A\n for <dev@dpdk.org>; Mon, 9 Mar 2020 12:40:52 +0100 (CET)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 09 Mar 2020 04:40:52 -0700", "from dpdk51.sh.intel.com ([10.67.110.245])\n by fmsmga002.fm.intel.com with ESMTP; 09 Mar 2020 04:40:50 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.70,533,1574150400\"; d=\"scan'208\";a=\"276483563\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com,\n\tbeilei.xing@intel.com", "Cc": "xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Tony Nguyen <anthony.l.nguyen@intel.com>,\n Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 9 Mar 2020 19:43:40 +0800", "Message-Id": "<20200309114357.31800-12-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20200309114357.31800-1-qi.z.zhang@intel.com>", "References": "<20200309114357.31800-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 11/28] net/ice/base: minor fixes", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This is a collection of minor fixes that were found during code review.\nChanges are:\n- Call ice_hweight8() instead of calculating it ourselves in\n ice_bits_max_set().\n- Call ice_test_and_clear_bit() over calling ice_is_bit_set() then\n ice_clear_bit() in ice_rem_vsi_rss_list().\n- Remove 'chrs' variable in ice_add_prof_id_flow() as it's not being\n used for anything.\n- Return result directly instead of assigning to variable then\n returning the variable in ice_rem_vsig().\n- Reduce scope, and don't initialize, 'or_vsig' in\n ice_add_prof_id_flow().\n- Return error immediately in ice_add_prof_id_vsig(). Since the memory\n wasn't allocated, there is no need to goto and attempt to free memory.\n- Show that values 37-38 are reserved in ice_flow_avf_hdr_field as the\n other reserved values are shown.\n- Fix RCT ordering\n- Remove initialization of values that aren't needed\n- Fix function headers to match function names\n- Use offsetof instead of calculating ourselves in ice_pkg_buf_alloc()\n- In ice_rem_prof(), do not set status to ICE_SUCCESS as, due to code\n flow, this will always be ICE_SUCCESS.\n- Remove unnecessary semicolon in ice_prof_gen_key()\n- Remove unnecessary initializations\n\nSigned-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_flex_pipe.c | 42 +++++++++++++-----------------------\n drivers/net/ice/base/ice_flow.c | 7 ++----\n drivers/net/ice/base/ice_flow.h | 1 +\n 3 files changed, 18 insertions(+), 32 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c\nindex 5dd7a0d38..21b7c2efd 100644\n--- a/drivers/net/ice/base/ice_flex_pipe.c\n+++ b/drivers/net/ice/base/ice_flex_pipe.c\n@@ -610,7 +610,7 @@ ice_gen_key_word(u8 val, u8 valid, u8 dont_care, u8 nvr_mtch, u8 *key,\n static bool ice_bits_max_set(const u8 *mask, u16 size, u16 max)\n {\n \tu16 count = 0;\n-\tu16 i, j;\n+\tu16 i;\n \n \t/* check each byte */\n \tfor (i = 0; i < size; i++) {\n@@ -626,11 +626,9 @@ static bool ice_bits_max_set(const u8 *mask, u16 size, u16 max)\n \t\t\treturn false;\n \n \t\t/* count the bits in this byte, checking threshold */\n-\t\tfor (j = 0; j < BITS_PER_BYTE; j++) {\n-\t\t\tcount += (mask[i] & (0x1 << j)) ? 1 : 0;\n-\t\t\tif (count > max)\n-\t\t\t\treturn false;\n-\t\t}\n+\t\tcount += ice_hweight8(mask[i]);\n+\t\tif (count > max)\n+\t\t\treturn false;\n \t}\n \n \treturn true;\n@@ -914,9 +912,8 @@ ice_update_pkg(struct ice_hw *hw, struct ice_buf *bufs, u32 count)\n \t\treturn status;\n \n \tfor (i = 0; i < count; i++) {\n-\t\tbool last = ((i + 1) == count);\n-\n \t\tstruct ice_buf_hdr *bh = (struct ice_buf_hdr *)(bufs + i);\n+\t\tbool last = ((i + 1) == count);\n \n \t\tstatus = ice_aq_update_pkg(hw, bh, LE16_TO_CPU(bh->data_end),\n \t\t\t\t\t last, &offset, &info, NULL);\n@@ -1806,7 +1803,7 @@ static u16 ice_pkg_buf_get_active_sections(struct ice_buf_build *bld)\n }\n \n /**\n- * ice_pkg_buf_header\n+ * ice_pkg_buf\n * @bld: pointer to pkg build (allocated by ice_pkg_buf_alloc())\n *\n * Return a pointer to the buffer's header\n@@ -3887,6 +3884,7 @@ ice_vsig_get_ref(struct ice_hw *hw, enum ice_block blk, u16 vsig, u16 *refs)\n {\n \tu16 idx = vsig & ICE_VSIG_IDX_M;\n \tstruct ice_vsig_vsi *ptr;\n+\n \t*refs = 0;\n \n \tif (!hw->blk[blk].xlt2.vsig_tbl[idx].in_use)\n@@ -4090,12 +4088,12 @@ ice_upd_prof_hw(struct ice_hw *hw, enum ice_block blk,\n \tstruct ice_buf_build *b;\n \tstruct ice_chs_chg *tmp;\n \tenum ice_status status;\n-\tu16 pkg_sects = 0;\n-\tu16 sects = 0;\n+\tu16 pkg_sects;\n \tu16 xlt1 = 0;\n \tu16 xlt2 = 0;\n \tu16 tcam = 0;\n \tu16 es = 0;\n+\tu16 sects;\n \n \t/* count number of sections we need */\n \tLIST_FOR_EACH_ENTRY(tmp, chgs, ice_chs_chg, list_entry) {\n@@ -4194,8 +4192,6 @@ static void ice_update_fd_mask(struct ice_hw *hw, u16 prof_id, u32 mask_sel)\n \t\t GLQF_FDMASK_SEL(prof_id), mask_sel);\n }\n \n-#define ICE_SRC_DST_MAX_COUNT\t8\n-\n struct ice_fd_src_dst_pair {\n \tu8 prot_id;\n \tu8 count;\n@@ -4754,9 +4750,7 @@ ice_rem_vsig(struct ice_hw *hw, enum ice_block blk, u16 vsig,\n \t\t} while (vsi_cur);\n \t}\n \n-\tstatus = ice_vsig_free(hw, blk, vsig);\n-\n-\treturn status;\n+\treturn ice_vsig_free(hw, blk, vsig);\n }\n \n /**\n@@ -4974,8 +4968,8 @@ static enum ice_status\n ice_add_prof_to_lst(struct ice_hw *hw, enum ice_block blk,\n \t\t struct LIST_HEAD_TYPE *lst, u64 hdl)\n {\n-\tstruct ice_vsig_prof *p;\n \tstruct ice_prof_map *map;\n+\tstruct ice_vsig_prof *p;\n \tu16 i;\n \n \tmap = ice_search_prof_id(hw, blk, hdl);\n@@ -5252,7 +5246,7 @@ ice_add_prof_id_vsig(struct ice_hw *hw, enum ice_block blk, u16 vsig, u64 hdl,\n \t/* new VSIG profile structure */\n \tt = (struct ice_vsig_prof *)ice_malloc(hw, sizeof(*t));\n \tif (!t)\n-\t\tgoto err_ice_add_prof_id_vsig;\n+\t\treturn ICE_ERR_NO_MEMORY;\n \n \tt->profile_cookie = map->profile_cookie;\n \tt->prof_id = map->prof_id;\n@@ -5371,7 +5365,7 @@ ice_create_prof_id_vsig(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl,\n }\n \n /**\n- * ice_create_vsig_from_list - create a new VSIG with a list of profiles\n+ * ice_create_vsig_from_lst - create a new VSIG with a list of profiles\n * @hw: pointer to the HW struct\n * @blk: hardware block\n * @vsi: the initial VSI that will be in VSIG\n@@ -5498,13 +5492,11 @@ ice_add_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl)\n \tstruct ice_vsig_prof *tmp1, *del1;\n \tstruct LIST_HEAD_TYPE union_lst;\n \tstruct ice_chs_chg *tmp, *del;\n-\tstruct LIST_HEAD_TYPE chrs;\n \tstruct LIST_HEAD_TYPE chg;\n \tenum ice_status status;\n-\tu16 vsig, or_vsig = 0;\n+\tu16 vsig;\n \n \tINIT_LIST_HEAD(&union_lst);\n-\tINIT_LIST_HEAD(&chrs);\n \tINIT_LIST_HEAD(&chg);\n \n \t/* Get profile */\n@@ -5516,6 +5508,7 @@ ice_add_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl)\n \tstatus = ice_vsig_find_vsi(hw, blk, vsi, &vsig);\n \tif (!status && vsig) {\n \t\tbool only_vsi;\n+\t\tu16 or_vsig;\n \t\tu16 ref;\n \n \t\t/* found in vsig */\n@@ -5625,11 +5618,6 @@ ice_add_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl)\n \t\tice_free(hw, del1);\n \t}\n \n-\tLIST_FOR_EACH_ENTRY_SAFE(del1, tmp1, &chrs, ice_vsig_prof, list) {\n-\t\tLIST_DEL(&del1->list);\n-\t\tice_free(hw, del1);\n-\t}\n-\n \treturn status;\n }\n \ndiff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c\nindex d52bce1ce..0838b3bd2 100644\n--- a/drivers/net/ice/base/ice_flow.c\n+++ b/drivers/net/ice/base/ice_flow.c\n@@ -1152,7 +1152,7 @@ ice_flow_add_prof_sync(struct ice_hw *hw, enum ice_block blk,\n \t\t struct ice_flow_prof **prof)\n {\n \tstruct ice_flow_prof_params params;\n-\tenum ice_status status = ICE_SUCCESS;\n+\tenum ice_status status;\n \tu8 i;\n \n \tif (!prof || (acts_cnt && !acts))\n@@ -1825,14 +1825,11 @@ void ice_rem_vsi_rss_list(struct ice_hw *hw, u16 vsi_handle)\n \tice_acquire_lock(&hw->rss_locks);\n \tLIST_FOR_EACH_ENTRY_SAFE(r, tmp, &hw->rss_list_head,\n \t\t\t\t ice_rss_cfg, l_entry) {\n-\t\tif (ice_is_bit_set(r->vsis, vsi_handle)) {\n-\t\t\tice_clear_bit(vsi_handle, r->vsis);\n-\n+\t\tif (ice_test_and_clear_bit(vsi_handle, r->vsis))\n \t\t\tif (!ice_is_any_bit_set(r->vsis, ICE_MAX_VSI)) {\n \t\t\t\tLIST_DEL(&r->l_entry);\n \t\t\t\tice_free(hw, r);\n \t\t\t}\n-\t\t}\n \t}\n \tice_release_lock(&hw->rss_locks);\n }\ndiff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h\nindex d7b10ccc3..4c2067f0c 100644\n--- a/drivers/net/ice/base/ice_flow.h\n+++ b/drivers/net/ice/base/ice_flow.h\n@@ -187,6 +187,7 @@ enum ice_flow_avf_hdr_field {\n \tICE_AVF_FLOW_FIELD_IPV4_SCTP,\n \tICE_AVF_FLOW_FIELD_IPV4_OTHER,\n \tICE_AVF_FLOW_FIELD_FRAG_IPV4,\n+\t/* Values 37-38 are reserved */\n \tICE_AVF_FLOW_FIELD_UNICAST_IPV6_UDP\t= 39,\n \tICE_AVF_FLOW_FIELD_MULTICAST_IPV6_UDP,\n \tICE_AVF_FLOW_FIELD_IPV6_UDP,\n", "prefixes": [ "11/28" ] }