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GET /api/patches/66425/?format=api
{ "id": 66425, "url": "http://patches.dpdk.org/api/patches/66425/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200309114357.31800-9-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200309114357.31800-9-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200309114357.31800-9-qi.z.zhang@intel.com", "date": "2020-03-09T11:43:37", "name": "[08/28] net/ice/base: use descriptive vairiable name than type", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "88e4057e19ee707287bb467a0e1899c4582d20ec", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 31221, "url": "http://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200309114357.31800-9-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 8843, "url": "http://patches.dpdk.org/api/series/8843/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8843", "date": "2020-03-09T11:43:29", "name": "update ice base code", "version": 1, "mbox": "http://patches.dpdk.org/series/8843/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/66425/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/66425/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D0DC1A052E;\n\tMon, 9 Mar 2020 12:41:54 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id BA9301C0CC;\n\tMon, 9 Mar 2020 12:40:49 +0100 (CET)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by dpdk.org (Postfix) with ESMTP id DCC131C0CC\n for <dev@dpdk.org>; Mon, 9 Mar 2020 12:40:47 +0100 (CET)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 09 Mar 2020 04:40:46 -0700", "from dpdk51.sh.intel.com ([10.67.110.245])\n by fmsmga002.fm.intel.com with ESMTP; 09 Mar 2020 04:40:45 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.70,533,1574150400\"; d=\"scan'208\";a=\"276483544\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com,\n\tbeilei.xing@intel.com", "Cc": "xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Bruce Allan <bruce.w.allan@intel.com>,\n Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 9 Mar 2020 19:43:37 +0800", "Message-Id": "<20200309114357.31800-9-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20200309114357.31800-1-qi.z.zhang@intel.com>", "References": "<20200309114357.31800-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 08/28] net/ice/base: use descriptive vairiable\n\tname than type", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The variable name 'type' is not very descriptive. Replace instances of\nthose with a variable name that is more descriptive or replace it if not\nneeded.\n\nSigned-off-by: Bruce Allan <bruce.w.allan@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_flex_pipe.c | 8 ++++----\n drivers/net/ice/base/ice_flow.c | 8 ++++----\n drivers/net/ice/base/ice_switch.c | 38 ++++++++++++++++++------------------\n 3 files changed, 27 insertions(+), 27 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c\nindex 82b27de0e..c18ccea48 100644\n--- a/drivers/net/ice/base/ice_flex_pipe.c\n+++ b/drivers/net/ice/base/ice_flex_pipe.c\n@@ -1506,11 +1506,11 @@ ice_get_sw_prof_type(struct ice_hw *hw, struct ice_fv *fv)\n /**\n * ice_get_sw_fv_bitmap - Get switch field vector bitmap based on profile type\n * @hw: pointer to hardware structure\n- * @type: type of profiles requested\n+ * @req_profs: type of profiles requested\n * @bm: pointer to memory for returning the bitmap of field vectors\n */\n void\n-ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type type,\n+ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type req_profs,\n \t\t ice_bitmap_t *bm)\n {\n \tstruct ice_pkg_enum state;\n@@ -1519,7 +1519,7 @@ ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type type,\n \n \tice_memset(&state, 0, sizeof(state), ICE_NONDMA_MEM);\n \n-\tif (type == ICE_PROF_ALL) {\n+\tif (req_profs == ICE_PROF_ALL) {\n \t\tu16 i;\n \n \t\tfor (i = 0; i < ICE_MAX_NUM_PROFILES; i++)\n@@ -1543,7 +1543,7 @@ ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type type,\n \t\t\t/* Determine field vector type */\n \t\t\tprof_type = ice_get_sw_prof_type(hw, fv);\n \n-\t\t\tif (type & prof_type)\n+\t\t\tif (req_profs & prof_type)\n \t\t\t\tice_set_bit((u16)offset, bm);\n \t\t}\n \t} while (fv);\ndiff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c\nindex 6c413e307..d52bce1ce 100644\n--- a/drivers/net/ice/base/ice_flow.c\n+++ b/drivers/net/ice/base/ice_flow.c\n@@ -1615,7 +1615,7 @@ enum ice_status ice_flow_rem_entry(struct ice_hw *hw, u64 entry_h)\n * ice_flow_set_fld_ext - specifies locations of field from entry's input buffer\n * @seg: packet segment the field being set belongs to\n * @fld: field to be set\n- * @type: type of the field\n+ * @field_type: type of the field\n * @val_loc: if not ICE_FLOW_FLD_OFF_INVAL, location of the value to match from\n * entry's input buffer\n * @mask_loc: if not ICE_FLOW_FLD_OFF_INVAL, location of mask value from entry's\n@@ -1636,16 +1636,16 @@ enum ice_status ice_flow_rem_entry(struct ice_hw *hw, u64 entry_h)\n */\n static void\n ice_flow_set_fld_ext(struct ice_flow_seg_info *seg, enum ice_flow_field fld,\n-\t\t enum ice_flow_fld_match_type type, u16 val_loc,\n+\t\t enum ice_flow_fld_match_type field_type, u16 val_loc,\n \t\t u16 mask_loc, u16 last_loc)\n {\n \tu64 bit = BIT_ULL(fld);\n \n \tseg->match |= bit;\n-\tif (type == ICE_FLOW_FLD_TYPE_RANGE)\n+\tif (field_type == ICE_FLOW_FLD_TYPE_RANGE)\n \t\tseg->range |= bit;\n \n-\tseg->fields[fld].type = type;\n+\tseg->fields[fld].type = field_type;\n \tseg->fields[fld].src.val = val_loc;\n \tseg->fields[fld].src.mask = mask_loc;\n \tseg->fields[fld].src.last = last_loc;\ndiff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c\nindex 0f2a5b3e9..adcda9645 100644\n--- a/drivers/net/ice/base/ice_switch.c\n+++ b/drivers/net/ice/base/ice_switch.c\n@@ -1872,7 +1872,7 @@ enum ice_status ice_get_initial_sw_cfg(struct ice_hw *hw)\n \t\t\tstruct ice_aqc_get_sw_cfg_resp_elem *ele;\n \t\t\tu16 pf_vf_num, swid, vsi_port_num;\n \t\t\tbool is_vf = false;\n-\t\t\tu8 type;\n+\t\t\tu8 res_type;\n \n \t\t\tele = rbuf[i].elements;\n \t\t\tvsi_port_num = LE16_TO_CPU(ele->vsi_port_num) &\n@@ -1887,10 +1887,10 @@ enum ice_status ice_get_initial_sw_cfg(struct ice_hw *hw)\n \t\t\t ICE_AQC_GET_SW_CONF_RESP_IS_VF)\n \t\t\t\tis_vf = true;\n \n-\t\t\ttype = LE16_TO_CPU(ele->vsi_port_num) >>\n-\t\t\t\tICE_AQC_GET_SW_CONF_RESP_TYPE_S;\n+\t\t\tres_type = (u8)(LE16_TO_CPU(ele->vsi_port_num) >>\n+\t\t\t\t\tICE_AQC_GET_SW_CONF_RESP_TYPE_S);\n \n-\t\t\tswitch (type) {\n+\t\t\tswitch (res_type) {\n \t\t\tcase ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT:\n \t\t\tcase ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT:\n \t\t\t\tif (j == num_total_ports) {\n@@ -1900,7 +1900,7 @@ enum ice_status ice_get_initial_sw_cfg(struct ice_hw *hw)\n \t\t\t\t\tgoto out;\n \t\t\t\t}\n \t\t\t\tice_init_port_info(hw->port_info,\n-\t\t\t\t\t\t vsi_port_num, type, swid,\n+\t\t\t\t\t\t vsi_port_num, res_type, swid,\n \t\t\t\t\t\t pf_vf_num, is_vf);\n \t\t\t\tj++;\n \t\t\t\tbreak;\n@@ -2355,7 +2355,7 @@ ice_update_vsi_list_rule(struct ice_hw *hw, u16 *vsi_handle_arr, u16 num_vsi,\n \tstruct ice_aqc_sw_rules_elem *s_rule;\n \tenum ice_status status;\n \tu16 s_rule_size;\n-\tu16 type;\n+\tu16 rule_type;\n \tint i;\n \n \tif (!num_vsi)\n@@ -2368,11 +2368,11 @@ ice_update_vsi_list_rule(struct ice_hw *hw, u16 *vsi_handle_arr, u16 num_vsi,\n \t lkup_type == ICE_SW_LKUP_PROMISC ||\n \t lkup_type == ICE_SW_LKUP_PROMISC_VLAN ||\n \t lkup_type == ICE_SW_LKUP_LAST)\n-\t\ttype = remove ? ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR :\n-\t\t\t\tICE_AQC_SW_RULES_T_VSI_LIST_SET;\n+\t\trule_type = remove ? ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR :\n+\t\t\tICE_AQC_SW_RULES_T_VSI_LIST_SET;\n \telse if (lkup_type == ICE_SW_LKUP_VLAN)\n-\t\ttype = remove ? ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR :\n-\t\t\t\tICE_AQC_SW_RULES_T_PRUNE_LIST_SET;\n+\t\trule_type = remove ? ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR :\n+\t\t\tICE_AQC_SW_RULES_T_PRUNE_LIST_SET;\n \telse\n \t\treturn ICE_ERR_PARAM;\n \n@@ -2390,7 +2390,7 @@ ice_update_vsi_list_rule(struct ice_hw *hw, u16 *vsi_handle_arr, u16 num_vsi,\n \t\t\tCPU_TO_LE16(ice_get_hw_vsi_num(hw, vsi_handle_arr[i]));\n \t}\n \n-\ts_rule->type = CPU_TO_LE16(type);\n+\ts_rule->type = CPU_TO_LE16(rule_type);\n \ts_rule->pdata.vsi_list.number_vsi = CPU_TO_LE16(num_vsi);\n \ts_rule->pdata.vsi_list.index = CPU_TO_LE16(vsi_list_id);\n \n@@ -5671,35 +5671,35 @@ static void\n ice_get_compat_fv_bitmap(struct ice_hw *hw, struct ice_adv_rule_info *rinfo,\n \t\t\t ice_bitmap_t *bm)\n {\n-\tenum ice_prof_type type;\n+\tenum ice_prof_type prof_type;\n \n \tswitch (rinfo->tun_type) {\n \tcase ICE_NON_TUN:\n-\t\ttype = ICE_PROF_NON_TUN;\n+\t\tprof_type = ICE_PROF_NON_TUN;\n \t\tbreak;\n \tcase ICE_ALL_TUNNELS:\n-\t\ttype = ICE_PROF_TUN_ALL;\n+\t\tprof_type = ICE_PROF_TUN_ALL;\n \t\tbreak;\n \tcase ICE_SW_TUN_VXLAN_GPE:\n \tcase ICE_SW_TUN_GENEVE:\n \tcase ICE_SW_TUN_VXLAN:\n \tcase ICE_SW_TUN_UDP:\n \tcase ICE_SW_TUN_GTP:\n-\t\ttype = ICE_PROF_TUN_UDP;\n+\t\tprof_type = ICE_PROF_TUN_UDP;\n \t\tbreak;\n \tcase ICE_SW_TUN_NVGRE:\n-\t\ttype = ICE_PROF_TUN_GRE;\n+\t\tprof_type = ICE_PROF_TUN_GRE;\n \t\tbreak;\n \tcase ICE_SW_TUN_PPPOE:\n-\t\ttype = ICE_PROF_TUN_PPPOE;\n+\t\tprof_type = ICE_PROF_TUN_PPPOE;\n \t\tbreak;\n \tcase ICE_SW_TUN_AND_NON_TUN:\n \tdefault:\n-\t\ttype = ICE_PROF_ALL;\n+\t\tprof_type = ICE_PROF_ALL;\n \t\tbreak;\n \t}\n \n-\tice_get_sw_fv_bitmap(hw, type, bm);\n+\tice_get_sw_fv_bitmap(hw, prof_type, bm);\n }\n \n /**\n", "prefixes": [ "08/28" ] }