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GET /api/patches/66421/?format=api
{ "id": 66421, "url": "http://patches.dpdk.org/api/patches/66421/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200309114357.31800-5-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200309114357.31800-5-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200309114357.31800-5-qi.z.zhang@intel.com", "date": "2020-03-09T11:43:33", "name": "[04/28] net/ice/base: read PSM clock frequency from register", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c7136a97c120daa2f525762765af5299d3bd6744", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 31221, "url": "http://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200309114357.31800-5-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 8843, "url": "http://patches.dpdk.org/api/series/8843/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8843", "date": "2020-03-09T11:43:29", "name": "update ice base code", "version": 1, "mbox": "http://patches.dpdk.org/series/8843/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/66421/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/66421/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D9B18A052E;\n\tMon, 9 Mar 2020 12:41:12 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 819C71C08E;\n\tMon, 9 Mar 2020 12:40:41 +0100 (CET)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by dpdk.org (Postfix) with ESMTP id 7C2C11C02B\n for <dev@dpdk.org>; Mon, 9 Mar 2020 12:40:39 +0100 (CET)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 09 Mar 2020 04:40:38 -0700", "from dpdk51.sh.intel.com ([10.67.110.245])\n by fmsmga002.fm.intel.com with ESMTP; 09 Mar 2020 04:40:36 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.70,533,1574150400\"; d=\"scan'208\";a=\"276483509\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com,\n\tbeilei.xing@intel.com", "Cc": "xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Ben Shelton <benjamin.h.shelton@intel.com>,\n Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 9 Mar 2020 19:43:33 +0800", "Message-Id": "<20200309114357.31800-5-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20200309114357.31800-1-qi.z.zhang@intel.com>", "References": "<20200309114357.31800-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 04/28] net/ice/base: read PSM clock frequency\n\tfrom register", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Read the GLGEN_CLKSTAT_SRC register to determine which PSM clock\nfrequency is selected. This ensures that the rate limiter profile\ncalculations will be correct.\n\nSigned-off-by: Ben Shelton <benjamin.h.shelton@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_common.c | 1 +\n drivers/net/ice/base/ice_sched.c | 59 +++++++++++++++++++++++++++++++++------\n drivers/net/ice/base/ice_sched.h | 7 ++++-\n drivers/net/ice/base/ice_type.h | 4 ++-\n 4 files changed, 61 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex 786e99d21..9ef1aeef2 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -672,6 +672,7 @@ enum ice_status ice_init_hw(struct ice_hw *hw)\n \t\t\t \"Failed to get scheduler allocated resources\\n\");\n \t\tgoto err_unroll_alloc;\n \t}\n+\tice_sched_get_psm_clk_freq(hw);\n \n \t/* Initialize port_info struct with scheduler data */\n \tstatus = ice_sched_init_port(hw->port_info);\ndiff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c\nindex 553fc28ff..26c4ba36f 100644\n--- a/drivers/net/ice/base/ice_sched.c\n+++ b/drivers/net/ice/base/ice_sched.c\n@@ -1369,6 +1369,46 @@ enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw)\n }\n \n /**\n+ * ice_sched_get_psm_clk_freq - determine the PSM clock frequency\n+ * @hw: pointer to the HW struct\n+ *\n+ * Determine the PSM clock frequency and store in HW struct\n+ */\n+void ice_sched_get_psm_clk_freq(struct ice_hw *hw)\n+{\n+\tu32 val, clk_src;\n+\n+\tval = rd32(hw, GLGEN_CLKSTAT_SRC);\n+\tclk_src = (val & GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M) >>\n+\t\tGLGEN_CLKSTAT_SRC_PSM_CLK_SRC_S;\n+\n+#define PSM_CLK_SRC_367_MHZ 0x0\n+#define PSM_CLK_SRC_416_MHZ 0x1\n+#define PSM_CLK_SRC_446_MHZ 0x2\n+#define PSM_CLK_SRC_390_MHZ 0x3\n+\n+\tswitch (clk_src) {\n+\tcase PSM_CLK_SRC_367_MHZ:\n+\t\thw->psm_clk_freq = ICE_PSM_CLK_367MHZ_IN_HZ;\n+\t\tbreak;\n+\tcase PSM_CLK_SRC_416_MHZ:\n+\t\thw->psm_clk_freq = ICE_PSM_CLK_416MHZ_IN_HZ;\n+\t\tbreak;\n+\tcase PSM_CLK_SRC_446_MHZ:\n+\t\thw->psm_clk_freq = ICE_PSM_CLK_446MHZ_IN_HZ;\n+\t\tbreak;\n+\tcase PSM_CLK_SRC_390_MHZ:\n+\t\thw->psm_clk_freq = ICE_PSM_CLK_390MHZ_IN_HZ;\n+\t\tbreak;\n+\tdefault:\n+\t\tice_debug(hw, ICE_DBG_SCHED, \"PSM clk_src unexpected %u\\n\",\n+\t\t\t clk_src);\n+\t\t/* fall back to a safe default */\n+\t\thw->psm_clk_freq = ICE_PSM_CLK_446MHZ_IN_HZ;\n+\t}\n+}\n+\n+/**\n * ice_sched_find_node_in_subtree - Find node in part of base node subtree\n * @hw: pointer to the HW struct\n * @base: pointer to the base node\n@@ -2867,7 +2907,7 @@ ice_sched_update_elem(struct ice_hw *hw, struct ice_sched_node *node,\n */\n static enum ice_status\n ice_sched_cfg_node_bw_alloc(struct ice_hw *hw, struct ice_sched_node *node,\n-\t\t\t enum ice_rl_type rl_type, u8 bw_alloc)\n+\t\t\t enum ice_rl_type rl_type, u16 bw_alloc)\n {\n \tstruct ice_aqc_txsched_elem_data buf;\n \tstruct ice_aqc_txsched_elem *data;\n@@ -3671,11 +3711,12 @@ ice_cfg_agg_bw_alloc(struct ice_port_info *pi, u32 agg_id, u8 ena_tcmap,\n \n /**\n * ice_sched_calc_wakeup - calculate RL profile wakeup parameter\n+ * @hw: pointer to the HW struct\n * @bw: bandwidth in Kbps\n *\n * This function calculates the wakeup parameter of RL profile.\n */\n-static u16 ice_sched_calc_wakeup(s32 bw)\n+static u16 ice_sched_calc_wakeup(struct ice_hw *hw, s32 bw)\n {\n \ts64 bytes_per_sec, wakeup_int, wakeup_a, wakeup_b, wakeup_f;\n \ts32 wakeup_f_int;\n@@ -3683,7 +3724,7 @@ static u16 ice_sched_calc_wakeup(s32 bw)\n \n \t/* Get the wakeup integer value */\n \tbytes_per_sec = DIV_64BIT(((s64)bw * 1000), BITS_PER_BYTE);\n-\twakeup_int = DIV_64BIT(ICE_RL_PROF_FREQUENCY, bytes_per_sec);\n+\twakeup_int = DIV_64BIT(hw->psm_clk_freq, bytes_per_sec);\n \tif (wakeup_int > 63) {\n \t\twakeup = (u16)((1 << 15) | wakeup_int);\n \t} else {\n@@ -3692,7 +3733,7 @@ static u16 ice_sched_calc_wakeup(s32 bw)\n \t\t */\n \t\twakeup_b = (s64)ICE_RL_PROF_MULTIPLIER * wakeup_int;\n \t\twakeup_a = DIV_64BIT((s64)ICE_RL_PROF_MULTIPLIER *\n-\t\t\t\t ICE_RL_PROF_FREQUENCY, bytes_per_sec);\n+\t\t\t\t hw->psm_clk_freq, bytes_per_sec);\n \n \t\t/* Get Fraction value */\n \t\twakeup_f = wakeup_a - wakeup_b;\n@@ -3712,13 +3753,15 @@ static u16 ice_sched_calc_wakeup(s32 bw)\n \n /**\n * ice_sched_bw_to_rl_profile - convert BW to profile parameters\n+ * @hw: pointer to the HW struct\n * @bw: bandwidth in Kbps\n * @profile: profile parameters to return\n *\n * This function converts the BW to profile structure format.\n */\n static enum ice_status\n-ice_sched_bw_to_rl_profile(u32 bw, struct ice_aqc_rl_profile_elem *profile)\n+ice_sched_bw_to_rl_profile(struct ice_hw *hw, u32 bw,\n+\t\t\t struct ice_aqc_rl_profile_elem *profile)\n {\n \tenum ice_status status = ICE_ERR_PARAM;\n \ts64 bytes_per_sec, ts_rate, mv_tmp;\n@@ -3738,7 +3781,7 @@ ice_sched_bw_to_rl_profile(u32 bw, struct ice_aqc_rl_profile_elem *profile)\n \tfor (i = 0; i < 64; i++) {\n \t\tu64 pow_result = BIT_ULL(i);\n \n-\t\tts_rate = DIV_64BIT((s64)ICE_RL_PROF_FREQUENCY,\n+\t\tts_rate = DIV_64BIT((s64)hw->psm_clk_freq,\n \t\t\t\t pow_result * ICE_RL_PROF_TS_MULTIPLIER);\n \t\tif (ts_rate <= 0)\n \t\t\tcontinue;\n@@ -3762,7 +3805,7 @@ ice_sched_bw_to_rl_profile(u32 bw, struct ice_aqc_rl_profile_elem *profile)\n \tif (found) {\n \t\tu16 wm;\n \n-\t\twm = ice_sched_calc_wakeup(bw);\n+\t\twm = ice_sched_calc_wakeup(hw, bw);\n \t\tprofile->rl_multiply = CPU_TO_LE16(mv);\n \t\tprofile->wake_up_calc = CPU_TO_LE16(wm);\n \t\tprofile->rl_encode = CPU_TO_LE16(encode);\n@@ -3831,7 +3874,7 @@ ice_sched_add_rl_profile(struct ice_port_info *pi,\n \tif (!rl_prof_elem)\n \t\treturn NULL;\n \n-\tstatus = ice_sched_bw_to_rl_profile(bw, &rl_prof_elem->profile);\n+\tstatus = ice_sched_bw_to_rl_profile(hw, bw, &rl_prof_elem->profile);\n \tif (status != ICE_SUCCESS)\n \t\tgoto exit_add_rl_prof;\n \ndiff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h\nindex d6b467477..1a8549931 100644\n--- a/drivers/net/ice/base/ice_sched.h\n+++ b/drivers/net/ice/base/ice_sched.h\n@@ -25,12 +25,16 @@\n \t((BIT(11) - 1) * 64) /* In Bytes */\n #define ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY\tICE_MAX_BURST_SIZE_ALLOWED\n \n-#define ICE_RL_PROF_FREQUENCY 446000000\n #define ICE_RL_PROF_ACCURACY_BYTES 128\n #define ICE_RL_PROF_MULTIPLIER 10000\n #define ICE_RL_PROF_TS_MULTIPLIER 32\n #define ICE_RL_PROF_FRACTION 512\n \n+#define ICE_PSM_CLK_367MHZ_IN_HZ 367647059\n+#define ICE_PSM_CLK_416MHZ_IN_HZ 416666667\n+#define ICE_PSM_CLK_446MHZ_IN_HZ 446428571\n+#define ICE_PSM_CLK_390MHZ_IN_HZ 390625000\n+\n struct rl_profile_params {\n \tu32 bw;\t\t\t/* in Kbps */\n \tu16 rl_multiplier;\n@@ -83,6 +87,7 @@ ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req,\n \t\t\t u16 *elems_ret, struct ice_sq_cd *cd);\n enum ice_status ice_sched_init_port(struct ice_port_info *pi);\n enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw);\n+void ice_sched_get_psm_clk_freq(struct ice_hw *hw);\n \n /* Functions to cleanup scheduler SW DB */\n void ice_sched_clear_port(struct ice_port_info *pi);\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex 9773a549f..237220ee8 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -524,7 +524,7 @@ struct ice_sched_node {\n #define ICE_TXSCHED_GET_EIR_BWALLOC(x)\t\\\n \tLE16_TO_CPU((x)->info.eir_bw.bw_alloc)\n \n-struct ice_sched_rl_profle {\n+struct ice_sched_rl_profile {\n \tu32 rate; /* In Kbps */\n \tstruct ice_aqc_rl_profile_elem info;\n };\n@@ -741,6 +741,8 @@ struct ice_hw {\n \tstruct ice_sched_rl_profile **cir_profiles;\n \tstruct ice_sched_rl_profile **eir_profiles;\n \tstruct ice_sched_rl_profile **srl_profiles;\n+\t/* PSM clock frequency for calculating RL profile params */\n+\tu32 psm_clk_freq;\n \tu64 debug_mask;\t\t/* BITMAP for debug mask */\n \tenum ice_mac_type mac_type;\n \n", "prefixes": [ "04/28" ] }