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GET /api/patches/66308/?format=api
{ "id": 66308, "url": "http://patches.dpdk.org/api/patches/66308/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200305153454.724874-6-pablo.de.lara.guarch@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200305153454.724874-6-pablo.de.lara.guarch@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200305153454.724874-6-pablo.de.lara.guarch@intel.com", "date": "2020-03-05T15:34:54", "name": "[RFC,5/5] crypto/aesni_gcm: support IPSec MB library v0.53", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "27d9a2d7adb8b2a313fc49e699f91a5d885c6411", "submitter": { "id": 9, "url": "http://patches.dpdk.org/api/people/9/?format=api", "name": "De Lara Guarch, Pablo", "email": "pablo.de.lara.guarch@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200305153454.724874-6-pablo.de.lara.guarch@intel.com/mbox/", "series": [ { "id": 8802, "url": "http://patches.dpdk.org/api/series/8802/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8802", "date": "2020-03-05T15:34:49", "name": "Support Intel IPSec MB v0.53 in DPDK 18.11", "version": 1, "mbox": "http://patches.dpdk.org/series/8802/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/66308/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/66308/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E5EDEA0564;\n\tThu, 5 Mar 2020 18:10:38 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D67931C00E;\n\tThu, 5 Mar 2020 18:09:46 +0100 (CET)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by dpdk.org (Postfix) with ESMTP id 6250D1BFE2\n for <dev@dpdk.org>; Thu, 5 Mar 2020 18:09:42 +0100 (CET)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 05 Mar 2020 09:09:41 -0800", "from silpixa00400565.ir.intel.com (HELO\n silpixa00400565.ger.corp.intel.com) ([10.237.222.249])\n by fmsmga002.fm.intel.com with ESMTP; 05 Mar 2020 09:09:40 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.70,518,1574150400\"; d=\"scan'208\";a=\"275173411\"", "From": "Pablo de Lara <pablo.de.lara.guarch@intel.com>", "To": "dev@dpdk.org", "Cc": "Pablo de Lara <pablo.de.lara.guarch@intel.com>", "Date": "Thu, 5 Mar 2020 15:34:54 +0000", "Message-Id": "<20200305153454.724874-6-pablo.de.lara.guarch@intel.com>", "X-Mailer": "git-send-email 2.24.1", "In-Reply-To": "<20200305153454.724874-1-pablo.de.lara.guarch@intel.com>", "References": "<20200305153454.724874-1-pablo.de.lara.guarch@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [RFC PATCH 5/5] crypto/aesni_gcm: support IPSec MB\n\tlibrary v0.53", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support for underlying Intel IPSec Multi-buffer library v0.53.\n\nSigned-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>\n---\n drivers/crypto/aesni_gcm/aesni_gcm_ops.h | 65 ++-------\n drivers/crypto/aesni_gcm/aesni_gcm_pmd.c | 130 +++++++++++++-----\n drivers/crypto/aesni_gcm/aesni_gcm_pmd_ops.c | 4 +-\n .../crypto/aesni_gcm/aesni_gcm_pmd_private.h | 4 +\n 4 files changed, 114 insertions(+), 89 deletions(-)", "diff": "diff --git a/drivers/crypto/aesni_gcm/aesni_gcm_ops.h b/drivers/crypto/aesni_gcm/aesni_gcm_ops.h\nindex 450616698..b2cc4002e 100644\n--- a/drivers/crypto/aesni_gcm/aesni_gcm_ops.h\n+++ b/drivers/crypto/aesni_gcm/aesni_gcm_ops.h\n@@ -17,14 +17,15 @@ enum aesni_gcm_vector_mode {\n \tRTE_AESNI_GCM_SSE,\n \tRTE_AESNI_GCM_AVX,\n \tRTE_AESNI_GCM_AVX2,\n+\tRTE_AESNI_GCM_AVX512,\n \tRTE_AESNI_GCM_VECTOR_NUM\n };\n \n enum aesni_gcm_key {\n-\tAESNI_GCM_KEY_128,\n-\tAESNI_GCM_KEY_192,\n-\tAESNI_GCM_KEY_256,\n-\tAESNI_GCM_KEY_NUM\n+\tGCM_KEY_128 = 0,\n+\tGCM_KEY_192,\n+\tGCM_KEY_256,\n+\tGCM_KEY_NUM\n };\n \n \n@@ -34,7 +35,7 @@ typedef void (*aesni_gcm_t)(const struct gcm_key_data *gcm_key_data,\n \t\tconst uint8_t *aad, uint64_t aad_len,\n \t\tuint8_t *auth_tag, uint64_t auth_tag_len);\n \n-typedef void (*aesni_gcm_precomp_t)(const void *key, struct gcm_key_data *gcm_data);\n+typedef void (*aesni_gcm_pre_t)(const void *key, struct gcm_key_data *gcm_data);\n \n typedef void (*aesni_gcm_init_t)(const struct gcm_key_data *gcm_key_data,\n \t\tstruct gcm_context_data *gcm_ctx_data,\n@@ -57,60 +58,12 @@ typedef void (*aesni_gcm_finalize_t)(const struct gcm_key_data *gcm_key_data,\n struct aesni_gcm_ops {\n \taesni_gcm_t enc; /**< GCM encode function pointer */\n \taesni_gcm_t dec; /**< GCM decode function pointer */\n-\taesni_gcm_precomp_t precomp; /**< GCM pre-compute */\n+\taesni_gcm_pre_t pre; /**< GCM pre-compute */\n \taesni_gcm_init_t init;\n \taesni_gcm_update_t update_enc;\n \taesni_gcm_update_t update_dec;\n-\taesni_gcm_finalize_t finalize;\n+\taesni_gcm_finalize_t finalize_enc;\n+\taesni_gcm_finalize_t finalize_dec;\n };\n \n-#define AES_GCM_FN(keylen, arch) \\\n-aes_gcm_enc_##keylen##_##arch,\\\n-aes_gcm_dec_##keylen##_##arch,\\\n-aes_gcm_pre_##keylen##_##arch,\\\n-aes_gcm_init_##keylen##_##arch,\\\n-aes_gcm_enc_##keylen##_update_##arch,\\\n-aes_gcm_dec_##keylen##_update_##arch,\\\n-aes_gcm_enc_##keylen##_finalize_##arch,\n-\n-static const struct aesni_gcm_ops gcm_ops[RTE_AESNI_GCM_VECTOR_NUM][AESNI_GCM_KEY_NUM] = {\n-\t[RTE_AESNI_GCM_NOT_SUPPORTED] = {\n-\t\t[AESNI_GCM_KEY_128] = {NULL},\n-\t\t[AESNI_GCM_KEY_192] = {NULL},\n-\t\t[AESNI_GCM_KEY_256] = {NULL}\n-\t},\n-\t[RTE_AESNI_GCM_SSE] = {\n-\t\t[AESNI_GCM_KEY_128] = {\n-\t\t\tAES_GCM_FN(128, sse)\n-\t\t},\n-\t\t[AESNI_GCM_KEY_192] = {\n-\t\t\tAES_GCM_FN(192, sse)\n-\t\t},\n-\t\t[AESNI_GCM_KEY_256] = {\n-\t\t\tAES_GCM_FN(256, sse)\n-\t\t}\n-\t},\n-\t[RTE_AESNI_GCM_AVX] = {\n-\t\t[AESNI_GCM_KEY_128] = {\n-\t\t\tAES_GCM_FN(128, avx_gen2)\n-\t\t},\n-\t\t[AESNI_GCM_KEY_192] = {\n-\t\t\tAES_GCM_FN(192, avx_gen2)\n-\t\t},\n-\t\t[AESNI_GCM_KEY_256] = {\n-\t\t\tAES_GCM_FN(256, avx_gen2)\n-\t\t}\n-\t},\n-\t[RTE_AESNI_GCM_AVX2] = {\n-\t\t[AESNI_GCM_KEY_128] = {\n-\t\t\tAES_GCM_FN(128, avx_gen4)\n-\t\t},\n-\t\t[AESNI_GCM_KEY_192] = {\n-\t\t\tAES_GCM_FN(192, avx_gen4)\n-\t\t},\n-\t\t[AESNI_GCM_KEY_256] = {\n-\t\t\tAES_GCM_FN(256, avx_gen4)\n-\t\t}\n-\t}\n-};\n #endif /* _AESNI_GCM_OPS_H_ */\ndiff --git a/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c b/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c\nindex ebdf7c35a..2bda5a560 100644\n--- a/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c\n+++ b/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c\n@@ -24,7 +24,7 @@ aesni_gcm_set_session_parameters(const struct aesni_gcm_ops *gcm_ops,\n \tconst struct rte_crypto_sym_xform *auth_xform;\n \tconst struct rte_crypto_sym_xform *aead_xform;\n \tuint8_t key_length;\n-\tuint8_t *key;\n+\tconst uint8_t *key;\n \n \t/* AES-GMAC */\n \tif (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH) {\n@@ -89,20 +89,20 @@ aesni_gcm_set_session_parameters(const struct aesni_gcm_ops *gcm_ops,\n \t/* Check key length and calculate GCM pre-compute. */\n \tswitch (key_length) {\n \tcase 16:\n-\t\tsess->key = AESNI_GCM_KEY_128;\n+\t\tsess->key = GCM_KEY_128;\n \t\tbreak;\n \tcase 24:\n-\t\tsess->key = AESNI_GCM_KEY_192;\n+\t\tsess->key = GCM_KEY_192;\n \t\tbreak;\n \tcase 32:\n-\t\tsess->key = AESNI_GCM_KEY_256;\n+\t\tsess->key = GCM_KEY_256;\n \t\tbreak;\n \tdefault:\n \t\tAESNI_GCM_LOG(ERR, \"Invalid key length\");\n \t\treturn -EINVAL;\n \t}\n \n-\tgcm_ops[sess->key].precomp(key, &sess->gdata_key);\n+\tgcm_ops[sess->key].pre(key, &sess->gdata_key);\n \n \t/* Digest check */\n \tif (sess->req_digest_length > 16) {\n@@ -195,6 +195,7 @@ process_gcm_crypto_op(struct aesni_gcm_qp *qp, struct rte_crypto_op *op,\n \tuint32_t offset, data_offset, data_length;\n \tuint32_t part_len, total_len, data_len;\n \tuint8_t *tag;\n+\tunsigned int oop = 0;\n \n \tif (session->op == AESNI_GCM_OP_AUTHENTICATED_ENCRYPTION ||\n \t\t\tsession->op == AESNI_GCM_OP_AUTHENTICATED_DECRYPTION) {\n@@ -216,27 +217,30 @@ process_gcm_crypto_op(struct aesni_gcm_qp *qp, struct rte_crypto_op *op,\n \t\tRTE_ASSERT(m_src != NULL);\n \t}\n \n+\tsrc = rte_pktmbuf_mtod_offset(m_src, uint8_t *, offset);\n+\n \tdata_len = m_src->data_len - offset;\n \tpart_len = (data_len < data_length) ? data_len :\n \t\t\tdata_length;\n \n-\t/* Destination buffer is required when segmented source buffer */\n-\tRTE_ASSERT((part_len == data_length) ||\n-\t\t\t((part_len != data_length) &&\n-\t\t\t\t\t(sym_op->m_dst != NULL)));\n-\t/* Segmented destination buffer is not supported */\n \tRTE_ASSERT((sym_op->m_dst == NULL) ||\n \t\t\t((sym_op->m_dst != NULL) &&\n \t\t\t\t\trte_pktmbuf_is_contiguous(sym_op->m_dst)));\n \n-\n-\tdst = sym_op->m_dst ?\n-\t\t\trte_pktmbuf_mtod_offset(sym_op->m_dst, uint8_t *,\n-\t\t\t\t\tdata_offset) :\n-\t\t\trte_pktmbuf_mtod_offset(sym_op->m_src, uint8_t *,\n+\t/* In-place */\n+\tif (sym_op->m_dst == NULL || (sym_op->m_dst == sym_op->m_src))\n+\t\tdst = src;\n+\t/* Out-of-place */\n+\telse {\n+\t\toop = 1;\n+\t\t/*\n+\t\t * Segmented destination buffer is not supported if operation is\n+\t\t * Out-of-place\n+\t\t */\n+\t\tRTE_ASSERT(rte_pktmbuf_is_contiguous(sym_op->m_dst));\n+\t\tdst = rte_pktmbuf_mtod_offset(sym_op->m_dst, uint8_t *,\n \t\t\t\t\tdata_offset);\n-\n-\tsrc = rte_pktmbuf_mtod_offset(m_src, uint8_t *, offset);\n+\t}\n \n \tiv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,\n \t\t\t\tsession->iv.offset);\n@@ -254,12 +258,15 @@ process_gcm_crypto_op(struct aesni_gcm_qp *qp, struct rte_crypto_op *op,\n \t\ttotal_len = data_length - part_len;\n \n \t\twhile (total_len) {\n-\t\t\tdst += part_len;\n \t\t\tm_src = m_src->next;\n \n \t\t\tRTE_ASSERT(m_src != NULL);\n \n \t\t\tsrc = rte_pktmbuf_mtod(m_src, uint8_t *);\n+\t\t\tif (oop)\n+\t\t\t\tdst += part_len;\n+\t\t\telse\n+\t\t\t\tdst = src;\n \t\t\tpart_len = (m_src->data_len < total_len) ?\n \t\t\t\t\tm_src->data_len : total_len;\n \n@@ -274,7 +281,7 @@ process_gcm_crypto_op(struct aesni_gcm_qp *qp, struct rte_crypto_op *op,\n \t\telse\n \t\t\ttag = sym_op->aead.digest.data;\n \n-\t\tqp->ops[session->key].finalize(&session->gdata_key,\n+\t\tqp->ops[session->key].finalize_enc(&session->gdata_key,\n \t\t\t\t&qp->gdata_ctx,\n \t\t\t\ttag,\n \t\t\t\tsession->gen_digest_length);\n@@ -291,12 +298,15 @@ process_gcm_crypto_op(struct aesni_gcm_qp *qp, struct rte_crypto_op *op,\n \t\ttotal_len = data_length - part_len;\n \n \t\twhile (total_len) {\n-\t\t\tdst += part_len;\n \t\t\tm_src = m_src->next;\n \n \t\t\tRTE_ASSERT(m_src != NULL);\n \n \t\t\tsrc = rte_pktmbuf_mtod(m_src, uint8_t *);\n+\t\t\tif (oop)\n+\t\t\t\tdst += part_len;\n+\t\t\telse\n+\t\t\t\tdst = src;\n \t\t\tpart_len = (m_src->data_len < total_len) ?\n \t\t\t\t\tm_src->data_len : total_len;\n \n@@ -308,7 +318,7 @@ process_gcm_crypto_op(struct aesni_gcm_qp *qp, struct rte_crypto_op *op,\n \t\t}\n \n \t\ttag = qp->temp_digest;\n-\t\tqp->ops[session->key].finalize(&session->gdata_key,\n+\t\tqp->ops[session->key].finalize_dec(&session->gdata_key,\n \t\t\t\t&qp->gdata_ctx,\n \t\t\t\ttag,\n \t\t\t\tsession->gen_digest_length);\n@@ -322,7 +332,7 @@ process_gcm_crypto_op(struct aesni_gcm_qp *qp, struct rte_crypto_op *op,\n \t\t\ttag = qp->temp_digest;\n \t\telse\n \t\t\ttag = sym_op->auth.digest.data;\n-\t\tqp->ops[session->key].finalize(&session->gdata_key,\n+\t\tqp->ops[session->key].finalize_enc(&session->gdata_key,\n \t\t\t\t&qp->gdata_ctx,\n \t\t\t\ttag,\n \t\t\t\tsession->gen_digest_length);\n@@ -338,7 +348,7 @@ process_gcm_crypto_op(struct aesni_gcm_qp *qp, struct rte_crypto_op *op,\n \t\t * the bytes passed.\n \t\t */\n \t\ttag = qp->temp_digest;\n-\t\tqp->ops[session->key].finalize(&session->gdata_key,\n+\t\tqp->ops[session->key].finalize_enc(&session->gdata_key,\n \t\t\t\t&qp->gdata_ctx,\n \t\t\t\ttag,\n \t\t\t\tsession->gen_digest_length);\n@@ -487,12 +497,8 @@ aesni_gcm_create(const char *name,\n \tstruct rte_cryptodev *dev;\n \tstruct aesni_gcm_private *internals;\n \tenum aesni_gcm_vector_mode vector_mode;\n+\tMB_MGR *mb_mgr;\n \n-\t/* Check CPU for support for AES instruction set */\n-\tif (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_AES)) {\n-\t\tAESNI_GCM_LOG(ERR, \"AES instructions not supported by CPU\");\n-\t\treturn -EFAULT;\n-\t}\n \tdev = rte_cryptodev_pmd_create(name, &vdev->device, init_params);\n \tif (dev == NULL) {\n \t\tAESNI_GCM_LOG(ERR, \"driver %s: create failed\",\n@@ -501,7 +507,9 @@ aesni_gcm_create(const char *name,\n \t}\n \n \t/* Check CPU for supported vector instruction set */\n-\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))\n+\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))\n+\t\tvector_mode = RTE_AESNI_GCM_AVX512;\n+\telse if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))\n \t\tvector_mode = RTE_AESNI_GCM_AVX2;\n \telse if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX))\n \t\tvector_mode = RTE_AESNI_GCM_AVX;\n@@ -517,27 +525,74 @@ aesni_gcm_create(const char *name,\n \n \tdev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |\n \t\t\tRTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |\n-\t\t\tRTE_CRYPTODEV_FF_CPU_AESNI |\n+\t\t\tRTE_CRYPTODEV_FF_IN_PLACE_SGL |\n \t\t\tRTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |\n \t\t\tRTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT;\n \n+\t/* Check CPU for support for AES instruction set */\n+\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AES))\n+\t\tdev->feature_flags |= RTE_CRYPTODEV_FF_CPU_AESNI;\n+\telse\n+\t\tAESNI_GCM_LOG(WARNING, \"AES instructions not supported by CPU\");\n+\n+\tmb_mgr = alloc_mb_mgr(0);\n+\tif (mb_mgr == NULL)\n+\t\treturn -ENOMEM;\n+\n \tswitch (vector_mode) {\n \tcase RTE_AESNI_GCM_SSE:\n \t\tdev->feature_flags |= RTE_CRYPTODEV_FF_CPU_SSE;\n+\t\tinit_mb_mgr_sse(mb_mgr);\n \t\tbreak;\n \tcase RTE_AESNI_GCM_AVX:\n \t\tdev->feature_flags |= RTE_CRYPTODEV_FF_CPU_AVX;\n+\t\tinit_mb_mgr_avx(mb_mgr);\n \t\tbreak;\n \tcase RTE_AESNI_GCM_AVX2:\n \t\tdev->feature_flags |= RTE_CRYPTODEV_FF_CPU_AVX2;\n+\t\tinit_mb_mgr_avx2(mb_mgr);\n \t\tbreak;\n-\tdefault:\n+\tcase RTE_AESNI_GCM_AVX512:\n+\t\tdev->feature_flags |= RTE_CRYPTODEV_FF_CPU_AVX2;\n+\t\tinit_mb_mgr_avx512(mb_mgr);\n \t\tbreak;\n+\tdefault:\n+\t\tAESNI_GCM_LOG(ERR, \"Unsupported vector mode %u\\n\", vector_mode);\n+\t\tgoto error_exit;\n \t}\n \n \tinternals = dev->data->dev_private;\n \n \tinternals->vector_mode = vector_mode;\n+\tinternals->mb_mgr = mb_mgr;\n+\n+\t/* Set arch independent function pointers, based on key size */\n+\tinternals->ops[GCM_KEY_128].enc = mb_mgr->gcm128_enc;\n+\tinternals->ops[GCM_KEY_128].dec = mb_mgr->gcm128_dec;\n+\tinternals->ops[GCM_KEY_128].pre = mb_mgr->gcm128_pre;\n+\tinternals->ops[GCM_KEY_128].init = mb_mgr->gcm128_init;\n+\tinternals->ops[GCM_KEY_128].update_enc = mb_mgr->gcm128_enc_update;\n+\tinternals->ops[GCM_KEY_128].update_dec = mb_mgr->gcm128_dec_update;\n+\tinternals->ops[GCM_KEY_128].finalize_enc = mb_mgr->gcm128_enc_finalize;\n+\tinternals->ops[GCM_KEY_128].finalize_dec = mb_mgr->gcm128_dec_finalize;\n+\n+\tinternals->ops[GCM_KEY_192].enc = mb_mgr->gcm192_enc;\n+\tinternals->ops[GCM_KEY_192].dec = mb_mgr->gcm192_dec;\n+\tinternals->ops[GCM_KEY_192].pre = mb_mgr->gcm192_pre;\n+\tinternals->ops[GCM_KEY_192].init = mb_mgr->gcm192_init;\n+\tinternals->ops[GCM_KEY_192].update_enc = mb_mgr->gcm192_enc_update;\n+\tinternals->ops[GCM_KEY_192].update_dec = mb_mgr->gcm192_dec_update;\n+\tinternals->ops[GCM_KEY_192].finalize_enc = mb_mgr->gcm192_enc_finalize;\n+\tinternals->ops[GCM_KEY_192].finalize_dec = mb_mgr->gcm192_dec_finalize;\n+\n+\tinternals->ops[GCM_KEY_256].enc = mb_mgr->gcm256_enc;\n+\tinternals->ops[GCM_KEY_256].dec = mb_mgr->gcm256_dec;\n+\tinternals->ops[GCM_KEY_256].pre = mb_mgr->gcm256_pre;\n+\tinternals->ops[GCM_KEY_256].init = mb_mgr->gcm256_init;\n+\tinternals->ops[GCM_KEY_256].update_enc = mb_mgr->gcm256_enc_update;\n+\tinternals->ops[GCM_KEY_256].update_dec = mb_mgr->gcm256_dec_update;\n+\tinternals->ops[GCM_KEY_256].finalize_enc = mb_mgr->gcm256_enc_finalize;\n+\tinternals->ops[GCM_KEY_256].finalize_dec = mb_mgr->gcm256_dec_finalize;\n \n \tinternals->max_nb_queue_pairs = init_params->max_nb_queue_pairs;\n \n@@ -549,6 +604,14 @@ aesni_gcm_create(const char *name,\n #endif\n \n \treturn 0;\n+\n+error_exit:\n+\tif (mb_mgr)\n+\t\tfree_mb_mgr(mb_mgr);\n+\n+\trte_cryptodev_pmd_destroy(dev);\n+\n+\treturn -1;\n }\n \n static int\n@@ -576,6 +639,7 @@ static int\n aesni_gcm_remove(struct rte_vdev_device *vdev)\n {\n \tstruct rte_cryptodev *cryptodev;\n+\tstruct aesni_gcm_private *internals;\n \tconst char *name;\n \n \tname = rte_vdev_device_name(vdev);\n@@ -586,6 +650,10 @@ aesni_gcm_remove(struct rte_vdev_device *vdev)\n \tif (cryptodev == NULL)\n \t\treturn -ENODEV;\n \n+\tinternals = cryptodev->data->dev_private;\n+\n+\tfree_mb_mgr(internals->mb_mgr);\n+\n \treturn rte_cryptodev_pmd_destroy(cryptodev);\n }\n \ndiff --git a/drivers/crypto/aesni_gcm/aesni_gcm_pmd_ops.c b/drivers/crypto/aesni_gcm/aesni_gcm_pmd_ops.c\nindex c343a393f..f599fc3f7 100644\n--- a/drivers/crypto/aesni_gcm/aesni_gcm_pmd_ops.c\n+++ b/drivers/crypto/aesni_gcm/aesni_gcm_pmd_ops.c\n@@ -222,7 +222,7 @@ aesni_gcm_pmd_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \tif (aesni_gcm_pmd_qp_set_unique_name(dev, qp))\n \t\tgoto qp_setup_cleanup;\n \n-\tqp->ops = (const struct aesni_gcm_ops *)gcm_ops[internals->vector_mode];\n+\tqp->ops = (const struct aesni_gcm_ops *)internals->ops;\n \n \tqp->processed_pkts = aesni_gcm_pmd_qp_create_processed_pkts_ring(qp,\n \t\t\tqp_conf->nb_descriptors, socket_id);\n@@ -277,7 +277,7 @@ aesni_gcm_pmd_sym_session_configure(struct rte_cryptodev *dev __rte_unused,\n \t\t\t\t\"Couldn't get object from session mempool\");\n \t\treturn -ENOMEM;\n \t}\n-\tret = aesni_gcm_set_session_parameters(gcm_ops[internals->vector_mode],\n+\tret = aesni_gcm_set_session_parameters(internals->ops,\n \t\t\t\tsess_private_data, xform);\n \tif (ret != 0) {\n \t\tAESNI_GCM_LOG(ERR, \"failed configure session parameters\");\ndiff --git a/drivers/crypto/aesni_gcm/aesni_gcm_pmd_private.h b/drivers/crypto/aesni_gcm/aesni_gcm_pmd_private.h\nindex 92b041354..fd43df3cf 100644\n--- a/drivers/crypto/aesni_gcm/aesni_gcm_pmd_private.h\n+++ b/drivers/crypto/aesni_gcm/aesni_gcm_pmd_private.h\n@@ -35,6 +35,10 @@ struct aesni_gcm_private {\n \t/**< Vector mode */\n \tunsigned max_nb_queue_pairs;\n \t/**< Max number of queue pairs supported by device */\n+\tMB_MGR *mb_mgr;\n+\t/**< Multi-buffer instance */\n+\tstruct aesni_gcm_ops ops[GCM_KEY_NUM];\n+\t/**< Function pointer table of the gcm APIs */\n };\n \n struct aesni_gcm_qp {\n", "prefixes": [ "RFC", "5/5" ] }