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GET /api/patches/66253/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 66253,
    "url": "http://patches.dpdk.org/api/patches/66253/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1583346152-10186-6-git-send-email-nicolas.chautru@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1583346152-10186-6-git-send-email-nicolas.chautru@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1583346152-10186-6-git-send-email-nicolas.chautru@intel.com",
    "date": "2020-03-04T18:22:22",
    "name": "[v2,05/15] test-bbdev: rename FPGA LTE macros to be more explicit",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "239657b6f7b9166ce6ccdbe1ad380e413db690e4",
    "submitter": {
        "id": 1314,
        "url": "http://patches.dpdk.org/api/people/1314/?format=api",
        "name": "Chautru, Nicolas",
        "email": "nicolas.chautru@intel.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patches.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1583346152-10186-6-git-send-email-nicolas.chautru@intel.com/mbox/",
    "series": [
        {
            "id": 8783,
            "url": "http://patches.dpdk.org/api/series/8783/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8783",
            "date": "2020-03-04T18:22:17",
            "name": "bbdev new features",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/8783/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/66253/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/66253/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 22D45A0573;\n\tWed,  4 Mar 2020 19:23:35 +0100 (CET)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 45B5C1BFF5;\n\tWed,  4 Mar 2020 19:22:54 +0100 (CET)",
            "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by dpdk.org (Postfix) with ESMTP id 4F6441BFA9\n for <dev@dpdk.org>; Wed,  4 Mar 2020 19:22:46 +0100 (CET)",
            "from fmsmga008.fm.intel.com ([10.253.24.58])\n by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 04 Mar 2020 10:22:43 -0800",
            "from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210])\n by fmsmga008.fm.intel.com with ESMTP; 04 Mar 2020 10:22:43 -0800"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.70,514,1574150400\"; d=\"scan'208\";a=\"234199006\"",
        "From": "Nicolas Chautru <nicolas.chautru@intel.com>",
        "To": "thomas@monjalon.net,\n\takhil.goyal@nxp.com,\n\tdev@dpdk.org",
        "Cc": "ferruh.yigit@intel.com,\n\tNic Chautru <nicolas.chautru@intel.com>",
        "Date": "Wed,  4 Mar 2020 10:22:22 -0800",
        "Message-Id": "<1583346152-10186-6-git-send-email-nicolas.chautru@intel.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": "<1583346152-10186-1-git-send-email-nicolas.chautru@intel.com>",
        "References": "<1582778348-113547-15-git-send-email-nicolas.chautru@intel.com>\n <1583346152-10186-1-git-send-email-nicolas.chautru@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v2 05/15] test-bbdev: rename FPGA LTE macros to\n\tbe more explicit",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Nic Chautru <nicolas.chautru@intel.com>\n\nSelf-contained and cosmetic renaming of macro\nso that to be more explict for future extension.\n\nSigned-off-by: Nic Chautru <nicolas.chautru@intel.com>\n---\n app/test-bbdev/test_bbdev_perf.c | 51 +++++++++++++++-------------------------\n 1 file changed, 19 insertions(+), 32 deletions(-)",
    "diff": "diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c\nindex d46966d..aa8bb71 100644\n--- a/app/test-bbdev/test_bbdev_perf.c\n+++ b/app/test-bbdev/test_bbdev_perf.c\n@@ -18,10 +18,6 @@\n #include <rte_hexdump.h>\n #include <rte_interrupts.h>\n \n-#ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC\n-#include <fpga_lte_fec.h>\n-#endif\n-\n #include \"main.h\"\n #include \"test_bbdev_vector.h\"\n \n@@ -31,15 +27,16 @@\n #define TEST_REPETITIONS 1000\n \n #ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC\n-#define FPGA_PF_DRIVER_NAME (\"intel_fpga_lte_fec_pf\")\n-#define FPGA_VF_DRIVER_NAME (\"intel_fpga_lte_fec_vf\")\n-#define VF_UL_QUEUE_VALUE 4\n-#define VF_DL_QUEUE_VALUE 4\n-#define UL_BANDWIDTH 3\n-#define DL_BANDWIDTH 3\n-#define UL_LOAD_BALANCE 128\n-#define DL_LOAD_BALANCE 128\n-#define FLR_TIMEOUT 610\n+#include <fpga_lte_fec.h>\n+#define FPGA_LTE_PF_DRIVER_NAME (\"intel_fpga_lte_fec_pf\")\n+#define FPGA_LTE_VF_DRIVER_NAME (\"intel_fpga_lte_fec_vf\")\n+#define VF_UL_4G_QUEUE_VALUE 4\n+#define VF_DL_4G_QUEUE_VALUE 4\n+#define UL_4G_BANDWIDTH 3\n+#define DL_4G_BANDWIDTH 3\n+#define UL_4G_LOAD_BALANCE 128\n+#define DL_4G_LOAD_BALANCE 128\n+#define FLR_4G_TIMEOUT 610\n #endif\n \n #define OPS_CACHE_SIZE 256U\n@@ -521,11 +518,11 @@ typedef int (test_case_function)(struct active_device *ad,\n  */\n #ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC\n \tif ((get_init_device() == true) &&\n-\t\t(!strcmp(info->drv.driver_name, FPGA_PF_DRIVER_NAME))) {\n+\t\t(!strcmp(info->drv.driver_name, FPGA_LTE_PF_DRIVER_NAME))) {\n \t\tstruct fpga_lte_fec_conf conf;\n \t\tunsigned int i;\n \n-\t\tprintf(\"Configure FPGA FEC Driver %s with default values\\n\",\n+\t\tprintf(\"Configure FPGA LTE FEC Driver %s with default values\\n\",\n \t\t\t\tinfo->drv.driver_name);\n \n \t\t/* clear default configuration before initialization */\n@@ -539,22 +536,22 @@ typedef int (test_case_function)(struct active_device *ad,\n \n \t\tfor (i = 0; i < FPGA_LTE_FEC_NUM_VFS; ++i) {\n \t\t\t/* Number of UL queues per VF (fpga supports 8 VFs) */\n-\t\t\tconf.vf_ul_queues_number[i] = VF_UL_QUEUE_VALUE;\n+\t\t\tconf.vf_ul_queues_number[i] = VF_UL_4G_QUEUE_VALUE;\n \t\t\t/* Number of DL queues per VF (fpga supports 8 VFs) */\n-\t\t\tconf.vf_dl_queues_number[i] = VF_DL_QUEUE_VALUE;\n+\t\t\tconf.vf_dl_queues_number[i] = VF_DL_4G_QUEUE_VALUE;\n \t\t}\n \n \t\t/* UL bandwidth. Needed for schedule algorithm */\n-\t\tconf.ul_bandwidth = UL_BANDWIDTH;\n+\t\tconf.ul_bandwidth = UL_4G_BANDWIDTH;\n \t\t/* DL bandwidth */\n-\t\tconf.dl_bandwidth = DL_BANDWIDTH;\n+\t\tconf.dl_bandwidth = DL_4G_BANDWIDTH;\n \n \t\t/* UL & DL load Balance Factor to 64 */\n-\t\tconf.ul_load_balance = UL_LOAD_BALANCE;\n-\t\tconf.dl_load_balance = DL_LOAD_BALANCE;\n+\t\tconf.ul_load_balance = UL_4G_LOAD_BALANCE;\n+\t\tconf.dl_load_balance = DL_4G_LOAD_BALANCE;\n \n \t\t/**< FLR timeout value */\n-\t\tconf.flr_time_out = FLR_TIMEOUT;\n+\t\tconf.flr_time_out = FLR_4G_TIMEOUT;\n \n \t\t/* setup FPGA PF with configuration information */\n \t\tret = fpga_lte_fec_configure(info->dev_name, &conf);\n@@ -2862,11 +2859,6 @@ typedef int (test_case_function)(struct active_device *ad,\n \n \t\tstart_time = rte_rdtsc_precise();\n \n-\t\t/*\n-\t\t * printf(\"Latency Debug %d\\n\",\n-\t\t * ops_enq[0]->ldpc_enc.cb_params.z_c); REMOVEME\n-\t\t */\n-\n \t\tenq = rte_bbdev_enqueue_ldpc_enc_ops(dev_id, queue_id,\n \t\t\t\t&ops_enq[enq], burst_sz);\n \t\tTEST_ASSERT(enq == burst_sz,\n@@ -2892,11 +2884,6 @@ typedef int (test_case_function)(struct active_device *ad,\n \t\t\tTEST_ASSERT_SUCCESS(ret, \"Validation failed!\");\n \t\t}\n \n-\t\t/*\n-\t\t * printf(\"Ready to free - deq %d num_to_process %d\\n\", FIXME\n-\t\t *\t\tdeq, num_to_process);\n-\t\t * printf(\"cache %d\\n\", ops_enq[0]->mempool->cache_size);\n-\t\t */\n \t\trte_bbdev_enc_op_free_bulk(ops_enq, deq);\n \t\tdequeued += deq;\n \t}\n",
    "prefixes": [
        "v2",
        "05/15"
    ]
}