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GET /api/patches/66170/?format=api
{ "id": 66170, "url": "http://patches.dpdk.org/api/patches/66170/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200302143209.11854-10-hemant.agrawal@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200302143209.11854-10-hemant.agrawal@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200302143209.11854-10-hemant.agrawal@nxp.com", "date": "2020-03-02T14:32:08", "name": "[09/10] net/enetc: improve prefetch in Rx ring clean", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "105f813f51adc6f54ec6b896850a2846dae58127", "submitter": { "id": 477, "url": "http://patches.dpdk.org/api/people/477/?format=api", "name": "Hemant Agrawal", "email": "hemant.agrawal@nxp.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200302143209.11854-10-hemant.agrawal@nxp.com/mbox/", "series": [ { "id": 8741, "url": "http://patches.dpdk.org/api/series/8741/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8741", "date": "2020-03-02T14:31:59", "name": "net/enetc: optimization and cleanup", "version": 1, "mbox": "http://patches.dpdk.org/series/8741/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/66170/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/66170/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 70D5EA0568;\n\tMon, 2 Mar 2020 10:01:59 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id BEBD81C0B6;\n\tMon, 2 Mar 2020 10:00:28 +0100 (CET)", "from inva020.nxp.com (inva020.nxp.com [92.121.34.13])\n by dpdk.org (Postfix) with ESMTP id 07B8C1C067\n for <dev@dpdk.org>; Mon, 2 Mar 2020 10:00:22 +0100 (CET)", "from inva020.nxp.com (localhost [127.0.0.1])\n by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id E07B21A0FDC;\n Mon, 2 Mar 2020 10:00:21 +0100 (CET)", "from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com\n [165.114.16.14])\n by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 206861A0FB1;\n Mon, 2 Mar 2020 10:00:19 +0100 (CET)", "from bf-netperf1.ap.com (bf-netperf1.ap.freescale.net\n [10.232.133.63])\n by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id C2D96402FA;\n Mon, 2 Mar 2020 17:00:15 +0800 (SGT)" ], "From": "Hemant Agrawal <hemant.agrawal@nxp.com>", "To": "ferruh.yigit@intel.com", "Cc": "dev@dpdk.org, g.singh@nxp.com,\n Alex Marginean <alexandru.marginean@nxp.com>", "Date": "Mon, 2 Mar 2020 20:02:08 +0530", "Message-Id": "<20200302143209.11854-10-hemant.agrawal@nxp.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200302143209.11854-1-hemant.agrawal@nxp.com>", "References": "<20200302143209.11854-1-hemant.agrawal@nxp.com>", "X-Virus-Scanned": "ClamAV using ClamSMTP", "Subject": "[dpdk-dev] [PATCH 09/10] net/enetc: improve prefetch in Rx ring\n\tclean", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Alex Marginean <alexandru.marginean@nxp.com>\n\nLS1028A does not have platform cache so any reads following a hardware\nwrite will go directly to DDR. Latency of such a read is in excess of 100\ncore cycles, so try to prefetch more in advance to mitigate this.\nHow much is worth prefetching really depends on traffic conditions. With\ncongested Rx this could go up to 4 cache lines or so. But if software\nkeeps up with hardware and follows behind Rx PI by a cache line then it's\nharmful in terms of performance to cache more. We would only prefetch\ndata that's yet to be written by ENETC, which will be evicted again anyway.\n\nSigned-off-by: Alex Marginean <alexandru.marginean@nxp.com>\n---\n drivers/net/enetc/enetc_rxtx.c | 38 +++++++++++++++++++++++++++++-----\n 1 file changed, 33 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/net/enetc/enetc_rxtx.c b/drivers/net/enetc/enetc_rxtx.c\nindex 1acc43a08..e57ecf2d4 100644\n--- a/drivers/net/enetc/enetc_rxtx.c\n+++ b/drivers/net/enetc/enetc_rxtx.c\n@@ -14,6 +14,8 @@\n #include \"enetc.h\"\n #include \"enetc_logs.h\"\n \n+#define ENETC_CACHE_LINE_RXBDS\t(RTE_CACHE_LINE_SIZE / \\\n+\t\t\t\t sizeof(union enetc_rx_bd))\n #define ENETC_RXBD_BUNDLE 16 /* Number of buffers to allocate at once */\n \n static int\n@@ -321,18 +323,37 @@ enetc_clean_rx_ring(struct enetc_bdr *rx_ring,\n \t\t int work_limit)\n {\n \tint rx_frm_cnt = 0;\n-\tint cleaned_cnt, i;\n+\tint cleaned_cnt, i, bd_count;\n \tstruct enetc_swbd *rx_swbd;\n+\tunion enetc_rx_bd *rxbd;\n \n-\tcleaned_cnt = enetc_bd_unused(rx_ring);\n \t/* next descriptor to process */\n \ti = rx_ring->next_to_clean;\n+\t/* next descriptor to process */\n+\trxbd = ENETC_RXBD(*rx_ring, i);\n+\trte_prefetch0(rxbd);\n+\tbd_count = rx_ring->bd_count;\n+\t/* LS1028A does not have platform cache so any software access following\n+\t * a hardware write will go directly to DDR. Latency of such a read is\n+\t * in excess of 100 core cycles, so try to prefetch more in advance to\n+\t * mitigate this.\n+\t * How much is worth prefetching really depends on traffic conditions.\n+\t * With congested Rx this could go up to 4 cache lines or so. But if\n+\t * software keeps up with hardware and follows behind Rx PI by a cache\n+\t * line or less then it's harmful in terms of performance to cache more.\n+\t * We would only prefetch BDs that have yet to be written by ENETC,\n+\t * which will have to be evicted again anyway.\n+\t */\n+\trte_prefetch0(ENETC_RXBD(*rx_ring,\n+\t\t\t\t (i + ENETC_CACHE_LINE_RXBDS) % bd_count));\n+\trte_prefetch0(ENETC_RXBD(*rx_ring,\n+\t\t\t\t (i + ENETC_CACHE_LINE_RXBDS * 2) % bd_count));\n+\n+\tcleaned_cnt = enetc_bd_unused(rx_ring);\n \trx_swbd = &rx_ring->q_swbd[i];\n \twhile (likely(rx_frm_cnt < work_limit)) {\n-\t\tunion enetc_rx_bd *rxbd;\n \t\tuint32_t bd_status;\n \n-\t\trxbd = ENETC_RXBD(*rx_ring, i);\n \t\tbd_status = rte_le_to_cpu_32(rxbd->r.lstatus);\n \t\tif (!bd_status)\n \t\t\tbreak;\n@@ -353,11 +374,18 @@ enetc_clean_rx_ring(struct enetc_bdr *rx_ring,\n \t\t\ti = 0;\n \t\t\trx_swbd = &rx_ring->q_swbd[i];\n \t\t}\n+\t\trxbd = ENETC_RXBD(*rx_ring, i);\n+\t\trte_prefetch0(ENETC_RXBD(*rx_ring,\n+\t\t\t\t\t (i + ENETC_CACHE_LINE_RXBDS) %\n+\t\t\t\t\t bd_count));\n+\t\trte_prefetch0(ENETC_RXBD(*rx_ring,\n+\t\t\t\t\t (i + ENETC_CACHE_LINE_RXBDS * 2) %\n+\t\t\t\t\t bd_count));\n \n-\t\trx_ring->next_to_clean = i;\n \t\trx_frm_cnt++;\n \t}\n \n+\trx_ring->next_to_clean = i;\n \tenetc_refill_rx_ring(rx_ring, cleaned_cnt);\n \n \treturn rx_frm_cnt;\n", "prefixes": [ "09/10" ] }