Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/66134/?format=api
{ "id": 66134, "url": "http://patches.dpdk.org/api/patches/66134/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1582879102-17977-6-git-send-email-xiaojun.liu@silicom.co.il/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1582879102-17977-6-git-send-email-xiaojun.liu@silicom.co.il>", "list_archive_url": "https://inbox.dpdk.org/dev/1582879102-17977-6-git-send-email-xiaojun.liu@silicom.co.il", "date": "2020-02-28T08:38:22", "name": "[v1,5/5] net/fm10k: add switch management support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "33954e0a63d07d5676391154fc4d07d1b906272d", "submitter": { "id": 1512, "url": "http://patches.dpdk.org/api/people/1512/?format=api", "name": "Xiaojun Liu", "email": "xiaojun.liu@silicom.co.il" }, "delegate": { "id": 31221, "url": "http://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1582879102-17977-6-git-send-email-xiaojun.liu@silicom.co.il/mbox/", "series": [ { "id": 8723, "url": "http://patches.dpdk.org/api/series/8723/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8723", "date": "2020-02-28T08:38:17", "name": "support fm10k switch management", "version": 1, "mbox": "http://patches.dpdk.org/series/8723/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/66134/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/66134/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E5562A0561;\n\tFri, 28 Feb 2020 09:40:45 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6AC4B1C022;\n\tFri, 28 Feb 2020 09:39:29 +0100 (CET)", "from EUR05-VI1-obe.outbound.protection.outlook.com\n (mail-vi1eur05on2124.outbound.protection.outlook.com [40.107.21.124])\n by dpdk.org (Postfix) with ESMTP id 274761C00D\n for <dev@dpdk.org>; Fri, 28 Feb 2020 09:39:25 +0100 (CET)", "from DB7PR04MB5196.eurprd04.prod.outlook.com (20.176.234.140) by\n DB7PR04MB5484.eurprd04.prod.outlook.com (20.178.106.147) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.2772.14; Fri, 28 Feb 2020 08:39:23 +0000", "from DB7PR04MB5196.eurprd04.prod.outlook.com\n ([fe80::a400:f6b9:34b1:ed]) by DB7PR04MB5196.eurprd04.prod.outlook.com\n ([fe80::a400:f6b9:34b1:ed%5]) with mapi id 15.20.2750.024; Fri, 28 Feb 2020\n 08:39:23 +0000", "from xj-desktop.net-perf.com (119.139.199.125) by\n HK2PR02CA0207.apcprd02.prod.outlook.com (2603:1096:201:20::19) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.2772.14 via Frontend Transport; Fri, 28 Feb 2020 08:39:21 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=nJJOSamoSLapzDXj21QN9YJSv1boxfysXsApfSrC9/+YdPehcAakOuoY+E+beOwpIP7Y1StzciYFNQGHmeZDXDFnOEIPUxet1b0aOZNLn4g55VfPJryr/h2XXI0jGQLk3/qLYTBCN7KnXv/bkJvPY83BiGTBxiF0I+j6cBGtXc0Y0imd75P+sjpw5dqJUzAurW/nL+0yfpyP+kxkmQJnXqddU+U3hSF2IODY5yPW/j29k/Iw8j6aTdItz0M4YvM3GUM6lP4whtA5zTrD2zip63By9Aqww/mNbT7UD8EfYL09XbqbchmamAdwIyzX4HQs2957h8o5qs8+w2fVnVnv2Q==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=niM0DXW4BJIZbxyriNarrdrr2l8cUNkygsjJWffA9Zc=;\n b=JOgHAzubs5cj2jfrRlE9DezAFLARj5CeFQjv0+3TtEw6CN6dMEpPJgwnAGubE1G9pRSax35IOPsf3kWoF7OiZqG7w88QJlTlBGiebW9DBKu1cJU5MD/Wt84sV5+JDcTFtRBhanGyKsEPSxg1hAfqD4lrQs6xbJncgdj5Tvx0/6KyFtXRl8XCSOZckQ2QGot0PKwj9Jjw8tUAPhrDqCmvr6R+tRR1xTZdoHy5R2aR01IVZIeV7wTKzSOVxzR6k0dNLotZzYQZ9FrSan6fU1YbI/mDbjF2aQP6GYjCIDTi/KAyOAXBIDAcpPdVE9Y6Wc/u6aY/C0a5ch/icHgSDrfxpw==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=silicom.co.il; dmarc=pass action=none\n header.from=silicom.co.il; dkim=pass header.d=silicom.co.il; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=SILICOMLTD.onmicrosoft.com; s=selector2-SILICOMLTD-onmicrosoft-com;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=niM0DXW4BJIZbxyriNarrdrr2l8cUNkygsjJWffA9Zc=;\n b=yCfFPQ3fkyl2/AsX/ng6WToRGJfQO+CsocXrN4M1yFwIxUN6oGEJF6g2fZBk3Hb3SRcQBzOtu9CtSgvllj5ubf4GBBryR26G0dPMYem5X1J1j8mmn0/KdnU+VShgx84Mpd6L12979ducO/LBOrQ8OvksJD1F7tNAclZp8rN1HOU=", "Authentication-Results": "spf=none (sender IP is )\n smtp.mailfrom=xiaojun.liu@silicom.co.il;", "From": "Xiaojun Liu <xiaojun.liu@silicom.co.il>", "To": "xiao.w.wang@intel.com, qi.z.zhang@intel.com, ngai-mint.kwan@intel.com,\n jacob.e.keller@intel.com", "Cc": "dev@dpdk.org,\n\tXiaojun Liu <xiaojun.liu@silicom.co.il>", "Date": "Fri, 28 Feb 2020 16:38:22 +0800", "Message-Id": "<1582879102-17977-6-git-send-email-xiaojun.liu@silicom.co.il>", "X-Mailer": [ "git-send-email 1.8.3.1", "git-send-email 1.8.3.1" ], "In-Reply-To": "<1582879102-17977-1-git-send-email-xiaojun.liu@silicom.co.il>", "References": "<1582207174-31037-2-git-send-email-xiaojun.liu@silicom.co.il>\n <1582879102-17977-1-git-send-email-xiaojun.liu@silicom.co.il>", "Content-Type": "text/plain", "X-ClientProxiedBy": "HK2PR02CA0207.apcprd02.prod.outlook.com\n (2603:1096:201:20::19) To DB7PR04MB5196.eurprd04.prod.outlook.com\n (2603:10a6:10:1a::12)", "MIME-Version": "1.0", "X-MS-Exchange-MessageSentRepresentingType": "1", "X-Originating-IP": "[119.139.199.125]", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "e1d1dd76-f8bd-4b20-34f0-08d7bc29b63a", "X-MS-TrafficTypeDiagnostic": "DB7PR04MB5484:", "X-MS-Exchange-Transport-Forked": "True", "X-Microsoft-Antispam-PRVS": "\n <DB7PR04MB54842CA6AE8EB416F75ABAC6BDE80@DB7PR04MB5484.eurprd04.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:478;", "X-Forefront-PRVS": "0327618309", "X-Forefront-Antispam-Report": "SFV:NSPM;\n SFS:(10019020)(376002)(136003)(346002)(366004)(396003)(39850400004)(189003)(199004)(86362001)(5660300002)(2906002)(8936002)(107886003)(4326008)(956004)(44832011)(66946007)(66556008)(2616005)(8676002)(81156014)(81166006)(66476007)(316002)(478600001)(6506007)(36756003)(16526019)(52116002)(186003)(30864003)(26005)(6486002)(6512007)(290074003);\n DIR:OUT; SFP:1102; SCL:1; SRVR:DB7PR04MB5484;\n H:DB7PR04MB5196.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en;\n PTR:InfoNoRecords; MX:1; A:1;", "Received-SPF": "None (protection.outlook.com: silicom.co.il does not designate\n permitted sender hosts)", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n u3L1zxp6bMCzr/WFf/O0r84X8Lgkfi+j1JPI7ePpS/yZn7Y97v1WQPw3q6CUrqkeasd8ja1OQIJtZ5XDCi462A74YONV7qRJVbHeFm+qwYj0nzYG+izGJhzxEZJ7bfwSOqUk7564p1d3nXbYqwWIiP995MngYFudvgpmO0b8Bz43Sp0NythweB/zLyroBAXREcAH+FtWzCUNZHDOy/HbuHWMCrUO/TujWuYUWVe5MHA2+B90MWIlsLRMu0pPWK7gK6ZeEzg60PL9ujgGHaqta5t2XUxAR+3C82U6pA0p93nQhwmQA/UKnsMP6GN4BvT2ieRO8aBkjnsbXEitVhcXP/KH3EBTh5GZBftGtFIfcB/9YLp53ljXeTUwCiagMftd6SHS9seg9HmIVkHSJVvAtyXJM26j0QYriVqL40SFdGgXlYGmjws7b4aqXjyxPMPE7rlTGJpdYdXHQIik3M8LdNU9F/78nwzfbZ6Gd2QxHjpfrrKwsc11UUi5DAEDTpsf", "X-MS-Exchange-AntiSpam-MessageData": "\n qeqgJqXHXtjrf9KByI4IpRcECgCnvV7XJWPOIka7EgeIxJ3IjJ/EzuONUAHLGDxKpd+/c6e/w6clHuA96ztdla7AuO/Klwf742qbh4EMbr0HIcxvOQA8hUBRU4cBGq8y7tsK1eamnwzFItqHWFm3fg==", "X-OriginatorOrg": "silicom.co.il", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e1d1dd76-f8bd-4b20-34f0-08d7bc29b63a", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "28 Feb 2020 08:39:23.5632 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "c9e326d8-ce47-4930-8612-cc99d3c87ad1", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n 2soJzFerL8cdsXJd9fRiOVSkTS1/psfnLL3u/EHOdSR4PfnWheIDMOf2kzmSELJ0XcHEOgqzZwKHj0MbrylDTRfZ6tsA/T6Pxsde1RRm4no=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DB7PR04MB5484", "Subject": "[dpdk-dev] [PATCH v1 5/5] net/fm10k: add switch management support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Split dev init to 2 parts.\nFirst only register the port in switch\nmanagement; second init hook will be\ncalled after all the pf are registered\nand switch initialization. It will finish\ndev init. Also add switch interrupt support.\nAdd fm10k_mirror_rule_set/fm10k_mirror_rule_reset\nto support mirror operation. Add fm10k_dev_filter_ctrl\nto support flow operation.\nAdd dpdk port and pf mapping, so\nthe dpdk port can map to a specific pf\nand 1 dpdk port can map to 2 pf to get\ntotal 100G throughput.\n\nTo enable the switch management, you need add\nCONFIG_RTE_FM10K_MANAGEMENT=y in\nconfig/common_linux when building.\n\nSigned-off-by: Xiaojun Liu <xiaojun.liu@silicom.co.il>\n---\n drivers/net/fm10k/base/fm10k_type.h | 1 +\n drivers/net/fm10k/fm10k_ethdev.c | 562 +++++++++++++++++++++++++++++---\n drivers/net/fm10k/switch/fm10k_switch.c | 20 +-\n drivers/net/fm10k/switch/fm10k_switch.h | 1 +\n 4 files changed, 541 insertions(+), 43 deletions(-)", "diff": "diff --git a/drivers/net/fm10k/base/fm10k_type.h b/drivers/net/fm10k/base/fm10k_type.h\nindex 84781ba..810e5ee 100644\n--- a/drivers/net/fm10k/base/fm10k_type.h\n+++ b/drivers/net/fm10k/base/fm10k_type.h\n@@ -717,6 +717,7 @@ struct fm10k_hw {\n \tu16 subsystem_vendor_id;\n \tu8 revision_id;\n \tu32 flags;\n+\tbool switch_ready;\n #define FM10K_HW_FLAG_CLOCK_OWNER\tBIT(0)\n };\n \ndiff --git a/drivers/net/fm10k/fm10k_ethdev.c b/drivers/net/fm10k/fm10k_ethdev.c\nindex 581c690..f11fa53 100644\n--- a/drivers/net/fm10k/fm10k_ethdev.c\n+++ b/drivers/net/fm10k/fm10k_ethdev.c\n@@ -13,6 +13,10 @@\n \n #include \"fm10k.h\"\n #include \"base/fm10k_api.h\"\n+#ifdef RTE_FM10K_MANAGEMENT\n+#include \"switch/fm10k_regs.h\"\n+#include \"switch/fm10k_switch.h\"\n+#endif\n \n /* Default delay to acquire mailbox lock */\n #define FM10K_MBXLOCK_DELAY_US 20\n@@ -461,9 +465,6 @@ struct fm10k_xstats_name_off {\n \n \tPMD_INIT_FUNC_TRACE();\n \n-\tif (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)\n-\t\tdev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;\n-\n \t/* multipe queue mode checking */\n \tret = fm10k_check_mq_mode(dev);\n \tif (ret != 0) {\n@@ -512,6 +513,15 @@ struct fm10k_xstats_name_off {\n \tstruct rte_eth_conf *dev_conf = &dev->data->dev_conf;\n \tuint32_t mrqc, *key, i, reta, j;\n \tuint64_t hf;\n+#ifdef RTE_FM10K_MANAGEMENT\n+\tuint16_t nb_rx_queues = dev->data->nb_rx_queues;\n+\tint mapped_num;\n+\tstruct fm10k_hw *mapped_hws[FM10K_SW_PEP_MAP_NUM_MAX];\n+\n+\tmapped_num = fm10k_switch_dpdk_mapped_hw_get(hw, mapped_hws);\n+\tif (mapped_num == 2)\n+\t\tnb_rx_queues /= 2;\n+#endif\n \n #define RSS_KEY_SIZE 40\n \tstatic uint8_t rss_intel_key[RSS_KEY_SIZE] = {\n@@ -642,26 +652,44 @@ struct fm10k_xstats_name_off {\n fm10k_dev_tx_init(struct rte_eth_dev *dev)\n {\n \tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+#ifdef RTE_FM10K_MANAGEMENT\n+\tstruct fm10k_hw *unmap_hw = hw;\n+\tuint32_t data;\n+#endif\n \tint i, ret;\n+\tuint16_t hw_queue_id;\n \tstruct fm10k_tx_queue *txq;\n \tuint64_t base_addr;\n \tuint32_t size;\n \n+#ifndef RTE_FM10K_MANAGEMENT\n \t/* Disable TXINT to avoid possible interrupt */\n \tfor (i = 0; i < hw->mac.max_queues; i++)\n \t\tFM10K_WRITE_REG(hw, FM10K_TXINT(i),\n \t\t\t\t3 << FM10K_TXINT_TIMER_SHIFT);\n+#else\n+\tfm10k_switch_dpdk_tx_queue_num_set(unmap_hw,\n+\t\tdev->data->nb_tx_queues);\n+#endif\n \n \t/* Setup TX queue */\n \tfor (i = 0; i < dev->data->nb_tx_queues; ++i) {\n+\t\thw_queue_id = i;\n+#ifdef RTE_FM10K_MANAGEMENT\n+\t\tfm10k_switch_dpdk_hw_queue_map(unmap_hw,\n+\t\t\ti, dev->data->nb_tx_queues,\n+\t\t\t&hw, &hw_queue_id);\n+#endif\n \t\ttxq = dev->data->tx_queues[i];\n \t\tbase_addr = txq->hw_ring_phys_addr;\n \t\tsize = txq->nb_desc * sizeof(struct fm10k_tx_desc);\n \n \t\t/* disable queue to avoid issues while updating state */\n-\t\tret = tx_queue_disable(hw, i);\n+\t\tret = tx_queue_disable(hw, hw_queue_id);\n \t\tif (ret) {\n-\t\t\tPMD_INIT_LOG(ERR, \"failed to disable queue %d\", i);\n+\t\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\t\t\"failed to disable queue %d\",\n+\t\t\t\t\thw_queue_id);\n \t\t\treturn -1;\n \t\t}\n \t\t/* Enable use of FTAG bit in TX descriptor, PFVTCTL\n@@ -669,7 +697,7 @@ struct fm10k_xstats_name_off {\n \t\t */\n \t\tif (fm10k_check_ftag(dev->device->devargs)) {\n \t\t\tif (hw->mac.type == fm10k_mac_pf) {\n-\t\t\t\tFM10K_WRITE_REG(hw, FM10K_PFVTCTL(i),\n+\t\t\t\tFM10K_WRITE_REG(hw, FM10K_PFVTCTL(hw_queue_id),\n \t\t\t\t\t\tFM10K_PFVTCTL_FTAG_DESC_ENABLE);\n \t\t\t\tPMD_INIT_LOG(DEBUG, \"FTAG mode is enabled\");\n \t\t\t} else {\n@@ -679,15 +707,25 @@ struct fm10k_xstats_name_off {\n \t\t}\n \n \t\t/* set location and size for descriptor ring */\n-\t\tFM10K_WRITE_REG(hw, FM10K_TDBAL(i),\n+\t\tFM10K_WRITE_REG(hw, FM10K_TDBAL(hw_queue_id),\n \t\t\t\tbase_addr & UINT64_LOWER_32BITS_MASK);\n-\t\tFM10K_WRITE_REG(hw, FM10K_TDBAH(i),\n+\t\tFM10K_WRITE_REG(hw, FM10K_TDBAH(hw_queue_id),\n \t\t\t\tbase_addr >> (CHAR_BIT * sizeof(uint32_t)));\n-\t\tFM10K_WRITE_REG(hw, FM10K_TDLEN(i), size);\n+\t\tFM10K_WRITE_REG(hw, FM10K_TDLEN(hw_queue_id), size);\n \n \t\t/* assign default SGLORT for each TX queue by PF */\n+#ifndef RTE_FM10K_MANAGEMENT\n \t\tif (hw->mac.type == fm10k_mac_pf)\n-\t\t\tFM10K_WRITE_REG(hw, FM10K_TX_SGLORT(i), hw->mac.dglort_map);\n+\t\t\tFM10K_WRITE_REG(hw,\n+\t\t\t\t\tFM10K_TX_SGLORT(hw_queue_id),\n+\t\t\t\t\thw->mac.dglort_map);\n+#else\n+\t\tif (hw->mac.type == fm10k_mac_pf) {\n+\t\t\tdata = FM10K_SW_MAKE_REG_FIELD\n+\t\t\t\t\t(TX_SGLORT_SGLORT, hw->mac.dglort_map);\n+\t\t\tFM10K_WRITE_REG(hw, FM10K_TX_SGLORT(hw_queue_id), data);\n+\t\t}\n+#endif\n \t}\n \n \t/* set up vector or scalar TX function as appropriate */\n@@ -700,18 +738,24 @@ struct fm10k_xstats_name_off {\n fm10k_dev_rx_init(struct rte_eth_dev *dev)\n {\n \tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+#ifndef RTE_FM10K_MANAGEMENT\n \tstruct fm10k_macvlan_filter_info *macvlan;\n \tstruct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);\n \tstruct rte_intr_handle *intr_handle = &pdev->intr_handle;\n+\tuint32_t logic_port = hw->mac.dglort_map;\n+\tuint16_t queue_stride = 0;\n+#else\n+\tstruct fm10k_hw *unmap_hw = hw;\n+#endif\n \tint i, ret;\n+\tuint16_t hw_queue_id;\n \tstruct fm10k_rx_queue *rxq;\n \tuint64_t base_addr;\n \tuint32_t size;\n \tuint32_t rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;\n-\tuint32_t logic_port = hw->mac.dglort_map;\n \tuint16_t buf_size;\n-\tuint16_t queue_stride = 0;\n \n+#ifndef RTE_FM10K_MANAGEMENT\n \t/* enable RXINT for interrupt mode */\n \ti = 0;\n \tif (rte_intr_dp_is_en(intr_handle)) {\n@@ -731,26 +775,36 @@ struct fm10k_xstats_name_off {\n \tfor (; i < hw->mac.max_queues; i++)\n \t\tFM10K_WRITE_REG(hw, FM10K_RXINT(i),\n \t\t\t3 << FM10K_RXINT_TIMER_SHIFT);\n+#else\n+\tfm10k_switch_dpdk_rx_queue_num_set(unmap_hw, dev->data->nb_rx_queues);\n+#endif\n \n \t/* Setup RX queues */\n \tfor (i = 0; i < dev->data->nb_rx_queues; ++i) {\n+\t\thw_queue_id = i;\n+#ifdef RTE_FM10K_MANAGEMENT\n+\t\tfm10k_switch_dpdk_hw_queue_map(unmap_hw,\n+\t\t\ti, dev->data->nb_rx_queues, &hw, &hw_queue_id);\n+#endif\n \t\trxq = dev->data->rx_queues[i];\n \t\tbase_addr = rxq->hw_ring_phys_addr;\n \t\tsize = rxq->nb_desc * sizeof(union fm10k_rx_desc);\n \n \t\t/* disable queue to avoid issues while updating state */\n-\t\tret = rx_queue_disable(hw, i);\n+\t\tret = rx_queue_disable(hw, hw_queue_id);\n \t\tif (ret) {\n-\t\t\tPMD_INIT_LOG(ERR, \"failed to disable queue %d\", i);\n+\t\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\t\t\"failed to disable queue %d\",\n+\t\t\t\t\thw_queue_id);\n \t\t\treturn -1;\n \t\t}\n \n \t\t/* Setup the Base and Length of the Rx Descriptor Ring */\n-\t\tFM10K_WRITE_REG(hw, FM10K_RDBAL(i),\n+\t\tFM10K_WRITE_REG(hw, FM10K_RDBAL(hw_queue_id),\n \t\t\t\tbase_addr & UINT64_LOWER_32BITS_MASK);\n-\t\tFM10K_WRITE_REG(hw, FM10K_RDBAH(i),\n+\t\tFM10K_WRITE_REG(hw, FM10K_RDBAH(hw_queue_id),\n \t\t\t\tbase_addr >> (CHAR_BIT * sizeof(uint32_t)));\n-\t\tFM10K_WRITE_REG(hw, FM10K_RDLEN(i), size);\n+\t\tFM10K_WRITE_REG(hw, FM10K_RDLEN(hw_queue_id), size);\n \n \t\t/* Configure the Rx buffer size for one buff without split */\n \t\tbuf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -\n@@ -764,7 +818,7 @@ struct fm10k_xstats_name_off {\n \t\t */\n \t\tbuf_size -= FM10K_RX_DATABUF_ALIGN;\n \n-\t\tFM10K_WRITE_REG(hw, FM10K_SRRCTL(i),\n+\t\tFM10K_WRITE_REG(hw, FM10K_SRRCTL(hw_queue_id),\n \t\t\t\t(buf_size >> FM10K_SRRCTL_BSIZEPKT_SHIFT) |\n \t\t\t\tFM10K_SRRCTL_LOOPBACK_SUPPRESS);\n \n@@ -774,9 +828,9 @@ struct fm10k_xstats_name_off {\n \t\t\trxq->offloads & DEV_RX_OFFLOAD_SCATTER) {\n \t\t\tuint32_t reg;\n \t\t\tdev->data->scattered_rx = 1;\n-\t\t\treg = FM10K_READ_REG(hw, FM10K_SRRCTL(i));\n+\t\t\treg = FM10K_READ_REG(hw, FM10K_SRRCTL(hw_queue_id));\n \t\t\treg |= FM10K_SRRCTL_BUFFER_CHAINING_EN;\n-\t\t\tFM10K_WRITE_REG(hw, FM10K_SRRCTL(i), reg);\n+\t\t\tFM10K_WRITE_REG(hw, FM10K_SRRCTL(hw_queue_id), reg);\n \t\t}\n \n \t\t/* Enable drop on empty, it's RO for VF */\n@@ -796,6 +850,7 @@ struct fm10k_xstats_name_off {\n \t/* update RX_SGLORT for loopback suppress*/\n \tif (hw->mac.type != fm10k_mac_pf)\n \t\treturn 0;\n+#ifndef RTE_FM10K_MANAGEMENT\n \tmacvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);\n \tif (macvlan->nb_queue_pools)\n \t\tqueue_stride = dev->data->nb_rx_queues / macvlan->nb_queue_pools;\n@@ -804,6 +859,7 @@ struct fm10k_xstats_name_off {\n \t\t\tlogic_port++;\n \t\tFM10K_WRITE_REG(hw, FM10K_RX_SGLORT(i), logic_port);\n \t}\n+#endif\n \n \treturn 0;\n }\n@@ -812,12 +868,29 @@ struct fm10k_xstats_name_off {\n fm10k_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n {\n \tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+#ifdef RTE_FM10K_MANAGEMENT\n+\tstruct fm10k_hw *unmap_hw = hw;\n+\tint ret;\n+#endif\n \tint err;\n \tuint32_t reg;\n \tstruct fm10k_rx_queue *rxq;\n+\tuint16_t hw_queue_id = rx_queue_id;\n \n \tPMD_INIT_FUNC_TRACE();\n \n+#ifdef RTE_FM10K_MANAGEMENT\n+\tret = fm10k_switch_dpdk_hw_queue_map(unmap_hw,\n+\t\t\trx_queue_id, dev->data->nb_rx_queues,\n+\t\t\t&hw, &hw_queue_id);\n+\tif (ret < 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Can not get the mapped HW and rx queue for:\"\n+\t\t\t\t\" %s %d\", dev->device->name, rx_queue_id);\n+\t\treturn -EIO;\n+\t} else if (ret != 1)\t/* reference port's queue don't need start */\n+\t\treturn 0;\n+#endif\n+\n \trxq = dev->data->rx_queues[rx_queue_id];\n \terr = rx_queue_reset(rxq);\n \tif (err == -ENOMEM) {\n@@ -836,23 +909,23 @@ struct fm10k_xstats_name_off {\n \t * this comment and the following two register writes when the\n \t * emulation platform is no longer being used.\n \t */\n-\tFM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);\n-\tFM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);\n+\tFM10K_WRITE_REG(hw, FM10K_RDH(hw_queue_id), 0);\n+\tFM10K_WRITE_REG(hw, FM10K_RDT(hw_queue_id), rxq->nb_desc - 1);\n \n \t/* Set PF ownership flag for PF devices */\n-\treg = FM10K_READ_REG(hw, FM10K_RXQCTL(rx_queue_id));\n+\treg = FM10K_READ_REG(hw, FM10K_RXQCTL(hw_queue_id));\n \tif (hw->mac.type == fm10k_mac_pf)\n \t\treg |= FM10K_RXQCTL_PF;\n \treg |= FM10K_RXQCTL_ENABLE;\n \t/* enable RX queue */\n-\tFM10K_WRITE_REG(hw, FM10K_RXQCTL(rx_queue_id), reg);\n+\tFM10K_WRITE_REG(hw, FM10K_RXQCTL(hw_queue_id), reg);\n \tFM10K_WRITE_FLUSH(hw);\n \n \t/* Setup the HW Rx Head and Tail Descriptor Pointers\n \t * Note: this must be done AFTER the queue is enabled\n \t */\n-\tFM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);\n-\tFM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);\n+\tFM10K_WRITE_REG(hw, FM10K_RDH(hw_queue_id), 0);\n+\tFM10K_WRITE_REG(hw, FM10K_RDT(hw_queue_id), rxq->nb_desc - 1);\n \tdev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;\n \n \treturn 0;\n@@ -879,21 +952,38 @@ struct fm10k_xstats_name_off {\n fm10k_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n {\n \tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+#ifdef RTE_FM10K_MANAGEMENT\n+\tstruct fm10k_hw *unmap_hw = hw;\n+\tint ret;\n+#endif\n \t/** @todo - this should be defined in the shared code */\n #define FM10K_TXDCTL_WRITE_BACK_MIN_DELAY\t0x00010000\n \tuint32_t txdctl = FM10K_TXDCTL_WRITE_BACK_MIN_DELAY;\n \tstruct fm10k_tx_queue *q = dev->data->tx_queues[tx_queue_id];\n+\tuint16_t hw_queue_id = tx_queue_id;\n \n \tPMD_INIT_FUNC_TRACE();\n \n+#ifdef RTE_FM10K_MANAGEMENT\n+\tret = fm10k_switch_dpdk_hw_queue_map(unmap_hw,\n+\t\ttx_queue_id, dev->data->nb_tx_queues, &hw, &hw_queue_id);\n+\tif (ret < 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Can not get the mapped HW and tx queue for:\"\n+\t\t\t\t\" %s %d\", dev->device->name, tx_queue_id);\n+\t\treturn -EIO;\n+\t} else if (ret != 1) {\n+\t\treturn 0;\n+\t}\n+#endif\n+\n \tq->ops->reset(q);\n \n \t/* reset head and tail pointers */\n-\tFM10K_WRITE_REG(hw, FM10K_TDH(tx_queue_id), 0);\n-\tFM10K_WRITE_REG(hw, FM10K_TDT(tx_queue_id), 0);\n+\tFM10K_WRITE_REG(hw, FM10K_TDH(hw_queue_id), 0);\n+\tFM10K_WRITE_REG(hw, FM10K_TDT(hw_queue_id), 0);\n \n \t/* enable TX queue */\n-\tFM10K_WRITE_REG(hw, FM10K_TXDCTL(tx_queue_id),\n+\tFM10K_WRITE_REG(hw, FM10K_TXDCTL(hw_queue_id),\n \t\t\t\tFM10K_TXDCTL_ENABLE | txdctl);\n \tFM10K_WRITE_FLUSH(hw);\n \tdev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;\n@@ -1084,9 +1174,25 @@ static inline int fm10k_glort_valid(struct fm10k_hw *hw)\n {\n \tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tint i, diag;\n+#ifdef RTE_FM10K_MANAGEMENT\n+\tstruct fm10k_hw *mapped_hws[FM10K_SW_PEP_MAP_NUM_MAX];\n+\tint j, mapped_num;\n+\tuint32_t data;\n+#endif\n \n \tPMD_INIT_FUNC_TRACE();\n \n+#ifdef RTE_FM10K_MANAGEMENT\n+\tmapped_num = fm10k_switch_dpdk_mapped_hw_get(hw, mapped_hws);\n+\tif (mapped_num < 0 || mapped_num > FM10K_SW_PEP_MAP_NUM_MAX) {\n+\t\tPMD_INIT_LOG(ERR, \"Can not get the mapped HW for %s\",\n+\t\t\t\tdev->device->name);\n+\t\treturn -EIO;\n+\t}\n+#endif\n+\n+\n+#ifndef RTE_FM10K_MANAGEMENT\n \t/* stop, init, then start the hw */\n \tdiag = fm10k_stop_hw(hw);\n \tif (diag != FM10K_SUCCESS) {\n@@ -1105,6 +1211,62 @@ static inline int fm10k_glort_valid(struct fm10k_hw *hw)\n \t\tPMD_INIT_LOG(ERR, \"Hardware start failed: %d\", diag);\n \t\treturn -EIO;\n \t}\n+#else\n+\tfor (j = 0; j < mapped_num; j++) {\n+\t\tstruct rte_pci_device *pdev =\n+\t\t\tRTE_ETH_DEV_TO_PCI((struct rte_eth_dev *)\n+\t\t\t(fm10k_switch_dpdk_port_rte_dev_get(mapped_hws[j])));\n+\t\tstruct rte_intr_handle *intr_handle = &pdev->intr_handle;\n+\n+\t\t/* stop, init, then start the hw */\n+\t\tdiag = fm10k_stop_hw(mapped_hws[j]);\n+\t\tif (diag != FM10K_SUCCESS) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Hardware stop failed: %d\", diag);\n+\t\t\treturn -EIO;\n+\t\t}\n+\n+\t\tdiag = fm10k_init_hw(mapped_hws[j]);\n+\t\tif (diag != FM10K_SUCCESS) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Hardware init failed: %d\", diag);\n+\t\t\treturn -EIO;\n+\t\t}\n+\n+\t\tdiag = fm10k_start_hw(mapped_hws[j]);\n+\t\tif (diag != FM10K_SUCCESS) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Hardware start failed: %d\", diag);\n+\t\t\treturn -EIO;\n+\t\t}\n+\n+\t\t/* Disable TXINT to avoid possible interrupt */\n+\t\tfor (i = 0; i < hw->mac.max_queues; i++)\n+\t\t\tFM10K_WRITE_REG(mapped_hws[j], FM10K_TXINT(i),\n+\t\t\t\t\t3 << FM10K_TXINT_TIMER_SHIFT);\n+\n+\t\t/* enable RXINT for interrupt mode */\n+\t\ti = 0;\n+\t\tif (rte_intr_dp_is_en(intr_handle)) {\n+\t\t\tfor (; i < dev->data->nb_rx_queues; i++) {\n+\t\t\t\tFM10K_WRITE_REG(mapped_hws[j],\n+\t\t\t\t\t\tFM10K_RXINT(i), Q2V(pdev, i));\n+\t\t\t\tif (mapped_hws[j]->mac.type == fm10k_mac_pf)\n+\t\t\t\t\tFM10K_WRITE_REG(mapped_hws[j],\n+\t\t\t\t\t\tFM10K_ITR(Q2V(pdev, i)),\n+\t\t\t\t\t\tFM10K_ITR_AUTOMASK |\n+\t\t\t\t\t\tFM10K_ITR_MASK_CLEAR);\n+\t\t\t\telse\n+\t\t\t\t\tFM10K_WRITE_REG(mapped_hws[j],\n+\t\t\t\t\t\tFM10K_VFITR(Q2V(pdev, i)),\n+\t\t\t\t\t\tFM10K_ITR_AUTOMASK |\n+\t\t\t\t\t\tFM10K_ITR_MASK_CLEAR);\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Disable other RXINT to avoid possible interrupt */\n+\t\tfor (; i < hw->mac.max_queues; i++)\n+\t\t\tFM10K_WRITE_REG(mapped_hws[j], FM10K_RXINT(i),\n+\t\t\t\t3 << FM10K_RXINT_TIMER_SHIFT);\n+\t}\n+#endif\n \n \tdiag = fm10k_dev_tx_init(dev);\n \tif (diag) {\n@@ -1156,10 +1318,26 @@ static inline int fm10k_glort_valid(struct fm10k_hw *hw)\n \t\t}\n \t}\n \n+#ifndef RTE_FM10K_MANAGEMENT\n \t/* Update default vlan when not in VMDQ mode */\n \tif (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))\n \t\tfm10k_vlan_filter_set(dev, hw->mac.default_vid, true);\n+#endif\n \n+#ifdef RTE_FM10K_MANAGEMENT\n+\t/* Admit all VLANs */\n+\tfor (j = 0; j <= 64; j++) {\n+\t\tfor (i = 0; i < FM10K_SW_VLAN_TABLE_ENTRIES; i++)\n+\t\t\tFM10K_WRITE_REG(hw,\n+\t\t\t\t\tFM10K_SW_VLAN_TABLE_ENTRY(j, i),\n+\t\t\t\t\t0xffffffff);\n+\t}\n+\n+\t/* Disable PEP loopback */\n+\tdata = FM10K_READ_REG(hw, FM10K_CTRL_EXT);\n+\tdata &= ~FM10K_SW_CTRL_EXT_SWITCH_LOOPBACK;\n+\tFM10K_WRITE_REG(hw, FM10K_CTRL_EXT, data);\n+#endif\n \tfm10k_link_update(dev, 0);\n \n \treturn 0;\n@@ -1327,12 +1505,24 @@ static int fm10k_xstats_get_names(__rte_unused struct rte_eth_dev *dev,\n \tstruct fm10k_hw_stats *hw_stats =\n \t\tFM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);\n \tint i;\n+#ifdef RTE_FM10K_MANAGEMENT\n+\tstruct fm10k_hw *unmap_hw = hw;\n+\tstruct fm10k_hw *mapped_hws[FM10K_SW_PEP_MAP_NUM_MAX];\n+\tint mapped_num;\n+\tuint16_t hw_queue_id;\n+#endif\n \n \tPMD_INIT_FUNC_TRACE();\n \n+\tipackets = 0;\n+\topackets = 0;\n+\tibytes = 0;\n+\tobytes = 0;\n+\timissed = 0;\n+\n+#ifndef RTE_FM10K_MANAGEMENT\n \tfm10k_update_hw_stats(hw, hw_stats);\n \n-\tipackets = opackets = ibytes = obytes = imissed = 0;\n \tfor (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&\n \t\t(i < hw->mac.max_queues); ++i) {\n \t\tstats->q_ipackets[i] = hw_stats->q[i].rx_packets.count;\n@@ -1346,6 +1536,49 @@ static int fm10k_xstats_get_names(__rte_unused struct rte_eth_dev *dev,\n \t\tobytes += stats->q_obytes[i];\n \t\timissed += stats->q_errors[i];\n \t}\n+#else\n+\t/* Get statistics from mapped device's queue */\n+\tmapped_num = fm10k_switch_dpdk_mapped_hw_get(unmap_hw, mapped_hws);\n+\tif (mapped_num < 0 || mapped_num > FM10K_SW_PEP_MAP_NUM_MAX) {\n+\t\tPMD_INIT_LOG(ERR, \"Can not get the mapped HW for %s\",\n+\t\t\t\tdev->device->name);\n+\t\treturn -EIO;\n+\t}\n+\n+\tfor (i = 0; i < mapped_num; i++) {\n+\t\tstruct rte_eth_dev *mydev =\n+\t\t\tfm10k_switch_dpdk_port_rte_dev_get(mapped_hws[i]);\n+\t\thw_stats = FM10K_DEV_PRIVATE_TO_STATS(mydev->data->dev_private);\n+\t\tfm10k_update_hw_stats(mapped_hws[i], hw_stats);\n+\t}\n+\n+\tif (mapped_num)\t{\n+\t\tfor (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&\n+\t\t\t(i < unmap_hw->mac.max_queues); ++i) {\n+\t\t\tfm10k_switch_dpdk_hw_queue_map(unmap_hw,\n+\t\t\t\t\ti, unmap_hw->mac.max_queues,\n+\t\t\t\t\t&hw, &hw_queue_id);\n+\t\t\tif (mapped_hws[1]) {\n+\t\t\t\tstruct rte_eth_dev *mydev;\n+\t\t\t\tmydev = fm10k_switch_dpdk_port_rte_dev_get(hw);\n+\t\t\t\thw_stats = FM10K_DEV_PRIVATE_TO_STATS\n+\t\t\t\t\t\t(mydev->data->dev_private);\n+\t\t\t}\n+\t\t\tstats->q_ipackets[i] =\n+\t\t\t\thw_stats->q[hw_queue_id].rx_packets.count;\n+\t\t\tstats->q_opackets[i] =\n+\t\t\t\thw_stats->q[hw_queue_id].tx_packets.count;\n+\t\t\tstats->q_ibytes[i] =\n+\t\t\t\thw_stats->q[hw_queue_id].rx_bytes.count;\n+\t\t\tstats->q_obytes[i] =\n+\t\t\t\thw_stats->q[hw_queue_id].tx_bytes.count;\n+\t\t\tipackets += stats->q_ipackets[i];\n+\t\t\topackets += stats->q_opackets[i];\n+\t\t\tibytes += stats->q_ibytes[i];\n+\t\t\tobytes += stats->q_obytes[i];\n+\t\t}\n+\t}\n+#endif\n \tstats->ipackets = ipackets;\n \tstats->opackets = opackets;\n \tstats->ibytes = ibytes;\n@@ -1808,8 +2041,7 @@ static uint64_t fm10k_get_rx_port_offloads_capa(struct rte_eth_dev *dev)\n \t\t\t DEV_RX_OFFLOAD_UDP_CKSUM |\n \t\t\t DEV_RX_OFFLOAD_TCP_CKSUM |\n \t\t\t DEV_RX_OFFLOAD_JUMBO_FRAME |\n-\t\t\t DEV_RX_OFFLOAD_HEADER_SPLIT |\n-\t\t\t DEV_RX_OFFLOAD_RSS_HASH);\n+\t\t\t DEV_RX_OFFLOAD_HEADER_SPLIT);\n }\n \n static int\n@@ -1818,14 +2050,28 @@ static uint64_t fm10k_get_rx_port_offloads_capa(struct rte_eth_dev *dev)\n \tconst struct rte_eth_rxconf *conf, struct rte_mempool *mp)\n {\n \tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+#ifdef RTE_FM10K_MANAGEMENT\n+\tstruct fm10k_hw *unmap_hw = hw;\n+#endif\n \tstruct fm10k_dev_info *dev_info =\n \t\tFM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);\n \tstruct fm10k_rx_queue *q;\n \tconst struct rte_memzone *mz;\n \tuint64_t offloads;\n+\tuint16_t hw_queue_id = queue_id;\n \n \tPMD_INIT_FUNC_TRACE();\n \n+#ifdef RTE_FM10K_MANAGEMENT\n+\tif (fm10k_switch_dpdk_hw_queue_map(unmap_hw,\n+\t\t\tqueue_id, dev->data->nb_rx_queues,\n+\t\t\t&hw, &hw_queue_id) < 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Can not get the mapped HW and queue for:\"\n+\t\t\t\t\" %s %d\", dev->device->name, queue_id);\n+\t\treturn -EIO;\n+\t}\n+#endif\n+\n \toffloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;\n \n \t/* make sure the mempool element size can account for alignment. */\n@@ -1871,7 +2117,7 @@ static uint64_t fm10k_get_rx_port_offloads_capa(struct rte_eth_dev *dev)\n \tq->port_id = dev->data->port_id;\n \tq->queue_id = queue_id;\n \tq->tail_ptr = (volatile uint32_t *)\n-\t\t&((uint32_t *)hw->hw_addr)[FM10K_RDT(queue_id)];\n+\t\t&((uint32_t *)hw->hw_addr)[FM10K_RDT(hw_queue_id)];\n \tq->offloads = offloads;\n \tif (handle_rxconf(q, conf))\n \t\treturn -EINVAL;\n@@ -2007,12 +2253,26 @@ static uint64_t fm10k_get_tx_port_offloads_capa(struct rte_eth_dev *dev)\n \tconst struct rte_eth_txconf *conf)\n {\n \tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+#ifdef RTE_FM10K_MANAGEMENT\n+\tstruct fm10k_hw *unmap_hw = hw;\n+#endif\n \tstruct fm10k_tx_queue *q;\n \tconst struct rte_memzone *mz;\n \tuint64_t offloads;\n+\tuint16_t hw_queue_id = queue_id;\n \n \tPMD_INIT_FUNC_TRACE();\n \n+#ifdef RTE_FM10K_MANAGEMENT\n+\tif (fm10k_switch_dpdk_hw_queue_map(unmap_hw,\n+\t\t\tqueue_id, dev->data->nb_tx_queues,\n+\t\t\t&hw, &hw_queue_id) < 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Can not get the mapped HW and queue for:\"\n+\t\t\t\t\" %s %d\", dev->device->name, queue_id);\n+\t\treturn -EIO;\n+\t}\n+#endif\n+\n \toffloads = conf->offloads | dev->data->dev_conf.txmode.offloads;\n \n \t/* make sure a valid number of descriptors have been requested */\n@@ -2054,7 +2314,7 @@ static uint64_t fm10k_get_tx_port_offloads_capa(struct rte_eth_dev *dev)\n \tq->offloads = offloads;\n \tq->ops = &def_txq_ops;\n \tq->tail_ptr = (volatile uint32_t *)\n-\t\t&((uint32_t *)hw->hw_addr)[FM10K_TDT(queue_id)];\n+\t\t&((uint32_t *)hw->hw_addr)[FM10K_TDT(hw_queue_id)];\n \tif (handle_txconf(q, conf))\n \t\treturn -EINVAL;\n \n@@ -2284,6 +2544,77 @@ static uint64_t fm10k_get_tx_port_offloads_capa(struct rte_eth_dev *dev)\n \treturn 0;\n }\n \n+#ifdef RTE_FM10K_MANAGEMENT\n+static int\n+fm10k_mirror_rule_set(struct rte_eth_dev *dev,\n+\t\t\tstruct rte_eth_mirror_conf *mirror_conf,\n+\t\t\tuint8_t sw_id, uint8_t on)\n+{\n+\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tPMD_INIT_LOG(DEBUG,\n+\t\t\t\"Mirror set, switch %d to port %d attach vlan %d on %d\",\n+\t\t\tsw_id, mirror_conf->dst_pool,\n+\t\t\tmirror_conf->vlan.vlan_id[0], on);\n+\n+\tif (on)\t{\n+\t\tif (fm10k_switch_mirror_set(hw,\n+\t\t\t\tmirror_conf->dst_pool,\n+\t\t\t\tmirror_conf->vlan.vlan_id[0]) < 0) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Input wrong port!!!\");\n+\t\t\treturn -1;\n+\t\t}\n+\t} else {\n+\t\tif (fm10k_switch_mirror_reset(hw) < 0) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Input wrong port!!!\");\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+\n+static int\n+fm10k_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)\n+{\n+\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tPMD_INIT_LOG(DEBUG, \"Mirror reset, switch %d\", sw_id);\n+\n+\tfm10k_switch_mirror_reset(hw);\n+\n+\treturn 0;\n+}\n+\n+static int\n+fm10k_dev_filter_ctrl(struct rte_eth_dev *dev,\n+\t\t enum rte_filter_type filter_type,\n+\t\t enum rte_filter_op filter_op,\n+\t\t void *arg)\n+{\n+\tint ret = 0;\n+\n+\tif (dev == NULL)\n+\t\treturn -EINVAL;\n+\n+\tswitch (filter_type) {\n+\tcase RTE_ETH_FILTER_GENERIC:\n+\t\tif (filter_op != RTE_ETH_FILTER_GET)\n+\t\t\treturn -EINVAL;\n+\t\t*(const void **)arg = fm10k_flow_ops_get();\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(WARNING, \"Filter type (%d) not supported\",\n+\t\t\t\t\t\t\tfilter_type);\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+#endif\n+\n static void\n fm10k_dev_enable_intr_pf(struct rte_eth_dev *dev)\n {\n@@ -2592,6 +2923,9 @@ static uint64_t fm10k_get_tx_port_offloads_capa(struct rte_eth_dev *dev)\n \t\tFM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);\n \tint status_mbx;\n \ts32 err;\n+#ifdef RTE_FM10K_MANAGEMENT\n+\tuint32_t writeback = 0;\n+#endif\n \n \tif (hw->mac.type != fm10k_mac_pf)\n \t\treturn;\n@@ -2605,11 +2939,20 @@ static uint64_t fm10k_get_tx_port_offloads_capa(struct rte_eth_dev *dev)\n \t}\n \n \t/* Handle switch up/down */\n-\tif (cause & FM10K_EICR_SWITCHNOTREADY)\n-\t\tPMD_INIT_LOG(ERR, \"INT: Switch is not ready\");\n+\tif (cause & FM10K_EICR_SWITCHNOTREADY) {\n+\t\tPMD_INIT_LOG(INFO, \"INT: Switch is not ready\");\n+#ifdef RTE_FM10K_MANAGEMENT\n+\t\thw->switch_ready = false;\n+\t\twriteback |= FM10K_EICR_SWITCHNOTREADY;\n+#endif\n+\t}\n \n \tif (cause & FM10K_EICR_SWITCHREADY) {\n \t\tPMD_INIT_LOG(INFO, \"INT: Switch is ready\");\n+#ifdef RTE_FM10K_MANAGEMENT\n+\t\thw->switch_ready = true;\n+\t\twriteback |= FM10K_EICR_SWITCHREADY;\n+#endif\n \t\tif (dev_info->sm_down == 1) {\n \t\t\tfm10k_mbx_lock(hw);\n \n@@ -2660,6 +3003,7 @@ static uint64_t fm10k_get_tx_port_offloads_capa(struct rte_eth_dev *dev)\n \t}\n \n \t/* Handle mailbox message */\n+#ifndef RTE_FM10K_MANAGEMENT\n \tfm10k_mbx_lock(hw);\n \terr = hw->mbx.ops.process(hw, &hw->mbx);\n \tfm10k_mbx_unlock(hw);\n@@ -2667,10 +3011,33 @@ static uint64_t fm10k_get_tx_port_offloads_capa(struct rte_eth_dev *dev)\n \tif (err == FM10K_ERR_RESET_REQUESTED) {\n \t\tPMD_INIT_LOG(INFO, \"INT: Switch is down\");\n \t\tdev_info->sm_down = 1;\n-\t\t_rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,\n+\t\t_rte_eth_dev_callback_process\n+\t\t\t\t(dev,\n+\t\t\t\tRTE_ETH_EVENT_INTR_LSC,\n \t\t\t\tNULL);\n \t}\n \n+#else\n+\tif (cause & FM10K_EICR_MAILBOX)\t{\n+\t\tfm10k_mbx_lock(hw);\n+\t\terr = hw->mbx.ops.process(hw, &hw->mbx);\n+\t\tfm10k_mbx_unlock(hw);\n+\t\twriteback |= FM10K_EICR_MAILBOX;\n+\t\tif (err == FM10K_ERR_RESET_REQUESTED) {\n+\t\t\tPMD_INIT_LOG(INFO, \"INT: Switch is down\");\n+\t\t\tdev_info->sm_down = 1;\n+\t\t\t_rte_eth_dev_callback_process\n+\t\t\t\t\t(dev,\n+\t\t\t\t\tRTE_ETH_EVENT_INTR_LSC,\n+\t\t\t\t\tNULL);\n+\t\t}\n+\t}\n+\n+\t/* Handle switch interrupt */\n+\tif (cause & FM10K_SW_EICR_SWITCH_INT)\n+\t\tfm10k_switch_intr(hw);\n+#endif\n+\n \t/* Handle SRAM error */\n \tif (cause & FM10K_EICR_SRAMERROR) {\n \t\tPMD_INIT_LOG(ERR, \"INT: SRAM error on PEP\");\n@@ -2682,15 +3049,27 @@ static uint64_t fm10k_get_tx_port_offloads_capa(struct rte_eth_dev *dev)\n \t\t/* Todo: print out error message after shared code updates */\n \t}\n \n+#ifndef RTE_FM10K_MANAGEMENT\n \t/* Clear these 3 events if having any */\n \tcause &= FM10K_EICR_SWITCHNOTREADY | FM10K_EICR_MAILBOX |\n \t\t FM10K_EICR_SWITCHREADY;\n \tif (cause)\n \t\tFM10K_WRITE_REG(hw, FM10K_EICR, cause);\n+#else\n+\tif (writeback)\n+\t\tFM10K_WRITE_REG(hw, FM10K_EICR, writeback);\n+#endif\n \n \t/* Re-enable interrupt from device side */\n-\tFM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |\n+#ifndef RTE_FM10K_MANAGEMENT\n+\tFM10K_WRITE_REG(hw, FM10K_ITR(0),\n+\t\t\t\t\tFM10K_ITR_AUTOMASK |\n \t\t\t\t\tFM10K_ITR_MASK_CLEAR);\n+#else\n+\tFM10K_WRITE_REG(hw, FM10K_ITR(0),\n+\t\tFM10K_SW_ITR_AUTO_MASK |\n+\t FM10K_SW_MAKE_REG_FIELD(ITR_MASK, FM10K_SW_ITR_MASK_W_ENABLE));\n+#endif\n \t/* Re-enable interrupt from host side */\n \trte_intr_ack(dev->intr_handle);\n }\n@@ -2897,6 +3276,11 @@ static uint64_t fm10k_get_tx_port_offloads_capa(struct rte_eth_dev *dev)\n \t.reta_query\t\t= fm10k_reta_query,\n \t.rss_hash_update\t= fm10k_rss_hash_update,\n \t.rss_hash_conf_get\t= fm10k_rss_hash_conf_get,\n+#ifdef RTE_FM10K_MANAGEMENT\n+\t.mirror_rule_set\t= fm10k_mirror_rule_set,\n+\t.mirror_rule_reset\t= fm10k_mirror_rule_reset,\n+\t.filter_ctrl\t\t= fm10k_dev_filter_ctrl,\n+#endif\n };\n \n static int ftag_check_handler(__rte_unused const char *key,\n@@ -3075,13 +3459,67 @@ static void __attribute__((cold))\n \tinfo->sm_down = false;\n }\n \n+#ifdef RTE_FM10K_MANAGEMENT\n+static int eth_fm10k_dev_init_hook(struct fm10k_hw *hw)\n+{\n+\tint i;\n+\tstruct rte_eth_dev *dev =\n+\t\t(struct rte_eth_dev *)fm10k_switch_dpdk_port_rte_dev_get(hw);\n+\n+\t/*\n+\t * Below function will trigger operations on mailbox, acquire lock to\n+\t * avoid race condition from interrupt handler. Operations on mailbox\n+\t * FIFO will trigger interrupt to PF/SM, in which interrupt handler\n+\t * will handle and generate an interrupt to our side. Then, FIFO in\n+\t * mailbox will be touched.\n+\t */\n+\tif (hw->mac.dglort_map == FM10K_DGLORTMAP_NONE)\t{\n+\t\tPMD_INIT_LOG(ERR, \"dglort_map is not ready\");\n+\t\treturn -1;\n+\t}\n+\n+\tfm10k_mbx_lock(hw);\n+\t/* Enable port first */\n+\thw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,\n+\t\t\t\t\tMAX_LPORT_NUM, 1);\n+\t/* Set unicast mode by default. App can change to other mode in other\n+\t * API func.\n+\t */\n+\thw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,\n+\t\t\t\t\tFM10K_XCAST_MODE_NONE);\n+\tfm10k_mbx_unlock(hw);\n+\n+\t/* Make sure default VID is ready before going forward. */\n+\tif (hw->mac.type == fm10k_mac_pf) {\n+\t\tfor (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {\n+\t\t\tif (hw->mac.default_vid)\n+\t\t\t\tbreak;\n+\t\t\t/* Delay some time to acquire async port VLAN info. */\n+\t\t\trte_delay_us(WAIT_SWITCH_MSG_US);\n+\t\t}\n+\n+\t\tif (hw->mac.default_vid == 0)\n+\t\t\thw->mac.default_vid = 1;\n+\t}\n+\n+\t/* Add default mac address */\n+\tfm10k_MAC_filter_set(dev, hw->mac.addr, true,\n+\t\tMAIN_VSI_POOL_NUMBER);\n+\n+\treturn 0;\n+}\n+#endif\n+\n static int\n eth_fm10k_dev_init(struct rte_eth_dev *dev)\n {\n \tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tstruct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);\n \tstruct rte_intr_handle *intr_handle = &pdev->intr_handle;\n-\tint diag, i;\n+\tint diag;\n+#ifndef RTE_FM10K_MANAGEMENT\n+\tint i;\n+#endif\n \tstruct fm10k_macvlan_filter_info *macvlan;\n \n \tPMD_INIT_FUNC_TRACE();\n@@ -3118,7 +3556,9 @@ static void __attribute__((cold))\n \t\t\t\" Try to blacklist unused devices.\");\n \t\treturn -EIO;\n \t}\n-\n+#ifdef RTE_FM10K_MANAGEMENT\n+\thw->sw_addr = (void *)pdev->mem_resource[4].addr;\n+#endif\n \t/* Store fm10k_adapter pointer */\n \thw->back = dev->data->dev_private;\n \n@@ -3129,6 +3569,25 @@ static void __attribute__((cold))\n \t\treturn -EIO;\n \t}\n \n+#ifdef RTE_FM10K_MANAGEMENT\n+\tif (hw->mac.type == fm10k_mac_pf) {\n+\t\tif (hw->hw_addr == NULL || hw->sw_addr == NULL) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Bad mem resource.\"\n+\t\t\t\t\t\" Try to blacklist unused devices.\");\n+\t\t\treturn -EIO;\n+\t\t}\n+\t} else {\n+\t\tif (hw->hw_addr == NULL) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Bad mem resource.\"\n+\t\t\t\t\t\" Try to blacklist unused devices.\");\n+\t\t\treturn -EIO;\n+\t\t}\n+\t}\n+\n+\t/* Store fm10k_adapter pointer */\n+\thw->back = dev->data->dev_private;\n+#endif\n+\n \t/* Initialize parameters */\n \tfm10k_params_init(dev);\n \n@@ -3209,6 +3668,7 @@ static void __attribute__((cold))\n \thw->mac.ops.update_int_moderator(hw);\n \n \t/* Make sure Switch Manager is ready before going forward. */\n+#ifndef RTE_FM10K_MANAGEMENT\n \tif (hw->mac.type == fm10k_mac_pf) {\n \t\tbool switch_ready = false;\n \n@@ -3216,13 +3676,13 @@ static void __attribute__((cold))\n \t\t\tfm10k_mbx_lock(hw);\n \t\t\thw->mac.ops.get_host_state(hw, &switch_ready);\n \t\t\tfm10k_mbx_unlock(hw);\n-\t\t\tif (switch_ready == true)\n+\t\t\tif (switch_ready)\n \t\t\t\tbreak;\n \t\t\t/* Delay some time to acquire async LPORT_MAP info. */\n \t\t\trte_delay_us(WAIT_SWITCH_MSG_US);\n \t\t}\n \n-\t\tif (switch_ready == false) {\n+\t\tif (switch_ready == 0) {\n \t\t\tPMD_INIT_LOG(ERR, \"switch is not ready\");\n \t\t\treturn -1;\n \t\t}\n@@ -3268,11 +3728,25 @@ static void __attribute__((cold))\n \t\tMAIN_VSI_POOL_NUMBER);\n \n \treturn 0;\n+#else\n+\tif (hw->mac.type == fm10k_mac_pf) {\n+\t\tbool master = FM10K_READ_REG(hw,\n+\t\t\t\tFM10K_CTRL) & FM10K_CTRL_BAR4_ALLOWED;\n+\t\treturn fm10k_switch_dpdk_port_start(hw,\n+\t\t\t\tdev, 1, master, eth_fm10k_dev_init_hook);\n+\t} else {\n+\t\treturn fm10k_switch_dpdk_port_start(hw,\n+\t\t\t\tdev, 0, false, eth_fm10k_dev_init_hook);\n+\t}\n+#endif\n }\n \n static int\n eth_fm10k_dev_uninit(struct rte_eth_dev *dev)\n {\n+#ifdef RTE_FM10K_MANAGEMENT\n+\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+#endif\n \tPMD_INIT_FUNC_TRACE();\n \n \t/* only uninitialize in the primary process */\n@@ -3282,6 +3756,10 @@ static void __attribute__((cold))\n \t/* safe to close dev here */\n \tfm10k_dev_close(dev);\n \n+#ifdef RTE_FM10K_MANAGEMENT\n+\tfm10k_switch_dpdk_port_stop(hw);\n+#endif\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/net/fm10k/switch/fm10k_switch.c b/drivers/net/fm10k/switch/fm10k_switch.c\nindex 009d62a..abe719d 100644\n--- a/drivers/net/fm10k/switch/fm10k_switch.c\n+++ b/drivers/net/fm10k/switch/fm10k_switch.c\n@@ -31,6 +31,10 @@\n #define FM10K_LED_POLL_INTERVAL_MS\t\t500\n #define FM10K_LED_BLINKS_PER_SECOND\t\t2\n \n+/* Max try times to acquire switch status */\n+#define FM10K_QUERY_SWITCH_STATE_TIMES\t\t10\n+/* Wait interval to get switch status */\n+#define FM10K_WAIT_SWITCH_MSG_US\t\t100000\n \n /*\n * use epl as external port map, only support QUAD_ON\n@@ -1914,6 +1918,19 @@ struct fm10k_switch*\n \t\t}\n \t}\n \n+\t/* Make sure Switch Manager is ready before going forward. */\n+\tfor (i = 0; i < FM10K_QUERY_SWITCH_STATE_TIMES; i++) {\n+\t\tif (master_hw->switch_ready)\n+\t\t\tbreak;\n+\t\t/* Delay some time to acquire async LPORT_MAP info. */\n+\t\trte_delay_us(FM10K_WAIT_SWITCH_MSG_US);\n+\t}\n+\n+\tif (!master_hw->switch_ready) {\n+\t\tPMD_INIT_LOG(ERR, \"switch is not ready\");\n+\t\treturn -1;\n+\t}\n+\n \t/* do initialize all ports, after switch is ready */\n \tfor (i = 0; i < FM10K_SW_LOGICAL_PORTS_MAX; i++) {\n \t\tuint32_t sglort;\n@@ -1941,8 +1958,9 @@ struct fm10k_switch*\n \t\t\t\treturn -1;\n \t\t\t}\n \t\t\thw->mac.dglort_map = sglort | 0xffff0000;\n+\t\t\thw->switch_ready = master_hw->switch_ready;\n+\t\t\tfunc(hw);\n \t\t}\n-\t\tfunc(hw);\n \t}\n \treturn 0;\n }\ndiff --git a/drivers/net/fm10k/switch/fm10k_switch.h b/drivers/net/fm10k/switch/fm10k_switch.h\nindex b4b363c..a2aa0d0 100644\n--- a/drivers/net/fm10k/switch/fm10k_switch.h\n+++ b/drivers/net/fm10k/switch/fm10k_switch.h\n@@ -34,6 +34,7 @@\n #define FM10K_SW_PEPS_MAX\t\t9\n #define FM10K_SW_PEPS_SUPPORTED\t\t4\n #define FM10K_SW_PEP_PORTS_MAX\t\t4\n+#define FM10K_SW_PEP_MAP_NUM_MAX\t2\n \n /*\n * GLORT\n", "prefixes": [ "v1", "5/5" ] }