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GET /api/patches/66133/?format=api

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{
    "id": 66133,
    "url": "http://patches.dpdk.org/api/patches/66133/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1582879102-17977-3-git-send-email-xiaojun.liu@silicom.co.il/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1582879102-17977-3-git-send-email-xiaojun.liu@silicom.co.il>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1582879102-17977-3-git-send-email-xiaojun.liu@silicom.co.il",
    "date": "2020-02-28T08:38:19",
    "name": "[v1,2/5] net/fm10k: add epl serdes and port control functions",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "af96cdd531cb2fd1e9c9413db9b7e96c6ede8f85",
    "submitter": {
        "id": 1512,
        "url": "http://patches.dpdk.org/api/people/1512/?format=api",
        "name": "Xiaojun Liu",
        "email": "xiaojun.liu@silicom.co.il"
    },
    "delegate": {
        "id": 31221,
        "url": "http://patches.dpdk.org/api/users/31221/?format=api",
        "username": "yexl",
        "first_name": "xiaolong",
        "last_name": "ye",
        "email": "xiaolong.ye@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1582879102-17977-3-git-send-email-xiaojun.liu@silicom.co.il/mbox/",
    "series": [
        {
            "id": 8723,
            "url": "http://patches.dpdk.org/api/series/8723/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8723",
            "date": "2020-02-28T08:38:17",
            "name": "support fm10k switch management",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/8723/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/66133/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/66133/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Xiaojun Liu <xiaojun.liu@silicom.co.il>",
        "To": "xiao.w.wang@intel.com, qi.z.zhang@intel.com, ngai-mint.kwan@intel.com,\n jacob.e.keller@intel.com",
        "Cc": "dev@dpdk.org,\n\tXiaojun Liu <xiaojun.liu@silicom.co.il>",
        "Date": "Fri, 28 Feb 2020 16:38:19 +0800",
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        "References": "<1582207174-31037-2-git-send-email-xiaojun.liu@silicom.co.il>\n <1582879102-17977-1-git-send-email-xiaojun.liu@silicom.co.il>",
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        "Subject": "[dpdk-dev] [PATCH v1 2/5] net/fm10k: add epl serdes and port\n\tcontrol functions",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
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        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Add epl serdes include loading spico,\ncontrolling pcsl, dma, dfe, ical. Add spico code.\nAdd state machine for epl lane and port, it creates\na pthread to handle the state changing event.\nAdd external port management, which will use\nstate machine to handle the event from lane and port.\nThe lane state will change between DOWN, WAIT_PLL_LOCK,\nWAIT_SIGNAL_OK, WAIT_DFE_ICAL, WAIT_DFE_PCAL, UP.\nThe port state will change between DOWN, WAIT_LANE_UP, UP.\n\nTo enable the switch management, you need add\nCONFIG_RTE_FM10K_MANAGEMENT=y in\nconfig/common_linux when building.\n\nSigned-off-by: Xiaojun Liu <xiaojun.liu@silicom.co.il>\n---\n drivers/net/fm10k/Makefile                  |    4 +\n drivers/net/fm10k/switch/fm10k_ext_port.c   |  840 ++++++++\n drivers/net/fm10k/switch/fm10k_ext_port.h   |  136 ++\n drivers/net/fm10k/switch/fm10k_serdes.c     | 1936 +++++++++++++++++\n drivers/net/fm10k/switch/fm10k_serdes.h     |   32 +\n drivers/net/fm10k/switch/fm10k_sm.c         |  190 ++\n drivers/net/fm10k/switch/fm10k_sm.h         |   81 +\n drivers/net/fm10k/switch/fm10k_spico_code.c | 2966 +++++++++++++++++++++++++++\n drivers/net/fm10k/switch/fm10k_spico_code.h |   21 +\n 9 files changed, 6206 insertions(+)\n create mode 100644 drivers/net/fm10k/switch/fm10k_ext_port.c\n create mode 100644 drivers/net/fm10k/switch/fm10k_ext_port.h\n create mode 100644 drivers/net/fm10k/switch/fm10k_serdes.c\n create mode 100644 drivers/net/fm10k/switch/fm10k_serdes.h\n create mode 100644 drivers/net/fm10k/switch/fm10k_sm.c\n create mode 100644 drivers/net/fm10k/switch/fm10k_sm.h\n create mode 100644 drivers/net/fm10k/switch/fm10k_spico_code.c\n create mode 100644 drivers/net/fm10k/switch/fm10k_spico_code.h",
    "diff": "diff --git a/drivers/net/fm10k/Makefile b/drivers/net/fm10k/Makefile\nindex 15ea187..0d3b688 100644\n--- a/drivers/net/fm10k/Makefile\n+++ b/drivers/net/fm10k/Makefile\n@@ -84,6 +84,10 @@ SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_api.c\n ifeq ($(CONFIG_RTE_FM10K_MANAGEMENT),y)\n SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_i2c.c\n SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_sbus.c\n+SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_ext_port.c\n+SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_serdes.c\n+SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_sm.c\n+SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_spico_code.c\n endif\n ifeq ($(CONFIG_RTE_ARCH_X86), y)\n SRCS-$(CONFIG_RTE_LIBRTE_FM10K_INC_VECTOR) += fm10k_rxtx_vec.c\ndiff --git a/drivers/net/fm10k/switch/fm10k_ext_port.c b/drivers/net/fm10k/switch/fm10k_ext_port.c\nnew file mode 100644\nindex 0000000..7f8efd0\n--- /dev/null\n+++ b/drivers/net/fm10k/switch/fm10k_ext_port.c\n@@ -0,0 +1,840 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019   Silicom Ltd. Connectivity Solutions\n+ */\n+\n+#include <rte_malloc.h>\n+\n+#include <rte_time.h>\n+#include <rte_kvargs.h>\n+#include <rte_hash.h>\n+#include <rte_flow.h>\n+#include <rte_flow_driver.h>\n+#include <rte_tm_driver.h>\n+\n+#include \"fm10k_debug.h\"\n+#include \"fm10k_ext_port.h\"\n+#include \"fm10k_i2c.h\"\n+#include \"fm10k_regs.h\"\n+#include \"fm10k_serdes.h\"\n+#include \"fm10k_sm.h\"\n+#include \"fm10k_switch.h\"\n+\n+\n+#define LANE_EVENT(e_)\t\t\tFM10K_SW_EXT_PORT_LANE_EVENT_##e_\n+#define LANE_TIMER(t_)\t\t\tFM10K_SW_EXT_PORT_LANE_TIMER_##t_\n+#define LANE_TIMEOUT(t_)\t\tFM10K_SW_EXT_PORT_LANE_##t_##_TIMEOUT_MS\n+#define LANE_POLL(t_)\t\t\tFM10K_SW_EXT_PORT_LANE_##t_##_POLL_MS\n+#define LANE_STATE(s_)\t\t\tFM10K_SW_EXT_PORT_LANE_STATE_##s_\n+#define LANE_FLAG(f_)\t\t\tFM10K_SW_EXT_PORT_LANE_FLAG_##f_\n+#define LANE_FLAGS(f_)\t\t\tFM10K_SW_EXT_PORT_LANE_FLAGS_##f_\n+#define LANE_FLAG_SET(l_, f_)\t\t((l_)->flags & LANE_FLAG(f_))\n+#define LANE_FLAGS_SET(l_, f_, f1_)\t\\\n+\t(((l_)->flags & LANE_FLAGS(f_)) == LANE_FLAGS(f1_))\n+\n+#define PORT_EVENT(e_)\t\t\tFM10K_SW_EXT_PORT_EVENT_##e_\n+#define PORT_STATE(s_)\t\t\tFM10K_SW_EXT_PORT_STATE_##s_\n+\n+static void fm10k_ext_ports_epl_intr\n+\t\t(struct fm10k_ext_ports *ports, unsigned int eplno);\n+static void fm10k_ext_port_intr(struct fm10k_ext_port *port, uint32_t epl_ip);\n+static void fm10k_ext_port_process_event(struct fm10k_sm *sm, uint16_t event);\n+static void fm10k_ext_port_bring_down(struct fm10k_ext_port *port);\n+static void fm10k_ext_port_lane_process_event\n+\t\t(struct fm10k_sm *sm, uint16_t event);\n+static void fm10k_ext_port_lane_process_timer\n+\t\t(struct fm10k_sm *sm, uint16_t timer);\n+static void fm10k_ext_port_restart_lane(struct fm10k_ext_port_lane *lane);\n+static void fm10k_ext_port_disable_lane(struct fm10k_ext_port_lane *lane);\n+static void fm10k_ext_port_phy_enable(struct fm10k_ext_port *port);\n+static void fm10k_ext_port_phy_disable(struct fm10k_ext_port *port);\n+\n+struct fm10k_ext_ports *\n+fm10k_ext_ports_attach(struct fm10k_switch *sw)\n+{\n+\tstruct fm10k_ext_ports *ports;\n+\tstruct fm10k_ext_port *port;\n+\tstruct fm10k_ext_port_lane *lane;\n+\tstruct fm10k_device_info *cfg = sw->info;\n+\tunsigned int is_quad, lane_speed;\n+\tunsigned int i, j;\n+\tunsigned int eplidx, laneno;\n+\n+\tFM10K_SW_TRACE(\"attaching external ports\\n\");\n+\n+\tports = (struct fm10k_ext_ports *)rte_zmalloc\n+\t\t\t(\"fm10k_ext_ports\", sizeof(struct fm10k_ext_ports), 0);\n+\tif (ports == NULL) {\n+\t\tFM10K_SW_ERR(\"failed to allocate external ports\\n\");\n+\t\tgoto fail;\n+\t}\n+\n+\tports->ports = (struct fm10k_ext_port *)rte_zmalloc\n+\t\t\t(\"fm10k_ext_port_list\",\n+\t\t\tsizeof(struct fm10k_ext_port) * cfg->num_ext_ports, 0);\n+\tif (ports->ports == NULL) {\n+\t\tFM10K_SW_ERR(\"failed to allocate external ports list\\n\");\n+\t\tgoto fail;\n+\t}\n+\tports->sw = sw;\n+\tports->num_ports = cfg->num_ext_ports;\n+\tports->ports_per_epl = cfg->num_ext_ports / cfg->num_epls;\n+\tports->epl_mask = 0;\n+\n+\tswitch (cfg->ext_port_speed) {\n+\tdefault:\n+\tcase 10:\n+\t\tis_quad = 0;\n+\t\tlane_speed = 10;\n+\t\tbreak;\n+\tcase 25:\n+\t\tis_quad = 0;\n+\t\tlane_speed = 25;\n+\t\tbreak;\n+\tcase 40:\n+\t\tis_quad = 1;\n+\t\tlane_speed = 10;\n+\t\tbreak;\n+\tcase 100:\n+\t\tis_quad = 1;\n+\t\tlane_speed = 25;\n+\t\tbreak;\n+\t}\n+\n+\tfor (i = 0; i < ports->num_ports; i++) {\n+\t\tport = &ports->ports[i];\n+\t\tport->ports = ports;\n+\t\tfm10k_ext_port_eplidx_lane(ports, i, &eplidx, &laneno);\n+\t\tport->portno = i;\n+\t\tport->eplno = eplidx ? sw->eplb_no : sw->epla_no;\n+\t\tsnprintf(port->name, sizeof(port->name), \"EPL[%u][%u]\",\n+\t\t    port->eplno, port->first_lane);\n+\t\tport->first_lane = laneno;\n+\t\tport->is_quad = is_quad;\n+\t\tport->num_lanes = port->is_quad ? 4 : 1;\n+\t\tport->lane_speed = lane_speed;\n+\t\tport->sm = fm10k_sm_attach\n+\t\t\t(FM10K_SW_EXT_PORT_NUM_EVENTS, 0,\n+\t\t    fm10k_ext_port_process_event, NULL,\n+\t\t    (void *)port);\n+\t\tif (port->sm == NULL)\n+\t\t\tgoto fail;\n+\t\tport->sm->portno = port->portno;\n+\t\tport->sm->laneno = 0;\n+\t\tport->an_im = FM10K_SW_AN_IM_ALL;\n+\t\tport->link_im = FM10K_SW_LINK_IM_ALL;\n+\n+\t\tfor (j = port->first_lane;\n+\t\t     j < port->first_lane + port->num_lanes; j++) {\n+\t\t\tlane = &port->lanes[j];\n+\t\t\tlane->port = port;\n+\t\t\tlane->abs_laneno = port->eplno * FM10K_SW_EPL_LANES + j;\n+\t\t\tlane->rel_laneno = j;\n+\t\t\tlane->im = FM10K_SW_SERDES_IM_ALL;\n+\t\t\tlane->sm = fm10k_sm_attach\n+\t\t\t\t(FM10K_SW_EXT_PORT_LANE_NUM_EVENTS,\n+\t\t\t    FM10K_SW_EXT_PORT_LANE_NUM_TIMERS,\n+\t\t\t    fm10k_ext_port_lane_process_event,\n+\t\t\t    fm10k_ext_port_lane_process_timer,\n+\t\t\t    (void *)lane);\n+\t\t\tif (lane->sm == NULL)\n+\t\t\t\tgoto fail;\n+\t\t\tlane->sm->portno = lane->port->portno;\n+\t\t\tlane->sm->laneno = lane->rel_laneno;\n+\t\t}\n+\n+\t\tports->epl_mask |= (1 << port->eplno);\n+\t}\n+\n+\treturn (ports);\n+fail:\n+\tif (ports)\n+\t\tfm10k_ext_ports_detach(ports);\n+\treturn NULL;\n+}\n+\n+void\n+fm10k_ext_ports_detach(struct fm10k_ext_ports *ports)\n+{\n+\tstruct fm10k_ext_port *port;\n+\tstruct fm10k_ext_port_lane *lane;\n+\tunsigned int i, j;\n+\n+\tFM10K_SW_TRACE(\"detaching external ports\\n\");\n+\n+\tif (ports->ports) {\n+\t\tfor (i = 0; i < ports->num_ports; i++) {\n+\t\t\tport = &ports->ports[i];\n+\n+\t\t\tif (port->sm)\n+\t\t\t\tfm10k_sm_detach(port->sm);\n+\t\t\tfor (j = port->first_lane;\n+\t\t\t     j < port->first_lane + port->num_lanes; j++) {\n+\t\t\t\tlane = &port->lanes[j];\n+\t\t\t\tif (lane->sm)\n+\t\t\t\t\tfm10k_sm_detach(lane->sm);\n+\t\t\t}\n+\n+\t\t\tfm10k_ext_port_phy_disable(port);\n+\t\t}\n+\t\trte_free(ports->ports);\n+\t}\n+\n+\trte_free(ports);\n+}\n+\n+unsigned int\n+fm10k_ext_ports_epl_intrs(struct fm10k_ext_ports *ports, uint64_t gid)\n+{\n+\tunsigned int i;\n+\tuint16_t epl_mask;\n+\n+\t/*\n+\t * Process EPL interrupts for all EPLs that are in use and have\n+\t * their bit set in global interrupt detect.\n+\t */\n+\tepl_mask = ports->epl_mask &\n+\t    FM10K_SW_REG_FIELD64(gid, GLOBAL_INTERRUPT_DETECT_EPL);\n+\tfor (i = 0; i < FM10K_SW_EPLS_MAX; i++)\n+\t\tif (epl_mask & (1 << i))\n+\t\t\tfm10k_ext_ports_epl_intr(ports, i);\n+\n+\treturn ports->epl_mask;\n+}\n+\n+static void\n+fm10k_ext_ports_epl_intr(struct fm10k_ext_ports *ports, unsigned int eplno)\n+{\n+\tstruct fm10k_switch *sw = ports->sw;\n+\tstruct fm10k_ext_port *port;\n+\tuint64_t gid;\n+\tunsigned int i, j;\n+\tuint32_t epl_ip;\n+\n+\t/*\n+\t * The global interrupt detect architecture makes it somewhat\n+\t * challenging to ensure events are not lost and spurious interrupts\n+\t * are not generated.\n+\t *\n+\t * The EPLs have an internal interrupt hierarchy whose reporting is\n+\t * rooted at EPL_IP.  Whenever an EPL transitions from having no\n+\t * unmasked interrupts pending to at least one unmasked interrupt\n+\t * pending or from having at least one unmasked interrupt pending to\n+\t * no unmasked interrupts pending, it sends a vector to the\n+\t * interrupt controller over a serial bus indicating the\n+\t * at-least-one/none pending state, and the controller updates the\n+\t * bit for that EPL in the global interrupt detect register\n+\t * accordingly.\n+\t *\n+\t * Because of the update-vector-in-flight potential, there is a race\n+\t * between re-enabling the EPL PCIe interrupt mask after servicing\n+\t * the EPL interrupts and the all-clear vector from the EPL reaching\n+\t * the interrupt controller - it's possible for the software to\n+\t * clear all the EPL-internal interrupt sources during servicing and\n+\t * then re-enable the EPL interrupt in the PCIe mask before the\n+\t * all-clear vector reaches the interrupt controller and clears the\n+\t * EPL pending bit in the global interrupt detect register.  This\n+\t * would result in a spurious EPL interrupt, potentially for every\n+\t * necessary EPL interrupt.\n+\t *\n+\t * The approach taken here to avoid spurious interrupts is to first\n+\t * mask off all EPL-internal sources, then poll the EPL bits in the\n+\t * global interrupt detect register until they clear (indicating the\n+\t * update vector from the EPL has reached the interrupt controller).\n+\t * Then software interrupt processing proceeds, and the EPL-internal\n+\t * masks are restored to their desired state at the end.  This\n+\t * ensures that when the EPL PCIe interrupt mask is re-enabled, the\n+\t * EPL pending bits in the global interrupt detect register will\n+\t * only be set if there are new, unprocessed EPL events of interest.\n+\t *\n+\t */\n+\tFM10K_SW_SWITCH_LOCK(sw);\n+\t/* Grab epl_ip before it is cleared by the masks below */\n+\tepl_ip = fm10k_read_switch_reg(sw, FM10K_SW_EPL_IP(eplno));\n+\tfor (i = 0; i < ports->num_ports; i++) {\n+\t\tport = &ports->ports[i];\n+\t\tif (port->eplno != eplno)\n+\t\t\tcontinue;\n+\n+\t\tfm10k_write_switch_reg(sw,\n+\t\t    FM10K_SW_AN_IM(eplno, port->first_lane),\n+\t\t    FM10K_SW_AN_IM_ALL);\n+\t\tfm10k_write_switch_reg(sw,\n+\t\t    FM10K_SW_LINK_IM(eplno, port->first_lane),\n+\t\t    FM10K_SW_LINK_IM_ALL);\n+\n+\t\tfor (j = port->first_lane;\n+\t\t     j < port->first_lane + port->num_lanes; j++) {\n+\t\t\tfm10k_write_switch_reg(sw,\n+\t\t\t    FM10K_SW_SERDES_IM(eplno, j),\n+\t\t\t    FM10K_SW_SERDES_IM_ALL);\n+\t\t}\n+\t}\n+\n+\t/*\n+\t * Wait for the all-clear vector to propagate over the internal\n+\t * interrupt serial bus to the global interrupt detect.\n+\t */\n+\tdo {\n+\t\tgid = fm10k_read_switch_reg64\n+\t\t\t\t(sw, FM10K_SW_GLOBAL_INTERRUPT_DETECT);\n+\t} while (gid & FM10K_SW_GLOBAL_INTERRUPT_DETECT_EPL(eplno));\n+\tFM10K_SW_SWITCH_UNLOCK(sw);\n+\n+\t/*\n+\t * Proceed with interrupt processing per-external-port.\n+\t */\n+\tfor (i = 0; i < ports->num_ports; i++) {\n+\t\tport = &ports->ports[i];\n+\t\tif (port->eplno != eplno)\n+\t\t\tcontinue;\n+\t\tfm10k_ext_port_intr(port, epl_ip);\n+\t}\n+}\n+\n+static void\n+fm10k_ext_port_intr(struct fm10k_ext_port *port, uint32_t epl_ip)\n+{\n+\tstruct fm10k_switch *sw = port->ports->sw;\n+\tstruct fm10k_ext_port_lane *lane;\n+\tunsigned int i;\n+\tuint32_t serdes_ip, data = 0;\n+\n+\tfor (i = port->first_lane;\n+\t     i < port->first_lane + port->num_lanes; i++) {\n+\t\tlane = &port->lanes[i];\n+\t\tif (epl_ip & FM10K_SW_EPL_IP_SERDES_INTERRUPT(i)) {\n+\t\t\tFM10K_SW_SWITCH_LOCK(sw);\n+\t\t\tserdes_ip = fm10k_read_switch_reg(sw,\n+\t\t\t    FM10K_SW_SERDES_IP(port->eplno, i));\n+\t\t\tserdes_ip &= ~lane->im;\n+\t\t\tfm10k_write_switch_reg(sw,\n+\t\t\t    FM10K_SW_SERDES_IP(port->eplno, i), serdes_ip);\n+\t\t\tif (serdes_ip & FM10K_SW_SERDES_IP_RX_SIGNAL_OK)\n+\t\t\t\tdata =\n+\t\t\t\t\tfm10k_read_switch_reg(sw,\n+\t\t\t\t\tFM10K_SW_LANE_SERDES_STATUS(port->eplno,\n+\t\t\t\t\ti));\n+\t\t\tFM10K_SW_SWITCH_UNLOCK(sw);\n+\n+\t\t\tif (serdes_ip & FM10K_SW_SERDES_IP_RX_SIGNAL_OK) {\n+\t\t\t\tfm10k_sm_send_event(lane->sm,\n+\t\t\t\t    (data &\n+\t\t\t\tFM10K_SW_LANE_SERDES_STATUS_RX_SIGNAL_OK) ?\n+\t\t\t\tLANE_EVENT(SIGNAL_OK) : LANE_EVENT(SIGNAL_NOK));\n+\t\t\t}\n+\n+\t\t\tif (serdes_ip & FM10K_SW_SERDES_IP_RX_RDY)\n+\t\t\t\tfm10k_sm_send_event(lane->sm,\n+\t\t\t\t    LANE_EVENT(RX_PLL_LOCK));\n+\n+\t\t\tif (serdes_ip & FM10K_SW_SERDES_IP_TX_RDY)\n+\t\t\t\tfm10k_sm_send_event(lane->sm,\n+\t\t\t\t    LANE_EVENT(TX_PLL_LOCK));\n+\t\t} else {\n+\t\t\tfm10k_sm_send_event(lane->sm,\n+\t\t\t    LANE_EVENT(RESTORE_IM));\n+\t\t}\n+\t}\n+}\n+\n+void\n+fm10k_ext_port_up(struct fm10k_ext_port *port)\n+{\n+\tfm10k_sm_send_event(port->sm, PORT_EVENT(BRING_UP));\n+}\n+\n+void\n+fm10k_ext_port_down(struct fm10k_ext_port *port)\n+{\n+\tfm10k_sm_send_event(port->sm, PORT_EVENT(BRING_DOWN));\n+}\n+\n+unsigned int\n+fm10k_ext_port_isup(struct fm10k_ext_port *port)\n+{\n+\t/* no locked needed as we are just inspecting\n+\t * the current value of an int\n+\t */\n+\tunsigned int port_state = port->sm->state;\n+\n+\treturn (port_state == FM10K_SW_EXT_PORT_STATE_UP);\n+}\n+\n+static void\n+fm10k_ext_port_process_event(struct fm10k_sm *sm, uint16_t event)\n+{\n+\tstruct fm10k_ext_port *port = sm->ctx;\n+\tstruct fm10k_ext_port_lane *lane;\n+\tunsigned int i;\n+\tunsigned int lanes_up;\n+\n+\tswitch (sm->state) {\n+\tcase PORT_STATE(DOWN):\n+\t\tif (event == PORT_EVENT(BRING_UP)) {\n+\t\t\tfm10k_ext_port_phy_enable(port);\n+\n+\t\t\tfor (i = port->first_lane;\n+\t\t\t     i < port->first_lane + port->num_lanes; i++) {\n+\t\t\t\tlane = &port->lanes[i];\n+\t\t\t\tfm10k_sm_send_event\n+\t\t\t\t\t(lane->sm, LANE_EVENT(BRING_UP));\n+\t\t\t}\n+\t\t\tsm->state = PORT_STATE(WAITING_FOR_LANES);\n+\t\t}\n+\t\tbreak;\n+\n+\tcase PORT_STATE(WAITING_FOR_LANES):\n+\t\tif (event == PORT_EVENT(LANE_UP)) {\n+\t\t\tlanes_up = 0;\n+\t\t\tfor (i = port->first_lane;\n+\t\t\t     i < port->first_lane + port->num_lanes; i++) {\n+\t\t\t\tlane = &port->lanes[i];\n+\t\t\t\tif (lane->sm->state != LANE_STATE(UP))\n+\t\t\t\t\tbreak;\n+\t\t\t\tlanes_up++;\n+\t\t\t}\n+\t\t\tif (lanes_up == port->num_lanes) {\n+\t\t\t\tsm->state = PORT_STATE(UP);\n+\t\t\t\tFM10K_SW_INFO\n+\t\t\t\t(\"Port %d is LINK UP\", port->portno);\n+\t\t\t}\n+\t\t} else if (event == PORT_EVENT(BRING_DOWN)) {\n+\t\t\tfm10k_ext_port_bring_down(port);\n+\t\t}\n+\t\tbreak;\n+\n+\tcase PORT_STATE(UP):\n+\t\tif (event == PORT_EVENT(LANE_DOWN)) {\n+\t\t\tsm->state = PORT_STATE(WAITING_FOR_LANES);\n+\t\t\tFM10K_SW_INFO(\"Port %d is LINK DOWN\", port->portno);\n+\t\t} else if (event == PORT_EVENT(BRING_DOWN)) {\n+\t\t\tfm10k_ext_port_bring_down(port);\n+\t\t\tFM10K_SW_INFO(\"Port %d is LINK DOWN\", port->portno);\n+\t\t}\n+\t}\n+}\n+\n+static void\n+fm10k_ext_port_bring_down(struct fm10k_ext_port *port)\n+{\n+\tstruct fm10k_sm *sm = port->sm;\n+\tstruct fm10k_ext_port_lane *lane;\n+\tunsigned int i;\n+\n+\tsm->state = PORT_STATE(DOWN);\n+\n+\tfm10k_ext_port_phy_disable(port);\n+\n+\tfor (i = port->first_lane;\n+\t     i < port->first_lane + port->num_lanes; i++) {\n+\t\tlane = &port->lanes[i];\n+\t\tfm10k_sm_send_event(lane->sm, LANE_EVENT(BRING_DOWN));\n+\t}\n+}\n+\n+static void\n+fm10k_ext_port_lane_process_event(struct fm10k_sm *sm, uint16_t event)\n+{\n+\tstruct fm10k_ext_port_lane *lane = sm->ctx;\n+\tstruct fm10k_ext_port *port = lane->port;\n+\tstruct fm10k_switch *sw = lane->port->ports->sw;\n+\tint error;\n+\n+\tswitch (sm->state) {\n+\tcase LANE_STATE(DOWN):\n+\t\tif (event == LANE_EVENT(BRING_UP)) {\n+\t\t\tlane->flags &= ~LANE_FLAGS(PLLS_LOCKED);\n+\n+\t\t\t/*\n+\t\t\t * Clear all pending interrupts.\n+\t\t\t */\n+\t\t\tFM10K_SW_SWITCH_LOCK(sw);\n+\t\t\tfm10k_write_switch_reg(sw,\n+\t\t\t    FM10K_SW_SERDES_IP(port->eplno, lane->rel_laneno),\n+\t\t\t    FM10K_SW_SERDES_IP_ALL);\n+\t\t\tFM10K_SW_SWITCH_UNLOCK(sw);\n+\n+\t\t\terror = fm10k_epl_serdes_start_bringup(lane);\n+\t\t\tif (error == 0) {\n+\t\t\t\tsm->state = LANE_STATE(WAIT_PLL_LOCK);\n+\n+\t\t\t\t/*\n+\t\t\t\t * Enable PLL lock interrupts.\n+\t\t\t\t */\n+\t\t\t\tlane->im &= ~(FM10K_SW_SERDES_IM_RX_RDY |\n+\t\t\t\t    FM10K_SW_SERDES_IM_TX_RDY);\n+\t\t\t}\n+\t\t}\n+\t\tbreak;\n+\n+\tcase LANE_STATE(WAIT_PLL_LOCK):\n+\t\tif (event == LANE_EVENT(RX_PLL_LOCK) ||\n+\t\t    event == LANE_EVENT(TX_PLL_LOCK)) {\n+\t\t\tif (event == LANE_EVENT(RX_PLL_LOCK))\n+\t\t\t\tlane->flags |= LANE_FLAG(RX_LOCKED);\n+\t\t\tif (event == LANE_EVENT(TX_PLL_LOCK))\n+\t\t\t\tlane->flags |= LANE_FLAG(TX_LOCKED);\n+\t\t\tif (LANE_FLAGS_SET(lane, PLLS_LOCKED, PLLS_LOCKED)) {\n+\t\t\t\terror = fm10k_epl_serdes_continue_bringup(lane);\n+\t\t\t\tif (error == 0) {\n+\t\t\t\t\tsm->state = LANE_STATE(WAIT_SIGNAL_OK);\n+\t\t\t\t\t/* unmask RX signal OK interrupt */\n+\t\t\t\t\tlane->im |=\n+\t\t\t\t\t\t(FM10K_SW_SERDES_IM_RX_RDY |\n+\t\t\t\t\t    FM10K_SW_SERDES_IM_TX_RDY);\n+\t\t\t\t\tlane->im &=\n+\t\t\t\t\t~FM10K_SW_SERDES_IM_RX_SIGNAL_OK;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t} else if (event == LANE_EVENT(BRING_DOWN)) {\n+\t\t\tfm10k_ext_port_disable_lane(lane);\n+\t\t}\n+\t\tbreak;\n+\n+\tcase LANE_STATE(WAIT_SIGNAL_OK):\n+\t\tif (event == LANE_EVENT(SIGNAL_OK)) {\n+\t\t\tsm->state = LANE_STATE(WAIT_DFE_ICAL);\n+\n+\t\t\tfm10k_epl_serdes_configure_for_dfe_tuning(lane);\n+\t\t\tfm10k_epl_serdes_start_dfe_ical(lane);\n+\n+\t\t\tlane->dfe_poll_time_ms = 0;\n+\t\t\tfm10k_sm_timer_start(sm, LANE_TIMER(DFE_TUNING),\n+\t\t\t    LANE_POLL(DFE_ICAL));\n+\t\t} else if (event == LANE_EVENT(BRING_DOWN)) {\n+\t\t\tfm10k_ext_port_disable_lane(lane);\n+\t\t}\n+\t\tbreak;\n+\n+\tcase LANE_STATE(WAIT_DFE_ICAL):\n+\t\tif (event == LANE_EVENT(DFE_TUNING_COMPLETE)) {\n+\t\t\tsm->state = LANE_STATE(WAIT_DFE_PCAL);\n+\n+\t\t\tfm10k_epl_serdes_start_dfe_pcal(lane);\n+\n+\t\t\tlane->dfe_poll_time_ms = 0;\n+\t\t\tfm10k_sm_timer_start(sm, LANE_TIMER(DFE_TUNING),\n+\t\t\t    LANE_POLL(DFE_PCAL));\n+\t\t} else if ((event == LANE_EVENT(DFE_TUNING_FAILED)) ||\n+\t\t    (event == LANE_EVENT(DFE_TUNING_TIMED_OUT))) {\n+\t\t\tfm10k_ext_port_restart_lane(lane);\n+\t\t}  else if (event == LANE_EVENT(BRING_DOWN)) {\n+\t\t\tfm10k_ext_port_disable_lane(lane);\n+\t\t}\n+\t\tbreak;\n+\n+\tcase LANE_STATE(WAIT_DFE_PCAL):\n+\t\tif (event == LANE_EVENT(DFE_TUNING_COMPLETE)) {\n+\t\t\tfm10k_epl_serdes_set_signal_detect(lane,\n+\t\t\t    FM10K_SW_LANE_OVERRIDE_NORMAL);\n+\n+\t\t\tsm->state = LANE_STATE(UP);\n+\t\t\tfm10k_sm_send_event(port->sm, PORT_EVENT(LANE_UP));\n+\t\t} else if ((event == LANE_EVENT(DFE_TUNING_FAILED)) ||\n+\t\t    (event == LANE_EVENT(DFE_TUNING_TIMED_OUT)) ||\n+\t\t    (event == LANE_EVENT(SIGNAL_NOK))) {\n+\t\t\tfm10k_ext_port_restart_lane(lane);\n+\t\t}  else if (event == LANE_EVENT(BRING_DOWN)) {\n+\t\t\tfm10k_ext_port_disable_lane(lane);\n+\t\t}\n+\t\tbreak;\n+\n+\tcase LANE_STATE(UP):\n+\t\tif (event == LANE_EVENT(SIGNAL_NOK))\n+\t\t\tfm10k_ext_port_restart_lane(lane);\n+\t\telse if (event == LANE_EVENT(BRING_DOWN))\n+\t\t\tfm10k_ext_port_disable_lane(lane);\n+\t\tbreak;\n+\t}\n+\n+\t/* Always restore the interrupt mask */\n+\tFM10K_SW_SWITCH_LOCK(sw);\n+\tfm10k_write_switch_reg(sw,\n+\t    FM10K_SW_SERDES_IM(port->eplno,\n+\t\tlane->rel_laneno),\n+\t    lane->im);\n+\tFM10K_SW_SWITCH_UNLOCK(sw);\n+}\n+\n+static void\n+fm10k_ext_port_lane_process_timer(struct fm10k_sm *sm, uint16_t timer)\n+{\n+\tstruct fm10k_ext_port_lane *lane = sm->ctx;\n+\tuint32_t status;\n+\n+\tswitch (sm->state) {\n+\tcase LANE_STATE(WAIT_DFE_ICAL):\n+\t\tif (timer == LANE_TIMER(DFE_TUNING)) {\n+\t\t\tlane->dfe_poll_time_ms += LANE_POLL(DFE_ICAL);\n+\t\t\tfm10k_epl_serdes_dfe_ical_status(lane, &status);\n+\n+\t\t\tif (status == FM10K_SW_SERDES_DFE_ICAL_IN_PROGRESS) {\n+\t\t\t\tif (lane->dfe_poll_time_ms <\n+\t\t\t\t    LANE_TIMEOUT(DFE_ICAL))\n+\t\t\t\t\tfm10k_sm_timer_start(sm,\n+\t\t\t\t\t    LANE_TIMER(DFE_TUNING),\n+\t\t\t\t\t    LANE_POLL(DFE_ICAL));\n+\t\t\t\telse\n+\t\t\t\t\tfm10k_sm_send_event(sm,\n+\t\t\t\t\t    LANE_EVENT(DFE_TUNING_TIMED_OUT));\n+\t\t\t} else if (status == FM10K_SW_SERDES_DFE_ICAL_CONVERGED)\n+\t\t\t\tfm10k_sm_send_event(sm,\n+\t\t\t\t    LANE_EVENT(DFE_TUNING_COMPLETE));\n+\t\t\telse\n+\t\t\t\tfm10k_sm_send_event(sm,\n+\t\t\t\t    LANE_EVENT(DFE_TUNING_FAILED));\n+\t\t}\n+\t\tbreak;\n+\n+\tcase LANE_STATE(WAIT_DFE_PCAL):\n+\t\tif (timer == LANE_TIMER(DFE_TUNING)) {\n+\t\t\tlane->dfe_poll_time_ms += LANE_POLL(DFE_PCAL);\n+\n+\t\t\tfm10k_epl_serdes_dfe_pcal_status(lane, &status);\n+\t\t\tif (status == FM10K_SW_SERDES_DFE_PCAL_IN_PROGRESS) {\n+\t\t\t\tif (lane->dfe_poll_time_ms <\n+\t\t\t\t    LANE_TIMEOUT(DFE_PCAL))\n+\t\t\t\t\tfm10k_sm_timer_start(sm,\n+\t\t\t\t\t    LANE_TIMER(DFE_TUNING),\n+\t\t\t\t\t    LANE_POLL(DFE_PCAL));\n+\t\t\t\telse\n+\t\t\t\t\tfm10k_sm_send_event(sm,\n+\t\t\t\t\t    LANE_EVENT(DFE_TUNING_TIMED_OUT));\n+\t\t\t} else {\n+\t\t\t\tfm10k_sm_send_event(sm,\n+\t\t\t\t    LANE_EVENT(DFE_TUNING_COMPLETE));\n+\t\t\t}\n+\t\t}\n+\t\tbreak;\n+\t}\n+}\n+\n+static void\n+fm10k_ext_port_restart_lane(struct fm10k_ext_port_lane *lane)\n+{\n+\tstruct fm10k_sm *sm = lane->sm;\n+\tstruct fm10k_ext_port *port = lane->port;\n+\tint error;\n+\n+\terror = fm10k_epl_serdes_start_bringup(lane);\n+\tif (error == 0) {\n+\t\tsm->state = LANE_STATE(WAIT_PLL_LOCK);\n+\n+\t\t/*\n+\t\t * Enable PLL lock interrupts.\n+\t\t */\n+\t\tlane->flags &= ~FM10K_SW_EXT_PORT_LANE_FLAGS_PLLS_LOCKED;\n+\t\tlane->im |= FM10K_SW_SERDES_IM_RX_SIGNAL_OK;\n+\t\tlane->im = ~(FM10K_SW_SERDES_IM_RX_RDY |\n+\t\t    FM10K_SW_SERDES_IM_TX_RDY);\n+\t}\n+\n+\tfm10k_sm_send_event(port->sm, PORT_EVENT(LANE_DOWN));\n+}\n+\n+static void\n+fm10k_ext_port_disable_lane(struct fm10k_ext_port_lane *lane)\n+{\n+\tstruct fm10k_sm *sm = lane->sm;\n+\n+\tfm10k_sm_timer_cancel(sm, LANE_TIMER(DFE_TUNING));\n+\tfm10k_epl_serdes_disable(lane);\n+\n+\t/*\n+\t * Disable all interrupts.\n+\t */\n+\tlane->im = FM10K_SW_SERDES_IM_ALL;\n+\n+\tsm->state = LANE_STATE(DOWN);\n+}\n+\n+void\n+fm10k_ext_port_eplidx_lane(struct fm10k_ext_ports *ports,\n+\t\tunsigned int ext_port_idx, unsigned int *eplidx,\n+\t\tunsigned int *lane)\n+{\n+\tFM10K_SW_ASSERT(ext_port_idx < ports->num_ports,\n+\t    (\"ext_port_idx out of range\"));\n+\n+\t*eplidx = ext_port_idx / ports->ports_per_epl;\n+\t*lane = ext_port_idx % ports->ports_per_epl;\n+}\n+\n+\n+static void\n+fm10k_ext_port_phy_enable(struct fm10k_ext_port *port)\n+{\n+\tstruct fm10k_switch *sw = port->ports->sw;\n+\tstruct fm10k_device_info *cfg = sw->info;\n+\n+\tswitch (FM10K_SW_CARD_ID(cfg->subvendor, cfg->subdevice)) {\n+\tcase FM10K_SW_CARD(SILICOM, PE340G2DBIR_QS41):\n+\tcase FM10K_SW_CARD(SILICOM_RB, PE340G2DBIR_QS41):\n+\tcase FM10K_SW_CARD(SILICOM, PE340G2DBIR_QS43):\n+\tcase FM10K_SW_CARD(SILICOM_RB, PE340G2DBIR_QS43):\n+\tcase FM10K_SW_CARD(SILICOM, PE340G2DBIR_QL4):\n+\tcase FM10K_SW_CARD(SILICOM_RB, PE340G2DBIR_QL4):\n+\t\tFM10K_SW_I2C_LOCK(sw->i2c);\n+\t\t/* Set up the first PCA9545 mux so we can get at the\n+\t\t * PCA9505 that the QSFP control lines are connected\n+\t\t * to.\n+\t\t */\n+\t\tfm10k_i2c_write8(sw->i2c, 0x70, 0x04);\n+\n+\t\t/* Configure the I/O pins on the PCA9505 that are\n+\t\t * connected to LpMode and ResetL on the QSFP as\n+\t\t * outputs, and set LpMode to low to enable high\n+\t\t * power mode and set ResetL to high to take it out\n+\t\t * of reset.\n+\t\t */\n+\t\tif (port->portno == 0) {\n+\t\t\tfm10k_i2c_write16(sw->i2c, 0x20, 0x18, 0xf6);\n+\t\t\tfm10k_i2c_write16(sw->i2c, 0x20, 0x08, 0x08);\n+\t\t} else {\n+\t\t\tfm10k_i2c_write16(sw->i2c, 0x20, 0x19, 0xf6);\n+\t\t\tfm10k_i2c_write16(sw->i2c, 0x20, 0x09, 0x08);\n+\t\t}\n+\t\tFM10K_SW_I2C_UNLOCK(sw->i2c);\n+\t\tbreak;\n+\n+\tcase FM10K_SW_CARD(SILICOM, PE3100G2DQIR_QXSL4):\n+\tcase FM10K_SW_CARD(SILICOM, PE3100G2DQIR_QXSL4_REV_2):\n+\t\t\tFM10K_SW_I2C_LOCK(sw->i2c);\n+\t\t\t/* Set up the first PCA9545 mux so we can get\n+\t\t\t * at the PCA9505 that the QSFP control lines\n+\t\t\t * are connected to.\n+\t\t\t */\n+\t\t\tfm10k_i2c_write8(sw->i2c, 0x70, 0x01);\n+\n+\t\t\t/* Configure the I/O pins on the PCA9505 that are\n+\t\t\t * connected to LpMode and ResetL on the QSFP as\n+\t\t\t * outputs, and set LpMode to low to enable high\n+\t\t\t * power mode and set ResetL to high to take it out\n+\t\t\t * of reset.\n+\t\t\t */\n+\t\t\tif (port->portno == 0) {\n+\t\t\t\tfm10k_i2c_write16(sw->i2c, 0x20, 0x18, 0xf6);\n+\t\t\t\tfm10k_i2c_write16(sw->i2c, 0x20, 0x08, 0x08);\n+\t\t\t} else {\n+\t\t\t\tfm10k_i2c_write16(sw->i2c, 0x20, 0x19, 0xf6);\n+\t\t\t\tfm10k_i2c_write16(sw->i2c, 0x20, 0x09, 0x08);\n+\t\t\t}\n+\t\t\tFM10K_SW_I2C_UNLOCK(sw->i2c);\n+\t\t\tbreak;\n+\n+\tcase FM10K_SW_CARD(SILICOM, PE3100G2DQIRL_QXSL4):\n+\tcase FM10K_SW_CARD(SILICOM, PE3100G2DQIRM_QXSL4):\n+\t\tFM10K_SW_I2C_LOCK(sw->i2c);\n+\n+\t\t/* Configure the I/O pins on the PCA9538 that are\n+\t\t * connected to LpMode and ResetL on the QSFP as\n+\t\t * outputs, and set LpMode to low to enable high\n+\t\t * power mode and set ResetL to high to take it out\n+\t\t * of reset.\n+\t\t */\n+\t\tif (port->portno == 0) {\n+\t\t\tfm10k_i2c_write16(sw->i2c, 0x60, 0x03, 0xcf);\n+\t\t\tfm10k_i2c_write16(sw->i2c, 0x60, 0x01, 0x10);\n+\t\t} else {\n+\t\t\tfm10k_i2c_write16(sw->i2c, 0x61, 0x03, 0xcf);\n+\t\t\tfm10k_i2c_write16(sw->i2c, 0x61, 0x01, 0x10);\n+\t\t}\n+\t\tFM10K_SW_I2C_UNLOCK(sw->i2c);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tFM10K_SW_ERR(\"don't know how to enable phy for this card \"\n+\t\t    \"(subvendor=0x%04x subdevice=0x%04x)\\n\",\n+\t\t    cfg->subvendor, cfg->subdevice);\n+\t\tbreak;\n+\t}\n+}\n+\n+static void\n+fm10k_ext_port_phy_disable(struct fm10k_ext_port *port)\n+{\n+\tstruct fm10k_switch *sw = port->ports->sw;\n+\tstruct fm10k_device_info *cfg = sw->info;\n+\n+\tswitch (FM10K_SW_CARD_ID(cfg->subvendor, cfg->subdevice)) {\n+\tcase FM10K_SW_CARD(SILICOM, PE340G2DBIR_QS41):\n+\tcase FM10K_SW_CARD(SILICOM_RB, PE340G2DBIR_QS41):\n+\tcase FM10K_SW_CARD(SILICOM, PE340G2DBIR_QS43):\n+\tcase FM10K_SW_CARD(SILICOM_RB, PE340G2DBIR_QS43):\n+\tcase FM10K_SW_CARD(SILICOM, PE340G2DBIR_QL4):\n+\tcase FM10K_SW_CARD(SILICOM_RB, PE340G2DBIR_QL4):\n+\t\tFM10K_SW_I2C_LOCK(sw->i2c);\n+\t\t/* Set up the first PCA9545 mux so we can get at the PCA9505\n+\t\t * that the QSFP control lines are connected to.\n+\t\t */\n+\t\tfm10k_i2c_write8(sw->i2c, 0x70, 0x04);\n+\n+\t\t/* Configure the I/O pins on the PCA9505 that are\n+\t\t * connected to LpMode and ResetL on the QSFP as\n+\t\t * outputs, and set LpMode to high to disable high\n+\t\t * power mode and set ResetL to low to put it in\n+\t\t * reset.\n+\t\t */\n+\t\tif (port->portno == 0) {\n+\t\t\tfm10k_i2c_write16(sw->i2c, 0x20, 0x18, 0xf6);\n+\t\t\tfm10k_i2c_write16(sw->i2c, 0x20, 0x08, 0x01);\n+\t\t} else {\n+\t\t\tfm10k_i2c_write16(sw->i2c, 0x20, 0x19, 0xf6);\n+\t\t\tfm10k_i2c_write16(sw->i2c, 0x20, 0x09, 0x01);\n+\t\t}\n+\t\tFM10K_SW_I2C_UNLOCK(sw->i2c);\n+\t\tbreak;\n+\n+\tcase FM10K_SW_CARD(SILICOM, PE3100G2DQIR_QXSL4):\n+\tcase FM10K_SW_CARD(SILICOM, PE3100G2DQIR_QXSL4_REV_2):\n+\tFM10K_SW_I2C_LOCK(sw->i2c);\n+\t/* Set up the first PCA9545 mux so we can get at the PCA9505\n+\t * that the QSFP control lines are connected to.\n+\t */\n+\tfm10k_i2c_write8(sw->i2c, 0x70, 0x01);\n+\n+\t/* Configure the I/O pins on the PCA9505 that are\n+\t * connected to LpMode and ResetL on the QSFP as\n+\t * outputs, and set LpMode to high to disable high\n+\t * power mode and set ResetL to low to put it in\n+\t * reset.\n+\t */\n+\tif (port->portno == 0) {\n+\t\tfm10k_i2c_write16(sw->i2c, 0x20, 0x18, 0xf6);\n+\t\tfm10k_i2c_write16(sw->i2c, 0x20, 0x08, 0x01);\n+\t} else {\n+\t\tfm10k_i2c_write16(sw->i2c, 0x20, 0x19, 0xf6);\n+\t\tfm10k_i2c_write16(sw->i2c, 0x20, 0x09, 0x01);\n+\t}\n+\tFM10K_SW_I2C_UNLOCK(sw->i2c);\n+\tbreak;\n+\tcase FM10K_SW_CARD(SILICOM, PE3100G2DQIRL_QXSL4):\n+\tcase FM10K_SW_CARD(SILICOM, PE3100G2DQIRM_QXSL4):\n+\t\tFM10K_SW_I2C_LOCK(sw->i2c);\n+\t\t/* Configure the I/O pins on the PCA9538 that are\n+\t\t * connected to LpMode and ResetL on the QSFP as\n+\t\t * outputs, and set LpMode to high to disable high\n+\t\t * power mode and set ResetL to low to put it in\n+\t\t * reset.\n+\t\t */\n+\t\tif (port->portno == 0) {\n+\t\t\tfm10k_i2c_write16(sw->i2c, 0x60, 0x03, 0xcf);\n+\t\t\tfm10k_i2c_write16(sw->i2c, 0x60, 0x01, 0x20);\n+\t\t\tFM10K_SW_ERR(\"%s config PCA9538 %#x set LpMode\",\n+\t\t\t\t\t__func__, 0x60);\n+\t\t} else {\n+\t\t\tfm10k_i2c_write16(sw->i2c, 0x61, 0x03, 0xcf);\n+\t\t\tfm10k_i2c_write16(sw->i2c, 0x61, 0x01, 0x20);\n+\t\t\tFM10K_SW_ERR(\"%s config PCA9538 %#x set LpMode\",\n+\t\t\t\t\t__func__, 0x61);\n+\t\t}\n+\t\tFM10K_SW_I2C_UNLOCK(sw->i2c);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tFM10K_SW_ERR(\"don't know how to disable phy for this card \"\n+\t\t    \"(subvendor=0x%04x subdevice=0x%04x)\\n\",\n+\t\t    cfg->subvendor, cfg->subdevice);\n+\t\tbreak;\n+\t}\n+}\ndiff --git a/drivers/net/fm10k/switch/fm10k_ext_port.h b/drivers/net/fm10k/switch/fm10k_ext_port.h\nnew file mode 100644\nindex 0000000..9cc0574\n--- /dev/null\n+++ b/drivers/net/fm10k/switch/fm10k_ext_port.h\n@@ -0,0 +1,136 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019   Silicom Ltd. Connectivity Solutions\n+ */\n+\n+#ifndef _FM10K_SW_EXT_PORT_H_\n+#define _FM10K_SW_EXT_PORT_H_\n+\n+#include \"fm10k_regs.h\"\n+#include \"fm10k_sm.h\"\n+#include \"fm10k_sbus.h\"\n+#include \"fm10k_switch.h\"\n+\n+\n+struct fm10k_sbus;\n+struct fm10k_switch;\n+\n+#define FM10K_SW_TRACE_ENABLE 0\n+\n+enum fm10k_ext_port_lane_state {\n+\tFM10K_SW_EXT_PORT_LANE_STATE_DOWN,\n+\tFM10K_SW_EXT_PORT_LANE_STATE_WAIT_PLL_LOCK,\n+\tFM10K_SW_EXT_PORT_LANE_STATE_WAIT_SIGNAL_OK,\n+\tFM10K_SW_EXT_PORT_LANE_STATE_WAIT_DFE_ICAL,\n+\tFM10K_SW_EXT_PORT_LANE_STATE_WAIT_DFE_PCAL,\n+\tFM10K_SW_EXT_PORT_LANE_STATE_UP\n+};\n+\n+enum fm10k_ext_port_lane_event {\n+\tFM10K_SW_EXT_PORT_LANE_EVENT_BRING_UP,\n+\tFM10K_SW_EXT_PORT_LANE_EVENT_RX_PLL_LOCK,\n+\tFM10K_SW_EXT_PORT_LANE_EVENT_TX_PLL_LOCK,\n+\tFM10K_SW_EXT_PORT_LANE_EVENT_SIGNAL_OK,\n+\tFM10K_SW_EXT_PORT_LANE_EVENT_SIGNAL_NOK,\n+\tFM10K_SW_EXT_PORT_LANE_EVENT_DFE_TUNING_COMPLETE,\n+\tFM10K_SW_EXT_PORT_LANE_EVENT_DFE_TUNING_FAILED,\n+\tFM10K_SW_EXT_PORT_LANE_EVENT_DFE_TUNING_TIMED_OUT,\n+\tFM10K_SW_EXT_PORT_LANE_EVENT_RESTORE_IM,\n+\tFM10K_SW_EXT_PORT_LANE_EVENT_BRING_DOWN,\n+\n+\tFM10K_SW_EXT_PORT_LANE_NUM_EVENTS\n+};\n+\n+enum fm10k_ext_port_lane_timer {\n+\tFM10K_SW_EXT_PORT_LANE_TIMER_PLL_LOCK,\n+\tFM10K_SW_EXT_PORT_LANE_TIMER_SIGNAL_OK,\n+\tFM10K_SW_EXT_PORT_LANE_TIMER_DFE_TUNING,\n+\n+\tFM10K_SW_EXT_PORT_LANE_NUM_TIMERS\n+};\n+\n+#define FM10K_SW_EXT_PORT_LANE_PLL_LOCK_TIMEOUT_MS\t\t2000\n+#define FM10K_SW_EXT_PORT_LANE_SIGNAL_OK_TIMEOUT_MS\t\t2000\n+#define FM10K_SW_EXT_PORT_LANE_DFE_ICAL_POLL_MS\t\t\t200\n+#define FM10K_SW_EXT_PORT_LANE_DFE_ICAL_TIMEOUT_MS\t\t3000\n+#define FM10K_SW_EXT_PORT_LANE_DFE_PCAL_POLL_MS\t\t\t100\n+#define FM10K_SW_EXT_PORT_LANE_DFE_PCAL_TIMEOUT_MS\t\t2000\n+\n+\n+enum fm10k_ext_port_state {\n+\tFM10K_SW_EXT_PORT_STATE_DOWN,\n+\tFM10K_SW_EXT_PORT_STATE_WAITING_FOR_LANES,\n+\tFM10K_SW_EXT_PORT_STATE_UP\n+};\n+\n+enum fm10k_ext_port_event {\n+\tFM10K_SW_EXT_PORT_EVENT_BRING_UP,\n+\tFM10K_SW_EXT_PORT_EVENT_BRING_DOWN,\n+\tFM10K_SW_EXT_PORT_EVENT_LANE_UP,\n+\tFM10K_SW_EXT_PORT_EVENT_LANE_DOWN,\n+\n+\tFM10K_SW_EXT_PORT_NUM_EVENTS\n+};\n+\n+struct fm10k_ext_port;\n+\n+struct fm10k_ext_port_lane {\n+\tstruct fm10k_ext_port *port;\n+\tstruct fm10k_sm *sm;\n+\tuint32_t im;\n+\tuint16_t dfe_poll_time_ms;\n+\tuint8_t abs_laneno;\n+\tuint8_t rel_laneno;\n+\tuint8_t flags;\n+};\n+\n+#define FM10K_SW_EXT_PORT_LANE_FLAG_RX_LOCKED\t\t0x01\n+#define FM10K_SW_EXT_PORT_LANE_FLAG_TX_LOCKED\t\t0x02\n+\n+#define FM10K_SW_EXT_PORT_LANE_FLAGS_PLLS_LOCKED\t\\\n+\t\t(FM10K_SW_EXT_PORT_LANE_FLAG_RX_LOCKED | \\\n+\t\tFM10K_SW_EXT_PORT_LANE_FLAG_TX_LOCKED)\n+\n+struct fm10k_ext_ports;\n+\n+struct fm10k_ext_port {\n+\tstruct fm10k_ext_ports *ports;\n+\tstruct fm10k_sm *sm;\n+\tstruct fm10k_ext_port_lane lanes[FM10K_SW_EPL_LANES];\n+\tchar name[10];\n+\tuint8_t portno;\n+\tuint8_t eplno;\n+\tuint8_t lport;\t\t/* filled in by switch */\n+\tuint8_t first_lane; /* range is [0..3] */\n+\tuint8_t num_lanes;\n+\tuint8_t is_quad;\n+\tuint8_t lane_speed;\n+\tuint8_t last_led_flags;\n+\tuint32_t an_im;\n+\tuint32_t link_im;\n+};\n+\n+#define FM10K_SW_EXT_PORT_LED_FLAG_UP\t\t0x01\n+#define FM10K_SW_EXT_PORT_LED_FLAG_ACTIVE\t0x02\n+\n+struct fm10k_ext_ports {\n+\tstruct fm10k_switch *sw;\n+\tstruct fm10k_ext_port *ports;\n+\tuint16_t epl_mask;\n+\tuint8_t num_ports;\n+\tuint8_t ports_per_epl;\n+};\n+\n+#define FM10K_SW_EXT_PORTS_EPL_USED(p_, n_)\t((p_)->epl_mask & (1 << (n_)))\n+\n+struct fm10k_ext_ports *fm10k_ext_ports_attach(struct fm10k_switch *sw);\n+void fm10k_ext_ports_detach(struct fm10k_ext_ports *ports);\n+unsigned int fm10k_ext_ports_epl_intrs(struct fm10k_ext_ports *ports,\n+\t\tuint64_t gid);\n+void fm10k_ext_port_up(struct fm10k_ext_port *port);\n+void fm10k_ext_port_down(struct fm10k_ext_port *port);\n+unsigned int fm10k_ext_port_isup(struct fm10k_ext_port *port);\n+void fm10k_ext_port_eplidx_lane(struct fm10k_ext_ports *ports,\n+\t\tunsigned int ext_port_idx, unsigned int *eplidx,\n+\t\tunsigned int *lane);\n+\n+#endif /* _FM10K_SW_EXT_PORT_H_ */\ndiff --git a/drivers/net/fm10k/switch/fm10k_serdes.c b/drivers/net/fm10k/switch/fm10k_serdes.c\nnew file mode 100644\nindex 0000000..01b76a3\n--- /dev/null\n+++ b/drivers/net/fm10k/switch/fm10k_serdes.c\n@@ -0,0 +1,1936 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019   Silicom Ltd. Connectivity Solutions\n+ */\n+\n+#include <rte_time.h>\n+#include <rte_kvargs.h>\n+#include <rte_hash.h>\n+#include <rte_flow.h>\n+#include <rte_flow_driver.h>\n+#include <rte_tm_driver.h>\n+\n+#include \"fm10k_debug.h\"\n+#include \"fm10k_ext_port.h\"\n+#include \"fm10k_regs.h\"\n+#include \"fm10k_sbus.h\"\n+#include \"fm10k_serdes.h\"\n+#include \"fm10k_spico_code.h\"\n+#include \"fm10k_switch.h\"\n+\n+\n+#define FM10K_SW_SERDES_BIST_TIMEOUT_MS\t\t\t5000\n+#define FM10K_SW_SBM_INTERRUPT_TIMEOUT_MS\t\t5000\n+#define FM10K_SW_SERDES_INTERRUPT_TIMEOUT_MS\t\t3000\n+#define FM10K_SW_SERDES_INT02_TIMEOUT_MS\t\t500\n+\n+#define FM10K_SW_SERDES_CONFIG_DELAY_US\t\t\t20\n+#define FM10K_SW_SERDES_RESET_DELAY_US\t\t\t22\n+#define FM10K_SW_SERDES_DFE_STOP_CYCLE_DELAY_US\t\t200\n+\n+#define FM10K_SW_SERDES_DIVIDER_ETHMODE_25G\t\t0xa5\n+#define FM10K_SW_SERDES_DIVIDER_ETHMODE_10G\t\t0x42\n+\n+#define FM10K_SW_SERDES_WIDTH_40\t\t\t3  /* 25G */\n+#define FM10K_SW_SERDES_WIDTH_20\t\t\t1  /* 10G */\n+\n+#define FM10K_SW_SERDES_EQ_SEL_PRECUR\t\t\t0\n+#define FM10K_SW_SERDES_EQ_SEL_ATTEN\t\t\t1\n+#define FM10K_SW_SERDES_EQ_SEL_POSTCUR\t\t\t2\n+\n+#define FM10K_SW_SERDES_DFE_DEFAULT_HF\t\t\t0x00\n+#define FM10K_SW_SERDES_DFE_DEFAULT_LF\t\t\t0x0c\n+#define FM10K_SW_SERDES_DFE_DEFAULT_DC\t\t\t0x38\n+#define FM10K_SW_SERDES_DFE_DEFAULT_BW\t\t\t0x0f\n+\n+#define FM10K_SW_SERDES_ICAL_STOP_MAX_CYCLES\t\t10\n+#define FM10K_SW_SERDES_PCAL_STOP_MAX_CYCLES\t\t500\n+\n+#define FM10K_SERDES_SPICO_REG_0X00\t\t\t0x00\n+#define FM10K_SERDES_SPICO_REG_0X01\t\t\t0x01\n+#define FM10K_SERDES_SPICO_REG_0X02\t\t\t0x02\n+#define FM10K_SERDES_SPICO_REG_0X03\t\t\t0x03\n+#define FM10K_SERDES_SPICO_REG_0X04\t\t\t0x04\n+#define FM10K_SERDES_SPICO_REG_0X05\t\t\t0x05\n+#define FM10K_SERDES_SPICO_REG_0X07\t\t\t0x07\n+#define FM10K_SERDES_SPICO_REG_0X08\t\t\t0x08\n+#define FM10K_SERDES_SPICO_REG_0X0A\t\t\t0x0A\n+#define FM10K_SERDES_SPICO_REG_0X0B\t\t\t0x0b\n+#define FM10K_SERDES_SPICO_REG_0X14\t\t\t0x14\n+#define FM10K_SERDES_SPICO_REG_0X16\t\t\t0x16\n+\n+\n+/*\n+ * These values correspond to IES FM_PORT_LINK_OPTIMIZATION_BALANCE\n+ * settings.\n+ */\n+#define FM10K_SW_LINK_OPT_PARAM_A10G\t\t\t0x4800\n+#define FM10K_SW_LINK_OPT_PARAM_B10G\t\t\t0xA000\n+#define FM10K_SW_LINK_OPT_PARAM_A25G\t\t\t0x10001\n+#define FM10K_SW_LINK_OPT_PARAM_B25G\t\t\t0x10001\n+\n+#define FM10K_SW_SERDES_DFE_DATA_LEVEL0_THRESHOLD\t10\n+\n+\n+static int fm10k_spico_ram_bist(struct fm10k_sbus *sb);\n+static int fm10k_load_epl_spico_code(struct fm10k_switch *sw);\n+static int fm10k_sbm_spico_upload_image(struct fm10k_sbus *sb,\n+\t\tconst uint16_t *image, unsigned int num_words);\n+static int fm10k_sbm_check_crc_version_build_id(struct fm10k_sbus *sb,\n+\t\tuint32_t expected_version_build_id);\n+static int fm10k_sbm_spico_do_crc(struct fm10k_sbus *sb);\n+static int fm10k_sbm_get_version_build_id(struct fm10k_sbus *sb,\n+\t\tuint32_t *version_build_id);\n+static int fm10k_serdes_swap_upload_image(struct fm10k_sbus *sb,\n+\t\tconst uint16_t *image, unsigned int num_words);\n+static int fm10k_serdes_swap_alt_upload_image(struct fm10k_sbus *sb,\n+\t\tconst uint16_t *image, unsigned int num_words);\n+static int fm10k_swap_image_check_crc(struct fm10k_sbus *sb,\n+\t\tunsigned int crc_code);\n+static int fm10k_serdes_spico_upload_image(struct fm10k_sbus *sb,\n+\t\tuint8_t dev, const uint16_t *image, unsigned int num_words);\n+static int fm10k_epl_serdes_check_crc_version_build_id(struct fm10k_switch *sw,\n+\t    uint32_t expected_version_build_id);\n+static int fm10k_epl_serdes_spico_do_crc(struct fm10k_switch *sw,\n+\t\tunsigned int serdes);\n+static int fm10k_epl_serdes_spico_reset(struct fm10k_switch *sw,\n+\t\tunsigned int serdes);\n+static int fm10k_epl_serdes_get_version_build_id(struct fm10k_switch *sw,\n+\t    unsigned int serdes, uint32_t *version_build_id);\n+static int fm10k_sbm_spico_int(struct fm10k_sbus *sb,\n+\t\tuint8_t int_num, uint32_t param, uint32_t *result);\n+static int fm10k_epl_serdes_spico_int(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, uint16_t int_num,\n+\t\tuint32_t param, uint32_t *result);\n+static int fm10k_epl_serdes_set_bit_rate(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, unsigned int divider);\n+static int fm10k_epl_serdes_set_width_mode(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, unsigned int width_mode);\n+static void fm10k_epl_serdes_set_pcsl_width_mode(struct fm10k_switch *sw,\n+\t    unsigned int serdes, unsigned int width_mode);\n+static int fm10k_epl_serdes_set_pcsl_bit_slip(struct fm10k_switch *sw,\n+\t\tunsigned int serdes);\n+static int fm10k_epl_serdes_init_signal_ok(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, unsigned int threshold);\n+static int fm10k_epl_serdes_set_tx_eq(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, unsigned int which, unsigned int tx_eq);\n+static int fm10k_epl_serdes_spico_int02_retry(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, uint32_t data, unsigned int timeout_ms);\n+static int fm10k_epl_serdes_dma_reg_write(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, unsigned int addr, uint32_t data);\n+static int fm10k_epl_serdes_dma_esb_write(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, unsigned int addr, uint32_t data);\n+static int fm10k_epl_serdes_dma_esb_read_modify_write(struct fm10k_switch *sw,\n+\t    unsigned int serdes, unsigned int addr, uint32_t data,\n+\t\tuint32_t mask, uint32_t *result);\n+static int fm10k_epl_serdes_dma_esb_read(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, unsigned int addr, uint32_t *result);\n+static int fm10k_epl_serdes_spico_wr_only_int(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, unsigned int int_num, uint32_t param);\n+static void fm10k_epl_serdes_eplno_lane(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, unsigned int *eplno, unsigned int *lane);\n+static int fm10k_epl_serdes_configure_near_loopback\n+\t\t(struct fm10k_ext_port_lane *lane);\n+static int fm10k_epl_serdes_config_dfe_param(struct fm10k_switch *sw,\n+\t    unsigned int serdes, uint32_t param);\n+static int fm10k_epl_serdes_get_dfe_status(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, uint32_t *status);\n+static int fm10k_epl_serdes_get_ical_result(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, uint32_t *converged);\n+\n+\n+int\n+fm10k_epl_serdes_reset_and_load_all(struct fm10k_switch *sw)\n+{\n+\tstruct fm10k_sbus *sb = sw->epl_sbus;\n+\tint error;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: initializing EPL serdes\", sb->name);\n+\n+\terror = fm10k_spico_ram_bist(sb);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_load_epl_spico_code(sw);\n+\tif (error)\n+\t\tgoto done;\n+\n+done:\n+\treturn (error);\n+}\n+\n+\n+int\n+fm10k_spico_ram_bist(struct fm10k_sbus *sb)\n+{\n+\tuint64_t start_time_us, elapsed_time_ms;\n+\tuint32_t data;\n+\tint error;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: starting SPICO RAM BIST\", sb->name);\n+\n+\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X00, 0x03);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X00, 0x05);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tstart_time_us = fm10k_uptime_us();\n+\telapsed_time_ms = 0;\n+\twhile (elapsed_time_ms < FM10K_SW_SERDES_BIST_TIMEOUT_MS) {\n+\t\telapsed_time_ms = (fm10k_uptime_us() - start_time_us) / 1000;\n+\t\terror = fm10k_sbus_read(sb,\n+\t\t\t\tFM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\t\tFM10K_SERDES_SPICO_REG_0X00, &data);\n+\t\tif (error)\n+\t\t\tgoto done;\n+\n+\t\tif (data & 0x18) {\n+\t\t\terror = fm10k_sbus_write(sb,\n+\t\t\t\t\tFM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\t\t\tFM10K_SERDES_SPICO_REG_0X00, 0x00);\n+\t\t\tif (error)\n+\t\t\t\tgoto done;\n+\t\t\tif ((data & 0x18) != 0x08) {\n+\t\t\t\tFM10K_SW_INFO(\"sbus %s: SPICO RAM \"\n+\t\t\t\t    \"BIST failed with bad status (0x%08x)\",\n+\t\t\t\t    sb->name, data);\n+\t\t\t\terror = -1;\n+\t\t\t\tgoto done;\n+\t\t\t}\n+\t\t\tgoto done;\n+\t\t}\n+\t}\n+\tfm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X00, 0x00);\n+\terror = -1;\n+\tFM10K_SW_INFO(\"sbus %s: SPICO RAM BIST timed out after %u \"\n+\t    \"ms\", sb->name, (uint32_t)elapsed_time_ms);\n+\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_load_epl_spico_code(struct fm10k_switch *sw)\n+{\n+\tstruct fm10k_sbus *sb = sw->epl_sbus;\n+\tconst uint16_t *sbm_code_image;\n+\tuint32_t sbm_code_size;\n+\tuint32_t sbm_code_version_build_id;\n+\tconst uint16_t *serdes_code_image;\n+\tuint32_t serdes_code_size;\n+\tuint32_t serdes_code_version_build_id;\n+\tconst uint16_t *swap_code_image;\n+\tuint32_t swap_code_size;\n+\tunsigned int swap_crc_code;\n+\tint error = 0;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: loading SPICO code\", sb->name);\n+\n+\tsbm_code_image = fm10000_sbus_master_code_prd;\n+\tsbm_code_size = fm10000_sbus_master_code_size_prd;\n+\tsbm_code_version_build_id =\n+\t    fm10000_sbus_master_code_version_build_id_prd;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: sbm code version=%4.4x build=%4.4x\",\n+\t    sb->name, sbm_code_version_build_id >> 16,\n+\t    sbm_code_version_build_id & 0xffff);\n+\n+\tserdes_code_image = fm10000_serdes_spico_code_prd2;\n+\tserdes_code_size = fm10000_serdes_spico_code_size_prd2;\n+\tserdes_code_version_build_id =\n+\t    fm10000_serdes_spico_code_version_build_id_prd2;\n+\tsw->epl_serdes_code_version_build_id = serdes_code_version_build_id;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: serdes code version=%4.4x build=%4.4x\",\n+\t    sb->name, serdes_code_version_build_id >> 16,\n+\t    serdes_code_version_build_id & 0xffff);\n+\n+\tswap_code_image = fm10000_serdes_swap_code_prd2;\n+\tswap_code_size = fm10000_serdes_swap_code_size_prd2;\n+\n+\terror = fm10k_sbm_spico_upload_image(sb, sbm_code_image,\n+\t    sbm_code_size);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_sbm_check_crc_version_build_id(sb,\n+\t    sbm_code_version_build_id);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tif (swap_code_size > 0) {\n+\t\tif ((sbm_code_version_build_id & 0x00008000) == 0) {\n+\t\t\terror = fm10k_serdes_swap_upload_image(sb,\n+\t\t\t    swap_code_image, swap_code_size);\n+\t\t\tswap_crc_code = 0x1a;\n+\t\t} else {\n+\t\t\terror = fm10k_serdes_swap_alt_upload_image(sb,\n+\t\t\t    swap_code_image, swap_code_size);\n+\t\t\tswap_crc_code = 0x04;\n+\t\t}\n+\t\tif (error)\n+\t\t\tgoto done;\n+\n+\t\terror = fm10k_swap_image_check_crc(sb, swap_crc_code);\n+\t\tif (error)\n+\t\t\tgoto done;\n+\t}\n+\n+\terror = fm10k_serdes_spico_upload_image(sb,\n+\t\t\tFM10K_SW_SBUS_ADDR_BROADCAST,\n+\t\t\tserdes_code_image, serdes_code_size);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_epl_serdes_check_crc_version_build_id(sw,\n+\t    serdes_code_version_build_id);\n+\tif (error)\n+\t\tgoto done;\n+\n+done:\n+\treturn (error);\n+}\n+\n+\n+static int\n+fm10k_sbm_spico_upload_image(struct fm10k_sbus *sb,\n+\t\tconst uint16_t *image, unsigned int num_words)\n+{\n+\tuint64_t start_time_us, elapsed_time_us;\n+\tunsigned int i;\n+\tuint32_t data;\n+\tint error;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: uploading SBM SPICO image \"\n+\t    \"(%u words)\", sb->name, num_words);\n+\n+\tdata = (1 << 6) | (1 << 7);\n+\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X01, data);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tdata &= ~(1 << 7);\n+\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X01, data);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tdata |= (1 << 9);\n+\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X01, data);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tstart_time_us = fm10k_uptime_us();\n+\tfor (i = 0; i < num_words; i++) {\n+\t\tdata = 0x80000000 | ((uint32_t)image[i] << 16) | i;\n+\t\terror = fm10k_sbus_write(sb,\n+\t\t\t\tFM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\t\tFM10K_SERDES_SPICO_REG_0X03, data);\n+\t\tif (error)\n+\t\t\tgoto done;\n+\t}\n+\telapsed_time_us = fm10k_uptime_us() - start_time_us;\n+\tFM10K_SW_TRACE(\"sbus %s: SBM image upload time %u ms\",\n+\t    sb->name, (uint32_t)(elapsed_time_us / 1000));\n+\n+\tdata = (1 << 6);\n+\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X01, data);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tdata = (1 << 18) | (1 << 19);\n+\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X16, data);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tdata = (1 << 6) | (1 << 8);\n+\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X01, data);\n+\tif (error)\n+\t\tgoto done;\n+\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_sbm_check_crc_version_build_id(struct fm10k_sbus *sb,\n+\t\tuint32_t expected_version_build_id)\n+{\n+\tint error;\n+\tuint32_t version_build_id;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: checking SBM SPICO code CRC \"\n+\t    \"and version\", sb->name);\n+\n+\terror = fm10k_sbm_spico_do_crc(sb);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_sbm_get_version_build_id(sb, &version_build_id);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tif (version_build_id != expected_version_build_id) {\n+\t\tFM10K_SW_INFO(\"sbus %s: SBM SPICO code version \"\n+\t\t    \"compare failed (expected 0x%08x, got 0x%08x)\",\n+\t\t    sb->name, expected_version_build_id, version_build_id);\n+\t\terror = -1;\n+\t\tgoto done;\n+\t}\n+\tFM10K_SW_TRACE(\"sbus %s: SBM SPICO image \"\n+\t    \"version=0x%4.4x build_id=0x%4.4x\", sb->name,\n+\t    version_build_id >> 16,\n+\t    version_build_id & 0xffff);\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_sbm_spico_do_crc(struct fm10k_sbus *sb)\n+{\n+\tint error;\n+\tuint32_t crc;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: performing SBM SPICO CRC \"\n+\t    \"check\", sb->name);\n+\n+\terror = fm10k_sbm_spico_int(sb, 0x02, 0, &crc);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tcrc = crc >> 16;\n+\tif (crc == 0xffff) {\n+\t\tFM10K_SW_INFO(\"sbus %s: SBM SPICO CRC check failed \"\n+\t\t    \"(CRC interrupt returned 0xffff)\", sb->name);\n+\t\terror = -1;\n+\t\tgoto done;\n+\t} else if (crc == 0x0001)\n+\t\tFM10K_SW_TRACE(\"sbus %s: SBM SPICO CRC check \"\n+\t\t    \"passed \", sb->name);\n+\telse\n+\t\tFM10K_SW_INFO(\"sbus %s: unexpected SBM SPICO CRC \"\n+\t\t    \"check result 0x%04x\", sb->name, crc);\n+\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_sbm_get_version_build_id(struct fm10k_sbus *sb,\n+\t\tuint32_t *version_build_id)\n+{\n+\tint error;\n+\tuint32_t result;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: getting SBM code version\",\n+\t    sb->name);\n+\n+\terror = fm10k_sbm_spico_int(sb, 0x00, 0, &result);\n+\tif (error)\n+\t\tgoto done;\n+\n+\t*version_build_id = result & 0xffff0000;\n+\terror = fm10k_sbm_spico_int(sb, 0x01, 0, &result);\n+\tif (error)\n+\t\tgoto done;\n+\n+\t*version_build_id |= (result >> 16) & 0xffff;\n+\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_serdes_swap_upload_image(struct fm10k_sbus *sb,\n+\t\tconst uint16_t *image, unsigned int num_words)\n+{\n+\tuint64_t start_time_us, elapsed_time_us;\n+\tunsigned int i;\n+\tuint32_t addr;\n+\tuint32_t reg01, reg05;\n+\tint error;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: uploading SBM swap image \"\n+\t    \"(%u words)\", sb->name, num_words);\n+\n+\terror = fm10k_sbm_spico_int(sb, 0x1c, 0, &addr);\n+\tif (error)\n+\t\tgoto done;\n+\n+\taddr >>= 16;\n+\tif (addr == 0xffff) {\n+\t\tFM10K_SW_INFO(\"sbus %s: invalid build - cannot \"\n+\t\t    \"upload SBM swap image\", sb->name);\n+\t\terror = -1;\n+\t\tgoto done;\n+\t}\n+\tFM10K_SW_TRACE(\"sbus %s: SBM swap image initial load \"\n+\t    \"address 0x%04x (%u)\", sb->name, addr, addr);\n+\n+\treg05 = 1;\n+\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X05, reg05);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_sbus_read(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X01, &reg01);\n+\tif (error)\n+\t\tgoto done;\n+\n+\treg01 |= (1 << 9);\n+\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X01, reg01);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tstart_time_us = fm10k_uptime_us();\n+\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X03, addr);\n+\tif (error)\n+\t\tgoto done;\n+\terror = fm10k_sbus_write(sb,\n+\t\t\tFM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X03, 0x80000000 | addr);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tfor (i = 0; i < num_words - 2; i += 3) {\n+\t\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X14,\n+\t\t\t0xc0000000 | image[i] |\n+\t\t\t((uint32_t)image[i + 1] << 10) |\n+\t\t\t((uint32_t)image[i + 2] << 20));\n+\t\tif (error)\n+\t\t\tgoto done;\n+\t}\n+\n+\tif (num_words - i == 2) {\n+\t\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X14,\n+\t\t\t0x80000000 | image[i] |\n+\t\t\t((uint32_t)image[i + 1] << 10));\n+\t\tif (error)\n+\t\t\tgoto done;\n+\t} else if (num_words - i == 1) {\n+\t\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X14,\n+\t\t\t0x40000000 | image[i]);\n+\t\tif (error)\n+\t\t\tgoto done;\n+\t}\n+\telapsed_time_us = fm10k_uptime_us() - start_time_us;\n+\tFM10K_SW_TRACE(\"sbus %s: SBM swap image upload time \"\n+\t    \"%u ms\", sb->name, (uint32_t)(elapsed_time_us / 1000));\n+\n+\treg01 &= ~(1 << 9);\n+\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\tFM10K_SERDES_SPICO_REG_0X01, reg01);\n+\tif (error)\n+\t\tgoto done;\n+\n+\treg05 &= ~(1 << 0);\n+\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\tFM10K_SERDES_SPICO_REG_0X05, reg05);\n+\tif (error)\n+\t\tgoto done;\n+\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_serdes_swap_alt_upload_image(struct fm10k_sbus *sb,\n+\t\tconst uint16_t *image, unsigned int num_words)\n+{\n+\tuint64_t start_time_us, elapsed_time_us;\n+\tunsigned int i;\n+\tuint32_t addr;\n+\tuint32_t reg01, reg05;\n+\tint error;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: alt-uploading SBM swap image \"\n+\t    \"(%u words)\", sb->name, num_words);\n+\n+\treg05 = 1;\n+\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\tFM10K_SERDES_SPICO_REG_0X05, reg05);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_sbus_read(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\tFM10K_SERDES_SPICO_REG_0X01, &reg01);\n+\tif (error)\n+\t\tgoto done;\n+\n+\treg01 |= (1 << 10) | (1 << 11);\n+\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\tFM10K_SERDES_SPICO_REG_0X01, reg01);\n+\tif (error)\n+\t\tgoto done;\n+\n+\taddr = 0x0400;\n+\tFM10K_SW_TRACE(\"sbus %s: SBM swap image initial load \"\n+\t    \"address 0x%04x (%u)\", sb->name, addr, addr);\n+\n+\tstart_time_us = fm10k_uptime_us();\n+\tfor (i = 0; i < num_words; i++) {\n+\t\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X04,\n+\t\t\t0x8000 | ((uint32_t)image[i + 1] << 16) |\n+\t\t\t(addr + i));\n+\t\tif (error)\n+\t\t\tgoto done;\n+\t}\n+\telapsed_time_us = fm10k_uptime_us() - start_time_us;\n+\tFM10K_SW_TRACE(\"sbus %s: SBM swap image alt-upload \"\n+\t    \"time %u ms\", sb->name, (uint32_t)(elapsed_time_us / 1000));\n+\n+\treg01 &= ~((1 << 10) | (1 << 11));\n+\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X01, reg01);\n+\tif (error)\n+\t\tgoto done;\n+\n+\treg05 &= ~(1 << 0);\n+\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X05, reg05);\n+\tif (error)\n+\t\tgoto done;\n+\n+done:\n+\treturn error;\n+}\n+\n+static int\n+fm10k_swap_image_check_crc(struct fm10k_sbus *sb, unsigned int crc_code)\n+{\n+\tint error;\n+\tuint32_t crc;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: performing SBM swap image CRC \"\n+\t    \"check\", sb->name);\n+\n+\terror =\n+\t    fm10k_sbm_spico_int(sb, crc_code, 0, &crc);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tcrc >>= 16;\n+\tif (crc == 0xffff) {\n+\t\tFM10K_SW_INFO(\"sbus %s: SBM swap image CRC check \"\n+\t\t    \"failed (CRC interrupt 0x%02x returned 0xffff)\",\n+\t\t    sb->name, crc_code);\n+\t\terror = -1;\n+\t\tgoto done;\n+\t} else if (crc == 0x0001)\n+\t\tFM10K_SW_TRACE(\"sbus %s: SBM swap image CRC \"\n+\t\t    \"check passed \", sb->name);\n+\telse\n+\t\tFM10K_SW_INFO(\"sbus %s: unexpected SBM swap image \"\n+\t\t    \"CRC check result 0x%04x\", sb->name, crc);\n+\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_serdes_spico_upload_image(struct fm10k_sbus *sb,\n+\t\tuint8_t dev, const uint16_t *image, unsigned int num_words)\n+{\n+\tuint64_t start_time_us, elapsed_time_us;\n+\tunsigned int i;\n+\tuint32_t data;\n+\tuint32_t reg07;\n+\tint error;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: uploading serdes SPICO image \"\n+\t    \"to bus address 0x%02x (%u words)\", sb->name, dev, num_words);\n+\n+\treg07 = (1 << 0) | (1 << 4);\n+\terror = fm10k_sbus_write(sb, dev, FM10K_SERDES_SPICO_REG_0X03, reg07);\n+\tif (error)\n+\t\tgoto done;\n+\n+\treg07 &= ~(1 << 0);\n+\terror = fm10k_sbus_write(sb, dev, FM10K_SERDES_SPICO_REG_0X07, reg07);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tdata = (1 << 30);\n+\terror = fm10k_sbus_write(sb, dev, FM10K_SERDES_SPICO_REG_0X00, data);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tdata = (1 << 4) | (1 << 5);\n+\terror = fm10k_sbus_write(sb, dev, FM10K_SERDES_SPICO_REG_0X08, data);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tstart_time_us = fm10k_uptime_us();\n+\tfor (i = 0; i < num_words; i += 3) {\n+\t\tdata = 0xc0000000 | image[i];\n+\t\tif (i + 1 < num_words) {\n+\t\t\tdata |= (uint32_t)image[i + 1] << 10;\n+\n+\t\t\tif (i + 2 < num_words)\n+\t\t\t\tdata |= (uint32_t)image[i + 2] << 20;\n+\t\t}\n+\t\terror = fm10k_sbus_write(sb, dev,\n+\t\t\t\tFM10K_SERDES_SPICO_REG_0X0A, data);\n+\t\tif (error)\n+\t\t\tgoto done;\n+\t}\n+\telapsed_time_us = fm10k_uptime_us() - start_time_us;\n+\tFM10K_SW_TRACE(\"sbus %s: serdes SPICO image upload \"\n+\t    \"time %u ms\", sb->name, (uint32_t)(elapsed_time_us / 1000));\n+\n+\terror = fm10k_sbus_write(sb, dev, FM10K_SERDES_SPICO_REG_0X00, 0);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_sbus_write(sb, dev,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X01, 0x20000000);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tdata = (1 << 18) | (1 << 19);\n+\terror = fm10k_sbus_write(sb, dev, FM10K_SERDES_SPICO_REG_0X0B, data);\n+\tif (error)\n+\t\tgoto done;\n+\n+\treg07 |= (1 << 0);\n+\terror = fm10k_sbus_write(sb, dev, FM10K_SERDES_SPICO_REG_0X07, reg07);\n+\tif (error)\n+\t\tgoto done;\n+\n+\treg07 &= ~(1 << 0);\n+\terror = fm10k_sbus_write(sb, dev, FM10K_SERDES_SPICO_REG_0X07, reg07);\n+\tif (error)\n+\t\tgoto done;\n+\n+\treg07 |= (1 << 1);\n+\terror = fm10k_sbus_write(sb, dev, FM10K_SERDES_SPICO_REG_0X07, reg07);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_sbus_write(sb, dev, FM10K_SERDES_SPICO_REG_0X08, 0);\n+\tif (error)\n+\t\tgoto done;\n+\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_epl_serdes_check_crc_version_build_id(struct fm10k_switch *sw,\n+\t\tuint32_t expected_version_build_id)\n+{\n+\tstruct fm10k_sbus *sb = sw->epl_sbus;\n+\tunsigned int first = 0;\n+\tunsigned int last = FM10K_SW_EPLS_MAX * FM10K_SW_EPL_LANES - 1;\n+\tunsigned int i;\n+\tint error;\n+\tuint32_t data;\n+\tuint32_t version_build_id;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: checking SPICO code CRC and \"\n+\t    \"version for serdes %u through %u\", sb->name, first, last);\n+\n+\tfor (i = first; i <= last; i++) {\n+\t\terror = fm10k_sbus_read(sb,\n+\t\t\t\tFM10K_SW_SBUS_ADDR_EPL_SERDES(i), 0xff, &data);\n+\t\tif (error || data != 0x01) {\n+\t\t\tFM10K_SW_TRACE(\"sbus %s: skipping \"\n+\t\t\t    \"serdes %u (error=%d, data=0x%08x)\", sb->name, i,\n+\t\t\t    error, data);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\terror = fm10k_epl_serdes_spico_do_crc(sw, i);\n+\t\tif (error)\n+\t\t\tgoto done;\n+\n+\t\terror = fm10k_epl_serdes_get_version_build_id(sw, i,\n+\t\t    &version_build_id);\n+\t\tif (error)\n+\t\t\tgoto done;\n+\n+\t\tif (version_build_id != expected_version_build_id) {\n+\t\t\tFM10K_SW_INFO(\"sbus %s: SERDES SPICO code \"\n+\t\t\t    \"version compare failed (expected 0x%08x, got \"\n+\t\t\t    \"0x%08x)\", sb->name, expected_version_build_id,\n+\t\t\t    version_build_id);\n+\t\t\terror = -1;\n+\t\t\tgoto done;\n+\t\t}\n+\t}\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u through %u are OK\",\n+\t    sb->name, first, last);\n+\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_epl_serdes_spico_do_crc(struct fm10k_switch *sw, unsigned int serdes)\n+{\n+\tstruct fm10k_sbus *sb = sw->epl_sbus;\n+\tint error;\n+\tuint32_t crc;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: performing SPICO \"\n+\t    \"CRC check\", sb->name, serdes);\n+\n+\terror = fm10k_epl_serdes_spico_int(sw, serdes, 0x3c, 0, &crc);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tif (crc != 0) {\n+\t\tFM10K_SW_INFO(\"sbus %s: serdes %u:  SPICO CRC check \"\n+\t\t    \"failed (CRC interrupt returned 0x%08x)\",\n+\t\t    sb->name, serdes, crc);\n+\t\terror = -1;\n+\t\tgoto done;\n+\t}\n+\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_epl_serdes_spico_reset(struct fm10k_switch *sw, unsigned int serdes)\n+{\n+\tstruct fm10k_sbus *sb = sw->epl_sbus;\n+\tint error;\n+\tuint32_t data;\n+\tuint8_t addr = FM10K_SW_SBUS_ADDR_EPL_SERDES(serdes);\n+\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: resetting SPICO\",\n+\t    sb->name, serdes);\n+\n+\tfm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US);\n+\terror = fm10k_sbus_write(sb, addr, FM10K_SERDES_SPICO_REG_0X00, 0x00);\n+\tif (error)\n+\t\tgoto done;\n+\tfm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US);\n+\n+\tdata = (1 << 0) | (1 << 4);\n+\terror = fm10k_sbus_write(sb, addr, FM10K_SERDES_SPICO_REG_0X07, data);\n+\tfm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tdata = (1 << 18) | (1 << 19);\n+\terror = fm10k_sbus_write(sb, addr, FM10K_SERDES_SPICO_REG_0X0B, data);\n+\tfm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tdata = (1 << 4);\n+\terror = fm10k_sbus_write(sb, addr, FM10K_SERDES_SPICO_REG_0X07, data);\n+\tfm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tdata = (1 << 1);\n+\terror = fm10k_sbus_write(sb, addr, FM10K_SERDES_SPICO_REG_0X07, data);\n+\tfm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_sbus_write(sb, addr, FM10K_SERDES_SPICO_REG_0X08, 0);\n+\tfm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US);\n+\tif (error)\n+\t\tgoto done;\n+\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_epl_serdes_get_version_build_id(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, uint32_t *version_build_id)\n+{\n+\tint error;\n+\tuint32_t data;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: getting code \"\n+\t    \"version\", sw->epl_sbus->name, serdes);\n+\n+\terror = fm10k_epl_serdes_spico_int(sw, serdes, 0x00, 0, &data);\n+\tif (error)\n+\t\tgoto done;\n+\n+\t*version_build_id = data << 16;\n+\terror = fm10k_epl_serdes_spico_int(sw, serdes, 0x3f, 0, &data);\n+\tif (error)\n+\t\tgoto done;\n+\n+\t*version_build_id |= data & 0xffff;\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_sbm_spico_int(struct fm10k_sbus *sb,\n+\t\tuint8_t int_num, uint32_t param, uint32_t *result)\n+{\n+\tuint64_t start_time_us, elapsed_time_ms;\n+\tuint32_t data;\n+\tint error;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: SBM interrupt 0x%02x \"\n+\t    \"(param=0x%08x)\", sb->name, int_num, param);\n+\n+\t/* int write */\n+\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X02,\n+\t\t\t(param << 16) | int_num);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_sbus_read(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X07, &data);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tdata |= (1 << 0);\n+\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X07, data);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tdata &= ~(1 << 0);\n+\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\tFM10K_SERDES_SPICO_REG_0X07, data);\n+\tif (error)\n+\t\tgoto done;\n+\n+\t/* int read */\n+\tstart_time_us = fm10k_uptime_us();\n+\telapsed_time_ms = 0;\n+\twhile (elapsed_time_ms < FM10K_SW_SBM_INTERRUPT_TIMEOUT_MS) {\n+\t\telapsed_time_ms = (fm10k_uptime_us() - start_time_us) / 1000;\n+\t\terror = fm10k_sbus_read(sb,\n+\t\t\t\tFM10K_SW_SBUS_ADDR_SPICO,\n+\t\t\t\tFM10K_SERDES_SPICO_REG_0X08, &data);\n+\t\tif (error)\n+\t\t\tgoto done;\n+\n+\t\tif ((data & 0x8000) || ((data & 0x3ff) == 0)) {\n+\t\t\tif (elapsed_time_ms > 5)\n+\t\t\t\tfm10k_udelay(5);\n+\t\t} else {\n+\t\t\tFM10K_SW_TRACE(\"sbus %s: SBM \"\n+\t\t\t    \"interrupt 0x%02x (param=0x%08x, result=0x%08x)\",\n+\t\t\t    sb->name, int_num, param, data);\n+\t\t\t*result = data;\n+\t\t\tgoto done;\n+\t\t}\n+\t}\n+\terror = -1;\n+\tFM10K_SW_INFO(\"sbus %s: SBM interrupt timed out after %u \"\n+\t    \"ms\", sb->name, (uint32_t)elapsed_time_ms);\n+\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_epl_serdes_spico_int(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, uint16_t int_num,\n+\t\tuint32_t param, uint32_t *result)\n+{\n+\tstruct fm10k_sbus *sb = sw->epl_sbus;\n+\tuint64_t start_time_us, elapsed_time_ms;\n+\tunsigned int sbus_addr;\n+\tint error;\n+\tuint32_t data, intr;\n+\n+\tsbus_addr = FM10K_SW_SBUS_ADDR_EPL_SERDES(serdes);\n+\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: (sbus addr 0x%02x) \"\n+\t    \"interrupt 0x%04x (param=0x%08x)\", sb->name, serdes, sbus_addr,\n+\t    int_num, param);\n+\n+\t/* int write */\n+\tstart_time_us = fm10k_uptime_us();\n+\telapsed_time_ms = 0;\n+\twhile (elapsed_time_ms < FM10K_SW_SERDES_INTERRUPT_TIMEOUT_MS) {\n+\t\telapsed_time_ms = (fm10k_uptime_us() - start_time_us) / 1000;\n+\t\terror = fm10k_sbus_read(sb, sbus_addr, 0x04, &data);\n+\t\tif (error)\n+\t\t\tgoto done;\n+\n+\t\tif (data & ((1 << 16) | (1 << 17))) {\n+\t\t\tif (elapsed_time_ms > 5)\n+\t\t\t\tfm10k_udelay(5);\n+\t\t} else {\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tif (elapsed_time_ms >= FM10K_SW_SERDES_INTERRUPT_TIMEOUT_MS) {\n+\t\terror = fm10k_sbus_read(sb, sbus_addr, 0x03, &intr);\n+\t\tFM10K_SW_INFO(\"sbus %s: serdes %u: interrupt timed out \"\n+\t\t    \"after %u ms (intr=0x%04x param=0x%04x error=%u \"\n+\t\t    \"reg[4]=0x%08x)\", sb->name, serdes,\n+\t\t    (uint32_t)elapsed_time_ms, intr >> 16, intr & 0xffff, error,\n+\t\t    data);\n+\t\terror = -1;\n+\t\tgoto done;\n+\t} else {\n+\t\terror = fm10k_sbus_write(sb, sbus_addr,\n+\t\t\t\tFM10K_SERDES_SPICO_REG_0X03,\n+\t\t\t\t((uint32_t)int_num << 16) | param);\n+\t\tif (error)\n+\t\t\tgoto done;\n+\t}\n+\n+\t/* int read */\n+\tstart_time_us = fm10k_uptime_us();\n+\telapsed_time_ms = 0;\n+\twhile (elapsed_time_ms < FM10K_SW_SERDES_INTERRUPT_TIMEOUT_MS) {\n+\t\telapsed_time_ms = (fm10k_uptime_us() - start_time_us) / 1000;\n+\t\terror = fm10k_sbus_read(sb, sbus_addr, 0x04, &data);\n+\t\tif (error)\n+\t\t\tgoto done;\n+\n+\t\tif (data & ((1 << 16) | (1 << 17))) {\n+\t\t\tif (elapsed_time_ms > 5)\n+\t\t\t\tfm10k_udelay(5);\n+\t\t} else {\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tif (elapsed_time_ms >= FM10K_SW_SERDES_INTERRUPT_TIMEOUT_MS) {\n+\t\terror = fm10k_sbus_read(sb, sbus_addr, 0x03, &intr);\n+\t\tFM10K_SW_INFO(\"sbus %s: serdes %u: interrupt timed out \"\n+\t\t    \"(2) after %u ms (intr=0x%04x param=0x%04x error=%u \"\n+\t\t    \"reg[4]=0x%08x)\", sb->name, serdes,\n+\t\t    (uint32_t)elapsed_time_ms, intr >> 16, intr & 0xffff, error,\n+\t\t    data);\n+\t\terror = -1;\n+\t\tgoto done;\n+\t} else {\n+\t\tFM10K_SW_TRACE(\"sbus %s: serdes %u: interrupt \"\n+\t\t    \"0x%04x (param=0x%08x, result=0x%08x)\", sb->name, serdes,\n+\t\t    int_num, param, data);\n+\t\tif (result)\n+\t\t\t*result = data;\n+\t}\n+\n+done:\n+\treturn (error);\n+}\n+\n+\n+int\n+fm10k_epl_serdes_start_bringup(struct fm10k_ext_port_lane *lane)\n+{\n+\tstruct fm10k_switch *sw = lane->port->ports->sw;\n+\tunsigned int serdes = lane->abs_laneno;\n+\tunsigned int speed = lane->port->lane_speed;\n+\tunsigned int divider, width_mode;\n+\tint error = 0;\n+\tuint32_t data;\n+\n+\t/*\n+\t * Bit rate and width\n+\t */\n+\tif (speed == 25) {\n+\t\t/* 25G */\n+\t\tdivider = FM10K_SW_SERDES_DIVIDER_ETHMODE_25G;\n+\t\twidth_mode = FM10K_SW_SERDES_WIDTH_40;\n+\t} else {\n+\t\t/* 10G */\n+\t\tdivider = FM10K_SW_SERDES_DIVIDER_ETHMODE_10G;\n+\t\twidth_mode = FM10K_SW_SERDES_WIDTH_20;\n+\t}\n+\n+\t/*\n+\t * state = CONFIGURED\n+\t */\n+\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: configuring\",\n+\t\t\tsw->epl_sbus->name, serdes);\n+\n+\terror = fm10k_epl_serdes_spico_reset(sw, serdes);\n+\tfm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_epl_serdes_spico_do_crc(sw, serdes);\n+\tfm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tfm10k_udelay(FM10K_SW_SERDES_CONFIG_DELAY_US);\n+\terror = fm10k_epl_serdes_set_bit_rate(sw, serdes, divider);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tfm10k_epl_serdes_set_pcsl_width_mode(sw, serdes,\n+\t    width_mode);\n+\n+\t/*\n+\t * Data select\n+\t */\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: setting TX data select\",\n+\t    sw->epl_sbus->name, serdes);\n+\terror = fm10k_epl_serdes_spico_int02_retry(sw, serdes, 0x1ff,\n+\t    FM10K_SW_SERDES_INT02_TIMEOUT_MS);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_epl_serdes_dma_reg_write(sw, serdes, 0x21, 0x0c00);\n+\tif (error)\n+\t\tgoto done;\n+\n+\t/*\n+\t * Configure TX equalization\n+\t *\n+\t * Use defaults - copper and optical are the same.\n+\t *\n+\t * DEFAULTS| precursor | cursor | postcursor |\n+\t * --------+-----------+--------+------------+\n+\t *  copper |     0     |    0   |     15     |\n+\t * --------+-----------+--------+------------+\n+\t *  optical|     0     |    0   |     15     |\n+\t * --------+-----------+--------+------------+\n+\t */\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: setting TX cursors\",\n+\t    sw->epl_sbus->name, serdes);\n+\terror = fm10k_epl_serdes_set_tx_eq(sw, serdes,\n+\t    FM10K_SW_SERDES_EQ_SEL_ATTEN, 0);\n+\tif (error)\n+\t\tgoto done;\n+\terror = fm10k_epl_serdes_set_tx_eq(sw, serdes,\n+\t    FM10K_SW_SERDES_EQ_SEL_PRECUR, 0);\n+\tif (error)\n+\t\tgoto done;\n+\terror = fm10k_epl_serdes_set_tx_eq(sw, serdes,\n+\t    FM10K_SW_SERDES_EQ_SEL_POSTCUR, 15);\n+\tif (error)\n+\t\tgoto done;\n+\n+\t/*\n+\t * Configure 'options', which means:\n+\t *   - PLL calibration mode\n+\t *   - Phase slip\n+\t *   - RX termination\n+\t */\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: setting PLL calibration mode\",\n+\t    sw->epl_sbus->name, serdes);\n+\t/* enable PLL calibration */\n+\tdata = (1 << 0) | (1 << 1);\n+\terror =\n+\t    fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x11, data);\n+\tif (error)\n+\t\tgoto done;\n+\t/* There appears to be no action to take for phase slip */\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: configuring RX termination\",\n+\t    sw->epl_sbus->name, serdes);\n+\t/* RX termination appears to default to AVDD */\n+\tdata = (1 << 0);\n+\terror =\n+\t    fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x2b, data);\n+\tif (error)\n+\t\tgoto done;\n+\n+\t/*\n+\t * Set TX and RX lane polarity.\n+\t * Assuming no inversion required.\n+\t */\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: configuring TX/RX lane polarity\",\n+\t    sw->epl_sbus->name, serdes);\n+\tdata = 0x0300;\n+\terror = fm10k_epl_serdes_spico_int(sw, serdes, 0x13, data, NULL);\n+\tif (error)\n+\t\tgoto done;\n+\n+\t/*\n+\t * Force local fault\n+\t */\n+\tfm10k_epl_serdes_set_signal_detect(lane,\n+\t\t\tFM10K_SW_LANE_OVERRIDE_FORCE_BAD);\n+\n+\t/*\n+\t * Enable TX/RX\n+\t */\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: enabling TX/RX\",\n+\t    sw->epl_sbus->name, serdes);\n+\tfm10k_epl_serdes_set_signal_detect(lane,\n+\t\t\tFM10K_SW_LANE_OVERRIDE_FORCE_BAD);\n+\terror =\n+\t    fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x01, 0x03);\n+\tif (error)\n+\t\tgoto done;\n+\n+\t/*\n+\t * Clear and enable interrupts\n+\t */\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: configuring interrupts\",\n+\t    sw->epl_sbus->name, serdes);\n+\terror = fm10k_sbus_write(sw->epl_sbus,\n+\t\t\tFM10K_SW_SBUS_ADDR_EPL_SERDES(serdes),\n+\t\t\tFM10K_SERDES_SPICO_REG_0X08, 0);\n+\tif (error)\n+\t\tgoto done;\n+\n+done:\n+\treturn (error);\n+}\n+\n+int\n+fm10k_epl_serdes_continue_bringup(struct fm10k_ext_port_lane *lane)\n+{\n+\tstruct fm10k_switch *sw = lane->port->ports->sw;\n+\tunsigned int serdes = lane->abs_laneno;\n+\tunsigned int speed = lane->port->lane_speed;\n+\tunsigned int width_mode;\n+\tint error = 0;\n+\tint near_loopback = sw->serdes_loopback;\n+\n+\tif (speed == 25) {\n+\t\t/* 25G */\n+\t\twidth_mode = FM10K_SW_SERDES_WIDTH_40;\n+\t} else {\n+\t\t/* 10G */\n+\t\twidth_mode = FM10K_SW_SERDES_WIDTH_20;\n+\t}\n+\n+\tfm10k_udelay(FM10K_SW_SERDES_CONFIG_DELAY_US);\n+\terror = fm10k_epl_serdes_set_pcsl_bit_slip(sw, serdes);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tfm10k_udelay(FM10K_SW_SERDES_CONFIG_DELAY_US);\n+\terror = fm10k_epl_serdes_set_width_mode(sw, serdes, width_mode);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: enabling TX output\",\n+\t    sw->epl_sbus->name, serdes);\n+\tfm10k_udelay(FM10K_SW_SERDES_CONFIG_DELAY_US);\n+\terror =\n+\t    fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x01, 0x07);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tfm10k_udelay(FM10K_SW_SERDES_CONFIG_DELAY_US);\n+\terror = fm10k_epl_serdes_init_signal_ok(sw, serdes, 0);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tif (near_loopback) {\n+\t\t/* enable near loopback */\n+\t\terror = fm10k_epl_serdes_configure_near_loopback(lane);\n+\t\tif (error)\n+\t\t\tgoto done;\n+\t}\n+\n+done:\n+\treturn (error);\n+}\n+\n+int\n+fm10k_epl_serdes_disable(struct fm10k_ext_port_lane *lane)\n+{\n+\tstruct fm10k_switch *sw = lane->port->ports->sw;\n+\tunsigned int serdes = lane->abs_laneno;\n+\tint error = 0;\n+\n+\tfm10k_epl_serdes_set_signal_detect(lane,\n+\t\t\tFM10K_SW_LANE_OVERRIDE_FORCE_BAD);\n+\n+\t/* is this delay necessary? in some places the IES SDK does this */\n+\tfm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US);\n+\terror = fm10k_epl_serdes_spico_reset(sw, serdes);\n+\tfm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US);\n+\tif (error)\n+\t\tgoto done;\n+\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_epl_serdes_set_bit_rate(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, unsigned int divider)\n+{\n+\tint error;\n+\tuint32_t data;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: setting bit rate\",\n+\t    sw->epl_sbus->name, serdes);\n+\n+\tdata = divider & 0x7ff;\n+\tdata |= (1 << 12);\n+\tdata |= (1 << 15);\n+\n+\terror = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x05, data);\n+\tif (error)\n+\t\tgoto done;\n+\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_epl_serdes_set_width_mode(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, unsigned int width_mode)\n+{\n+\tint error;\n+\tuint32_t data;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: setting width mode to %u\",\n+\t    sw->epl_sbus->name, serdes, width_mode);\n+\n+\tdata = FM10K_SW_SERDES_WIDTH_20 | (FM10K_SW_SERDES_WIDTH_20 << 4);\n+\tfm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US);\n+\terror = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x14, data);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tdata = width_mode | (width_mode << 4);\n+\tfm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US);\n+\terror = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x14, data);\n+\tif (error)\n+\t\tgoto done;\n+\n+done:\n+\tfm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US);\n+\treturn error;\n+}\n+\n+static int\n+fm10k_epl_serdes_set_tx_eq(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, unsigned int which, unsigned int tx_eq)\n+{\n+\tint error;\n+\tuint32_t data;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: setting TX cursor %u to %u\",\n+\t    sw->epl_sbus->name, serdes, which, tx_eq);\n+\n+\tdata = (tx_eq & 0xff) | (which << 14);\n+\terror = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x15, data);\n+\tif (error)\n+\t\tgoto done;\n+\n+done:\n+\treturn error;\n+}\n+\n+void\n+fm10k_epl_serdes_set_signal_detect(struct fm10k_ext_port_lane *lane,\n+\t\tunsigned int override)\n+{\n+\tstruct fm10k_switch *sw = lane->port->ports->sw;\n+\tunsigned int eplno = lane->port->eplno;\n+\tuint32_t data;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: setting signal detect to %s\",\n+\t    sw->epl_sbus->name, lane->abs_laneno,\n+\t    (override == 0) ? \"NORMAL\" :\n+\t    (override == 1) ? \"FORCE_GOOD\" :\n+\t    (override == 2) ? \"FORCE_BAD\" : \"<unknown>\");\n+\n+\tFM10K_SW_SWITCH_LOCK(sw);\n+\tdata = fm10k_read_switch_reg(sw,\n+\t    FM10K_SW_LANE_SIGNAL_DETECT_CFG(eplno, lane->rel_laneno));\n+\tFM10K_SW_REPLACE_REG_FIELD(data,\n+\t    LANE_SIGNAL_DETECT_CFG_SD_OVERRIDE,\n+\t    override, data);\n+\tfm10k_write_switch_reg(sw,\n+\t    FM10K_SW_LANE_SIGNAL_DETECT_CFG(eplno, lane->rel_laneno), data);\n+\tFM10K_SW_SWITCH_UNLOCK(sw);\n+}\n+\n+static void\n+fm10k_epl_serdes_set_pcsl_width_mode(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, unsigned int width_mode)\n+{\n+\tunsigned int eplno, lane;\n+\tuint32_t pcsl_cfg;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: setting pcsl width mode\",\n+\t    sw->epl_sbus->name, serdes);\n+\n+\tfm10k_epl_serdes_eplno_lane(sw, serdes, &eplno, &lane);\n+\n+\tFM10K_SW_SWITCH_LOCK(sw);\n+\tpcsl_cfg = fm10k_read_switch_reg(sw, FM10K_SW_PCSL_CFG(eplno, lane));\n+\tif (width_mode == FM10K_SW_SERDES_WIDTH_40) {\n+\t\tpcsl_cfg &= ~FM10K_SW_PCSL_CFG_RX_GB_NARROW;\n+\t\tpcsl_cfg &= ~FM10K_SW_PCSL_CFG_TX_GB_NARROW;\n+\t} else {\n+\t\tpcsl_cfg |= FM10K_SW_PCSL_CFG_RX_GB_NARROW;\n+\t\tpcsl_cfg |= FM10K_SW_PCSL_CFG_TX_GB_NARROW;\n+\t}\n+\tpcsl_cfg &= ~FM10K_SW_PCSL_CFG_RX_BIT_SLIP_ENABLE;\n+\tfm10k_write_switch_reg(sw, FM10K_SW_PCSL_CFG(eplno, lane), pcsl_cfg);\n+\tFM10K_SW_SWITCH_UNLOCK(sw);\n+}\n+\n+static int\n+fm10k_epl_serdes_set_pcsl_bit_slip(struct fm10k_switch *sw,\n+\t\tunsigned int serdes)\n+{\n+\tunsigned int eplno, lane;\n+\tint error;\n+\tuint32_t int_return, pcsl_cfg;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: setting pcsl bit slip\",\n+\t    sw->epl_sbus->name, serdes);\n+\n+\tfm10k_epl_serdes_eplno_lane(sw, serdes, &eplno, &lane);\n+\terror =\n+\t    fm10k_epl_serdes_spico_int(sw, serdes, 0x0c, (1 << 7), &int_return);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tFM10K_SW_SWITCH_LOCK(sw);\n+\tpcsl_cfg = fm10k_read_switch_reg(sw, FM10K_SW_PCSL_CFG(eplno, lane));\n+\tpcsl_cfg |= FM10K_SW_PCSL_CFG_RX_BIT_SLIP_ENABLE;\n+\tif (int_return & 0x1)\n+\t\tpcsl_cfg |= FM10K_SW_PCSL_CFG_RX_BIT_SLIP_INITIAL;\n+\tfm10k_write_switch_reg(sw, FM10K_SW_PCSL_CFG(eplno, lane), pcsl_cfg);\n+\tFM10K_SW_SWITCH_UNLOCK(sw);\n+\n+\terror = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x0c, (1 << 8));\n+\tif (error)\n+\t\tgoto done;\n+\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_epl_serdes_init_signal_ok(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, unsigned int threshold)\n+{\n+\tint error;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: setting signal OK threshold to %u\",\n+\t    sw->epl_sbus->name, serdes, threshold);\n+\n+\terror =\n+\t    fm10k_epl_serdes_spico_int(sw, serdes, 0x20, 0x20, NULL);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_epl_serdes_dma_esb_read_modify_write(sw, serdes, 0x080,\n+\t    (threshold & 0xf) << 2, 0x3c, NULL);\n+\tif (error)\n+\t\tgoto done;\n+\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_epl_serdes_spico_int02_retry(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, uint32_t data, unsigned int timeout_ms)\n+{\n+\tuint64_t start_time_us, elapsed_time_ms;\n+\tuint32_t result;\n+\tint error;\n+\n+\tstart_time_us = fm10k_uptime_us();\n+\telapsed_time_ms = 0;\n+\twhile (elapsed_time_ms < timeout_ms) {\n+\t\telapsed_time_ms = (fm10k_uptime_us() - start_time_us) / 1000;\n+\t\terror =\n+\t\t    fm10k_epl_serdes_spico_int(sw, serdes, 0x02, data, &result);\n+\t\tif (result == 0x02) {\n+\t\t\terror = 0;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tfm10k_udelay(FM10K_SW_SERDES_CONFIG_DELAY_US);\n+\t}\n+\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_epl_serdes_dma_reg_write(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, unsigned int addr, uint32_t data)\n+{\n+\tint error;\n+\n+\terror = fm10k_epl_serdes_spico_int(sw, serdes, 0x18,\n+\t    0x8000 | (addr & 0xff), NULL);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_epl_serdes_spico_int(sw, serdes, 0x19, data, NULL);\n+\tif (error)\n+\t\tgoto done;\n+\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_epl_serdes_dma_esb_read(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, unsigned int addr, uint32_t *result)\n+{\n+\tint error;\n+\n+\terror = fm10k_epl_serdes_spico_int(sw, serdes, 0x18,\n+\t    0x4000 | (addr & 0x3fff), result);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_epl_serdes_spico_int(sw, serdes, 0x1a, 0x00, result);\n+\tif (error)\n+\t\tgoto done;\n+\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_epl_serdes_dma_esb_write(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, unsigned int addr, uint32_t data)\n+{\n+\tint error;\n+\n+\terror = fm10k_epl_serdes_spico_int(sw, serdes, 0x18,\n+\t    0x4000 | (addr & 0x3fff), NULL);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_epl_serdes_spico_int(sw, serdes, 0x19, data, NULL);\n+\tif (error)\n+\t\tgoto done;\n+\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_epl_serdes_dma_esb_read_modify_write(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, unsigned int addr,\n+\t\tuint32_t data, uint32_t mask, uint32_t *result)\n+{\n+\tint error;\n+\tuint32_t read_data;\n+\n+\terror = fm10k_epl_serdes_dma_esb_read(sw, serdes, addr, &read_data);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_epl_serdes_dma_esb_write(sw, serdes, addr,\n+\t    (data & mask) | (read_data & ~mask));\n+\tif (error)\n+\t\tgoto done;\n+\tif (result)\n+\t\t*result = (data & mask) | (read_data & ~mask);\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_epl_serdes_spico_wr_only_int(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, unsigned int int_num, uint32_t param)\n+{\n+\tint error;\n+\tuint32_t result;\n+\n+\terror = fm10k_epl_serdes_spico_int(sw, serdes, int_num, param, &result);\n+\tif (error)\n+\t\tgoto done;\n+\tif (result != int_num) {\n+\t\terror = -1;\n+\t\tgoto done;\n+\t}\n+done:\n+\treturn (error);\n+}\n+\n+static void\n+fm10k_epl_serdes_eplno_lane(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, unsigned int *eplno, unsigned int *lane)\n+{\n+\tif (sw) {\n+\t\t*eplno = serdes / FM10K_SW_EPL_LANES;\n+\t\t*lane = serdes % FM10K_SW_EPL_LANES;\n+\t}\n+}\n+\n+static int\n+fm10k_epl_serdes_configure_near_loopback(struct fm10k_ext_port_lane *lane)\n+{\n+\tstruct fm10k_switch *sw = lane->port->ports->sw;\n+\tunsigned int serdes = lane->abs_laneno;\n+\tuint32_t data;\n+\tint error;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: configuring near loopback\",\n+\t    sw->epl_sbus->name, serdes);\n+\n+\t/* assuming no lane polarity has been set */\n+\t/* set near loopback mode */\n+\tfm10k_udelay(FM10K_SW_SERDES_CONFIG_DELAY_US);\n+\tdata = (1 << 8) | (1 << 0);\n+\terror = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x08, data);\n+\tif (error)\n+\t\tgoto done;\n+\n+\t/* disable tx output, leave tx/ex enabled */\n+\tfm10k_udelay(FM10K_SW_SERDES_CONFIG_DELAY_US);\n+\terror =\n+\t    fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x01, 0x03);\n+\tif (error)\n+\t\tgoto done;\n+\n+\t/* set signal detect override to normal */\n+\tfm10k_epl_serdes_set_signal_detect(lane, FM10K_SW_LANE_OVERRIDE_NORMAL);\n+\n+done:\n+\treturn (error);\n+}\n+\n+int\n+fm10k_epl_serdes_configure_for_dfe_tuning(struct fm10k_ext_port_lane *lane)\n+{\n+\tstruct fm10k_switch *sw = lane->port->ports->sw;\n+\tunsigned int serdes = lane->abs_laneno;\n+\tint error;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: configuring serdes for dfe tuning\",\n+\t    sw->epl_sbus->name, serdes);\n+\n+\t/*\n+\t * Configure the serdes to run DFE tuning\n+\t */\n+\n+\terror = fm10k_epl_serdes_spico_int(sw, serdes, 0x26,\n+\t    ((2 << 12) | (0 << 8) | (FM10K_SW_SERDES_DFE_DEFAULT_HF & 0xff)),\n+\t    NULL);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_epl_serdes_spico_int(sw, serdes, 0x26,\n+\t    ((2 << 12) | (1 << 8) | (FM10K_SW_SERDES_DFE_DEFAULT_LF & 0xff)),\n+\t    NULL);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_epl_serdes_spico_int(sw, serdes, 0x26,\n+\t    ((2 << 12) | (2 << 8) | (FM10K_SW_SERDES_DFE_DEFAULT_DC & 0xff)),\n+\t    NULL);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_epl_serdes_spico_int(sw, serdes, 0x26,\n+\t    ((2 << 12) | (3 << 8) | (FM10K_SW_SERDES_DFE_DEFAULT_BW & 0xff)),\n+\t    NULL);\n+\tif (error)\n+\t\tgoto done;\n+\n+\t/* allow early link up */\n+\terror = fm10k_epl_serdes_spico_int(sw, serdes, 0x26, 0x5b01, NULL);\n+\tif (error)\n+\t\tgoto done;\n+\n+done:\n+\treturn (error);\n+}\n+\n+int\n+fm10k_epl_serdes_start_dfe_ical(struct fm10k_ext_port_lane *lane)\n+{\n+\tstruct fm10k_switch *sw = lane->port->ports->sw;\n+\tunsigned int serdes = lane->abs_laneno;\n+\tunsigned int speed = lane->port->lane_speed;\n+\tint error;\n+\tuint32_t param;\n+\n+\t/*\n+\t * Start DFE tuning initial calibration (ical)\n+\t */\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: starting dfe ical\",\n+\t    sw->epl_sbus->name, serdes);\n+\n+\tif (speed == 25)\n+\t\tparam = FM10K_SW_LINK_OPT_PARAM_A25G;\n+\telse\n+\t\tparam = FM10K_SW_LINK_OPT_PARAM_A10G;\n+\n+\tif ((sw->epl_serdes_code_version_build_id >> 16) > 0x1055)\n+\t\terror = fm10k_epl_serdes_config_dfe_param(sw, serdes, param);\n+\n+\terror = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x0a, 0x01);\n+\tif (error)\n+\t\tgoto done;\n+\n+done:\n+\treturn (error);\n+}\n+\n+int\n+fm10k_epl_serdes_dfe_ical_status(struct fm10k_ext_port_lane *lane,\n+\t\tuint32_t *status)\n+{\n+\tstruct fm10k_switch *sw = lane->port->ports->sw;\n+\tunsigned int serdes = lane->abs_laneno;\n+\tint error;\n+\tuint32_t dfe_status, converged;\n+\n+\terror = fm10k_epl_serdes_get_dfe_status(sw, serdes, &dfe_status);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tif ((dfe_status & 0x11) == 0x11) {\n+\t\t*status = FM10K_SW_SERDES_DFE_ICAL_IN_PROGRESS;\n+\t} else {\n+\t\terror = fm10k_epl_serdes_get_ical_result(sw,\n+\t\t\t\tserdes, &converged);\n+\t\tif (error)\n+\t\t\tgoto done;\n+\t\tif (converged)\n+\t\t\t*status = FM10K_SW_SERDES_DFE_ICAL_CONVERGED;\n+\t\telse\n+\t\t\t*status = FM10K_SW_SERDES_DFE_ICAL_FAILED;\n+\t}\n+\n+done:\n+\treturn (error);\n+}\n+\n+int\n+fm10k_epl_serdes_start_dfe_pcal(struct fm10k_ext_port_lane *lane)\n+{\n+\tstruct fm10k_switch *sw = lane->port->ports->sw;\n+\tunsigned int serdes = lane->abs_laneno;\n+\tunsigned int speed = lane->port->lane_speed;\n+\tint error;\n+\tuint32_t param;\n+\n+\t/*\n+\t * Start DFE tuning periodic calibration (pcal), just one\n+\t */\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: starting dfe pcal\",\n+\t    sw->epl_sbus->name, serdes);\n+\tif (speed == 25)\n+\t\tparam = FM10K_SW_LINK_OPT_PARAM_B25G;\n+\telse\n+\t\tparam = FM10K_SW_LINK_OPT_PARAM_B10G;\n+\n+\tif ((sw->epl_serdes_code_version_build_id >> 16) > 0x1055)\n+\t\terror = fm10k_epl_serdes_config_dfe_param(sw, serdes, param);\n+\n+\terror = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x0a, 0x02);\n+\tif (error)\n+\t\tgoto done;\n+\n+done:\n+\treturn (error);\n+}\n+\n+int\n+fm10k_epl_serdes_dfe_pcal_status(struct fm10k_ext_port_lane *lane,\n+\t\tuint32_t *status)\n+{\n+\tstruct fm10k_switch *sw = lane->port->ports->sw;\n+\tunsigned int serdes = lane->abs_laneno;\n+\tint error;\n+\tuint32_t dfe_status;\n+\n+\terror = fm10k_epl_serdes_get_dfe_status(sw, serdes, &dfe_status);\n+\tif (error)\n+\t\tgoto done;\n+\tif (dfe_status & 0x02)\n+\t\t*status = FM10K_SW_SERDES_DFE_PCAL_COMPLETE;\n+\telse\n+\t\t*status = FM10K_SW_SERDES_DFE_PCAL_IN_PROGRESS;\n+\n+done:\n+\treturn (error);\n+}\n+\n+int\n+fm10k_epl_serdes_stop_dfe_tuning(struct fm10k_ext_port_lane *lane,\n+\t\tunsigned int force_reset)\n+{\n+\tstruct fm10k_switch *sw = lane->port->ports->sw;\n+\tunsigned int serdes = lane->abs_laneno;\n+\tint error;\n+\tunsigned int ical_stopped, pcal_stopped;\n+\tunsigned int i;\n+\tuint32_t dfe_status, status;\n+\n+\terror = fm10k_epl_serdes_get_dfe_status(sw, serdes, &dfe_status);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tical_stopped = 0;\n+\tpcal_stopped = 0;\n+\n+\tif (!force_reset) {\n+\t\tif (dfe_status & 0x3) {\n+\t\t\t/* stop all DFE tuning */\n+\t\t\terror = fm10k_epl_serdes_spico_wr_only_int(sw, serdes,\n+\t\t\t    0x0a, 0);\n+\t\t\tif (error)\n+\t\t\t\tgoto done;\n+\n+\t\t\tfor (i = 0;\n+\t\t\t     i < FM10K_SW_SERDES_ICAL_STOP_MAX_CYCLES;\n+\t\t\t     i++) {\n+\t\t\t\terror = fm10k_epl_serdes_dfe_ical_status(lane,\n+\t\t\t\t    &status);\n+\t\t\t\tif (error)\n+\t\t\t\t\tgoto done;\n+\t\t\t\tif (status !=\n+\t\t\t\t    FM10K_SW_SERDES_DFE_ICAL_IN_PROGRESS) {\n+\t\t\t\t\tical_stopped = 1;\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t\tfm10k_udelay\n+\t\t\t\t(FM10K_SW_SERDES_DFE_STOP_CYCLE_DELAY_US);\n+\t\t\t}\n+\n+\t\t\tif (ical_stopped)\n+\t\t\t\tfor (i = 0;\n+\t\t\t\t     i < FM10K_SW_SERDES_PCAL_STOP_MAX_CYCLES;\n+\t\t\t\t     i++) {\n+\t\t\t\t\terror =\n+\t\t\t\t\t\tfm10k_epl_serdes_dfe_pcal_status\n+\t\t\t\t\t\t(lane, &status);\n+\t\t\t\t\tif (error)\n+\t\t\t\t\t\tgoto done;\n+\t\t\t\t\tif (status !=\n+\t\t\t\t\tFM10K_SW_SERDES_DFE_PCAL_IN_PROGRESS) {\n+\t\t\t\t\t\tpcal_stopped = 0;\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t\t}\n+\t\t\t\t\tfm10k_udelay\n+\t\t\t\t(FM10K_SW_SERDES_DFE_STOP_CYCLE_DELAY_US);\n+\t\t\t\t}\n+\t\t}\n+\n+\t\tif (ical_stopped && pcal_stopped && (dfe_status & 0x40)) {\n+\t\t\terror = fm10k_epl_serdes_start_dfe_pcal(lane);\n+\t\t\tif (error)\n+\t\t\t\tgoto done;\n+\t\t\tpcal_stopped = 0;\n+\t\t\tfor (i = 0;\n+\t\t\t\ti < FM10K_SW_SERDES_PCAL_STOP_MAX_CYCLES; i++) {\n+\t\t\t\terror = fm10k_epl_serdes_dfe_pcal_status(lane,\n+\t\t\t\t    &status);\n+\t\t\t\tif (error)\n+\t\t\t\t\tgoto done;\n+\t\t\t\tif (status !=\n+\t\t\t\t    FM10K_SW_SERDES_DFE_PCAL_IN_PROGRESS) {\n+\t\t\t\t\tpcal_stopped = 1;\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t\tfm10k_udelay\n+\t\t\t\t(FM10K_SW_SERDES_DFE_STOP_CYCLE_DELAY_US);\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tif (!ical_stopped || !pcal_stopped) {\n+\t\terror = -1;\n+\t\tgoto done;\n+\t}\n+\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_epl_serdes_config_dfe_param(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, uint32_t param)\n+{\n+\tint error;\n+\n+\terror = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x18, 0x07);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x19,\n+\t    param & 0xffff);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x19,\n+\t    param >> 16);\n+\tif (error)\n+\t\tgoto done;\n+\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_epl_serdes_get_dfe_status(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, uint32_t *status)\n+{\n+\tint error;\n+\n+\terror = fm10k_epl_serdes_spico_int(sw, serdes, 0x126, (0x0b << 8),\n+\t    status);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: serdes %u: dfe status: \"\n+\t    \"coarse_active=%u fine_active=%u adaptive=%u\",\n+\t    sw->epl_sbus->name, serdes, *status & (1 << 0),\n+\t    *status & (1 << 1), *status & (1 << 6));\n+\n+done:\n+\treturn (error);\n+}\n+\n+static int\n+fm10k_epl_serdes_get_ical_result(struct fm10k_switch *sw,\n+\t\tunsigned int serdes, uint32_t *converged)\n+{\n+\tuint32_t val1;\n+\tuint32_t val2;\n+\tuint32_t diff;\n+\tint error;\n+\n+\t*converged = 0;\n+\n+\terror = fm10k_epl_serdes_spico_int(sw, serdes, 0x126,\n+\t    (4 << 12), &val1);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_epl_serdes_spico_int(sw, serdes, 0x126,\n+\t    (4 << 12) | (1 << 8), &val2);\n+\tif (error)\n+\t\tgoto done;\n+\n+\t/* sign extension */\n+\tif (val1 & 0x8000)\n+\t\tval1 |= 0xffff0000;\n+\tif (val2 & 0x8000)\n+\t\tval2 |= 0xffff0000;\n+\tdiff = abs(val2 - val1);\n+\n+\tif (diff >= FM10K_SW_SERDES_DFE_DATA_LEVEL0_THRESHOLD)\n+\t\t*converged = 1;\n+\n+done:\n+\treturn (error);\n+}\ndiff --git a/drivers/net/fm10k/switch/fm10k_serdes.h b/drivers/net/fm10k/switch/fm10k_serdes.h\nnew file mode 100644\nindex 0000000..f13ad3a\n--- /dev/null\n+++ b/drivers/net/fm10k/switch/fm10k_serdes.h\n@@ -0,0 +1,32 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019   Silicom Ltd. Connectivity Solutions\n+ */\n+\n+#ifndef _FM10K_SW_SERDES_H_\n+#define _FM10K_SW_SERDES_H_\n+\n+\n+#define FM10K_SW_SERDES_DFE_ICAL_IN_PROGRESS\t\t0\n+#define FM10K_SW_SERDES_DFE_ICAL_CONVERGED\t\t1\n+#define FM10K_SW_SERDES_DFE_ICAL_FAILED\t\t\t2\n+#define FM10K_SW_SERDES_DFE_PCAL_IN_PROGRESS\t\t0\n+#define FM10K_SW_SERDES_DFE_PCAL_COMPLETE\t\t1\n+\n+\n+int fm10k_epl_serdes_reset_and_load_all(struct fm10k_switch *sw);\n+int fm10k_epl_serdes_start_bringup(struct fm10k_ext_port_lane *lane);\n+int fm10k_epl_serdes_continue_bringup(struct fm10k_ext_port_lane *lane);\n+int fm10k_epl_serdes_disable(struct fm10k_ext_port_lane *lane);\n+int fm10k_epl_serdes_configure_for_dfe_tuning(struct fm10k_ext_port_lane *lane);\n+int fm10k_epl_serdes_start_dfe_ical(struct fm10k_ext_port_lane *lane);\n+int fm10k_epl_serdes_dfe_ical_status\n+\t\t(struct fm10k_ext_port_lane *lane, uint32_t *status);\n+int fm10k_epl_serdes_start_dfe_pcal(struct fm10k_ext_port_lane *lane);\n+int fm10k_epl_serdes_dfe_pcal_status\n+\t\t(struct fm10k_ext_port_lane *lane, uint32_t *status);\n+int fm10k_epl_serdes_stop_dfe_tuning\n+\t\t(struct fm10k_ext_port_lane *lane, unsigned int force_reset);\n+void fm10k_epl_serdes_set_signal_detect\n+\t\t(struct fm10k_ext_port_lane *lane, unsigned int override);\n+\n+#endif /* _FM10K_SW_SERDES_H_ */\ndiff --git a/drivers/net/fm10k/switch/fm10k_sm.c b/drivers/net/fm10k/switch/fm10k_sm.c\nnew file mode 100644\nindex 0000000..26fe7dd\n--- /dev/null\n+++ b/drivers/net/fm10k/switch/fm10k_sm.c\n@@ -0,0 +1,190 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019   Silicom Ltd. Connectivity Solutions\n+ */\n+\n+#include <stdint.h>\n+#include <stdlib.h>\n+#include <rte_malloc.h>\n+\n+#include \"../base/fm10k_osdep.h\"\n+#include \"fm10k_debug.h\"\n+#include \"fm10k_sm.h\"\n+\n+static void *fm10k_sm_handle_event(void *ptr);\n+static void *fm10k_sm_handle_timer(void *ptr);\n+static void fm10k_sm_event_heap_init(struct fm10k_sm_event_heap *heap);\n+static uint16_t fm10k_sm_event_heap_pop(struct fm10k_sm_event_heap *heap);\n+static void fm10k_sm_event_heap_push\n+\t\t(struct fm10k_sm_event_heap *heap, uint16_t id);\n+\n+\n+struct fm10k_sm *\n+fm10k_sm_attach(uint16_t num_events,\n+\t\tuint16_t num_timers, fm10k_sm_process_event_t event_handler,\n+\t\tfm10k_sm_process_timer_t timer_handler, void *ctx)\n+{\n+\tstruct fm10k_sm *sm;\n+\tstruct fm10k_sm_timer *timer;\n+\tunsigned int i;\n+\n+\tsm = (struct fm10k_sm *)rte_zmalloc(\"fm10k_sm\",\n+\t\t\t\t\tsizeof(struct fm10k_sm), 0);\n+\tif (sm == NULL)\n+\t\tgoto fail;\n+\n+\tsm->is_running = true;\n+\tsm->num_events = num_events;\n+\tfm10k_sm_event_heap_init(&sm->events);\n+\tpthread_create(&sm->event_task, NULL, fm10k_sm_handle_event, sm);\n+\tsm->num_timers = num_timers;\n+\tif (sm->num_timers > 0) {\n+\t\tsm->timers = (struct fm10k_sm_timer *)rte_zmalloc\n+\t\t\t(\"fm10k_sm_timers\",\n+\t\t\tsizeof(struct fm10k_sm_timer) * sm->num_timers, 0);\n+\t\tif (sm->timers == NULL)\n+\t\t\tgoto fail;\n+\t}\n+\n+\tsm->event_handler = event_handler;\n+\tsm->timer_handler = timer_handler;\n+\tsm->ctx = ctx;\n+\n+\tfor (i = 0; i < sm->num_timers; i++) {\n+\t\ttimer = &sm->timers[i];\n+\t\tsem_init(&timer->tq, 0, 0);\n+\t\ttimer->sm = sm;\n+\t\tpthread_create(&timer->t, NULL, fm10k_sm_handle_timer, timer);\n+\t\ttimer->timer_id = i;\n+\t}\n+\n+\treturn sm;\n+\n+fail:\n+\tif (sm)\n+\t\tfm10k_sm_detach(sm);\n+\n+\treturn NULL;\n+}\n+\n+void\n+fm10k_sm_detach(struct fm10k_sm *sm)\n+{\n+\tint i;\n+\n+\tsm->is_running = false;\n+\tpthread_join(sm->event_task, NULL);\n+\tfor (i = 0; i < sm->num_timers; i++)\n+\t\tpthread_join(sm->timers[i].t, NULL);\n+\trte_free(sm);\n+}\n+\n+void\n+fm10k_sm_send_event(struct fm10k_sm *sm, uint16_t event_id)\n+{\n+\tfm10k_sm_event_heap_push(&sm->events, event_id);\n+}\n+\n+void\n+fm10k_sm_timer_start(struct fm10k_sm *sm, uint16_t timer_id,\n+\t\tunsigned int timeout_ms)\n+{\n+\tstruct fm10k_sm_timer *timer = &sm->timers[timer_id];\n+\n+\tgettimeofday(&timer->start, 0);\n+\ttimer->timeout_ms = timeout_ms;\n+\ttimer->running = 1;\n+\tsem_post(&timer->tq);\n+}\n+\n+/*\n+ * It is possible that an expiration events from this timer will\n+ * occur after this is called.\n+ */\n+void\n+fm10k_sm_timer_cancel(struct fm10k_sm *sm, uint16_t timer_id)\n+{\n+\tstruct fm10k_sm_timer *timer = &sm->timers[timer_id];\n+\ttimer->running = 0;\n+}\n+\n+static void *\n+fm10k_sm_handle_event(void *ctx)\n+{\n+\tstruct fm10k_sm *sm = ctx;\n+\tuint16_t event_id;\n+\n+\twhile (sm->is_running) {\n+\t\tevent_id = fm10k_sm_event_heap_pop(&sm->events);\n+\t\tsm->event_handler(sm, event_id);\n+\t}\n+\treturn NULL;\n+}\n+\n+static void *\n+fm10k_sm_handle_timer(void *ctx)\n+{\n+\tstruct fm10k_sm_timer *timer = ctx;\n+\tstruct fm10k_sm *sm = timer->sm;\n+\tstruct timeval now;\n+\tstruct timeval sleep;\n+\tuint64_t cost, timeout;\n+\n+\twhile (sm->is_running) {\n+\t\tsem_wait(&timer->tq);\n+\t\tif (timer->running)\t{\n+\t\t\tgettimeofday(&now, 0);\n+\t\t\tcost = (now.tv_sec - timer->start.tv_sec) * 1000000;\n+\t\t\tcost += (now.tv_usec - timer->start.tv_usec);\n+\t\t\tif (cost < timer->timeout_ms * 1000) {\n+\t\t\t\ttimeout = timer->timeout_ms * 1000;\n+\t\t\t\ttimeout -= cost;\n+\t\t\t\tsleep.tv_sec = timeout / 1000000;\n+\t\t\t\tsleep.tv_usec = timeout % 1000000;\n+\t\t\t\tselect(0, NULL, NULL, NULL, &sleep);\n+\t\t\t}\n+\t\t\tif (timer->running)\n+\t\t\t\tsm->timer_handler(sm, timer->timer_id);\n+\t\t}\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+\n+static void\n+fm10k_sm_event_heap_init(struct fm10k_sm_event_heap *heap)\n+{\n+\theap->count = 0;\n+\tpthread_mutex_init(&heap->lock, NULL);\n+\tsem_init(&heap->s, 0, 0);\n+}\n+\n+static uint16_t\n+fm10k_sm_event_heap_pop(struct fm10k_sm_event_heap *heap)\n+{\n+\tint i;\n+\tuint16_t id;\n+\n+\tsem_wait(&heap->s);\n+\tpthread_mutex_lock(&heap->lock);\n+\tid = heap->heap[0];\n+\tfor (i = 1; i < heap->count; i++)\n+\t\theap->heap[i - 1] = heap->heap[i];\n+\theap->count--;\n+\tpthread_mutex_unlock(&heap->lock);\n+\treturn id;\n+}\n+\n+static void\n+fm10k_sm_event_heap_push(struct fm10k_sm_event_heap *heap, uint16_t id)\n+{\n+\tpthread_mutex_lock(&heap->lock);\n+\tif (heap->count >= FM10K_SM_ID_HEAP_MAX) {\n+\t\tpthread_mutex_unlock(&heap->lock);\n+\t\treturn;\n+\t}\n+\theap->heap[heap->count] = id;\n+\theap->count++;\n+\tpthread_mutex_unlock(&heap->lock);\n+\tsem_post(&heap->s);\n+}\ndiff --git a/drivers/net/fm10k/switch/fm10k_sm.h b/drivers/net/fm10k/switch/fm10k_sm.h\nnew file mode 100644\nindex 0000000..8daadfa\n--- /dev/null\n+++ b/drivers/net/fm10k/switch/fm10k_sm.h\n@@ -0,0 +1,81 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019   Silicom Ltd. Connectivity Solutions\n+ */\n+\n+#ifndef _FM10K_SW_SM_H_\n+#define _FM10K_SW_SM_H_\n+\n+#include <stdint.h>\n+\n+#include <signal.h>\n+#include <sys/time.h>\n+#include <pthread.h>\n+#include <semaphore.h>\n+#include <stdbool.h>\n+\n+\n+/*\n+ * This framework provides state machine implementation support for use in\n+ * the rest of the driver.\n+ *\n+ * The model is that for a given state machine, there are N>0 events\n+ * identified by the integers [0..N-1] and there are M>=0 timers identified\n+ * by the integers [0..M-1].\n+ *\n+ * The timers are one-shot timers.\n+ *\n+ * Since all state machine processing occurs in the context of the\n+ * task queue, if that task queue was created with only a single thread, then\n+ * no locking is required in the provided event and timer handlers to\n+ * prevent overlapping execution.\n+ *\n+ */\n+\n+struct fm10k_sm;\n+\n+struct fm10k_sm_timer {\n+\tstruct fm10k_sm *sm;\n+\tpthread_t t;\n+\tsem_t tq;\n+\tstruct timeval start;\n+\tuint16_t timeout_ms;\n+\tuint16_t timer_id;\n+\tuint8_t running;\n+};\n+\n+typedef void (*fm10k_sm_process_event_t)(struct fm10k_sm *sm, uint16_t event);\n+typedef void (*fm10k_sm_process_timer_t)(struct fm10k_sm *sm, uint16_t timer);\n+\n+#define FM10K_SM_ID_HEAP_MAX\t128\n+struct fm10k_sm_event_heap {\n+\tpthread_mutex_t lock;\n+\tsem_t s;\n+\tuint16_t count;\n+\tuint16_t heap[FM10K_SM_ID_HEAP_MAX];\n+};\n+\n+struct fm10k_sm {\n+\tbool is_running;\n+\tpthread_t event_task;\n+\tstruct fm10k_sm_timer *timers;\n+\tstruct fm10k_sm_event_heap events;\n+\tfm10k_sm_process_event_t event_handler;\n+\tfm10k_sm_process_timer_t timer_handler;\n+\tvoid *ctx;\n+\tunsigned int state;\n+\tuint16_t num_events;\n+\tuint16_t num_timers;\n+\tuint8_t portno;\n+\tuint8_t laneno;\n+};\n+\n+struct fm10k_sm *fm10k_sm_attach(uint16_t num_events,\n+\t    uint16_t num_timers, fm10k_sm_process_event_t event_handler,\n+\t    fm10k_sm_process_timer_t timer_handler, void *ctx);\n+void fm10k_sm_detach(struct fm10k_sm *sm);\n+void fm10k_sm_send_event(struct fm10k_sm *sm, uint16_t event_id);\n+void fm10k_sm_timer_start(struct fm10k_sm *sm,\n+\t\tuint16_t timer_id, unsigned int timeout_ms);\n+void fm10k_sm_timer_cancel(struct fm10k_sm *sm, uint16_t timer_id);\n+\n+#endif /* _FM10K_SW_SM_H_ */\ndiff --git a/drivers/net/fm10k/switch/fm10k_spico_code.c b/drivers/net/fm10k/switch/fm10k_spico_code.c\nnew file mode 100644\nindex 0000000..cfab632\n--- /dev/null\n+++ b/drivers/net/fm10k/switch/fm10k_spico_code.c\n@@ -0,0 +1,2966 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019   Silicom Ltd. Connectivity Solutions\n+ */\n+\n+#include \"fm10k_spico_code.h\"\n+\n+\n+/* Production versions */\n+\n+\n+/* SBus master code (production version)\n+ *  source file:   release_2015_01_14/sbus_master.0x1013_0001.rom\n+ */\n+\n+const uint32_t fm10000_sbus_master_code_version_build_id_prd = 0x10130001;\n+const uint32_t fm10000_sbus_master_code_size_prd             = 3338;\n+\n+const uint16_t fm10000_sbus_master_code_prd[] = {\n+\t0x132, 0x002, 0x006, 0x000, 0x390, 0x002, 0x080, 0x247,\n+\t0x071, 0x247, 0x01f, 0x247, 0x020, 0x247, 0x02e, 0x247,\n+\t0x02f, 0x247, 0x03f, 0x247, 0x040, 0x247, 0x042, 0x247,\n+\t0x043, 0x247, 0x03d, 0x0c0, 0x02d, 0x247, 0x031, 0x247,\n+\t0x032, 0x081, 0x18b, 0x247, 0x039, 0x248, 0x03a, 0x181,\n+\t0x247, 0x034, 0x248, 0x036, 0x209, 0x247, 0x033, 0x248,\n+\t0x035, 0x305, 0x034, 0x247, 0x037, 0x248, 0x038, 0x190,\n+\t0x247, 0x03b, 0x248, 0x03c, 0x3d4, 0x1ff, 0x00c, 0x3d5,\n+\t0x100, 0x00c, 0x3d4, 0x2ff, 0x00c, 0x3c7, 0x0fe, 0x018,\n+\t0x0c2, 0x019, 0x044, 0x233, 0x000, 0x152, 0x01b, 0x347,\n+\t0x01b, 0x030, 0x085, 0x187, 0x247, 0x03e, 0x3c7, 0x100,\n+\t0x041, 0x080, 0x247, 0x065, 0x3c4, 0x3fc, 0x010, 0x3d4,\n+\t0x22f, 0x00e, 0x347, 0x033, 0x008, 0x247, 0x008, 0x081,\n+\t0x189, 0x227, 0x2c7, 0x044, 0x220, 0x2c7, 0x045, 0x220,\n+\t0x2c7, 0x046, 0x220, 0x2c7, 0x047, 0x220, 0x2c7, 0x048,\n+\t0x220, 0x2c7, 0x049, 0x220, 0x2c7, 0x04a, 0x220, 0x2c7,\n+\t0x04b, 0x3a7, 0x05b, 0x1a7, 0x3a5, 0x08d, 0x2c7, 0x04c,\n+\t0x0c0, 0x04d, 0x044, 0x07d, 0x001, 0x0df, 0x02c, 0x000,\n+\t0x009, 0x322, 0x02c, 0x009, 0x005, 0x347, 0x02d, 0x02c,\n+\t0x3d4, 0x3df, 0x00e, 0x307, 0x02c, 0x384, 0x01f, 0x229,\n+\t0x220, 0x3b0, 0x0aa, 0x287, 0x199, 0x390, 0x000, 0x041,\n+\t0x040, 0x045, 0x020, 0x12c, 0x000, 0x020, 0x163, 0x000,\n+\t0x020, 0x175, 0x000, 0x020, 0x27e, 0x000, 0x020, 0x362,\n+\t0x000, 0x020, 0x10a, 0x000, 0x020, 0x10a, 0x000, 0x020,\n+\t0x1de, 0x000, 0x020, 0x330, 0x001, 0x020, 0x270, 0x001,\n+\t0x020, 0x2af, 0x001, 0x020, 0x2a1, 0x001, 0x020, 0x338,\n+\t0x001, 0x020, 0x285, 0x001, 0x020, 0x2b9, 0x001, 0x020,\n+\t0x2a8, 0x001, 0x020, 0x001, 0x002, 0x020, 0x105, 0x001,\n+\t0x020, 0x19e, 0x001, 0x020, 0x3e6, 0x000, 0x020, 0x10a,\n+\t0x000, 0x020, 0x10a, 0x000, 0x020, 0x10a, 0x000, 0x020,\n+\t0x10a, 0x000, 0x020, 0x10a, 0x000, 0x020, 0x10a, 0x000,\n+\t0x020, 0x10a, 0x000, 0x020, 0x10a, 0x000, 0x020, 0x10a,\n+\t0x000, 0x020, 0x10a, 0x000, 0x020, 0x10a, 0x000, 0x020,\n+\t0x10a, 0x000, 0x044, 0x140, 0x000, 0x054, 0x362, 0x03d,\n+\t0x000, 0x001, 0x0b0, 0x364, 0x03d, 0x001, 0x001, 0x0c6,\n+\t0x307, 0x02e, 0x044, 0x187, 0x000, 0x055, 0x141, 0x02e,\n+\t0x307, 0x030, 0x302, 0x02e, 0x00b, 0x374, 0x0c0, 0x02e,\n+\t0x327, 0x02d, 0x000, 0x367, 0x044, 0x140, 0x000, 0x3d4,\n+\t0x3df, 0x00e, 0x207, 0x009, 0x00a, 0x04f, 0x04e, 0x055,\n+\t0x3d5, 0x200, 0x014, 0x000, 0x35d, 0x054, 0x000, 0x3f8,\n+\t0x055, 0x081, 0x364, 0x010, 0x001, 0x001, 0x00d, 0x364,\n+\t0x011, 0x002, 0x009, 0x009, 0x3c4, 0x3fe, 0x010, 0x3d4,\n+\t0x3bf, 0x00e, 0x080, 0x101, 0x364, 0x010, 0x002, 0x001,\n+\t0x00a, 0x364, 0x011, 0x001, 0x001, 0x006, 0x3c4, 0x3fd,\n+\t0x010, 0x111, 0x045, 0x347, 0x026, 0x018, 0x347, 0x027,\n+\t0x019, 0x347, 0x028, 0x01b, 0x347, 0x029, 0x01c, 0x044,\n+\t0x222, 0x000, 0x0a1, 0x000, 0x31e, 0x347, 0x026, 0x018,\n+\t0x347, 0x027, 0x019, 0x044, 0x233, 0x000, 0x347, 0x01b,\n+\t0x028, 0x347, 0x01c, 0x029, 0x0a2, 0x000, 0x30c, 0x044,\n+\t0x1b9, 0x000, 0x362, 0x01b, 0x000, 0x001, 0x016, 0x362,\n+\t0x01b, 0x001, 0x001, 0x013, 0x362, 0x01b, 0x002, 0x001,\n+\t0x00d, 0x362, 0x01b, 0x003, 0x001, 0x013, 0x362, 0x01b,\n+\t0x004, 0x001, 0x013, 0x04e, 0x045, 0x364, 0x03d, 0x002,\n+\t0x001, 0x005, 0x044, 0x01a, 0x001, 0x000, 0x3f7, 0x348,\n+\t0x01b, 0x01a, 0x000, 0x3f2, 0x348, 0x01b, 0x01a, 0x000,\n+\t0x3ed, 0x101, 0x247, 0x018, 0x3d7, 0x0ff, 0x019, 0x000,\n+\t0x074, 0x3c7, 0x100, 0x014, 0x364, 0x004, 0x100, 0x009,\n+\t0x00f, 0x044, 0x08d, 0x001, 0x2c7, 0x042, 0x044, 0x1de,\n+\t0x001, 0x001, 0x005, 0x044, 0x239, 0x001, 0x055, 0x0c1,\n+\t0x03d, 0x0bf, 0x000, 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0x010, 0x00e,\n+\t0x387, 0x0b2, 0x187, 0x385, 0x080, 0x247, 0x017, 0x08e,\n+\t0x187, 0x385, 0x0e6, 0x247, 0x016, 0x0c0, 0x015, 0x3c5,\n+\t0x001, 0x014, 0x3c5, 0x004, 0x014, 0x3c4, 0x3fe, 0x014,\n+\t0x3c5, 0x002, 0x014, 0x3d4, 0x3ef, 0x00e, 0x000, 0x006,\n+\t0x082, 0x208, 0x244, 0x03d, 0x0df, 0x02c, 0x0b3, 0x020,\n+\t0x091, 0x000, 0x307, 0x018, 0x3a7, 0x051, 0x044, 0x061,\n+\t0x001, 0x2c7, 0x061, 0x04c, 0x324, 0x061, 0x001, 0x020,\n+\t0x040, 0x3b7, 0x126, 0x08b, 0x187, 0x044, 0x1c4, 0x001,\n+\t0x009, 0x005, 0x3c7, 0x022, 0x01b, 0x042, 0x364, 0x01b,\n+\t0x022, 0x009, 0x027, 0x04c, 0x348, 0x061, 0x061, 0x324,\n+\t0x061, 0x04d, 0x151, 0x050, 0x000, 0x01c, 0x327, 0x04f,\n+\t0x3a4, 0x0ff, 0x322, 0x050, 0x00f, 0x014, 0x040, 0x0aa,\n+\t0x084, 0x044, 0x1c4, 0x001, 0x042, 0x362, 0x01b, 0x00a,\n+\t0x009, 0x008, 0x04c, 0x325, 0x061, 0x04d, 0x141, 0x050,\n+\t0x045, 0x384, 0x0ff, 0x040, 0x193, 0x220, 0x042, 0x384,\n+\t0x00f, 0x041, 0x0a1, 0x111, 0x003, 0x005, 0x2a9, 0x000,\n+\t0x3fc, 0x042, 0x045, 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0x282,\n+\t0x00b, 0x3f1, 0x045, 0x3b7, 0x03b, 0x307, 0x01e, 0x000,\n+\t0x0b2, 0x091, 0x020, 0x362, 0x002, 0x054, 0x327, 0x06f,\n+\t0x009, 0x009, 0x044, 0x08d, 0x001, 0x001, 0x080, 0x000,\n+\t0x00d, 0x044, 0x2f8, 0x001, 0x362, 0x01b, 0x012, 0x009,\n+\t0x076, 0x044, 0x0b2, 0x001, 0x2c7, 0x042, 0x044, 0x1de,\n+\t0x001, 0x287, 0x001, 0x06b, 0x2c7, 0x01d, 0x327, 0x040,\n+\t0x3a4, 0x0ff, 0x2c7, 0x018, 0x0c9, 0x01a, 0x044, 0x2d7,\n+\t0x001, 0x044, 0x206, 0x001, 0x324, 0x035, 0x0c0, 0x01a,\n+\t0x087, 0x187, 0x385, 0x06c, 0x282, 0x00b, 0x015, 0x0c1,\n+\t0x01a, 0x087, 0x187, 0x385, 0x0bc, 0x282, 0x00b, 0x00c,\n+\t0x0c2, 0x01a, 0x088, 0x187, 0x08c, 0x282, 0x00b, 0x004,\n+\t0x0c3, 0x01a, 0x0a0, 0x287, 0x044, 0x300, 0x001, 0x001,\n+\t0x010, 0x041, 0x307, 0x01a, 0x18b, 0x305, 0x042, 0x385,\n+\t0x0e0, 0x3b7, 0x33b, 0x044, 0x1b1, 0x001, 0x043, 0x121,\n+\t0x307, 0x030, 0x282, 0x00b, 0x3e8, 0x307, 0x03e, 0x044,\n+\t0x205, 0x000, 0x0a0, 0x287, 0x044, 0x300, 0x001, 0x001,\n+\t0x00b, 0x041, 0x307, 0x01d, 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0x347, 0x02b, 0x009, 0x000, 0x2d7, 0x347, 0x023,\n+\t0x02d, 0x055, 0x347, 0x023, 0x02c, 0x000, 0x2ce, 0x347,\n+\t0x023, 0x021, 0x000, 0x2c9, 0x307, 0x021, 0x000, 0x006,\n+\t0x307, 0x021, 0x141, 0x021, 0x327, 0x023, 0x04d, 0x000,\n+\t0x2bc, 0x347, 0x023, 0x021, 0x307, 0x021, 0x000, 0x006,\n+\t0x307, 0x021, 0x141, 0x021, 0x04c, 0x2c7, 0x009, 0x000,\n+\t0x2ac, 0x08c, 0x347, 0x023, 0x06f, 0x055, 0x247, 0x02c,\n+\t0x000, 0x2ab, 0x08d, 0x000, 0x3f7, 0x08e, 0x000, 0x3f4,\n+\t0x08f, 0x000, 0x3f1, 0x307, 0x022, 0x183, 0x19b, 0x262,\n+\t0x009, 0x00b, 0x007, 0x347, 0x037, 0x008, 0x000, 0x292,\n+\t0x390, 0x044, 0x000, 0x3ca, 0x397, 0x003, 0x189, 0x395,\n+\t0x105, 0x105, 0x247, 0x009, 0x000, 0x27f, 0x000, 0x27d,\n+\t0x364, 0x004, 0x002, 0x009, 0x090, 0x364, 0x004, 0x008,\n+\t0x009, 0x165, 0x364, 0x004, 0x004, 0x009, 0x08e, 0x0c0,\n+\t0x007, 0x3d5, 0x080, 0x00e, 0x347, 0x006, 0x062, 0x0c0,\n+\t0x064, 0x307, 0x062, 0x197, 0x384, 0x00f, 0x229, 0x220,\n+\t0x3b0, 0x3ca, 0x287, 0x199, 0x390, 0x002, 0x041, 0x040,\n+\t0x045, 0x345, 0x033, 0x064, 0x347, 0x064, 0x007, 0x344,\n+\t0x035, 0x007, 0x3d4, 0x37f, 0x00e, 0x3c5, 0x020, 0x00e,\n+\t0x04e, 0x047, 0x020, 0x3ff, 0x002, 0x020, 0x00a, 0x003,\n+\t0x020, 0x011, 0x003, 0x020, 0x01a, 0x003, 0x020, 0x01d,\n+\t0x003, 0x020, 0x020, 0x003, 0x020, 0x3fa, 0x002, 0x020,\n+\t0x3fa, 0x002, 0x020, 0x3fa, 0x002, 0x020, 0x3fa, 0x002,\n+\t0x020, 0x3fa, 0x002, 0x020, 0x3fa, 0x002, 0x020, 0x3fa,\n+\t0x002, 0x020, 0x3fa, 0x002, 0x020, 0x3fa, 0x002, 0x020,\n+\t0x3fa, 0x002, 0x345, 0x037, 0x064, 0x000, 0x3bf, 0x3b7,\n+\t0x010, 0x1a7, 0x3a5, 0x013, 0x324, 0x038, 0x2c7, 0x064,\n+\t0x000, 0x3b1, 0x3b7, 0x000, 0x1a7, 0x3a5, 0x001, 0x000,\n+\t0x3f5, 0x088, 0x055, 0x247, 0x02c, 0x347, 0x062, 0x06e,\n+\t0x000, 0x3ad, 0x089, 0x000, 0x3f7, 0x08a, 0x000, 0x3f4,\n+\t0x08b, 0x000, 0x3f1, 0x055, 0x0c3, 0x02c, 0x3d5, 0x100,\n+\t0x00e, 0x000, 0x39c, 0x347, 0x011, 0x066, 0x3c4, 0x3fc,\n+\t0x066, 0x364, 0x065, 0x040, 0x009, 0x0a3, 0x044, 0x085,\n+\t0x003, 0x001, 0x06f, 0x044, 0x06b, 0x003, 0x001, 0x005,\n+\t0x055, 0x000, 0x384, 0x044, 0x074, 0x003, 0x3c4, 0x37f,\n+\t0x065, 0x1b5, 0x3a4, 0x038, 0x3c4, 0x3c7, 0x065, 0x2c5,\n+\t0x065, 0x1b2, 0x2e2, 0x007, 0x001, 0x047, 0x2e2, 0x006,\n+\t0x001, 0x043, 0x2e2, 0x002, 0x001, 0x047, 0x2e2, 0x001,\n+\t0x001, 0x031, 0x3d7, 0x07f, 0x064, 0x0a6, 0x044, 0x0bf,\n+\t0x003, 0x000, 0x35c, 0x364, 0x010, 0x002, 0x009, 0x005,\n+\t0x364, 0x011, 0x001, 0x045, 0x3d5, 0x040, 0x00e, 0x3c5,\n+\t0x001, 0x010, 0x3c4, 0x3bf, 0x065, 0x327, 0x066, 0x00b,\n+\t0x005, 0x3c5, 0x040, 0x065, 0x045, 0x327, 0x004, 0x307,\n+\t0x066, 0x198, 0x384, 0x038, 0x1b8, 0x3a4, 0x038, 0x222,\n+\t0x045, 0x3b7, 0x010, 0x1a7, 0x3a5, 0x013, 0x2c7, 0x064,\n+\t0x0a7, 0x000, 0x3cd, 0x347, 0x066, 0x064, 0x044, 0x0cd,\n+\t0x003, 0x000, 0x324, 0x055, 0x0c4, 0x02c, 0x000, 0x31f,\n+\t0x044, 0x074, 0x003, 0x3c5, 0x080, 0x065, 0x3c4, 0x3f8,\n+\t0x065, 0x3a4, 0x1fc, 0x081, 0x245, 0x065, 0x1b1, 0x390,\n+\t0x066, 0x04d, 0x3c5, 0x100, 0x065, 0x000, 0x308, 0x3c4,\n+\t0x07f, 0x064, 0x1c1, 0x064, 0x307, 0x066, 0x198, 0x384,\n+\t0x038, 0x285, 0x188, 0x245, 0x064, 0x3c4, 0x003, 0x010,\n+\t0x345, 0x064, 0x010, 0x3c5, 0x002, 0x010, 0x045, 0x044,\n+\t0x085, 0x003, 0x009, 0x009, 0x307, 0x065, 0x364, 0x065,\n+\t0x080, 0x009, 0x00c, 0x044, 0x06b, 0x003, 0x009, 0x35a,\n+\t0x044, 0x074, 0x003, 0x000, 0x3b0, 0x044, 0x074, 0x003,\n+\t0x384, 0x007, 0x262, 0x007, 0x001, 0x2d1, 0x141, 0x065,\n+\t0x101, 0x324, 0x035, 0x000, 0x3bb, 0x3d5, 0x010, 0x00e,\n+\t0x055, 0x0d3, 0x02c, 0x000, 0x2c2, 0x04e, 0x062, 0x0b1,\n+\t0x0e7, 0x079\n+\n+};  /* end fm10000_sbus_master_code_prd */\n+\n+/* Spico SerDes code (production version 2)\n+ *  source file:   serdes.0x2055/serdes.0x2055_0045.rom\n+ *  KR support\n+ */\n+const uint32_t fm10000_serdes_spico_code_version_build_id_prd2 = 0x20550045;\n+const uint32_t fm10000_serdes_spico_code_size_prd2             = 12167;\n+\n+const uint16_t fm10000_serdes_spico_code_prd2[] = {\n+\t0x035, 0x006, 0x00a, 0x000, 0x1a7, 0x006, 0x020, 0x055,\n+\t0x000, 0x045, 0x3c7, 0x03f, 0x000, 0x0c0, 0x200, 0x307,\n+\t0x200, 0x304, 0x02b, 0x009, 0x00b, 0x0a0, 0x397, 0x3bb,\n+\t0x04d, 0x111, 0x272, 0x1ff, 0x009, 0x3fc, 0x3c8, 0x000,\n+\t0x21e, 0x3ce, 0x3ff, 0x21f, 0x348, 0x21f, 0x21d, 0x34e,\n+\t0x21d, 0x221, 0x34e, 0x221, 0x21c, 0x34e, 0x21c, 0x220,\n+\t0x3c7, 0x3fd, 0x23d, 0x3c7, 0x020, 0x23e, 0x3c7, 0x077,\n+\t0x22d, 0x0c0, 0x202, 0x044, 0x36d, 0x003, 0x044, 0x360,\n+\t0x002, 0x3d7, 0x303, 0x030, 0x347, 0x032, 0x236, 0x3b7,\n+\t0x213, 0x090, 0x044, 0x1a9, 0x000, 0x3b7, 0x204, 0x387,\n+\t0x07c, 0x044, 0x1a9, 0x000, 0x0a4, 0x397, 0x27c, 0x044,\n+\t0x1a9, 0x000, 0x3d5, 0x230, 0x232, 0x345, 0x21d, 0x232,\n+\t0x3b7, 0x221, 0x081, 0x18b, 0x044, 0x1b7, 0x000, 0x3b7,\n+\t0x080, 0x044, 0x192, 0x000, 0x385, 0x00c, 0x384, 0x3cf,\n+\t0x044, 0x1bd, 0x000, 0x3c5, 0x040, 0x021, 0x3b7, 0x020,\n+\t0x387, 0x021, 0x189, 0x044, 0x1a9, 0x000, 0x0c0, 0x008,\n+\t0x0c0, 0x005, 0x0c0, 0x00b, 0x0c0, 0x000, 0x3c5, 0x020,\n+\t0x027, 0x055, 0x307, 0x221, 0x304, 0x233, 0x009, 0x012,\n+\t0x374, 0x027, 0x200, 0x001, 0x00d, 0x044, 0x340, 0x001,\n+\t0x264, 0x080, 0x009, 0x006, 0x3b8, 0x200, 0x2c4, 0x027,\n+\t0x054, 0x364, 0x200, 0x004, 0x029, 0x3de, 0x003, 0x364,\n+\t0x33b, 0x010, 0x029, 0x3de, 0x003, 0x054, 0x364, 0x200,\n+\t0x040, 0x029, 0x034, 0x008, 0x364, 0x2cf, 0x040, 0x009,\n+\t0x01c, 0x307, 0x026, 0x384, 0x003, 0x266, 0x003, 0x009,\n+\t0x014, 0x362, 0x26b, 0x0e0, 0x009, 0x00f, 0x364, 0x234,\n+\t0x002, 0x001, 0x00a, 0x3c5, 0x060, 0x2cf, 0x0c0, 0x26b,\n+\t0x3c5, 0x040, 0x200, 0x054, 0x364, 0x200, 0x100, 0x029,\n+\t0x22f, 0x003, 0x054, 0x044, 0x141, 0x001, 0x055, 0x364,\n+\t0x23f, 0x003, 0x001, 0x012, 0x044, 0x34c, 0x001, 0x029,\n+\t0x0af, 0x006, 0x044, 0x340, 0x001, 0x227, 0x326, 0x249,\n+\t0x1ba, 0x029, 0x0af, 0x006, 0x3c4, 0x3df, 0x000, 0x364,\n+\t0x33c, 0x020, 0x001, 0x017, 0x364, 0x059, 0x080, 0x001,\n+\t0x012, 0x364, 0x24b, 0x080, 0x009, 0x00d, 0x364, 0x001,\n+\t0x080, 0x009, 0x008, 0x3c5, 0x080, 0x24b, 0x044, 0x12d,\n+\t0x005, 0x055, 0x364, 0x200, 0x080, 0x001, 0x00d, 0x3c4,\n+\t0x3fd, 0x26f, 0x3c4, 0x3fe, 0x200, 0x366, 0x200, 0x080,\n+\t0x001, 0x00f, 0x140, 0x200, 0x009, 0x365, 0x364, 0x23f,\n+\t0x003, 0x009, 0x360, 0x04f, 0x04e, 0x000, 0x35c, 0x3c5,\n+\t0x030, 0x000, 0x347, 0x244, 0x054, 0x374, 0x000, 0x2c0,\n+\t0x009, 0x34c, 0x387, 0x0c1, 0x187, 0x245, 0x054, 0x04f,\n+\t0x055, 0x141, 0x26c, 0x347, 0x245, 0x200, 0x347, 0x245,\n+\t0x26d, 0x0c0, 0x245, 0x364, 0x026, 0x002, 0x001, 0x336,\n+\t0x364, 0x020, 0x005, 0x009, 0x007, 0x0c2, 0x26f, 0x044,\n+\t0x1b8, 0x001, 0x055, 0x364, 0x020, 0x005, 0x009, 0x326,\n+\t0x362, 0x26b, 0x0e0, 0x009, 0x321, 0x364, 0x234, 0x002,\n+\t0x001, 0x31c, 0x3c5, 0x060, 0x2cf, 0x3c5, 0x040, 0x200,\n+\t0x000, 0x314, 0x044, 0x290, 0x001, 0x3c5, 0x080, 0x200,\n+\t0x347, 0x2cf, 0x26b, 0x3c4, 0x0e0, 0x26b, 0x3c4, 0x3bf,\n+\t0x2cf, 0x045, 0x387, 0x080, 0x020, 0x2f8, 0x001, 0x387,\n+\t0x02f, 0x111, 0x009, 0x3ff, 0x045, 0x054, 0x111, 0x009,\n+\t0x3fe, 0x045, 0x044, 0x1a0, 0x000, 0x307, 0x032, 0x054,\n+\t0x045, 0x044, 0x1a0, 0x000, 0x307, 0x033, 0x054, 0x045,\n+\t0x055, 0x2c7, 0x030, 0x364, 0x035, 0x001, 0x009, 0x3fd,\n+\t0x045, 0x044, 0x1a0, 0x000, 0x305, 0x033, 0x000, 0x012,\n+\t0x044, 0x1a0, 0x000, 0x306, 0x033, 0x000, 0x00b, 0x208,\n+\t0x044, 0x1a0, 0x000, 0x304, 0x033, 0x055, 0x2c7, 0x030,\n+\t0x247, 0x031, 0x345, 0x21d, 0x030, 0x140, 0x035, 0x009,\n+\t0x3fe, 0x346, 0x21d, 0x030, 0x054, 0x045, 0x040, 0x140,\n+\t0x036, 0x00b, 0x020, 0x044, 0x206, 0x000, 0x344, 0x21f,\n+\t0x036, 0x3c4, 0x3ef, 0x036, 0x09f, 0x044, 0x189, 0x000,\n+\t0x000, 0x010, 0x040, 0x140, 0x036, 0x003, 0x00c, 0x044,\n+\t0x206, 0x000, 0x345, 0x21d, 0x036, 0x3c4, 0x3ef, 0x036,\n+\t0x054, 0x327, 0x22b, 0x3a4, 0x003, 0x133, 0x009, 0x00e,\n+\t0x0a1, 0x1aa, 0x2a8, 0x2c4, 0x021, 0x08f, 0x044, 0x189,\n+\t0x000, 0x2a8, 0x2c5, 0x021, 0x042, 0x045, 0x055, 0x088,\n+\t0x3c5, 0x010, 0x036, 0x000, 0x37e, 0x3c4, 0x3fe, 0x026,\n+\t0x327, 0x22c, 0x3a4, 0x007, 0x2e6, 0x001, 0x001, 0x01b,\n+\t0x044, 0x1e2, 0x000, 0x364, 0x234, 0x001, 0x009, 0x013,\n+\t0x364, 0x33b, 0x007, 0x001, 0x00d, 0x044, 0x3b6, 0x003,\n+\t0x364, 0x33c, 0x020, 0x009, 0x005, 0x044, 0x066, 0x004,\n+\t0x054, 0x045, 0x364, 0x233, 0x002, 0x009, 0x00d, 0x347,\n+\t0x271, 0x270, 0x044, 0x2f6, 0x002, 0x009, 0x005, 0x044,\n+\t0x02b, 0x008, 0x374, 0x232, 0x200, 0x001, 0x0a5, 0x3d7,\n+\t0x200, 0x27b, 0x044, 0x29c, 0x001, 0x044, 0x2f6, 0x002,\n+\t0x009, 0x005, 0x044, 0x028, 0x008, 0x3b7, 0x221, 0x364,\n+\t0x22b, 0x003, 0x009, 0x007, 0x083, 0x18b, 0x044, 0x1a9,\n+\t0x000, 0x398, 0x200, 0x244, 0x232, 0x3b7, 0x221, 0x091,\n+\t0x189, 0x385, 0x128, 0x044, 0x1a9, 0x000, 0x083, 0x044,\n+\t0x1b7, 0x000, 0x3b7, 0x220, 0x044, 0x192, 0x000, 0x197,\n+\t0x264, 0x007, 0x009, 0x005, 0x091, 0x000, 0x003, 0x081,\n+\t0x3b7, 0x221, 0x189, 0x044, 0x1b7, 0x000, 0x364, 0x246,\n+\t0x010, 0x009, 0x002, 0x3b7, 0x221, 0x081, 0x18d, 0x044,\n+\t0x1a9, 0x000, 0x081, 0x189, 0x044, 0x1a9, 0x000, 0x387,\n+\t0x2d7, 0x044, 0x1b8, 0x000, 0x364, 0x22b, 0x003, 0x009,\n+\t0x009, 0x3b7, 0x221, 0x081, 0x18b, 0x044, 0x1b7, 0x000,\n+\t0x364, 0x02b, 0x020, 0x009, 0x020, 0x0a3, 0x364, 0x22b,\n+\t0x003, 0x001, 0x006, 0x044, 0x025, 0x008, 0x0a0, 0x307,\n+\t0x251, 0x197, 0x384, 0x00f, 0x220, 0x001, 0x005, 0x044,\n+\t0x182, 0x000, 0x327, 0x251, 0x3a4, 0x01f, 0x001, 0x005,\n+\t0x044, 0x0d9, 0x001, 0x044, 0x1ce, 0x000, 0x364, 0x232,\n+\t0x100, 0x001, 0x005, 0x044, 0x0a9, 0x001, 0x3c4, 0x3f0,\n+\t0x22d, 0x3c5, 0x001, 0x026, 0x364, 0x026, 0x002, 0x001,\n+\t0x1c5, 0x044, 0x283, 0x001, 0x3b7, 0x300, 0x387, 0x020,\n+\t0x000, 0x2c1, 0x307, 0x036, 0x00b, 0x3ea, 0x044, 0x1ce,\n+\t0x000, 0x000, 0x3e5, 0x387, 0x3ff, 0x327, 0x22c, 0x3a4,\n+\t0x007, 0x131, 0x001, 0x01a, 0x3d5, 0x200, 0x232, 0x000,\n+\t0x006, 0x080, 0x131, 0x001, 0x011, 0x3b7, 0x205, 0x044,\n+\t0x1bd, 0x000, 0x3b7, 0x222, 0x044, 0x1bd, 0x000, 0x3b7,\n+\t0x251, 0x044, 0x1bd, 0x000, 0x3b7, 0x214, 0x100, 0x009,\n+\t0x00a, 0x044, 0x1bd, 0x000, 0x3c4, 0x37b, 0x021, 0x000,\n+\t0x29e, 0x3c5, 0x084, 0x021, 0x000, 0x299, 0x364, 0x233,\n+\t0x002, 0x009, 0x00d, 0x347, 0x272, 0x270, 0x044, 0x2f6,\n+\t0x002, 0x009, 0x005, 0x044, 0x02e, 0x008, 0x307, 0x22d,\n+\t0x384, 0x070, 0x386, 0x010, 0x001, 0x04a, 0x364, 0x02b,\n+\t0x020, 0x009, 0x045, 0x3b7, 0x071, 0x387, 0x128, 0x044,\n+\t0x1a9, 0x000, 0x387, 0x368, 0x044, 0x1b8, 0x000, 0x387,\n+\t0x2d7, 0x044, 0x1b8, 0x000, 0x0a1, 0x307, 0x22b, 0x384,\n+\t0x030, 0x001, 0x003, 0x0ac, 0x307, 0x256, 0x384, 0x01f,\n+\t0x220, 0x001, 0x005, 0x044, 0x0de, 0x001, 0x080, 0x327,\n+\t0x22b, 0x3a4, 0x030, 0x3a2, 0x030, 0x009, 0x00e, 0x0a1,\n+\t0x1ab, 0x2a8, 0x2c4, 0x024, 0x08f, 0x044, 0x189, 0x000,\n+\t0x2a8, 0x2c5, 0x024, 0x327, 0x256, 0x1b7, 0x3a4, 0x07f,\n+\t0x220, 0x001, 0x005, 0x044, 0x0e2, 0x001, 0x044, 0x2f6,\n+\t0x002, 0x009, 0x007, 0x0c0, 0x27b, 0x044, 0x29c, 0x001,\n+\t0x044, 0x0e6, 0x001, 0x3c4, 0x30f, 0x22d, 0x044, 0x2f6,\n+\t0x002, 0x009, 0x005, 0x044, 0x031, 0x008, 0x345, 0x21d,\n+\t0x01c, 0x307, 0x21d, 0x304, 0x233, 0x001, 0x007, 0x3a7,\n+\t0x071, 0x044, 0x1a9, 0x000, 0x3c5, 0x002, 0x026, 0x044,\n+\t0x141, 0x001, 0x020, 0x283, 0x001, 0x055, 0x3c4, 0x3ef,\n+\t0x027, 0x3c4, 0x3fd, 0x026, 0x364, 0x26f, 0x002, 0x001,\n+\t0x008, 0x3c4, 0x3fd, 0x26f, 0x044, 0x290, 0x001, 0x344,\n+\t0x21f, 0x01c, 0x3c4, 0x3bf, 0x200, 0x3c4, 0x39f, 0x2cf,\n+\t0x0c0, 0x2d8, 0x0c0, 0x26b, 0x364, 0x234, 0x002, 0x009,\n+\t0x012, 0x364, 0x33b, 0x007, 0x001, 0x00d, 0x044, 0x066,\n+\t0x004, 0x364, 0x33c, 0x020, 0x009, 0x005, 0x044, 0x3b6,\n+\t0x003, 0x054, 0x0a0, 0x081, 0x189, 0x020, 0x1a9, 0x000,\n+\t0x044, 0x3fd, 0x000, 0x387, 0x3ff, 0x044, 0x02b, 0x001,\n+\t0x3a7, 0x022, 0x020, 0x1bd, 0x000, 0x0a0, 0x081, 0x189,\n+\t0x020, 0x1a9, 0x000, 0x080, 0x044, 0x02b, 0x001, 0x3b7,\n+\t0x300, 0x387, 0x020, 0x044, 0x1a9, 0x000, 0x364, 0x024,\n+\t0x002, 0x001, 0x006, 0x399, 0x305, 0x000, 0x004, 0x397,\n+\t0x200, 0x044, 0x322, 0x001, 0x3a7, 0x022, 0x044, 0x1bd,\n+\t0x000, 0x364, 0x232, 0x002, 0x001, 0x005, 0x044, 0x382,\n+\t0x001, 0x000, 0x0c9, 0x3a7, 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0x233,\n+\t0x364, 0x026, 0x002, 0x001, 0x008, 0x3c5, 0x008, 0x232,\n+\t0x044, 0x3b5, 0x000, 0x307, 0x24d, 0x384, 0x070, 0x001,\n+\t0x091, 0x382, 0x030, 0x001, 0x0a6, 0x3b7, 0x301, 0x044,\n+\t0x192, 0x000, 0x384, 0x3c7, 0x385, 0x018, 0x044, 0x1bd,\n+\t0x000, 0x3c4, 0x3f7, 0x024, 0x000, 0x0a4, 0x347, 0x24d,\n+\t0x22b, 0x364, 0x233, 0x006, 0x001, 0x033, 0x307, 0x22b,\n+\t0x364, 0x233, 0x002, 0x001, 0x023, 0x364, 0x233, 0x080,\n+\t0x001, 0x00a, 0x307, 0x24d, 0x197, 0x384, 0x007, 0x044,\n+\t0x3a4, 0x008, 0x364, 0x233, 0x100, 0x001, 0x00c, 0x307,\n+\t0x24d, 0x19b, 0x384, 0x007, 0x385, 0x010, 0x044, 0x3a4,\n+\t0x008, 0x3c4, 0x27f, 0x233, 0x000, 0x00b, 0x3c5, 0x003,\n+\t0x22a, 0x197, 0x044, 0x39c, 0x008, 0x003, 0x298, 0x044,\n+\t0x082, 0x00b, 0x0a2, 0x1ab, 0x324, 0x020, 0x021, 0x181,\n+\t0x006, 0x045, 0x3b7, 0x301, 0x087, 0x044, 0x1b7, 0x000,\n+\t0x3b7, 0x211, 0x082, 0x044, 0x1b7, 0x000, 0x3c4, 0x3f7,\n+\t0x021, 0x000, 0x36c, 0x3b7, 0x301, 0x044, 0x192, 0x000,\n+\t0x384, 0x3f8, 0x105, 0x044, 0x1bd, 0x000, 0x3b7, 0x211,\n+\t0x082, 0x044, 0x1a9, 0x000, 0x3c5, 0x008, 0x021, 0x344,\n+\t0x21f, 0x021, 0x3b7, 0x250, 0x088, 0x044, 0x1a9, 0x000,\n+\t0x3b7, 0x211, 0x082, 0x044, 0x1a9, 0x000, 0x000, 0x347,\n+\t0x3b7, 0x301, 0x387, 0x3c7, 0x044, 0x1b8, 0x000, 0x3a7,\n+\t0x060, 0x083, 0x044, 0x1b7, 0x000, 0x3b7, 0x070, 0x083,\n+\t0x18a, 0x044, 0x1b7, 0x000, 0x3c4, 0x3f7, 0x024, 0x000,\n+\t0x36f, 0x3b7, 0x301, 0x044, 0x192, 0x000, 0x384, 0x3c7,\n+\t0x385, 0x028, 0x044, 0x1bd, 0x000, 0x3c5, 0x048, 0x024,\n+\t0x3a7, 0x060, 0x083, 0x044, 0x1a9, 0x000, 0x3b7, 0x070,\n+\t0x083, 0x18a, 0x044, 0x1a9, 0x000, 0x000, 0x351, 0x307,\n+\t0x22b, 0x284, 0x2a8, 0x2c4, 0x24d, 0x245, 0x24d, 0x2a8,\n+\t0x045, 0x2f4, 0x200, 0x001, 0x008, 0x364, 0x2cf, 0x007,\n+\t0x029, 0x1dc, 0x007, 0x287, 0x385, 0x300, 0x208, 0x001,\n+\t0x04b, 0x364, 0x33b, 0x010, 0x029, 0x1dc, 0x007, 0x3c5,\n+\t0x002, 0x00c, 0x287, 0x384, 0x0ff, 0x305, 0x21d, 0x1b7,\n+\t0x2e4, 0x001, 0x001, 0x01d, 0x040, 0x384, 0x007, 0x117,\n+\t0x001, 0x00c, 0x3c5, 0x040, 0x02d, 0x081, 0x044, 0x189,\n+\t0x000, 0x3c4, 0x3bf, 0x02d, 0x042, 0x247, 0x029, 0x364,\n+\t0x018, 0x001, 0x009, 0x005, 0x3c5, 0x010, 0x021, 0x2e4,\n+\t0x002, 0x001, 0x017, 0x264, 0x080, 0x001, 0x005, 0x0a4,\n+\t0x1a7, 0x285, 0x040, 0x3c5, 0x080, 0x02d, 0x081, 0x044,\n+\t0x189, 0x000, 0x3c4, 0x37f, 0x02d, 0x042, 0x247, 0x02a,\n+\t0x000, 0x014, 0x38e, 0x3ff, 0x1b8, 0x00a, 0x00a, 0x244,\n+\t0x029, 0x3c4, 0x3ef, 0x021, 0x3c4, 0x3fd, 0x00c, 0x120,\n+\t0x001, 0x004, 0x244, 0x02a, 0x020, 0x181, 0x006, 0x289,\n+\t0x00a, 0x004, 0x2c7, 0x251, 0x22e, 0x364, 0x026, 0x001,\n+\t0x021, 0x181, 0x006, 0x041, 0x3a4, 0x01f, 0x001, 0x005,\n+\t0x044, 0x0d9, 0x001, 0x043, 0x1b7, 0x001, 0x005, 0x044,\n+\t0x182, 0x000, 0x020, 0x181, 0x006, 0x2e4, 0x002, 0x009,\n+\t0x01b, 0x3c4, 0x2ff, 0x232, 0x120, 0x001, 0x012, 0x3d5,\n+\t0x300, 0x232, 0x044, 0x099, 0x00b, 0x32a, 0x026, 0x00a,\n+\t0x008, 0x044, 0x20d, 0x000, 0x044, 0x232, 0x000, 0x020,\n+\t0x181, 0x006, 0x042, 0x307, 0x240, 0x20a, 0x040, 0x020,\n+\t0x181, 0x006, 0x289, 0x00a, 0x004, 0x2c7, 0x256, 0x22e,\n+\t0x364, 0x026, 0x002, 0x021, 0x181, 0x006, 0x041, 0x3a4,\n+\t0x01f, 0x001, 0x005, 0x044, 0x0de, 0x001, 0x043, 0x1b7,\n+\t0x001, 0x005, 0x044, 0x0e2, 0x001, 0x020, 0x181, 0x006,\n+\t0x364, 0x23f, 0x003, 0x009, 0x007, 0x044, 0x340, 0x001,\n+\t0x247, 0x249, 0x054, 0x347, 0x249, 0x248, 0x2c7, 0x23f,\n+\t0x083, 0x18a, 0x385, 0x018, 0x364, 0x23f, 0x001, 0x001,\n+\t0x006, 0x245, 0x057, 0x000, 0x005, 0x208, 0x244, 0x057,\n+\t0x087, 0x18c, 0x385, 0x0e0, 0x364, 0x23f, 0x002, 0x001,\n+\t0x009, 0x245, 0x057, 0x044, 0x27d, 0x001, 0x000, 0x005,\n+\t0x208, 0x244, 0x057, 0x020, 0x181, 0x006, 0x2c7, 0x246,\n+\t0x3b7, 0x300, 0x044, 0x192, 0x000, 0x384, 0x33f, 0x327,\n+\t0x246, 0x3a4, 0x0c0, 0x285, 0x3b7, 0x300, 0x044, 0x1bd,\n+\t0x000, 0x3b7, 0x200, 0x044, 0x192, 0x000, 0x0a3, 0x1a9,\n+\t0x2a8, 0x284, 0x040, 0x307, 0x246, 0x384, 0x030, 0x264,\n+\t0x010, 0x001, 0x012, 0x040, 0x041, 0x3b7, 0x201, 0x044,\n+\t0x192, 0x000, 0x384, 0x3e0, 0x385, 0x006, 0x044, 0x1bd,\n+\t0x000, 0x043, 0x042, 0x185, 0x2a8, 0x284, 0x227, 0x042,\n+\t0x285, 0x3b7, 0x200, 0x044, 0x1bd, 0x000, 0x307, 0x246,\n+\t0x384, 0x007, 0x044, 0x375, 0x00b, 0x3a7, 0x073, 0x307,\n+\t0x246, 0x184, 0x00a, 0x014, 0x044, 0x192, 0x000, 0x384,\n+\t0x3e2, 0x327, 0x246, 0x1b5, 0x3a4, 0x01c, 0x285, 0x3a7,\n+\t0x073, 0x044, 0x1bd, 0x000, 0x000, 0x006, 0x081, 0x044,\n+\t0x1a9, 0x000, 0x020, 0x181, 0x006, 0x3c5, 0x001, 0x00c,\n+\t0x187, 0x0a7, 0x1a7, 0x2a8, 0x324, 0x00c, 0x225, 0x2c7,\n+\t0x00c, 0x045, 0x04e, 0x087, 0x011, 0x054, 0x084\n+\n+};  /* end fm10000_serdes_spico_code_prd2 */\n+\n+\n+\n+/* Spico Swap code (production version 2)\n+ *  source file:   serdes.0x2055_0045.swap\n+ *  Note: if swap code exists, if must be loaded on top of\n+ *  the sbus master image.\n+ */\n+\n+const uint32_t fm10000_serdes_swap_code_version_build_id_prd2 = 0x20550045;\n+const uint32_t fm10000_serdes_swap_code_size_prd2             = 7842;\n+\n+const uint16_t fm10000_serdes_swap_code_prd2[] = {\n+\t0x01e, 0x09d, 0x002, 0x000, 0x000, 0x008, 0x00f, 0x07b,\n+\t0x020, 0x01e, 0x00f, 0x069, 0x01d, 0x029, 0x00b, 0x01d,\n+\t0x02c, 0x382, 0x04e, 0x020, 0x23b, 0x009, 0x020, 0x28e,\n+\t0x00a, 0x020, 0x03a, 0x00a, 0x020, 0x0fe, 0x00a, 0x020,\n+\t0x3f3, 0x008, 0x020, 0x013, 0x009, 0x020, 0x075, 0x00a,\n+\t0x0c1, 0x244, 0x3c5, 0x040, 0x245, 0x3c4, 0x3bf, 0x200,\n+\t0x044, 0x172, 0x000, 0x020, 0x0d3, 0x000, 0x020, 0x2c3,\n+\t0x008, 0x020, 0x375, 0x00b, 0x0c1, 0x201, 0x045, 0x020,\n+\t0x04a, 0x009, 0x020, 0x04e, 0x009, 0x020, 0x256, 0x002,\n+\t0x020, 0x17f, 0x009, 0x020, 0x23f, 0x006, 0x020, 0x285,\n+\t0x00a, 0x020, 0x209, 0x00b, 0x020, 0x257, 0x006, 0x020,\n+\t0x117, 0x008, 0x020, 0x394, 0x00a, 0x020, 0x048, 0x00b,\n+\t0x020, 0x1dc, 0x007, 0x020, 0x27f, 0x00a, 0x020, 0x2d2,\n+\t0x006, 0x020, 0x1e2, 0x007, 0x020, 0x295, 0x00b, 0x020,\n+\t0x3a8, 0x001, 0x020, 0x277, 0x00b, 0x020, 0x2ba, 0x00b,\n+\t0x020, 0x2d5, 0x006, 0x020, 0x326, 0x006, 0x020, 0x350,\n+\t0x006, 0x020, 0x1dc, 0x007, 0x020, 0x35a, 0x006, 0x020,\n+\t0x0a4, 0x00b, 0x020, 0x38e, 0x006, 0x020, 0x011, 0x007,\n+\t0x020, 0x016, 0x007, 0x020, 0x31e, 0x007, 0x020, 0x324,\n+\t0x007, 0x020, 0x3b6, 0x007, 0x020, 0x02a, 0x007, 0x020,\n+\t0x041, 0x007, 0x020, 0x060, 0x007, 0x020, 0x06d, 0x007,\n+\t0x020, 0x072, 0x007, 0x020, 0x2d1, 0x007, 0x020, 0x1dc,\n+\t0x007, 0x020, 0x1dc, 0x007, 0x020, 0x1dc, 0x007, 0x020,\n+\t0x1dc, 0x007, 0x020, 0x252, 0x007, 0x020, 0x293, 0x007,\n+\t0x020, 0x2d8, 0x00b, 0x020, 0x1dc, 0x007, 0x020, 0x1dc,\n+\t0x007, 0x020, 0x16f, 0x007, 0x020, 0x185, 0x007, 0x020,\n+\t0x1dc, 0x007, 0x020, 0x1dc, 0x007, 0x020, 0x1dc, 0x007,\n+\t0x020, 0x1dc, 0x007, 0x020, 0x30e, 0x00b, 0x020, 0x1dc,\n+\t0x007, 0x020, 0x1dc, 0x007, 0x020, 0x1dc, 0x007, 0x020,\n+\t0x1dc, 0x007, 0x020, 0x1dc, 0x007, 0x020, 0x1dc, 0x007,\n+\t0x020, 0x1dc, 0x007, 0x020, 0x1dc, 0x007, 0x020, 0x1dc,\n+\t0x007, 0x020, 0x077, 0x007, 0x020, 0x0b1, 0x007, 0x020,\n+\t0x103, 0x007, 0x020, 0x1c5, 0x008, 0x020, 0x1dc, 0x007,\n+\t0x020, 0x168, 0x007, 0x287, 0x264, 0x004, 0x001, 0x049,\n+\t0x3c5, 0x00c, 0x00c, 0x3c5, 0x020, 0x33b, 0x18e, 0x00a,\n+\t0x013, 0x044, 0x04c, 0x004, 0x3a4, 0x001, 0x001, 0x014,\n+\t0x364, 0x052, 0x001, 0x009, 0x093, 0x044, 0x0bc, 0x004,\n+\t0x000, 0x08e, 0x3c4, 0x2ff, 0x053, 0x3c4, 0x030, 0x027,\n+\t0x000, 0x3ec, 0x3c4, 0x3fe, 0x052, 0x000, 0x081, 0x043,\n+\t0x327, 0x33b, 0x020, 0x1de, 0x007, 0x2e4, 0x080, 0x009,\n+\t0x00d, 0x3d5, 0x220, 0x33c, 0x100, 0x009, 0x06e, 0x044,\n+\t0x3b6, 0x003, 0x000, 0x06c, 0x3d5, 0x120, 0x33c, 0x100,\n+\t0x009, 0x022, 0x044, 0x066, 0x004, 0x000, 0x061, 0x384,\n+\t0x003, 0x3c4, 0x3df, 0x33b, 0x262, 0x003, 0x001, 0x3d9,\n+\t0x3c4, 0x32d, 0x33c, 0x3c4, 0x3ef, 0x027, 0x2e4, 0x040,\n+\t0x009, 0x3d5, 0x100, 0x009, 0x007, 0x044, 0x063, 0x004,\n+\t0x000, 0x046, 0x364, 0x200, 0x004, 0x029, 0x1dc, 0x007,\n+\t0x0c0, 0x2d8, 0x111, 0x001, 0x028, 0x3c5, 0x002, 0x33c,\n+\t0x3c5, 0x001, 0x33b, 0x344, 0x21f, 0x33c, 0x287, 0x19b,\n+\t0x247, 0x361, 0x287, 0x183, 0x19b, 0x247, 0x360, 0x0c0,\n+\t0x35e, 0x2e4, 0x020, 0x001, 0x004, 0x0c5, 0x35e, 0x2e4,\n+\t0x010, 0x001, 0x005, 0x3c5, 0x080, 0x33c, 0x289, 0x384,\n+\t0x010, 0x245, 0x33c, 0x044, 0x001, 0x004, 0x364, 0x33c,\n+\t0x002, 0x001, 0x005, 0x3c5, 0x004, 0x200, 0x364, 0x33c,\n+\t0x020, 0x009, 0x005, 0x044, 0x097, 0x004, 0x020, 0x181,\n+\t0x006, 0x287, 0x19b, 0x11d, 0x001, 0x002, 0x287, 0x1a3,\n+\t0x1b3, 0x19b, 0x180, 0x390, 0x1d7, 0x040, 0x199, 0x390,\n+\t0x008, 0x040, 0x045, 0x000, 0x021, 0x000, 0x073, 0x000,\n+\t0x05f, 0x000, 0x023, 0x000, 0x025, 0x000, 0x033, 0x000,\n+\t0x035, 0x000, 0x037, 0x000, 0x041, 0x000, 0x01f, 0x000,\n+\t0x021, 0x000, 0x023, 0x000, 0x031, 0x000, 0x082, 0x000,\n+\t0x002, 0x020, 0x1dc, 0x007, 0x044, 0x378, 0x003, 0x3c4,\n+\t0x3fd, 0x233, 0x000, 0x072, 0x2c7, 0x363, 0x000, 0x06e,\n+\t0x2c7, 0x362, 0x000, 0x06a, 0x2c7, 0x341, 0x000, 0x066,\n+\t0x2c7, 0x33f, 0x000, 0x062, 0x2c7, 0x340, 0x000, 0x05e,\n+\t0x2c7, 0x344, 0x000, 0x05a, 0x2c7, 0x342, 0x000, 0x056,\n+\t0x2c7, 0x343, 0x000, 0x052, 0x2c7, 0x341, 0x2c7, 0x33f,\n+\t0x2c7, 0x340, 0x000, 0x04a, 0x307, 0x340, 0x300, 0x341,\n+\t0x300, 0x33f, 0x282, 0x007, 0x006, 0x2c7, 0x23e, 0x000,\n+\t0x03d, 0x043, 0x0a1, 0x020, 0x1de, 0x007, 0x287, 0x384,\n+\t0x003, 0x181, 0x3c4, 0x3f3, 0x052, 0x245, 0x052, 0x3a4,\n+\t0x00c, 0x3c4, 0x3f3, 0x33c, 0x2c5, 0x33c, 0x000, 0x026,\n+\t0x3c5, 0x002, 0x233, 0x3c7, 0x3ff, 0x352, 0x3c7, 0x3ff,\n+\t0x353, 0x1d3, 0x353, 0x0cf, 0x354, 0x1cb, 0x354, 0x3c5,\n+\t0x0c0, 0x354, 0x3c9, 0x222, 0x355, 0x3c5, 0x001, 0x33c,\n+\t0x0c0, 0x356, 0x1b0, 0x00a, 0x006, 0x081, 0x18a, 0x247,\n+\t0x356, 0x1ab, 0x2c7, 0x357, 0x020, 0x181, 0x006, 0x287,\n+\t0x001, 0x025, 0x197, 0x3a4, 0x00f, 0x262, 0x003, 0x001,\n+\t0x03d, 0x131, 0x001, 0x020, 0x131, 0x001, 0x021, 0x131,\n+\t0x001, 0x022, 0x131, 0x001, 0x025, 0x131, 0x001, 0x026,\n+\t0x131, 0x001, 0x027, 0x132, 0x182, 0x390, 0x377, 0x280,\n+\t0x04c, 0x042, 0x020, 0x1de, 0x007, 0x044, 0x361, 0x003,\n+\t0x000, 0x3d4, 0x327, 0x373, 0x000, 0x3f5, 0x327, 0x372,\n+\t0x000, 0x3f1, 0x327, 0x2b3, 0x322, 0x2b2, 0x000, 0x3eb,\n+\t0x327, 0x374, 0x000, 0x3e7, 0x327, 0x375, 0x000, 0x3e3,\n+\t0x327, 0x376, 0x000, 0x3df, 0x307, 0x369, 0x282, 0x272,\n+\t0x369, 0x00e, 0x003, 0x108, 0x04c, 0x000, 0x3d4, 0x364,\n+\t0x33c, 0x001, 0x001, 0x01b, 0x364, 0x33b, 0x020, 0x009,\n+\t0x016, 0x0a0, 0x307, 0x04f, 0x181, 0x00a, 0x003, 0x0a4,\n+\t0x100, 0x00b, 0x004, 0x3a5, 0x080, 0x307, 0x050, 0x194,\n+\t0x384, 0x040, 0x225, 0x2c7, 0x392, 0x081, 0x189, 0x314,\n+\t0x053, 0x001, 0x007, 0x3c5, 0x008, 0x027, 0x000, 0x005,\n+\t0x3c4, 0x3f7, 0x027, 0x364, 0x33c, 0x020, 0x001, 0x007,\n+\t0x347, 0x21d, 0x35a, 0x000, 0x018, 0x347, 0x050, 0x368,\n+\t0x3b7, 0x201, 0x1a5, 0x140, 0x04f, 0x00b, 0x00b, 0x364,\n+\t0x052, 0x020, 0x001, 0x3f3, 0x2c5, 0x33c, 0x000, 0x005,\n+\t0x2a8, 0x2c4, 0x33c, 0x081, 0x189, 0x304, 0x053, 0x001,\n+\t0x007, 0x3c5, 0x008, 0x027, 0x000, 0x005, 0x3c4, 0x3f7,\n+\t0x027, 0x3c5, 0x080, 0x053, 0x3c4, 0x37f, 0x053, 0x364,\n+\t0x33b, 0x020, 0x009, 0x00a, 0x364, 0x33c, 0x020, 0x009,\n+\t0x005, 0x044, 0x132, 0x004, 0x020, 0x08d, 0x006, 0x2c7,\n+\t0x231, 0x2e4, 0x100, 0x001, 0x045, 0x2e4, 0x001, 0x001,\n+\t0x020, 0x3b7, 0x213, 0x084, 0x044, 0x1a9, 0x000, 0x3b7,\n+\t0x250, 0x084, 0x044, 0x1a9, 0x000, 0x399, 0x305, 0x3a7,\n+\t0x022, 0x044, 0x1a9, 0x000, 0x044, 0x322, 0x001, 0x3c5,\n+\t0x002, 0x024, 0x3c5, 0x008, 0x292, 0x000, 0x020, 0x3c4,\n+\t0x3fd, 0x024, 0x364, 0x234, 0x002, 0x001, 0x009, 0x3a7,\n+\t0x022, 0x399, 0x305, 0x044, 0x1b7, 0x000, 0x3b7, 0x213,\n+\t0x084, 0x044, 0x1b7, 0x000, 0x3b7, 0x250, 0x084, 0x044,\n+\t0x1b7, 0x000, 0x3c4, 0x007, 0x292, 0x044, 0x06e, 0x003,\n+\t0x307, 0x231, 0x274, 0x200, 0x001, 0x01b, 0x274, 0x010,\n+\t0x001, 0x00b, 0x387, 0x020, 0x245, 0x021, 0x185, 0x245,\n+\t0x024, 0x000, 0x00b, 0x387, 0x3df, 0x244, 0x021, 0x185,\n+\t0x385, 0x0ff, 0x244, 0x024, 0x044, 0x03a, 0x00a, 0x045,\n+\t0x327, 0x230, 0x364, 0x233, 0x004, 0x001, 0x003, 0x045,\n+\t0x0c2, 0x22a, 0x347, 0x275, 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0x2d5, 0x2f7, 0x044, 0x253,\n+\t0x00b, 0x055, 0x3c4, 0x3fc, 0x2cf, 0x364, 0x2cf, 0x040,\n+\t0x009, 0x019, 0x3c4, 0x39d, 0x2cf, 0x0ce, 0x2ce, 0x364,\n+\t0x2cf, 0x001, 0x009, 0x007, 0x0cf, 0x2ce, 0x3c4, 0x3fe,\n+\t0x2cf, 0x364, 0x2cf, 0x010, 0x009, 0x005, 0x3c4, 0x3bf,\n+\t0x200, 0x3c4, 0x1ff, 0x2cf, 0x044, 0x33f, 0x002, 0x020,\n+\t0x0d3, 0x000, 0x347, 0x2cb, 0x306, 0x044, 0x1e6, 0x00a,\n+\t0x044, 0x333, 0x008, 0x151, 0x2f7, 0x009, 0x3f5, 0x045,\n+\t0x397, 0x201, 0x0a0, 0x044, 0x18a, 0x002, 0x020, 0x1bf,\n+\t0x003, 0x397, 0x2ba, 0x04c, 0x118, 0x04d, 0x109, 0x272,\n+\t0x2c1, 0x00b, 0x3fa, 0x045, 0x397, 0x2b2, 0x04c, 0x2c7,\n+\t0x303, 0x101, 0x04c, 0x322, 0x303, 0x00b, 0x009, 0x04c,\n+\t0x111, 0x04d, 0x101, 0x327, 0x303, 0x04d, 0x101, 0x272,\n+\t0x2c1, 0x00b, 0x3ed, 0x045, 0x2f4, 0x200, 0x001, 0x008,\n+\t0x364, 0x2cf, 0x007, 0x029, 0x1dc, 0x007, 0x287, 0x385,\n+\t0x300, 0x208, 0x001, 0x04b, 0x364, 0x33b, 0x010, 0x029,\n+\t0x1dc, 0x007, 0x3c5, 0x002, 0x00c, 0x287, 0x384, 0x0ff,\n+\t0x305, 0x21d, 0x1b7, 0x2e4, 0x001, 0x001, 0x01d, 0x040,\n+\t0x384, 0x007, 0x117, 0x001, 0x00c, 0x3c5, 0x040, 0x02d,\n+\t0x081, 0x044, 0x189, 0x000, 0x3c4, 0x3bf, 0x02d, 0x042,\n+\t0x247, 0x029, 0x364, 0x018, 0x001, 0x009, 0x005, 0x3c5,\n+\t0x010, 0x021, 0x2e4, 0x002, 0x001, 0x017, 0x264, 0x080,\n+\t0x001, 0x005, 0x0a4, 0x1a7, 0x285, 0x040, 0x3c5, 0x080,\n+\t0x02d, 0x081, 0x044, 0x189, 0x000, 0x3c4, 0x37f, 0x02d,\n+\t0x042, 0x247, 0x02a, 0x000, 0x014, 0x38e, 0x3ff, 0x1b8,\n+\t0x00a, 0x00a, 0x244, 0x029, 0x3c4, 0x3ef, 0x021, 0x3c4,\n+\t0x3fd, 0x00c, 0x120, 0x001, 0x004, 0x244, 0x02a, 0x020,\n+\t0x181, 0x006, 0x364, 0x23f, 0x003, 0x009, 0x007, 0x044,\n+\t0x340, 0x001, 0x247, 0x249, 0x054, 0x347, 0x249, 0x248,\n+\t0x2c7, 0x23f, 0x083, 0x18a, 0x385, 0x018, 0x364, 0x23f,\n+\t0x001, 0x001, 0x006, 0x245, 0x057, 0x000, 0x005, 0x208,\n+\t0x244, 0x057, 0x087, 0x18c, 0x385, 0x0e0, 0x364, 0x23f,\n+\t0x002, 0x001, 0x009, 0x245, 0x057, 0x044, 0x27d, 0x001,\n+\t0x000, 0x005, 0x208, 0x244, 0x057, 0x020, 0x181, 0x006,\n+\t0x04e, 0x0ce, 0x045, 0x03c, 0x0f5, 0x04e, 0x0fd, 0x07e,\n+\t0x00a, 0x0f9\n+\n+};  /* end fm10000_serdes_swap_code_prd2 */\ndiff --git a/drivers/net/fm10k/switch/fm10k_spico_code.h b/drivers/net/fm10k/switch/fm10k_spico_code.h\nnew file mode 100644\nindex 0000000..c172638\n--- /dev/null\n+++ b/drivers/net/fm10k/switch/fm10k_spico_code.h\n@@ -0,0 +1,21 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019   Silicom Ltd. Connectivity Solutions\n+ */\n+\n+#ifndef _FM10K_SPICO_CODE_H_\n+#define _FM10K_SPICO_CODE_H_\n+#include <stdint.h>\n+\n+extern const uint32_t fm10000_sbus_master_code_version_build_id_prd;\n+extern const uint32_t fm10000_sbus_master_code_size_prd;\n+extern const uint16_t fm10000_sbus_master_code_prd[];\n+\n+extern const uint32_t fm10000_serdes_spico_code_version_build_id_prd2;\n+extern const uint32_t fm10000_serdes_spico_code_size_prd2;\n+extern const uint16_t fm10000_serdes_spico_code_prd2[];\n+\n+extern const uint32_t fm10000_serdes_swap_code_version_build_id_prd2;\n+extern const uint32_t fm10000_serdes_swap_code_size_prd2;\n+extern const uint16_t fm10000_serdes_swap_code_prd2[];\n+\n+#endif /* _FM10K_SPICO_CODE_H_ */\n",
    "prefixes": [
        "v1",
        "2/5"
    ]
}