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{
    "id": 66130,
    "url": "http://patches.dpdk.org/api/patches/66130/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1582879102-17977-2-git-send-email-xiaojun.liu@silicom.co.il/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1582879102-17977-2-git-send-email-xiaojun.liu@silicom.co.il>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1582879102-17977-2-git-send-email-xiaojun.liu@silicom.co.il",
    "date": "2020-02-28T08:38:18",
    "name": "[v1,1/5] net/fm10k: add basic functions for switch management",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "0e6d259f008878c4a0d5e7b72ce084ef41aba602",
    "submitter": {
        "id": 1512,
        "url": "http://patches.dpdk.org/api/people/1512/?format=api",
        "name": "Xiaojun Liu",
        "email": "xiaojun.liu@silicom.co.il"
    },
    "delegate": {
        "id": 31221,
        "url": "http://patches.dpdk.org/api/users/31221/?format=api",
        "username": "yexl",
        "first_name": "xiaolong",
        "last_name": "ye",
        "email": "xiaolong.ye@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1582879102-17977-2-git-send-email-xiaojun.liu@silicom.co.il/mbox/",
    "series": [
        {
            "id": 8723,
            "url": "http://patches.dpdk.org/api/series/8723/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8723",
            "date": "2020-02-28T08:38:17",
            "name": "support fm10k switch management",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/8723/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/66130/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/66130/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Xiaojun Liu <xiaojun.liu@silicom.co.il>",
        "To": "xiao.w.wang@intel.com, qi.z.zhang@intel.com, ngai-mint.kwan@intel.com,\n jacob.e.keller@intel.com",
        "Cc": "dev@dpdk.org,\n\tXiaojun Liu <xiaojun.liu@silicom.co.il>",
        "Date": "Fri, 28 Feb 2020 16:38:18 +0800",
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        "References": "<1582207174-31037-2-git-send-email-xiaojun.liu@silicom.co.il>\n <1582879102-17977-1-git-send-email-xiaojun.liu@silicom.co.il>",
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        "Subject": "[dpdk-dev] [PATCH v1 1/5] net/fm10k: add basic functions for switch\n\tmanagement",
        "X-BeenThere": "dev@dpdk.org",
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        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org",
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    },
    "content": "Add I2C to control the inside LED and PHY.\nAll the operations of I2C are using fm10k I2C register.\nAdd SBUS to communicate with spico(micro code in serdes)\nby using fm10k SBUS register. This is like I2C operations.\nAdd registers defination, which include all the registers\nwill be used in the driver. Add switch management log API.\nAdd switch management structures. Modify Makefile to add\nnew files building. Add CONFIG_RTE_FM10K_MANAGEMENT=n\nin config/common_linux.\n\nTo enable the switch management, you need add\nCONFIG_RTE_FM10K_MANAGEMENT=y in\nconfig/common_linux when building.\n\nSigned-off-by: Xiaojun Liu <xiaojun.liu@silicom.co.il>\n---\n config/common_linux                     |    7 +\n drivers/net/fm10k/Makefile              |   14 +\n drivers/net/fm10k/switch/fm10k_debug.h  |   19 +\n drivers/net/fm10k/switch/fm10k_i2c.c    |  310 +++++\n drivers/net/fm10k/switch/fm10k_i2c.h    |   54 +\n drivers/net/fm10k/switch/fm10k_regs.h   | 2302 +++++++++++++++++++++++++++++++\n drivers/net/fm10k/switch/fm10k_sbus.c   |  292 ++++\n drivers/net/fm10k/switch/fm10k_sbus.h   |   40 +\n drivers/net/fm10k/switch/fm10k_switch.h |  335 +++++\n 9 files changed, 3373 insertions(+)\n create mode 100644 drivers/net/fm10k/switch/fm10k_debug.h\n create mode 100644 drivers/net/fm10k/switch/fm10k_i2c.c\n create mode 100644 drivers/net/fm10k/switch/fm10k_i2c.h\n create mode 100644 drivers/net/fm10k/switch/fm10k_regs.h\n create mode 100644 drivers/net/fm10k/switch/fm10k_sbus.c\n create mode 100644 drivers/net/fm10k/switch/fm10k_sbus.h\n create mode 100644 drivers/net/fm10k/switch/fm10k_switch.h",
    "diff": "diff --git a/config/common_linux b/config/common_linux\nindex 8168106..75a4fa8 100644\n--- a/config/common_linux\n+++ b/config/common_linux\n@@ -66,3 +66,10 @@ CONFIG_RTE_LIBRTE_HINIC_PMD=y\n # Hisilicon HNS3 PMD driver\n #\n CONFIG_RTE_LIBRTE_HNS3_PMD=y\n+\n+#\n+# FM10K switch management\n+#\n+CONFIG_RTE_FM10K_MANAGEMENT=n\n+\n+\ndiff --git a/drivers/net/fm10k/Makefile b/drivers/net/fm10k/Makefile\nindex 29e659d..15ea187 100644\n--- a/drivers/net/fm10k/Makefile\n+++ b/drivers/net/fm10k/Makefile\n@@ -11,6 +11,9 @@ LIB = librte_pmd_fm10k.a\n CFLAGS += -O3\n CFLAGS += $(WERROR_FLAGS)\n CFLAGS += -DALLOW_EXPERIMENTAL_API\n+ifeq ($(CONFIG_RTE_FM10K_MANAGEMENT),y)\n+CFLAGS += -DENABLE_FM10K_MANAGEMENT\n+endif\n \n EXPORT_MAP := rte_pmd_fm10k_version.map\n \n@@ -49,6 +52,9 @@ endif\n LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring\n LDLIBS += -lrte_ethdev -lrte_net -lrte_kvargs -lrte_hash\n LDLIBS += -lrte_bus_pci\n+ifeq ($(CONFIG_RTE_FM10K_MANAGEMENT),y)\n+LDLIBS += -lpthread\n+endif\n \n #\n # Add extra flags for base driver source files to disable warnings in them\n@@ -58,6 +64,10 @@ $(foreach obj, $(BASE_DRIVER_OBJS), $(eval CFLAGS_$(obj)+=$(CFLAGS_BASE_DRIVER))\n \n VPATH += $(SRCDIR)/base\n \n+ifeq ($(CONFIG_RTE_FM10K_MANAGEMENT),y)\n+VPATH += $(SRCDIR)/switch\n+endif\n+\n #\n # all source are stored in SRCS-y\n # base driver is based on the package of cid-fm10k.2017.01.24.tar.gz\n@@ -71,6 +81,10 @@ SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_common.c\n SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_mbx.c\n SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_vf.c\n SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_api.c\n+ifeq ($(CONFIG_RTE_FM10K_MANAGEMENT),y)\n+SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_i2c.c\n+SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_sbus.c\n+endif\n ifeq ($(CONFIG_RTE_ARCH_X86), y)\n SRCS-$(CONFIG_RTE_LIBRTE_FM10K_INC_VECTOR) += fm10k_rxtx_vec.c\n endif\ndiff --git a/drivers/net/fm10k/switch/fm10k_debug.h b/drivers/net/fm10k/switch/fm10k_debug.h\nnew file mode 100644\nindex 0000000..f7b5c06\n--- /dev/null\n+++ b/drivers/net/fm10k/switch/fm10k_debug.h\n@@ -0,0 +1,19 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019   Silicom Ltd. Connectivity Solutions\n+ */\n+\n+#ifndef _FM10K_DEBUG_H_\n+#define _FM10K_DEBUG_H_\n+\n+\n+#define FM10K_SW_ERR(...)\t\tPMD_INIT_LOG(ERR, __VA_ARGS__)\n+#define FM10K_SW_INFO(...)\t\tPMD_INIT_LOG(INFO, __VA_ARGS__)\n+#define FM10K_SW_TRACE(...)\t\tPMD_INIT_LOG(DEBUG, __VA_ARGS__)\n+\n+#define FM10K_SW_ASSERT(...)\t\tdo {} while (0)\n+\n+#define FM10K_SW_STATS_TRACE_ENABLE\t1\n+#define FM10K_SW_FFU_CONF_TRACE_ENABLE\t0\n+#define FM10K_SW_MIRROR_TRACE_ENABLE\t0\n+\n+#endif /* _FM10K_DEBUG_H_ */\ndiff --git a/drivers/net/fm10k/switch/fm10k_i2c.c b/drivers/net/fm10k/switch/fm10k_i2c.c\nnew file mode 100644\nindex 0000000..28b0c34\n--- /dev/null\n+++ b/drivers/net/fm10k/switch/fm10k_i2c.c\n@@ -0,0 +1,310 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019   Silicom Ltd. Connectivity Solutions\n+ */\n+\n+#include <rte_malloc.h>\n+\n+#include <rte_time.h>\n+#include <rte_kvargs.h>\n+#include <rte_hash.h>\n+#include <rte_flow.h>\n+#include <rte_flow_driver.h>\n+#include <rte_tm_driver.h>\n+\n+#include \"fm10k_debug.h\"\n+#include \"fm10k_i2c.h\"\n+#include \"fm10k_regs.h\"\n+#include \"fm10k_switch.h\"\n+\n+static void fm10k_i2c_init(struct fm10k_i2c *);\n+\n+struct fm10k_i2c *\n+fm10k_i2c_attach(struct fm10k_switch *sw)\n+{\n+\tstruct fm10k_i2c *i2c;\n+\n+\tFM10K_SW_TRACE(\"i2c: attaching\");\n+\n+\ti2c = (struct fm10k_i2c *)rte_zmalloc(\"fm10k_i2c\",\n+\t\t\tsizeof(struct fm10k_i2c), 0);\n+\tif (i2c == NULL) {\n+\t\tFM10K_SW_INFO(\"i2c: failed to allocate context\");\n+\t\tgoto fail;\n+\t}\n+\n+\ti2c->sw = sw;\n+\tpthread_mutex_init(&i2c->req_lock, NULL);\n+\tpthread_mutex_init(&i2c->bus_lock, NULL);\n+\tsem_init(&i2c->req_cv, 0, 0);\n+\n+\tfm10k_i2c_init(i2c);\n+\n+\tFM10K_SW_TRACE(\"i2c: attach successful\");\n+\treturn i2c;\n+fail:\n+\tif (i2c)\n+\t\tfm10k_i2c_detach(i2c);\n+\treturn NULL;\n+}\n+\n+void\n+fm10k_i2c_detach(struct fm10k_i2c *i2c)\n+{\n+\tFM10K_SW_TRACE(\"i2c: detaching\");\n+\n+\trte_free(i2c);\n+}\n+\n+static void\n+fm10k_i2c_init(struct fm10k_i2c *i2c)\n+{\n+\tstruct fm10k_switch *sw = i2c->sw;\n+\tstruct fm10k_device_info *cfg = sw->info;\n+\tuint32_t freq = FM10K_SW_I2C_CFG_DIVIDER_400_KHZ;\n+\tuint32_t data;\n+\n+\tif (FM10K_SW_CARD_ID(cfg->subvendor, cfg->subdevice) ==\n+\t\t\tFM10K_SW_CARD(SILICOM, PE3100G2DQIRM_QXSL4))\n+\t\tfreq = FM10K_SW_I2C_CFG_DIVIDER_100_KHZ;\n+\n+\t/* clear any pending interrupt */\n+\tfm10k_write_switch_reg(sw, FM10K_SW_I2C_CTRL,\n+\t\tFM10K_SW_I2C_CTRL_INTERRUPT_PENDING);\n+\n+\t/* 400 KHz, master mode, unmask interrupt */\n+\tdata = fm10k_read_switch_reg(sw, FM10K_SW_I2C_CFG);\n+\tdata &= ~FM10K_SW_I2C_CFG_SLAVE_ENABLE;\n+\tif (FM10K_SW_CARD_ID(cfg->subvendor, cfg->subdevice) ==\n+\t\t\tFM10K_SW_CARD(SILICOM, PE3100G2DQIRM_QXSL4))\n+\t\tFM10K_SW_REPLACE_REG_FIELD(data, I2C_CFG_DIVIDER, freq, data);\n+\tdata &=  ~FM10K_SW_I2C_CFG_INTERRUPT_MASK;\n+\tfm10k_write_switch_reg(sw, FM10K_SW_I2C_CFG, data);\n+\n+\tif (FM10K_SW_CARD_ID(cfg->subvendor, cfg->subdevice) ==\n+\t\t\tFM10K_SW_CARD(SILICOM, PE3100G2DQIRM_QXSL4))\n+\t\t/* reset I2C */\n+\t\tfm10k_gpio_output_set(sw, 5, 1);\n+}\n+\n+unsigned int\n+fm10k_i2c_intr(struct fm10k_i2c *i2c)\n+{\n+\tstruct fm10k_switch *sw = i2c->sw;\n+\tstruct fm10k_i2c_req *req;\n+\tint i;\n+\tuint32_t data[3];\n+\tuint32_t ctrl;\n+\n+\treq = i2c->cur_req;\n+\n+\tFM10K_SW_SWITCH_LOCK(sw);\n+\tctrl = fm10k_read_switch_reg(sw, FM10K_SW_I2C_CTRL);\n+\tfm10k_write_switch_reg(sw, FM10K_SW_I2C_CTRL,\n+\t    FM10K_SW_I2C_CTRL_INTERRUPT_PENDING);\n+\n+\treq->status = FM10K_SW_REG_FIELD(ctrl, I2C_CTRL_COMMAND_COMPLETED);\n+\n+\tif ((req->cmd == FM10K_SW_I2C_COMMAND_RD ||\n+\t\t\treq->cmd == FM10K_SW_I2C_COMMAND_WR_RD) &&\n+\t\t\treq->status == FM10K_SW_I2C_COMPLETION_NORMAL) {\n+\t\tfor (i = 0; i < FM10K_SW_HOWMANY(req->read_len, 4, 4); i++)\n+\t\t\tdata[i] = fm10k_read_switch_reg\n+\t\t\t\t\t\t(sw, FM10K_SW_I2C_DATA(i));\n+\n+\t\tfor (i = 0; i < req->read_len; i++)\n+\t\t\treq->msg[i] =\n+\t\t\t\t(data[i / 4] >> (24 - (i % 4) * 8)) & 0xff;\n+\t}\n+\tFM10K_SW_SWITCH_UNLOCK(sw);\n+\tsem_post(&i2c->req_cv);\n+\n+\treturn 1;\n+}\n+\n+int\n+fm10k_i2c_exec(struct fm10k_i2c *i2c, struct fm10k_i2c_req *req)\n+{\n+\tstruct fm10k_switch *sw = i2c->sw;\n+\tint i;\n+\tuint32_t ctrl;\n+\tuint32_t data[3];\n+\n+\tif (((req->cmd == FM10K_SW_I2C_COMMAND_WR ||\n+\t\t    req->cmd == FM10K_SW_I2C_COMMAND_WR_RD) &&\n+\t\treq->write_len > FM10K_SW_I2C_MSG_MAX) ||\n+\t    ((req->cmd == FM10K_SW_I2C_COMMAND_RD ||\n+\t\treq->cmd == FM10K_SW_I2C_COMMAND_WR_RD) &&\n+\t\t((req->read_len == 0  ||\n+\t\t    req->read_len > FM10K_SW_I2C_MSG_MAX))))\n+\t\treturn (-1);\n+\n+\tFM10K_SW_TRACE(\"i2c: initiating command %u\", req->cmd);\n+\n+\tctrl =\n+\t    FM10K_SW_MAKE_REG_FIELD(I2C_CTRL_ADDR, req->addr << 1) |\n+\t    FM10K_SW_MAKE_REG_FIELD(I2C_CTRL_COMMAND, req->cmd);\n+\n+\tif (req->cmd == FM10K_SW_I2C_COMMAND_WR ||\n+\t\t\treq->cmd == FM10K_SW_I2C_COMMAND_WR_RD) {\n+\t\tctrl |= FM10K_SW_MAKE_REG_FIELD\n+\t\t\t\t(I2C_CTRL_LENGTH_W, req->write_len);\n+\n+\t\tdata[0] = 0;\n+\t\tdata[1] = 0;\n+\t\tdata[2] = 0;\n+\n+\t\tfor (i = 0; i < req->write_len; i++)\n+\t\t\tdata[i / 4] |= req->msg[i] << (24 - (i % 4) * 8);\n+\n+\t\tfor (i = 0; i < FM10K_SW_HOWMANY(req->write_len, 4, 4); i++)\n+\t\t\tfm10k_write_switch_reg(sw,\n+\t\t\t\t\tFM10K_SW_I2C_DATA(i), data[i]);\n+\t}\n+\n+\tif (req->cmd == FM10K_SW_I2C_COMMAND_RD ||\n+\t    req->cmd == FM10K_SW_I2C_COMMAND_WR_RD)\n+\t\tctrl |= FM10K_SW_MAKE_REG_FIELD\n+\t\t\t\t(I2C_CTRL_LENGTH_R, req->read_len);\n+\n+\treq->status = FM10K_SW_I2C_COMPLETION_RUNNING;\n+\ti2c->cur_req = req;\n+\n+\tFM10K_SW_SWITCH_LOCK(sw);\n+\t/* zero command field */\n+\tfm10k_write_switch_reg(sw, FM10K_SW_I2C_CTRL, 0);\n+\t/* initiate command */\n+\tfm10k_write_switch_reg(sw, FM10K_SW_I2C_CTRL, ctrl);\n+\tFM10K_SW_SWITCH_UNLOCK(sw);\n+\n+\twhile (req->status == FM10K_SW_I2C_COMPLETION_RUNNING)\n+\t\tsem_wait(&i2c->req_cv);\n+\n+\treturn 0;\n+}\n+\n+int\n+fm10k_i2c_read8(struct fm10k_i2c *i2c, uint8_t addr, uint8_t *result)\n+{\n+\tstruct fm10k_i2c_req req;\n+\tint error;\n+\n+\treq.addr = addr;\n+\treq.cmd = FM10K_SW_I2C_COMMAND_RD;\n+\treq.read_len = 1;\n+\treq.msg[0] = 0;\n+\n+\terror = fm10k_i2c_exec(i2c, &req);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tif (req.status != FM10K_SW_I2C_COMPLETION_NORMAL) {\n+\t\tFM10K_SW_INFO(\"i2c read failed (%u)\", req.status);\n+\t\terror = -1;\n+\t\tgoto done;\n+\t}\n+\n+\t*result = req.msg[0];\n+\n+done:\n+\treturn (error);\n+}\n+\n+int\n+fm10k_i2c_read8_ext(struct fm10k_i2c *i2c,\n+\t\tuint8_t addr, uint8_t reg, uint8_t *result)\n+{\n+\tstruct fm10k_i2c_req req;\n+\tint error;\n+\n+\treq.addr = addr;\n+\treq.cmd = FM10K_SW_I2C_COMMAND_WR_RD;\n+\treq.write_len = 1;\n+\treq.read_len = 1;\n+\treq.msg[0] = reg;\n+\n+\terror = fm10k_i2c_exec(i2c, &req);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tif (req.status != FM10K_SW_I2C_COMPLETION_NORMAL) {\n+\t\tFM10K_SW_INFO(\"i2c read failed (%u)\", req.status);\n+\t\terror = -1;\n+\t\tgoto done;\n+\t}\n+\n+\t*result = req.msg[0];\n+done:\n+\treturn (error);\n+}\n+\n+int\n+fm10k_i2c_write8(struct fm10k_i2c *i2c, uint8_t addr, uint8_t data)\n+{\n+\tstruct fm10k_i2c_req req;\n+\tint error;\n+\n+\treq.addr = addr;\n+\treq.cmd = FM10K_SW_I2C_COMMAND_WR;\n+\treq.write_len = 1;\n+\treq.msg[0] = data;\n+\n+\terror = fm10k_i2c_exec(i2c, &req);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tif (req.status != FM10K_SW_I2C_COMPLETION_NORMAL) {\n+\t\terror = -1;\n+\t\tgoto done;\n+\t}\n+\n+done:\n+\treturn (error);\n+}\n+\n+int\n+fm10k_i2c_write16(struct fm10k_i2c *i2c,\n+\t\tuint8_t addr, uint8_t data0, uint8_t data1)\n+{\n+\tstruct fm10k_i2c_req req;\n+\tint error;\n+\n+\treq.addr = addr;\n+\treq.cmd = FM10K_SW_I2C_COMMAND_WR;\n+\treq.write_len = 2;\n+\treq.msg[0] = data0;\n+\treq.msg[1] = data1;\n+\n+\terror = fm10k_i2c_exec(i2c, &req);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tif (req.status != FM10K_SW_I2C_COMPLETION_NORMAL) {\n+\t\terror = -1;\n+\t\tgoto done;\n+\t}\n+done:\n+\treturn (error);\n+}\n+\n+int\n+fm10k_i2c_probe(struct fm10k_i2c *i2c, uint8_t addr)\n+{\n+\tstruct fm10k_i2c_req req;\n+\tint error;\n+\n+\treq.addr = addr;\n+\treq.cmd = FM10K_SW_I2C_COMMAND_WR;\n+\treq.write_len = 0;\n+\n+\terror = fm10k_i2c_exec(i2c, &req);\n+\tif (error)\n+\t\tgoto done;\n+\n+\tif (req.status != FM10K_SW_I2C_COMPLETION_NORMAL) {\n+\t\terror = -1;\n+\t\tgoto done;\n+\t}\n+\n+done:\n+\treturn (error);\n+}\ndiff --git a/drivers/net/fm10k/switch/fm10k_i2c.h b/drivers/net/fm10k/switch/fm10k_i2c.h\nnew file mode 100644\nindex 0000000..f835afe\n--- /dev/null\n+++ b/drivers/net/fm10k/switch/fm10k_i2c.h\n@@ -0,0 +1,54 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019   Silicom Ltd. Connectivity Solutions\n+ */\n+\n+#ifndef _FM10K_SW_I2C_H_\n+#define _FM10K_SW_I2C_H_\n+\n+#include <semaphore.h>\n+#include <pthread.h>\n+#include \"rte_spinlock.h\"\n+#include \"fm10k_debug.h\"\n+\n+#define FM10K_SW_I2C_MSG_MAX\t12\n+\n+struct fm10k_i2c_req {\n+\tuint8_t addr; /* 7-bit address */\n+\tuint8_t cmd;  /* FM10K_SW_I2C_COMMAND_* */\n+\tuint8_t write_len;\n+\tuint8_t read_len;\n+\tuint8_t status; /* FM10K_SW_I2C_COMPLETION_ */\n+\tuint8_t msg[FM10K_SW_I2C_MSG_MAX];\n+};\n+\n+struct fm10k_i2c {\n+\tstruct fm10k_switch *sw;\n+\tpthread_mutex_t bus_lock;\n+\tpthread_mutex_t req_lock;\n+\tsem_t req_cv;\n+\tstruct fm10k_i2c_req *cur_req;\n+};\n+\n+#define FM10K_SW_I2C_LOCK(i2c_)\t\\\n+\tpthread_mutex_lock(&(i2c_)->bus_lock)\n+#define FM10K_SW_I2C_UNLOCK(i2c_)\t\\\n+\tpthread_mutex_unlock(&(i2c_)->bus_lock)\n+\n+#define FM10K_SW_I2C_REQ_LOCK(i2c_)\t\\\n+\t\t\tpthread_mutex_lock(&((i2c_)->req_lock))\n+#define FM10K_SW_I2C_REQ_UNLOCK(i2c_) \\\n+\t\t\tpthread_mutex_unlock(&((i2c_)->req_lock))\n+\n+struct fm10k_i2c *fm10k_i2c_attach(struct fm10k_switch *sw);\n+void fm10k_i2c_detach(struct fm10k_i2c *i2c);\n+unsigned int fm10k_i2c_intr(struct fm10k_i2c *i2c);\n+int fm10k_i2c_exec(struct fm10k_i2c *i2c, struct fm10k_i2c_req *req);\n+int fm10k_i2c_read8(struct fm10k_i2c *i2c, uint8_t addr, uint8_t *result);\n+int fm10k_i2c_read8_ext(struct fm10k_i2c *i2c,\n+\t\t\t\tuint8_t addr, uint8_t reg, uint8_t *result);\n+int fm10k_i2c_write8(struct fm10k_i2c *i2c, uint8_t addr, uint8_t data);\n+int fm10k_i2c_write16(struct fm10k_i2c *i2c,\n+\t\t\t\tuint8_t addr, uint8_t data0, uint8_t data1);\n+int fm10k_i2c_probe(struct fm10k_i2c *i2c, uint8_t addr);\n+\n+#endif /* _FM10K_SW_I2C_H_ */\ndiff --git a/drivers/net/fm10k/switch/fm10k_regs.h b/drivers/net/fm10k/switch/fm10k_regs.h\nnew file mode 100644\nindex 0000000..2663773\n--- /dev/null\n+++ b/drivers/net/fm10k/switch/fm10k_regs.h\n@@ -0,0 +1,2302 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019   Silicom Ltd. Connectivity Solutions\n+ */\n+\n+#ifndef _FM10K_REGS_H_\n+#define _FM10K_REGS_H_\n+\n+#include <stdint.h>\n+\n+\n+/* Convert a 32-bit word offset into a byte offset */\n+#define FM10K_SW_REG_OFF(wo_)\t\t\t(wo_)\n+#define FM10K_SW_MASK32(max_bit_, min_bit_)\t\\\n+\t\t((0xffffffffU << (min_bit_)) & \\\n+\t\t(0xffffffffU >> (31 - (max_bit_))))\n+#define FM10K_SW_REG_FIELD(r_, name_)\t\t\\\n+\t\t(((uint32_t)(r_) & \\\n+\t\tFM10K_SW_MASK32(FM10K_SW_##name_##_msb, \\\n+\t\tFM10K_SW_##name_##_lsb)) >> FM10K_SW_##name_##_lsb)\n+#define FM10K_SW_REG_FIELD_IDX(r_, name_, i_, i1_, i2_)\t\\\n+\t\t(((uint32_t)(r_) & \\\n+\t\tFM10K_SW_MASK32(FM10K_SW_##name_##_msb(i_), \\\n+\t\tFM10K_SW_##name_##_lsb(i2_))) >> \\\n+\t\tFM10K_SW_##name_##_lsb(i3_))\n+#define FM10K_SW_MAKE_REG_FIELD(name_, v_)\t\\\n+\t\t(((uint32_t)(v_) << FM10K_SW_##name_##_lsb) & \\\n+\t\tFM10K_SW_MASK32(FM10K_SW_##name_##_msb, \\\n+\t\tFM10K_SW_##name_##_lsb))\n+#define FM10K_SW_MAKE_REG_FIELD_IDX(name_, i_, v_, i1_, i2_)\t\\\n+\t\t(((uint32_t)(v_) << FM10K_SW_##name_##_lsb(i_)) & \\\n+\t\tFM10K_SW_MASK32(FM10K_SW_##name_##_msb(i1_), \\\n+\t\tFM10K_SW_##name_##_lsb(i2_)))\n+#define FM10K_SW_REPLACE_REG_FIELD(r_, name_, v_, r1_)\t\\\n+\t\t(r_ = (((r1_) & \\\n+\t\t~FM10K_SW_MASK32(FM10K_SW_##name_##_msb, \\\n+\t\tFM10K_SW_##name_##_lsb)) | \\\n+\t\tFM10K_SW_MAKE_REG_FIELD(name_, v_)))\n+#define FM10K_SW_REPLACE_REG_FIELD_IDX(r_, name_, i_, v_, r1_, i1_, i2_) \\\n+\t\t(r_ = (((r1_) & \\\n+\t\t~FM10K_SW_MASK32(FM10K_SW_##name_##_msb(i1_), \\\n+\t\tFM10K_SW_##name_##_lsb(i2_))) | \\\n+\t\tFM10K_SW_MAKE_REG_FIELD_IDX(name_, i_, v_)))\n+#define FM10K_SW_MASK64(max_bit_, min_bit_)\t\t\\\n+\t\t((0xffffffffffffffffULL << (min_bit_)) & \\\n+\t\t(0xffffffffffffffffULL >> (63 - (max_bit_))))\n+#define FM10K_SW_REG_FIELD64(r_, name_)\t\t\\\n+\t\t(((uint64_t)(r_) & \\\n+\t\tFM10K_SW_MASK64(FM10K_SW_##name_##_msb64, \\\n+\t\tFM10K_SW_##name_##_lsb64)) >> \\\n+\t\tFM10K_SW_##name_##_lsb64)\n+#define FM10K_SW_REG_FIELD_IDX64(r_, name_, i_, i1_, i2_)\t\\\n+\t\t(((uint64_t)(r_) & \\\n+\t\tFM10K_SW_MASK64(FM10K_SW_##name_##_msb64(i_), \\\n+\t\tFM10K_SW_##name_##_lsb64(i1_))) >> \\\n+\t\tFM10K_SW_##name_##_lsb64(i2_))\n+#define FM10K_SW_MAKE_REG_FIELD64(name_, v_)\t\t\\\n+\t\t(((uint64_t)(v_) << FM10K_SW_##name_##_lsb64) & \\\n+\t\tFM10K_SW_MASK64(FM10K_SW_##name_##_msb64, \\\n+\t\tFM10K_SW_##name_##_lsb64))\n+#define FM10K_SW_MAKE_REG_FIELD_IDX64(name_, i_, v_, i1_, i2_)\t\\\n+\t\t(((uint64_t)(v_) << FM10K_SW_##name_##_lsb64(i_)) & \\\n+\t\tFM10K_SW_MASK64(FM10K_SW_##name_##_msb64(i1_), \\\n+\t\tFM10K_SW_##name_##_lsb64(i2_)))\n+#define FM10K_SW_REPLACE_REG_FIELD64(r_, name_, v_, r1_)\t\\\n+\t\t(r_ = (((r1_) & \\\n+\t\t~FM10K_SW_MASK64(FM10K_SW_##name_##_msb64, \\\n+\t\tFM10K_SW_##name_##_lsb64)) | \\\n+\t\tFM10K_SW_MAKE_REG_FIELD64(name_, v_)))\n+#define FM10K_SW_REPLACE_REG_FIELD_IDX64(r_, name_, i_, v_, r1_, i1_, i2_) \\\n+\t\t(r_ = (((r1_) & \\\n+\t\t~FM10K_SW_MASK64(FM10K_SW_##name_##_msb64(i1_), \\\n+\t\tFM10K_SW_##name_##_lsb64(i2_))) | \\\n+\t\tFM10K_SW_MAKE_REG_FIELD_IDX64(name_, i_, v_)))\n+\n+/* These operate on arrays of 32-bit words */\n+#define FM10K_SW_SET_ARRAY_BIT(a_, name_, b_, a1_)\t\\\n+\t\t((a_)[FM10K_SW_##name_##_bit / 32] = \\\n+\t\t((a1_)[FM10K_SW_##name_##_bit / 32] & \\\n+\t\t~(1 << (FM10K_SW_##name_##_bit % 32))) | \\\n+\t\t(((b_) & 0x1) << (FM10K_SW_##name_##_bit % 32)))\n+\n+/* Does not support fields that cross 32-bit boundaries */\n+#define FM10K_SW_MAKE_ARRAY_FIELD(name_, v_)\t\t\\\n+\t\t(((uint32_t)(v_) << (FM10K_SW_##name_##_lsb % 32)) & \\\n+\t\tFM10K_SW_MASK32(FM10K_SW_##name_##_msb % 32, \\\n+\t\tFM10K_SW_##name_##_lsb % 32))\n+\n+/* Does not support fields that cross 32-bit boundaries */\n+#define FM10K_SW_REPLACE_ARRAY_FIELD(a_, name_, v_, a1_)\t\\\n+\t\t((a_)[FM10K_SW_##name_##_lsb / 32] = \\\n+\t\t(((a1_)[FM10K_SW_##name_##_lsb / 32] & \\\n+\t\t~FM10K_SW_MASK32(FM10K_SW_##name_##_msb % 32, \\\n+\t\tFM10K_SW_##name_##_lsb % 32)) | \\\n+\t\tFM10K_SW_MAKE_ARRAY_FIELD(name_, v_)))\n+\n+\n+/*\n+ * BAR0 registers\n+ */\n+/* Interrupt throttle timer selection values */\n+#define\tFM10K_SW_INT_TIMER_0\t\t\t0\n+#define\tFM10K_SW_INT_TIMER_1\t\t\t1\n+#define\tFM10K_SW_INT_TIMER_IMMEDIATE\t\t2\n+#define\tFM10K_SW_INT_TIMER_DISABLED\t\t3\n+\n+#define FM10K_SW_CTRL\t\t\t\tFM10K_SW_REG_OFF(0x0)\n+#define\tFM10K_SW_CTRL_BAR4_ALLOWED\t\t(1 << 2)\n+#define FM10K_SW_CTRL_EXT\t\t\tFM10K_SW_REG_OFF(0x1)\n+#define FM10K_SW_CTRL_EXT_NS_DIS\t\t(1 << 0)\n+#define\tFM10K_SW_CTRL_EXT_RO_DIS\t\t(1 << 1)\n+#define\tFM10K_SW_CTRL_EXT_SWITCH_LOOPBACK\t(1 << 2)\n+#define FM10K_SW_EXVET\t\t\t\tFM10K_SW_REG_OFF(0x2)\n+#define FM10K_SW_GCR\t\t\t\tFM10K_SW_REG_OFF(0x3)\n+#define FM10K_SW_FACTPS\t\t\t\tFM10K_SW_REG_OFF(0x4)\n+#define FM10K_SW_GCR_EXT\t\t\tFM10K_SW_REG_OFF(0x5)\n+#define FM10K_SW_EICR\t\t\t\tFM10K_SW_REG_OFF(0x6)\n+#define\tFM10K_SW_EICR_PCA_FAULT_SHIFT\t\t0\n+#define\tFM10K_SW_EICR_PCA_FAULT\t\t\t\\\n+\t\t(1 << FM10K_SW_EICR_PCA_FAULT_SHIFT)\n+#define\tFM10K_SW_EICR_THI_FAULT_SHIFT\t\t2\n+#define\tFM10K_SW_EICR_THI_FAULT\t\t\t\\\n+\t\t(1 << FM10K_SW_EICR_THI_FAULT_SHIFT)\n+#define\tFM10K_SW_EICR_FUM_FAULT_SHIFT\t\t5\n+#define\tFM10K_SW_EICR_FUM_FAULT\t\t\t\\\n+\t\t(1 << FM10K_SW_EICR_FUM_FAULT_SHIFT)\n+#define\tFM10K_SW_EICR_MAILBOX_SHIFT\t\t6\n+#define\tFM10K_SW_EICR_MAILBOX\t\t\t\\\n+\t\t(1 << FM10K_SW_EICR_MAILBOX_SHIFT)\n+#define\tFM10K_SW_EICR_SWITCH_READY_SHIFT\t7\n+#define\tFM10K_SW_EICR_SWITCH_READY\t\t\\\n+\t\t(1 << FM10K_SW_EICR_SWITCH_READY_SHIFT)\n+#define\tFM10K_SW_EICR_SWITCH_NREADY_SHIFT\t8\n+#define\tFM10K_SW_EICR_SWITCH_NREADY\t\t\\\n+\t\t(1 << FM10K_SW_EICR_SWITCH_NREADY_SHIFT)\n+#define\tFM10K_SW_EICR_SWITCH_INT_SHIFT\t\t9\n+#define\tFM10K_SW_EICR_SWITCH_INT\t\t\\\n+\t\t(1 << FM10K_SW_EICR_SWITCH_INT_SHIFT)\n+#define\tFM10K_SW_EICR_SRAM_ERROR_SHIFT\t\t10\n+#define\tFM10K_SW_EICR_SRAM_ERROR\t\t\\\n+\t\t(1 << FM10K_SW_EICR_SRAM_ERROR_SHIFT)\n+#define\tFM10K_SW_EICR_VFLR_SHIFT\t\t11\n+#define\tFM10K_SW_EICR_VFLR\t\t\t\\\n+\t\t(1 << FM10K_SW_EICR_VFLR_SHIFT)\n+#define\tFM10K_SW_EICR_MAX_HOLD_TIME_SHIFT\t12\n+#define\tFM10K_SW_EICR_MAX_HOLD_TIME\t\t\\\n+\t\t(1 << FM10K_SW_EICR_MAX_HOLD_TIME_SHIFT)\n+#define FM10K_SW_EIMR\t\t\t\tFM10K_SW_REG_OFF(0x7)\n+#define\tFM10K_SW_EIMR_DISABLE_ALL\t\t0x55555555\n+#define\tFM10K_SW_EIMR_NO_CHANGE\t\t\t0x0\n+#define\tFM10K_SW_EIMR_DISABLE\t\t\t0x1\n+#define\tFM10K_SW_EIMR_ENABLE\t\t\t0x2\n+#define\tFM10K_SW_EIMR_FIELD(i_, v_)\t\t\\\n+\t\t(FM10K_SW_EIMR_##v_ << (FM10K_SW_EICR_##i_##_SHIFT * 2))\n+#define\tFM10K_SW_EIMR_ENABLED(e_, i_)\t\t\\\n+\t\t((((e_) >> (FM10K_SW_EICR_##i_##_SHIFT * 2)) & 0x3) == \\\n+\t\tFM10K_SW_EIMR_ENABLE)\n+#define FM10K_SW_PCA_FAULT\t\t\tFM10K_SW_REG_OFF(0x8)\n+#define FM10K_SW_THI_FAULT\t\t\tFM10K_SW_REG_OFF(0x10)\n+#define FM10K_SW_FUM_FAULT\t\t\tFM10K_SW_REG_OFF(0x1C)\n+#define FM10K_SW_MAXHOLDQ(n_)\t\t\tFM10K_SW_REG_OFF(0x20 + (n_))\n+#define\tFM10K_SW_MAXHOLDQ_ENTRIES\t\t8\n+#define FM10K_SW_SM_AREA\t\t\tFM10K_SW_REG_OFF(0x28)\n+#define FM10K_SW_DGLORTMAP(n_)\t\t\tFM10K_SW_REG_OFF(0x30 + (n_))\n+#define\tFM10K_SW_DGLORTMAP_ENTRIES\t\t8\n+#define\tFM10K_SW_DGLORTMAP_MATCH_ANY\t\t0x00000000\n+#define\tFM10K_SW_DGLORTMAP_MATCH_NONE\t\t0x0000ffff\n+#define\tFM10K_SW_DGLORTMAP_VALUE_lsb\t\t0\n+#define\tFM10K_SW_DGLORTMAP_VALUE_msb\t\t15\n+#define\tFM10K_SW_DGLORTMAP_MASK_lsb\t\t16\n+#define\tFM10K_SW_DGLORTMAP_MASK_msb\t\t31\n+#define FM10K_SW_DGLORTDEC(n_)\t\t\tFM10K_SW_REG_OFF(0x38 + (n_))\n+#define\tFM10K_SW_DGLORTDEC_Q_LENGTH_lsb\t\t0\n+#define\tFM10K_SW_DGLORTDEC_Q_LENGTH_msb\t\t3\n+#define\tFM10K_SW_DGLORTDEC_VSI_LENGTH_lsb\t4\n+#define\tFM10K_SW_DGLORTDEC_VSI_LENGTH_msb\t6\n+#define\tFM10K_SW_DGLORTDEC_VSI_BASE_lsb\t\t7\n+#define\tFM10K_SW_DGLORTDEC_VSI_BASE_msb\t\t13\n+#define\tFM10K_SW_DGLORTDEC_PC_LENGTH_lsb\t14\n+#define\tFM10K_SW_DGLORTDEC_PC_LENGTH_msb\t15\n+#define\tFM10K_SW_DGLORTDEC_Q_BASE_lsb\t\t16\n+#define\tFM10K_SW_DGLORTDEC_Q_BASE_msb\t\t23\n+#define\tFM10K_SW_DGLORTDEC_RSS_LENGTH_MAX\t7\n+#define\tFM10K_SW_DGLORTDEC_RSS_LENGTH_lsb\t24\n+#define\tFM10K_SW_DGLORTDEC_RSS_LENGTH_msb\t26\n+#define\tFM10K_SW_DGLORTDEC_INNTER_RSS\t\t(1 << 27)\n+#define FM10K_SW_TUNNEL_CFG\t\t\tFM10K_SW_REG_OFF(0x40)\n+#define FM10K_SW_SWPRI_MAP(pri_)\t\tFM10K_SW_REG_OFF(0x50 + (pri_))\n+#define FM10K_SW_RSSRK(f_, n_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x800 + 0x10 * (f_) + (n_))\n+#define FM10K_SW_RSSRK_ENTRIES\t\t\t10\n+#define FM10K_SW_RETA(f_, n_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x1000 + 0x20 * (f_) + (n_))\n+#define FM10K_SW_RETA_ENTRIES\t\t\t32\n+#define FM10K_SW_RETA_ENTRY(e0_, e1_, e2_, e3_)\t\\\n+\t\t(((e0_) & 0xff) | (((e1_) & 0xff) << 8) | \\\n+\t\t(((e2_) & 0xff) << 16) | (((e3_) & 0xff) << 24))\n+#define FM10K_SW_TC_CREDIT(g_)\t\t\tFM10K_SW_REG_OFF(0x2000 + (g_))\n+#define FM10K_SW_TC_MAXCREDIT(g_)\t\tFM10K_SW_REG_OFF(0x2040 + (g_))\n+#define FM10K_SW_TC_RATE(g_)\t\t\tFM10K_SW_REG_OFF(0x2080 + (g_))\n+#define FM10K_SW_TC_RATE_STATUS\t\t\tFM10K_SW_REG_OFF(0x20C0)\n+#define FM10K_SW_PAUSE\t\t\t\tFM10K_SW_REG_OFF(0x20C2)\n+#define FM10K_SW_DMA_CTRL\t\t\tFM10K_SW_REG_OFF(0x20C3)\n+#define\tFM10K_SW_DMA_CTRL_TX_ENABLE\t\t(1 << 0)\n+#define\tFM10K_SW_DMA_CTRL_TX_HOST_PENDING\t(1 << 1)\n+#define\tFM10K_SW_DMA_CTRL_TX_DATA\t\t(1 << 2)\n+#define\tFM10K_SW_DMA_CTRL_TX_ACTIVE\t\t(1 << 3)\n+#define\tFM10K_SW_DMA_CTRL_RX_ENABLE\t\t(1 << 4)\n+#define\tFM10K_SW_DMA_CTRL_RX_HOST_PENDING\t(1 << 5)\n+#define\tFM10K_SW_DMA_CTRL_RX_DATA\t\t(1 << 6)\n+#define\tFM10K_SW_DMA_CTRL_RX_ACTIVE\t\t(1 << 7)\n+#define\tFM10K_SW_DMA_CTRL_RX_DESC_SIZE_32\t(1 << 8)\n+#define\tFM10K_SW_DMA_CTRL_MIN_MSS_lsb\t\t9\n+#define\tFM10K_SW_DMA_CTRL_MIN_MSS_msb\t\t22\n+#define\tFM10K_SW_DMA_CTRL_MAX_HOLD_TIME_lsb\t23\n+#define\tFM10K_SW_DMA_CTRL_MAX_HOLD_TIME_msb\t27\n+#define\tFM10K_SW_DMA_CTRL_DATA_PATH_RESET\t(1 << 29)\n+#define\tFM10K_SW_DMA_CTRL_MAX_QS_lsb\t\t30\n+#define\tFM10K_SW_DMA_CTRL_MAX_QS_msb\t\t31\n+#define\tFM10K_SW_DMA_CTRL_MAX_QS_256\t\t0\n+#define\tFM10K_SW_DMA_CTRL_MAX_QS_128\t\t1\n+#define\tFM10K_SW_DMA_CTRL_MAX_QS_64\t\t2\n+#define FM10K_SW_DMA_CTRL2\t\t\tFM10K_SW_REG_OFF(0x20C4)\n+#define FM10K_SW_DTXTCPFLGL\t\t\tFM10K_SW_REG_OFF(0x20C5)\n+#define FM10K_SW_DTXTCPFLGH\t\t\tFM10K_SW_REG_OFF(0x20C6)\n+#define FM10K_SW_TPH_CTRL\t\t\tFM10K_SW_REG_OFF(0x20C7)\n+#define FM10K_SW_MRQC(f_)\t\t\t\\\n+\t\t\tFM10K_SW_REG_OFF(0x2100 + (f_))\n+#define\tFM10K_SW_MRQC_TCPIPV4\t\t\t(1 << 0)\n+#define\tFM10K_SW_MRQC_IPV4\t\t\t(1 << 1)\n+#define\tFM10K_SW_MRQC_IPV6\t\t\t(1 << 4)\n+#define\tFM10K_SW_MRQC_TCPIPV6\t\t\t(1 << 5)\n+#define\tFM10K_SW_MRQC_UDPIPV4\t\t\t(1 << 6)\n+#define\tFM10K_SW_MRQC_UDPIPV6\t\t\t(1 << 7)\n+#define FM10K_SW_TQMAP(nvf_, vf_, vq_, vf1_, vq1_)\t\\\n+\t\tFM10K_SW_REG_OFF(0x2800 + (((nvf_) & ~0x7) ? \\\n+\t\t((vf_) * 32 + ((vq_) & 0x1f)) : ((vf1_) * 256 + (vq1_))))\n+#define FM10K_SW_RQMAP(nvf_, vf_, vq_, vf1_, vq1_) \\\n+\t\tFM10K_SW_REG_OFF(0x3000 + (((nvf_) & ~0x7) ? \\\n+\t\t((vf_) * 32 + ((vq_) & 0x1f)) : ((vf1_) * 256 + (vq1_))))\n+#define FM10K_SW_STATS_TIMEOUT\t\t\tFM10K_SW_REG_OFF(0x3800)\n+#define FM10K_SW_STATS_UR\t\t\tFM10K_SW_REG_OFF(0x3801)\n+#define FM10K_SW_STATS_CA\t\t\tFM10K_SW_REG_OFF(0x3802)\n+#define FM10K_SW_STATS_UM\t\t\tFM10K_SW_REG_OFF(0x3803)\n+#define FM10K_SW_STATS_XEC\t\t\tFM10K_SW_REG_OFF(0x3804)\n+#define FM10K_SW_STATS_VLAN_DROP\t\tFM10K_SW_REG_OFF(0x3805)\n+#define FM10K_SW_STATS_LOOPBACK_DROP\t\tFM10K_SW_REG_OFF(0x3806)\n+#define FM10K_SW_STATS_NODESC_DROP\t\tFM10K_SW_REG_OFF(0x3807)\n+#define FM10K_SW_RRTIME_CFG\t\t\tFM10K_SW_REG_OFF(0x3808)\n+#define FM10K_SW_RRTIME_LIMIT(n_)\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x380C + 0x40 * (n_))\n+#define FM10K_SW_RRTIME_COUNT(n_)\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x3810 + 0x40 * (n_))\n+#define FM10K_SW_SYSTIME\t\t\tFM10K_SW_REG_OFF(0x3814)\n+#define FM10K_SW_SYSTIME0\t\t\tFM10K_SW_REG_OFF(0x3816)\n+#define FM10K_SW_SYSTIME_CFG\t\t\tFM10K_SW_REG_OFF(0x3818)\n+#define FM10K_SW_PFVFBME\t\t\tFM10K_SW_REG_OFF(0x381A)\n+#define FM10K_SW_PHYADDR\t\t\tFM10K_SW_REG_OFF(0x381C)\n+#define FM10K_SW_RDBAL(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x4000 + 0x40 * (q_))\n+#define FM10K_SW_RDBAH(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x4001 + 0x40 * (q_))\n+#define FM10K_SW_RDLEN(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x4002 + 0x40 * (q_))\n+#define FM10K_SW_TPH_RXCTRL(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x4003 + 0x40 * (q_))\n+#define\tFM10K_SW_TPH_RXCTRL_DESC_TPHEN\t\t(1 << 5)\n+#define\tFM10K_SW_TPH_RXCTRL_HEADER_TPHEN\t(1 << 6)\n+#define\tFM10K_SW_TPH_RXCTRL_PAYLOAD_TPHEN\t(1 << 7)\n+#define\tFM10K_SW_TPH_RXCTRL_DESC_READ_RO_EN\t(1 << 9)\n+#define\tFM10K_SW_TPH_RXCTRL_DESC_WRITE_RO_EN\t(1 << 11)\n+#define\tFM10K_SW_TPH_RXCTRL_DATA_WRITE_RO_EN\t(1 << 13)\n+#define\tFM10K_SW_TPH_RXCTRL_REP_HEADER_RO_EN\t(1 << 15)\n+#define FM10K_SW_RDH(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x4004 + 0x40 * (q_))\n+#define FM10K_SW_RDT(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x4005 + 0x40 * (q_))\n+#define\tFM10K_SW_RDT_RDT_lsb\t\t\t0\n+#define\tFM10K_SW_RDT_RDT_msb\t\t\t15\n+#define FM10K_SW_RXQCTL(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x4006 + 0x40 * (q_))\n+#define\tFM10K_SW_RXQCTL_ENABLE\t\t\t(1 << 0)\n+#define\tFM10K_SW_RXQCTL_VF_lsb\t\t\t2\n+#define\tFM10K_SW_RXQCTL_VF_msb\t\t\t7\n+#define\tFM10K_SW_RXQCTL_OWNED_BY_VF\t\t(1 << 8)\n+#define FM10K_SW_RXDCTL(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x4007 + 0x40 * (q_))\n+#define\tFM10K_SW_RXDCTL_MAX_TIME_lsb\t\t0\n+#define\tFM10K_SW_RXDCTL_MAX_TIME_msb\t\t7\n+#define\tFM10K_SW_RXDCTL_WRITE_BACK_IMM\t\t(1 << 8)\n+#define\tFM10K_SW_RXDCTL_DROP_ON_EMPTY\t\t(1 << 9)\n+#define\tFM10K_SW_RXDCTL_WRITE_RSS_HASH\t\t(1 << 10)\n+#define FM10K_SW_RXINT(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x4008 + 0x40 * (q_))\n+#define\tFM10K_SW_RXINT_INT_lsb\t\t\t0\n+#define\tFM10K_SW_RXINT_INT_msb\t\t\t7\n+#define\tFM10K_SW_RXINT_INT_TIMER_lsb\t\t8\n+#define\tFM10K_SW_RXINT_INT_TIMER_msb\t\t9\n+#define FM10K_SW_SRRCTL(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x4009 + 0x40 * (q_))\n+#define\tFM10K_SW_SRRCTL_BSIZE_PACKET_lsb\t0\n+#define\tFM10K_SW_SRRCTL_BSIZE_PACKET_msb\t7\n+#define\tFM10K_SW_SRRCTL_BSIZE_HEADER_lsb\t8\n+#define\tFM10K_SW_SRRCTL_BSIZE_HEADER_msb\t13\n+#define\tFM10K_SW_SRRCTL_DESC_TYPE_lsb\t\t14\n+#define\tFM10K_SW_SRRCTL_DESC_TYPE_msb\t\t15\n+#define\tFM10K_SW_SRRCTL_DESC_TYPE_NO_SPLIT\t0\n+#define\tFM10K_SW_SRRCTL_DESC_TYPE_HDR_SPLIT\t1\n+#define\tFM10K_SW_SRRCTL_DESC_TYPE_SIZE_SPLIT\t2\n+#define\tFM10K_SW_SRRCTL_PSR_TYPE_lsb\t\t16\n+#define\tFM10K_SW_SRRCTL_PSR_TYPE_msb\t\t29\n+#define\tFM10K_SW_SRRCTL_LOOPBACK_SUPPRESS\t(1 << 30)\n+#define\tFM10K_SW_SRRCTL_BUFFER_CHAINING_EN\t(1 << 31)\n+#define FM10K_SW_QPRC(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x400A + 0x40 * (q_))\n+#define FM10K_SW_QPRDC(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x400B + 0x40 * (q_))\n+#define FM10K_SW_QBRC_L(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x400C + 0x40 * (q_))\n+#define FM10K_SW_QBRC_H(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x400D + 0x40 * (q_))\n+#define FM10K_SW_RX_SGLORT(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x400E + 0x40 * (q_))\n+#define FM10K_SW_TDBAL(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x8000 + 0x40 * (q_))\n+#define FM10K_SW_TDBAH(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x8001 + 0x40 * (q_))\n+#define FM10K_SW_TDLEN(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x8002 + 0x40 * (q_))\n+#define FM10K_SW_TPH_TXCTRL(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x8003 + 0x40 * (q_))\n+#define\tFM10K_SW_TPH_TXCTRL_DESC_TPHEN\t\t(1 << 5)\n+#define\tFM10K_SW_TPH_TXCTRL_DESC_READ_RO_EN\t(1 << 9)\n+#define\tFM10K_SW_TPH_TXCTRL_DESC_WRITE_RO_EN\t(1 << 11)\n+#define\tFM10K_SW_TPH_TXCTRL_DATA_READ_RO_EN\t(1 << 13)\n+#define FM10K_SW_TDH(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x8004 + 0x40 * (q_))\n+#define FM10K_SW_TDT(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x8005 + 0x40 * (q_))\n+#define\tFM10K_SW_TDT_TDT_lsb\t\t\t0\n+#define\tFM10K_SW_TDT_TDT_msb\t\t\t15\n+#define FM10K_SW_TXDCTL(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x8006 + 0x40 * (q_))\n+#define\tFM10K_SW_TXDCTL_PTHRESH_lsb\t\t0\n+#define\tFM10K_SW_TXDCTL_PTHRESH_msb\t\t6\n+#define\tFM10K_SW_TXDCTL_HTHRESH_lsb\t\t7\n+#define\tFM10K_SW_TXDCTL_HTHRESH_msb\t\t13\n+#define\tFM10K_SW_TXDCTL_ENABLE\t\t\t(1 << 14)\n+#define\tFM10K_SW_TXDCTL_MAX_TIME_lsb\t\t16\n+#define\tFM10K_SW_TXDCTL_MAX_TIME_msb\t\t27\n+#define\tFM10K_SW_TXDCTL_PUSH_DESC\t\t(1 << 28)\n+#define FM10K_SW_TXQCTL(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x8007 + 0x40 * (q_))\n+#define\tFM10K_SW_TXQCTL_VF_lsb\t\t\t0\n+#define\tFM10K_SW_TXQCTL_VF_msb\t\t\t5\n+#define\tFM10K_SW_TXQCTL_OWNED_BY_VF\t\t(1 << 6)\n+#define\tFM10K_SW_TXQCTL_PC_lsb\t\t\t7\n+#define\tFM10K_SW_TXQCTL_PC_msb\t\t\t9\n+#define\tFM10K_SW_TXQCTL_TC_lsb\t\t\t10\n+#define\tFM10K_SW_TXQCTL_TC_msb\t\t\t15\n+#define\tFM10K_SW_TXQCTL_VID_lsb\t\t\t16\n+#define\tFM10K_SW_TXQCTL_VID_msb\t\t\t27\n+#define\tFM10K_SW_TXQCTL_UNLIMITED_BW\t\t(1 << 28)\n+#define\tFM10K_SW_TXQCTL_PUSH_MODE_DIS\t\t(1 << 29)\n+#define FM10K_SW_TXINT(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x8008 + 0x40 * (q_))\n+#define\tFM10K_SW_TXINT_INT_lsb\t\t\t0\n+#define\tFM10K_SW_TXINT_INT_msb\t\t\t7\n+#define\tFM10K_SW_TXINT_INT_TIMER_lsb\t\t8\n+#define\tFM10K_SW_TXINT_INT_TIMER_msb\t\t9\n+#define FM10K_SW_QPTC(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x8009 + 0x40 * (q_))\n+#define FM10K_SW_QBTC_L(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x800A + 0x40 * (q_))\n+#define FM10K_SW_QBTC_H(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x800B + 0x40 * (q_))\n+#define FM10K_SW_TQDLOC(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x800C + 0x40 * (q_))\n+#define\tFM10K_SW_TQDLOC_BASE_lsb\t\t0\n+#define\tFM10K_SW_TQDLOC_BASE_msb\t\t15\n+#define\tFM10K_SW_TQDLOC_SIZE_lsb\t\t16\n+#define\tFM10K_SW_TQDLOC_SIZE_msb\t\t19\n+#define\tFM10K_SW_TQDLOC_SIZE_32\t\t\t5\n+#define\tFM10K_SW_TQDLOC_SIZE_64\t\t\t6\n+#define\tFM10K_SW_TQDLOC_SIZE_128\t\t7\n+#define FM10K_SW_TX_SGLORT(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x800D + 0x40 * (q_))\n+#define\tFM10K_SW_TX_SGLORT_SGLORT_lsb\t\t0\n+#define\tFM10K_SW_TX_SGLORT_SGLORT_msb\t\t15\n+#define FM10K_SW_PFVTCTL(q_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x800E + 0x40 * (q_))\n+#define FM10K_SW_TX_DESC(q_, d_, w_)\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x40000 + \\\n+\t\t0x400 * (q_) + 0x4 * (d_) + (w_))\n+#define FM10K_SW_PBACL(n_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x10000 + (n_))\n+#define FM10K_SW_INT_MAP(n_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x10080 + (n_))\n+#define\tFM10K_SW_INT_MAP_ENTRIES\t\t8\n+#define\tFM10K_SW_INT_MAP_INDEX_MAILBOX\t\t0\n+#define\tFM10K_SW_INT_MAP_INDEX_FAULT\t\t1\n+#define\tFM10K_SW_INT_MAP_INDEX_SWITCH_UP_DOWN\t2\n+#define\tFM10K_SW_INT_MAP_INDEX_SWITCH\t\t3\n+#define\tFM10K_SW_INT_MAP_INDEX_SRAM\t\t4\n+#define\tFM10K_SW_INT_MAP_INDEX_VFLR\t\t5\n+#define\tFM10K_SW_INT_MAP_INDEX_MAX_HOLD_TIME\t6\n+#define\tFM10K_SW_INT_MAP_INT_lsb\t\t0\n+#define\tFM10K_SW_INT_MAP_INT_msb\t\t7\n+#define\tFM10K_SW_INT_MAP_INT_TIMER_lsb\t\t8\n+#define\tFM10K_SW_INT_MAP_INT_TIMER_msb\t\t9\n+#define FM10K_SW_MSIX_VECTOR(v_)\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x11000 + 0x4 * (v_))\n+#define FM10K_SW_INT_CTRL\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x12000)\n+#define\tFM10K_SW_INT_CTRL_NEXT_VECTOR_lsb\t0\n+#define\tFM10K_SW_INT_CTRL_NEXT_VECTOR_msb\t9\n+#define\tFM10K_SW_INT_CTRL_ENABLE_MODERATOR\t(1 << 10)\n+#define FM10K_SW_ITR(v_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x12400 + (v_))\n+\n+/*\n+ * Interrupt throttle timer intervals in microseconds.  These provide the\n+ * direct values for programming the ITR interval field when using a Gen3\n+ * PCLK, otherwise they need to be scaled appropriately.\n+ */\n+#define FM10K_SW_ITR_INTERVAL_20K\t\t50\n+#define FM10K_SW_ITR_INTERVAL_40K\t\t25\n+#define FM10K_SW_ITR_INTERVAL_0_lsb\t\t0\n+#define FM10K_SW_ITR_INTERVAL_0_msb\t\t11\n+#define FM10K_SW_ITR_INTERVAL_1_lsb\t\t12\n+#define FM10K_SW_ITR_INTERVAL_1_msb\t\t23\n+#define FM10K_SW_ITR_TIMER_0_EXPIRED\t\t(1 << 24)\n+#define FM10K_SW_ITR_TIMER_1_EXPIRED\t\t(1 << 25)\n+#define FM10K_SW_ITR_PENDING_0\t\t\t(1 << 26)\n+#define FM10K_SW_ITR_PENDING_1\t\t\t(1 << 27)\n+#define FM10K_SW_ITR_PENDING_2\t\t\t(1 << 28)\n+#define FM10K_SW_ITR_AUTO_MASK\t\t\t(1 << 29)\n+#define FM10K_SW_ITR_MASK_lsb\t\t\t30\n+#define FM10K_SW_ITR_MASK_msb\t\t\t31\n+#define\tFM10K_SW_ITR_MASK_R_ENABLED\t\t0\n+#define\tFM10K_SW_ITR_MASK_R_BLOCKED\t\t1\n+#define\tFM10K_SW_ITR_MASK_W_KEEP\t\t0\n+#define\tFM10K_SW_ITR_MASK_W_BLOCK\t\t1\n+#define\tFM10K_SW_ITR_MASK_W_ENABLE\t\t2\n+#define FM10K_SW_ITR2(v_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x12800 + 0x2 * (v_))\n+#define FM10K_SW_IP\t\t\t\tFM10K_SW_REG_OFF(0x13000)\n+#define FM10K_SW_IP_HOT_RESET\t\t\t(1 << 0)\n+#define FM10K_SW_IP_DEVICE_STATE_CHANGE\t\t(1 << 1)\n+#define FM10K_SW_IP_MAILBOX\t\t\t(1 << 2)\n+#define FM10K_SW_IP_VPD_REQUEST\t\t\t(1 << 3)\n+#define FM10K_SW_IP_SRAM_ERROR\t\t\t(1 << 4)\n+#define FM10K_SW_IP_PFLR\t\t\t(1 << 5)\n+#define FM10K_SW_IP_DATA_PATH_RESET\t\t(1 << 6)\n+#define FM10K_SW_IP_OUT_OF_RESET\t\t(1 << 7)\n+#define FM10K_SW_IP_NOT_IN_RESET\t\t(1 << 8)\n+#define FM10K_SW_IP_TIMEOUT\t\t\t(1 << 9)\n+#define FM10K_SW_IP_VFLR\t\t\t(1 << 10)\n+#define FM10K_SW_IM\t\t\t\tFM10K_SW_REG_OFF(0x13001)\n+#define FM10K_SW_IM_ALL\t\t\t\tFM10K_SW_MASK32(10, 0)\n+#define FM10K_SW_IM_HOT_RESET\t\t\t(1 << 0)\n+#define FM10K_SW_IM_DEVICE_STATE_CHANGE\t\t(1 << 1)\n+#define FM10K_SW_IM_MAILBOX\t\t\t(1 << 2)\n+#define FM10K_SW_IM_VPD_REQUEST\t\t\t(1 << 3)\n+#define FM10K_SW_IM_SRAM_ERROR\t\t\t(1 << 4)\n+#define FM10K_SW_IM_PFLR\t\t\t(1 << 5)\n+#define FM10K_SW_IM_DATA_PATH_RESET\t\t(1 << 6)\n+#define FM10K_SW_IM_OUT_OF_RESET\t\t(1 << 7)\n+#define FM10K_SW_IM_TIMEOUT\t\t\t(1 << 9)\n+#define FM10K_SW_IM_VFLR\t\t\t(1 << 10)\n+#define FM10K_SW_IB\t\t\t\tFM10K_SW_REG_OFF(0x13002)\n+#define FM10K_SW_SRAM_IP\t\t\tFM10K_SW_REG_OFF(0x13003)\n+#define FM10K_SW_SRAM_IM\t\t\tFM10K_SW_REG_OFF(0x13004)\n+#define FM10K_SW_VLAN_TABLE(f_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x14000 + 0x80 * (f_))\n+#define FM10K_SW_VLAN_TABLE_ENTRIES\t\t128\n+#define FM10K_SW_VLAN_TABLE_ENTRY(f_, n_) \\\n+\t\tFM10K_SW_REG_OFF(0x14000 + 0x80 * (f_) + (n_))\n+#define FM10K_SW_VLAN_TABLE_VLAN_ENTRY(f_, vl_)\t\\\n+\t\tFM10K_SW_REG_OFF(0x14000 + 0x80 * (f_) + ((vl_) >> 5))\n+#define FM10K_SW_VLAN_TABLE_VLAN_BIT(vl_)\t(1 << ((vl_) & 0x1f))\n+#define FM10K_SW_MBMEM(n_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x18000 + (n_))\n+#define FM10K_SW_MBX(vf_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x18800 + (vf_))\n+#define FM10K_SW_MBICR(vf_)\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x18840 + ((vf_) >> 5))\n+#define FM10K_SW_GMBX\t\t\t\tFM10K_SW_REG_OFF(0x18842)\n+#define FM10K_SW_GMBX_GLOBAL_REQ\t\t(1 << 1)\n+#define FM10K_SW_GMBX_GLOBAL_ACK\t\t(1 << 2)\n+#define FM10K_SW_GMBX_PF_REQ_INTERRUPT\t\t(1 << 3)\n+#define FM10K_SW_GMBX_PF_ACK_INTERRUPT\t\t(1 << 4)\n+#define FM10K_SW_GMBX_PF_INTERRUPT_ENABLE_lsb\t5\n+#define FM10K_SW_GMBX_PF_INTERRUPT_ENABLE_msb\t6\n+#define\tFM10K_SW_GMBX_INTERRUPT_NO_CHANGE\t0\n+#define\tFM10K_SW_GMBX_INTERRUPT_ENABLE\t\t1\n+#define\tFM10K_SW_GMBX_INTERRUPT_DISABLE\t\t2\n+#define FM10K_SW_GMBX_PF_REQ\t\t\t(1 << 7)\n+#define FM10K_SW_GMBX_PF_ACK\t\t\t(1 << 8)\n+#define FM10K_SW_GMBX_GLOBAL_REQ_INTERRUPT\t(1 << 9)\n+#define FM10K_SW_GMBX_GLOBAL_ACK_INTERRUPT\t(1 << 10)\n+#define FM10K_SW_GMBX_GLOBAL_INTERRUPT_ENABLE_lsb\t11\n+#define FM10K_SW_GMBX_GLOBAL_INTERRUPT_ENABLE_msb\t12\n+#define FM10K_SW_PFVFLRE\t\t\tFM10K_SW_REG_OFF(0x18844)\n+#define FM10K_SW_PFVFLREC\t\t\tFM10K_SW_REG_OFF(0x18846)\n+#define FM10K_SW_TEST_CFG0\t\t\tFM10K_SW_REG_OFF(0x18849)\n+#define FM10K_SW_INT_SRAM_CTRL\t\t\tFM10K_SW_REG_OFF(0x18850)\n+#define FM10K_SW_FUM_SRAM_CTRL\t\t\tFM10K_SW_REG_OFF(0x18852)\n+#define FM10K_SW_PCA_SRAM_CTRL\t\t\tFM10K_SW_REG_OFF(0x18854)\n+#define FM10K_SW_PP_SRAM_CTRL\t\t\tFM10K_SW_REG_OFF(0x18858)\n+#define FM10K_SW_PCW_SRAM_CTRL\t\t\tFM10K_SW_REG_OFF(0x1885C)\n+#define FM10K_SW_RHI_SRAM_CTRL1\t\t\tFM10K_SW_REG_OFF(0x18872)\n+#define FM10K_SW_RHI_SRAM_CTRL2\t\t\tFM10K_SW_REG_OFF(0x18860)\n+#define FM10K_SW_THI_SRAM_CTRL1\t\t\tFM10K_SW_REG_OFF(0x18864)\n+#define FM10K_SW_THI_SRAM_CTRL2\t\t\tFM10K_SW_REG_OFF(0x18868)\n+#define FM10K_SW_TIMEOUT_CFG\t\t\tFM10K_SW_REG_OFF(0x1886B)\n+#define FM10K_SW_LVMMC\t\t\t\tFM10K_SW_REG_OFF(0x18880)\n+#define FM10K_SW_LVMMI\t\t\t\tFM10K_SW_REG_OFF(0x18881)\n+#define FM10K_SW_HOST_MISC\t\t\tFM10K_SW_REG_OFF(0x19000)\n+#define FM10K_SW_HOST_LANE_CTRL\t\t\tFM10K_SW_REG_OFF(0x19001)\n+#define FM10K_SW_SERDES_CTRL(l_)\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x19010 + 0x2 * (l_))\n+\n+/*\n+ * BAR4 registers\n+ */\n+\n+/*\n+ * Access to non-master PEP registers via BAR4\n+ */\n+#define FM10K_SW_PCIE_GLOBAL(p_, r_)\t\\\n+\t\t(FM10K_SW_REG_OFF(((p_) + 1) << 20) | FM10K_SW_##r_)\n+\n+/*\n+ * SBUS register fields for use with both the PCIE and EPL SBUS interfaces.\n+ */\n+#define FM10K_SW_SBUS_CFG_SBUS_CONTROLLER_RESET\t(1 << 0)\n+#define FM10K_SW_SBUS_CFG_ROM_ENABLE\t\t(1 << 1)\n+#define FM10K_SW_SBUS_CFG_ROM_BUSY\t\t(1 << 2)\n+#define FM10K_SW_SBUS_CFG_BIST_DONE_PASS\t(1 << 3)\n+#define FM10K_SW_SBUS_CFG_BIST_DONE_FAIL\t(1 << 4)\n+\n+#define FM10K_SW_SBUS_COMMAND_REGISTER_lsb\t0\n+#define FM10K_SW_SBUS_COMMAND_REGISTER_msb\t7\n+#define FM10K_SW_SBUS_COMMAND_ADDRESS_lsb\t8\n+#define FM10K_SW_SBUS_COMMAND_ADDRESS_msb\t15\n+#define FM10K_SW_SBUS_COMMAND_OP_lsb\t\t16\n+#define FM10K_SW_SBUS_COMMAND_OP_msb\t\t23\n+#define FM10K_SW_SBUS_OP_RESET\t\t\t0x20\n+#define FM10K_SW_SBUS_OP_WRITE\t\t\t0x21\n+#define FM10K_SW_SBUS_OP_READ\t\t\t0x22\n+#define FM10K_SW_SBUS_COMMAND_EXECUTE\t\t(1 << 24)\n+#define FM10K_SW_SBUS_COMMAND_BUSY\t\t(1 << 25)\n+#define FM10K_SW_SBUS_COMMAND_RESULT_CODE_lsb\t26\n+#define FM10K_SW_SBUS_COMMAND_RESULT_CODE_msb\t28\n+#define FM10K_SW_SBUS_RESULT_RESET\t\t0x00\n+#define FM10K_SW_SBUS_RESULT_WRITE\t\t0x01\n+#define FM10K_SW_SBUS_RESULT_READ\t\t0x04\n+\n+#define FM10K_SW_SBUS_ADDR_EPL_RMON2\t\t1\n+#define FM10K_SW_SBUS_ADDR_EPL_LANE(e_, l_)\t(4 * (e_) + (l_) + 2)\n+#define FM10K_SW_SBUS_ADDR_EPL_SERDES(s_)\t((s_) + 2)\n+#define FM10K_SW_SBUS_ADDR_EPL_RMON3\t\t38\n+#define FM10K_SW_SBUS_ADDR_EPL_PMRO\t\t39\n+\n+/* Common to both EPL and PCIE\n+ */\n+#define FM10K_SW_SBUS_ADDR_SPICO\t\t253\n+#define FM10K_SW_SBUS_ADDR_SBUS_CONTROLLER\t254\n+#define FM10K_SW_SBUS_ADDR_BROADCAST\t\t0xFF\n+\n+\n+#define FM10K_SW_MGMT_BASE\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x000000)\n+#define FM10K_SW_MGMT_REG(wo_)\t\t\t\\\n+\t\t(FM10K_SW_MGMT_BASE + FM10K_SW_REG_OFF(wo_))\n+\n+#define FM10K_SW_FATAL_CODE\t\t\tFM10K_SW_MGMT_REG(0x0)\n+#define FM10K_SW_LAST_FATAL_CODE\t\tFM10K_SW_MGMT_REG(0x1)\n+#define FM10K_SW_FATAL_COUNT\t\t\tFM10K_SW_MGMT_REG(0x2)\n+#define FM10K_SW_SOFT_RESET\t\t\tFM10K_SW_MGMT_REG(0x3)\n+#define FM10K_SW_SOFT_RESET_COLD_RESET\t\t(1 << 0)\n+#define FM10K_SW_SOFT_RESET_EPL_RESET\t\t(1 << 1)\n+#define FM10K_SW_SOFT_RESET_SWITCH_RESET\t(1 << 2)\n+#define FM10K_SW_SOFT_RESET_SWITCH_READY\t(1 << 3)\n+#define FM10K_SW_SOFT_RESET_PCIE_RESET(p_)\t(1 << ((p_) + 4))\n+#define FM10K_SW_SOFT_RESET_PCIE_ACTIVE(p_)\t(1 << ((p_) + 13))\n+#define FM10K_SW_DEVICE_CFG\t\t\tFM10K_SW_MGMT_REG(0x4)\n+#define FM10K_SW_DEVICE_CFG_PCIE_MODE_PAIRS\t4\n+#define FM10K_SW_DEVICE_CFG_PCIE_MODE_2X4(p_)\t(1 << (p_))\n+#define FM10K_SW_DEVICE_CFG_PCIE_100G_DIS\t(1 << 4)\n+#define FM10K_SW_DEVICE_CFG_FEATURE_lsb\t\t5\n+#define FM10K_SW_DEVICE_CFG_FEATURE_msb\t\t6\n+#define\tFM10K_SW_DEVICE_CFG_PCIE_FULL\t\t0\n+#define\tFM10K_SW_DEVICE_CFG_PCIE_HALF\t\t1\n+#define\tFM10K_SW_DEVICE_CFG_PCIE_BASIC\t\t2\n+#define FM10K_SW_DEVICE_CFG_PCIE_EN(p_)\t\t(1 << (7 + (p_)))\n+#define FM10K_SW_RESET_CFG\t\t\tFM10K_SW_MGMT_REG(0x5)\n+#define FM10K_SW_WATCHDOG_CFG\t\t\tFM10K_SW_MGMT_REG(0x6)\n+#define FM10K_SW_MGMT_SCRATCH(n_)\t\tFM10K_SW_MGMT_REG(0x8 + (n_))\n+#define FM10K_SW_VITAL_PRODUCT_DATA\t\tFM10K_SW_MGMT_REG(0x304)\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT\tFM10K_SW_MGMT_REG(0x400)\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_PCIE_BSM_lsb64\t0\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_PCIE_BSM_msb64\t8\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_PCIE_BSM(n_)\t(1ULL << (n_))\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_PCIE_lsb64\t9\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_PCIE_msb64\t17\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_PCIE(n_)\t\\\n+\t\t(1ULL << ((n_) + 9))\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_EPL_lsb64\t18\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_EPL_msb64\t26\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_EPL(n_)\t\\\n+\t\t(1ULL << ((n_) + 18))\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_TUNNEL_lsb64\t27\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_TUNNEL_msb64\t28\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_TUNNEL(n_)\t\\\n+\t\t(1ULL << ((n_) + 27))\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_CORE\t\t(1ULL << 29)\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_SOFTWARE\t(1ULL << 30)\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_GPIO\t\t(1ULL << 31)\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_I2C\t\t(1ULL << 32)\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_MDIO\t\t(1ULL << 33)\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_CRM\t\t(1ULL << 34)\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_FH_TAIL\t(1ULL << 35)\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_FH_HEAD\t(1ULL << 36)\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_SBUS_EPL\t(1ULL << 37)\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_SBUS_PCIE\t(1ULL << 38)\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_PINS\t\t(1ULL << 39)\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_FIBM\t\t(1ULL << 40)\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_BSM\t\t(1ULL << 41)\n+#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_XCLK\t\t(1ULL << 42)\n+#define FM10K_SW_INTERRUPT_MASK_INT\t\t\t\\\n+\t\tFM10K_SW_MGMT_REG(0x402)\n+#define FM10K_SW_INTERRUPT_MASK_PCIE(p_)\t\t\\\n+\t\tFM10K_SW_MGMT_REG(0x420 + 0x2 * (p_))\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_PCIE_BSM_lsb64\t0\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_PCIE_BSM_msb64\t8\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_PCIE_BSM(n_)\t(1ULL << (n_))\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_PCIE_lsb64\t\t9\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_PCIE_msb64\t\t17\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_PCIE(n_)\t\t\\\n+\t\t(1ULL << ((n_) + 9))\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_EPL_lsb64\t\t18\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_EPL_msb64\t\t26\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_EPL(n_)\t\t\\\n+\t\t(1ULL << ((n_) + 18))\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_TUNNEL_lsb64\t27\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_TUNNEL_msb64\t28\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_TUNNEL(n_)\t\t\\\n+\t\t(1ULL << ((n_) + 27))\n+\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_CORE\t(1ULL << 29)\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_SOFTWARE\t(1ULL << 30)\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_GPIO\t(1ULL << 31)\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_I2C\t(1ULL << 32)\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_MDIO\t(1ULL << 33)\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_CRM\t(1ULL << 34)\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_FH_TAIL\t(1ULL << 35)\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_FH_HEAD\t(1ULL << 36)\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_SBUS_EPL\t(1ULL << 37)\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_SBUS_PCIE\t(1ULL << 38)\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_PINS\t(1ULL << 39)\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_FIBM\t(1ULL << 40)\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_BSM\t(1ULL << 41)\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_XCLK\t(1ULL << 42)\n+#define FM10K_SW_INTERRUPT_MASK_PCIE_ALL\tFM10K_SW_MASK64(42, 0)\n+#define FM10K_SW_INTERRUPT_MASK_FIBM\t\tFM10K_SW_MGMT_REG(0x440)\n+#define FM10K_SW_INTERRUPT_MASK_BSM\t\tFM10K_SW_MGMT_REG(0x442)\n+#define FM10K_SW_CORE_INTERRUPT_DETECT\t\tFM10K_SW_MGMT_REG(0x444)\n+#define FM10K_SW_CORE_INTERRUPT_MASK\t\tFM10K_SW_MGMT_REG(0x445)\n+#define FM10K_SW_SRAM_ERR_IP\t\t\tFM10K_SW_MGMT_REG(0x446)\n+#define FM10K_SW_SRAM_ERR_IM\t\t\tFM10K_SW_MGMT_REG(0x448)\n+#define FM10K_SW_PINS_STAT\t\t\tFM10K_SW_MGMT_REG(0x44A)\n+#define FM10K_SW_PINS_IP\t\t\tFM10K_SW_MGMT_REG(0x44B)\n+#define FM10K_SW_PINS_IM\t\t\tFM10K_SW_MGMT_REG(0x44C)\n+#define FM10K_SW_SW_IP\t\t\t\tFM10K_SW_MGMT_REG(0x44D)\n+#define FM10K_SW_SW_IM\t\t\t\tFM10K_SW_MGMT_REG(0x44E)\n+#define FM10K_SW_SW_TEST_AND_SET\t\tFM10K_SW_MGMT_REG(0x44F)\n+#define FM10K_SW_LSM_CLKOBS_CTRL\t\tFM10K_SW_MGMT_REG(0x450)\n+#define FM10K_SW_CHIP_VERSION\t\t\tFM10K_SW_MGMT_REG(0x452)\n+#define FM10K_SW_BSM_SCRATCH(n_)\t\tFM10K_SW_MGMT_REG(0x800 + (n_))\n+#define FM10K_SW_BSM_CTRL\t\t\tFM10K_SW_MGMT_REG(0xC00)\n+#define FM10K_SW_BSM_ARGS\t\t\tFM10K_SW_MGMT_REG(0xC01)\n+#define FM10K_SW_BSM_ADDR_OFFSET(n_)\t\tFM10K_SW_MGMT_REG(0xC04 + (n_))\n+#define FM10K_SW_BSM_COUNTER(n_)\t\tFM10K_SW_MGMT_REG(0xC08 + (n_))\n+#define FM10K_SW_BSM_SRAM_CTRL\t\t\tFM10K_SW_MGMT_REG(0xC0A)\n+#define FM10K_SW_BSM_IP\t\t\t\tFM10K_SW_MGMT_REG(0xC0B)\n+#define FM10K_SW_BSM_IM\t\t\t\tFM10K_SW_MGMT_REG(0xC0C)\n+#define FM10K_SW_PIN_STRAP_STAT\t\t\tFM10K_SW_MGMT_REG(0xC0D)\n+#define FM10K_SW_FUSE_DATA_0\t\t\tFM10K_SW_MGMT_REG(0xC0E)\n+#define FM10K_SW_FUSE_SKU_lsb\t\t\t11\n+#define FM10K_SW_FUSE_SKU_msb\t\t\t15\n+#define FM10K_SW_FUSE_SKU_FM10840\t\t0\n+#define FM10K_SW_FUSE_SKU_FM10420\t\t1\n+#define FM10K_SW_FUSE_SKU_FM10064\t\t2\n+#define FM10K_SW_FUSE_DATA_1\t\t\tFM10K_SW_MGMT_REG(0xC0F)\n+#define FM10K_SW_BIST_CTRL\t\t\tFM10K_SW_MGMT_REG(0xC10)\n+#define FM10K_SW_BIST_CTRL_BIST_RUN_PCIE(p_)\t(1ULL << (p_))\n+#define FM10K_SW_BIST_CTRL_BIST_RUN_EPL\t\t(1ULL << 9)\n+#define FM10K_SW_BIST_CTRL_BIST_RUN_FABRIC\t(1ULL << 10)\n+#define FM10K_SW_BIST_CTRL_BIST_RUN_TUNNEL\t(1ULL << 11)\n+#define FM10K_SW_BIST_CTRL_BIST_RUN_BSM\t\t(1ULL << 12)\n+#define FM10K_SW_BIST_CTRL_BIST_RUN_CRM\t\t(1ULL << 13)\n+#define FM10K_SW_BIST_CTRL_BIST_RUN_FIBM\t(1ULL << 14)\n+#define FM10K_SW_BIST_CTRL_BIST_RUN_SBM\t\t(1ULL << 15)\n+#define FM10K_SW_BIST_CTRL_BIST_MODE_PCIE(p_)\t(1ULL << (p_))\n+#define FM10K_SW_BIST_CTRL_BIST_MODE_EPL\t(1ULL << 41)\n+#define FM10K_SW_BIST_CTRL_BIST_MODE_FABRIC\t(1ULL << 42)\n+#define FM10K_SW_BIST_CTRL_BIST_MODE_TUNNEL\t(1ULL << 43)\n+#define FM10K_SW_BIST_CTRL_BIST_MODE_BSM\t(1ULL << 44)\n+#define FM10K_SW_BIST_CTRL_BIST_MODE_CRM\t(1ULL << 45)\n+#define FM10K_SW_BIST_CTRL_BIST_MODE_FIBM\t(1ULL << 46)\n+#define FM10K_SW_BIST_CTRL_BIST_MODE_SBM\t(1ULL << 47)\n+#define FM10K_SW_REI_CTRL\t\t\tFM10K_SW_MGMT_REG(0xC12)\n+#define FM10K_SW_REI_STAT\t\t\tFM10K_SW_MGMT_REG(0xC13)\n+#define FM10K_SW_GPIO_CFG\t\t\tFM10K_SW_MGMT_REG(0xC15)\n+#define FM10K_SW_GPIO_DATA\t\t\tFM10K_SW_MGMT_REG(0xC16)\n+#define FM10K_SW_GPIO_IP\t\t\tFM10K_SW_MGMT_REG(0xC17)\n+#define FM10K_SW_GPIO_IM\t\t\tFM10K_SW_MGMT_REG(0xC18)\n+#define FM10K_SW_I2C_CFG\t\t\tFM10K_SW_MGMT_REG(0xC19)\n+#define FM10K_SW_I2C_CFG_SLAVE_ENABLE\t\t(1 << 0)\n+#define FM10K_SW_I2C_CFG_ADDR_lsb\t\t1\n+#define FM10K_SW_I2C_CFG_ADDR_msb\t\t7\n+#define FM10K_SW_I2C_CFG_DIVIDER_lsb\t\t8\n+#define FM10K_SW_I2C_CFG_DIVIDER_msb\t\t19\n+#define\tFM10K_SW_I2C_CFG_DIVIDER_100_KHZ\t52\n+#define\tFM10K_SW_I2C_CFG_DIVIDER_400_KHZ\t10\n+#define FM10K_SW_I2C_CFG_INTERRUPT_MASK\t\t(1 << 20)\n+#define FM10K_SW_I2C_CFG_DEBOUNCE_FILTER_COUNT_LIMIT_lsb\t21\n+#define FM10K_SW_I2C_CFG_DEBOUNCE_FILTER_COUNT_LIMIT_msb\t27\n+#define FM10K_SW_I2C_DATA(n_)\t\t\tFM10K_SW_MGMT_REG(0xC1C + (n_))\n+#define FM10K_SW_I2C_CTRL\t\t\tFM10K_SW_MGMT_REG(0xC20)\n+#define FM10K_SW_I2C_CTRL_ADDR_lsb\t\t0\n+#define FM10K_SW_I2C_CTRL_ADDR_msb\t\t7\n+#define FM10K_SW_I2C_CTRL_COMMAND_lsb\t\t8\n+#define FM10K_SW_I2C_CTRL_COMMAND_msb\t\t9\n+#define\tFM10K_SW_I2C_COMMAND_NULL\t\t0\n+#define\tFM10K_SW_I2C_COMMAND_WR\t\t\t1\n+#define\tFM10K_SW_I2C_COMMAND_WR_RD\t\t2\n+#define\tFM10K_SW_I2C_COMMAND_RD\t\t\t3\n+#define FM10K_SW_I2C_CTRL_LENGTH_W_lsb\t\t10\n+#define FM10K_SW_I2C_CTRL_LENGTH_W_msb\t\t13\n+#define FM10K_SW_I2C_CTRL_LENGTH_R_lsb\t\t14\n+#define FM10K_SW_I2C_CTRL_LENGTH_R_msb\t\t17\n+#define FM10K_SW_I2C_CTRL_LENGTH_SENT_lsb\t18\n+#define FM10K_SW_I2C_CTRL_LENGTH_SENT_msb\t21\n+#define FM10K_SW_I2C_CTRL_COMMAND_COMPLETED_lsb 22\n+#define FM10K_SW_I2C_CTRL_COMMAND_COMPLETED_msb 25\n+#define\tFM10K_SW_I2C_COMPLETION_RUNNING\t\t0\n+#define\tFM10K_SW_I2C_COMPLETION_NORMAL\t\t1\n+#define\tFM10K_SW_I2C_COMPLETION_PREMATURE\t2\n+#define\tFM10K_SW_I2C_COMPLETION_NO_DEVICE\t3\n+#define\tFM10K_SW_I2C_COMPLETION_TIMEOUT\t\t4\n+#define\tFM10K_SW_I2C_COMPLETION_LOST_ARB\t5\n+#define\tFM10K_SW_I2C_COMPLETION_BUS_WAIT\t6\n+#define\tFM10K_SW_I2C_COMPLETION_INVALID\t\t7\n+#define FM10K_SW_I2C_CTRL_INTERRUPT_PENDING\t(1 << 26)\n+#define FM10K_SW_MDIO_CFG\t\t\tFM10K_SW_MGMT_REG(0xC22)\n+#define FM10K_SW_MDIO_DATA\t\t\tFM10K_SW_MGMT_REG(0xC23)\n+#define FM10K_SW_MDIO_CTRL\t\t\tFM10K_SW_MGMT_REG(0xC24)\n+#define FM10K_SW_SPI_TX_DATA\t\t\tFM10K_SW_MGMT_REG(0xC26)\n+#define FM10K_SW_SPI_RX_DATA\t\t\tFM10K_SW_MGMT_REG(0xC27)\n+#define FM10K_SW_SPI_HEADER\t\t\tFM10K_SW_MGMT_REG(0xC28)\n+#define FM10K_SW_SPI_CTRL\t\t\tFM10K_SW_MGMT_REG(0xC29)\n+#define FM10K_SW_LED_CFG\t\t\tFM10K_SW_MGMT_REG(0xC2B)\n+#define FM10K_SW_SCAN_DATA_IN\t\t\tFM10K_SW_MGMT_REG(0xC2D)\n+#define FM10K_SW_SCAN_DATA_IN_SCAN_DATA_lsb\t0\n+#define FM10K_SW_SCAN_DATA_IN_SCAN_DATA_msb\t24\n+#define FM10K_SW_SCAN_DATA_IN_SHIFT_IN\t\t(1 << 25)\n+#define FM10K_SW_SCAN_DATA_IN_SHIFT_OUT\t\t(1 << 26)\n+#define FM10K_SW_SCAN_DATA_IN_UPDATE_NODES\t(1 << 27)\n+#define FM10K_SW_SCAN_DATA_IN_INJECT\t\t(1 << 28)\n+#define FM10K_SW_SCAN_DATA_IN_DRAIN\t\t(1 << 29)\n+#define FM10K_SW_SCAN_DATA_IN_PASSTHRU\t\t(1 << 30)\n+#define FM10K_SW_SCAN_DATA_IN_SINGLE\t\t(1 << 31)\n+#define FM10K_SW_CRM_DATA(m_, n_)\t\t\\\n+\t\tFM10K_SW_MGMT_REG(0x1000 + 0x2 * (m_) + (n_))\n+\n+#define FM10K_SW_CRM_CTRL\t\tFM10K_SW_MGMT_REG(0x2000)\n+#define FM10K_SW_CRM_STATUS\t\tFM10K_SW_MGMT_REG(0x2001)\n+#define FM10K_SW_CRM_TIME\t\tFM10K_SW_MGMT_REG(0x2002)\n+#define FM10K_SW_CRM_SRAM_CTRL\t\tFM10K_SW_MGMT_REG(0x2004)\n+#define FM10K_SW_CRM_IP\t\t\tFM10K_SW_MGMT_REG(0x2008)\n+#define FM10K_SW_CRM_IM\t\t\tFM10K_SW_MGMT_REG(0x200C)\n+#define FM10K_SW_CRM_COMMAND(n_)\tFM10K_SW_MGMT_REG(0x2080 + 0x2 * (n_))\n+#define FM10K_SW_CRM_REGISTER(n_)\tFM10K_SW_MGMT_REG(0x2100 + 0x2 * (n_))\n+#define FM10K_SW_CRM_PERIOD(n_)\t\tFM10K_SW_MGMT_REG(0x2180 + 0x2 * (n_))\n+#define FM10K_SW_CRM_PARAM(n_)\t\tFM10K_SW_MGMT_REG(0x2200 + (n_))\n+#define FM10K_SW_PLL_PCIE_CTRL\t\tFM10K_SW_MGMT_REG(0x2241)\n+#define FM10K_SW_PLL_PCIE_STAT\t\tFM10K_SW_MGMT_REG(0x2242)\n+#define FM10K_SW_SBUS_PCIE_CFG\t\tFM10K_SW_MGMT_REG(0x2243)\n+#define FM10K_SW_SBUS_PCIE_COMMAND\tFM10K_SW_MGMT_REG(0x2244)\n+#define FM10K_SW_SBUS_PCIE_REQUEST\tFM10K_SW_MGMT_REG(0x2245)\n+#define FM10K_SW_SBUS_PCIE_RESPONSE\tFM10K_SW_MGMT_REG(0x2246)\n+#define FM10K_SW_SBUS_PCIE_SPICO_IN\tFM10K_SW_MGMT_REG(0x2247)\n+#define FM10K_SW_SBUS_PCIE_SPICO_OUT\tFM10K_SW_MGMT_REG(0x2248)\n+#define FM10K_SW_SBUS_PCIE_IP\t\tFM10K_SW_MGMT_REG(0x2249)\n+#define FM10K_SW_SBUS_PCIE_IM\t\tFM10K_SW_MGMT_REG(0x224A)\n+#define FM10K_SW_MGMT_SYSTIME_CFG\tFM10K_SW_MGMT_REG(0x224C)\n+#define FM10K_SW_MGMT_SYSTIME\t\tFM10K_SW_MGMT_REG(0x224E)\n+#define FM10K_SW_MGMT_SYSTIME0\t\tFM10K_SW_MGMT_REG(0x2250)\n+#define FM10K_SW_SYSTIME_PULSE_(n_)\tFM10K_SW_MGMT_REG(0x2252 + (n_))\n+#define FM10K_SW_SYSTIME_CAPTURE_LO(n_)\tFM10K_SW_MGMT_REG(0x2258 + 0x2 * (n_))\n+#define FM10K_SW_SYSTIME_CAPTURE_HI(n_)\t\\\n+\t\tFM10K_SW_MGMT_REG(0x2258 + 0x2 * (n_) + 0x1)\n+#define FM10K_SW_PCIE_XPLL_CTRL\t\tFM10K_SW_MGMT_REG(0x3000)\n+#define FM10K_SW_PCIE_CLK_CTRL\t\tFM10K_SW_MGMT_REG(0x3001)\n+#define FM10K_SW_PCIE_CLK_CTRL2\t\tFM10K_SW_MGMT_REG(0x3002)\n+#define FM10K_SW_PCIE_CLKMON_RATIO_CFG\tFM10K_SW_MGMT_REG(0x3003)\n+#define FM10K_SW_PCIE_CLKMON_TOLERANCE_CFG\tFM10K_SW_MGMT_REG(0x3004)\n+#define FM10K_SW_PCIE_CLKMON_DEADLINES_CFG\tFM10K_SW_MGMT_REG(0x3005)\n+#define FM10K_SW_PCIE_CLK_STAT\t\tFM10K_SW_MGMT_REG(0x3006)\n+#define FM10K_SW_PCIE_CLK_IP\t\tFM10K_SW_MGMT_REG(0x3007)\n+#define FM10K_SW_PCIE_CLK_IM\t\tFM10K_SW_MGMT_REG(0x3008)\n+#define FM10K_SW_PCIE_WARM_RESET_DELAY\tFM10K_SW_MGMT_REG(0x3009)\n+#define FM10K_SW_EPL_BASE\t\tFM10K_SW_REG_OFF(0x0E0000)\n+#define FM10K_SW_EPL_PORT_REG(p_, r_)\t\\\n+\t\t(FM10K_SW_EPL_BASE + FM10K_SW_REG_OFF(0x400 * (p_) + (r_)))\n+#define FM10K_SW_EPL_LANE_REG(p_, l_, r_)\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x80 * (l_) + (r_))\n+\n+/* EPL enumerated types\n+ */\n+#define FM10K_SW_EPL_QPL_MODE_XX_XX_XX_XX\t\t0\n+#define FM10K_SW_EPL_QPL_MODE_L1_L1_L1_L1\t\t1\n+#define FM10K_SW_EPL_QPL_MODE_XX_XX_XX_L4\t\t2\n+#define FM10K_SW_EPL_QPL_MODE_XX_XX_L4_XX\t\t3\n+#define FM10K_SW_EPL_QPL_MODE_XX_L4_XX_XX\t\t4\n+#define FM10K_SW_EPL_QPL_MODE_L4_XX_XX_XX\t\t5\n+#define FM10K_SW_EPL_PCS_SEL_DISABLE\t\t\t0\n+#define FM10K_SW_EPL_PCS_SEL_AN_73\t\t\t1\n+#define FM10K_SW_EPL_PCS_SEL_SGMII_10\t\t\t2\n+#define FM10K_SW_EPL_PCS_SEL_SGMII_100\t\t\t3\n+#define FM10K_SW_EPL_PCS_SEL_SGMII_1000\t\t\t4\n+#define FM10K_SW_EPL_PCS_SEL_1000BASEX\t\t\t5\n+#define FM10K_SW_EPL_PCS_SEL_10GBASER\t\t\t6\n+#define FM10K_SW_EPL_PCS_SEL_40GBASER\t\t\t7\n+#define FM10K_SW_EPL_PCS_SEL_100GBASER\t\t\t8\n+\n+#define FM10K_SW_LANE_OVERRIDE_NORMAL\t\t\t0\n+#define FM10K_SW_LANE_OVERRIDE_FORCE_GOOD\t\t1\n+#define FM10K_SW_LANE_OVERRIDE_FORCE_BAD\t\t2\n+\n+#define FM10K_SW_TX_MAX_FCS_MODE_PASSTHRU\t\t0\n+#define FM10K_SW_TX_MAX_FCS_MODE_PASSSTHRU_CHECK\t1\n+#define FM10K_SW_TX_MAX_FCS_MODE_REPLACE_GOOD\t\t2\n+#define FM10K_SW_TX_MAX_FCS_MODE_REPLACE_BAD\t\t3\n+#define FM10K_SW_TX_MAX_FCS_MODE_REPLACE_NORMAL\t\t4\n+\n+#define FM10K_SW_TX_MAC_DRAIN_MODE_DRAIN_DRAIN\t\t0\n+#define FM10K_SW_TX_MAC_DRAIN_MODE_DRAIN_NORMAL\t\t1\n+#define FM10K_SW_TX_MAC_DRAIN_MODE_HOLD_NORMAL\t\t2\n+#define FM10K_SW_TX_MAC_DRAIN_MODE_HOLD_HOLD\t\t3\n+\n+#define FM10K_SW_TX_MAC_FAULT_MODE_NORMAL\t\t0\n+#define FM10K_SW_TX_MAC_FAULT_MODE_FORCE_IDLE\t\t1\n+#define FM10K_SW_TX_MAC_FAULT_MODE_FORCE_LOCAL_FAULT\t2\n+#define FM10K_SW_TX_MAC_FAULT_MODE_FORCE_REMOTE_FAULT\t3\n+#define FM10K_SW_TX_MAC_FAULT_MODE_FORCE_LINK_INTERRUPTION\t4\n+#define FM10K_SW_TX_MAC_FAULT_MODE_FORCE_OK\t\t5\n+#define FM10K_SW_TX_MAC_FAULT_MODE_FORCE_ERROR\t\t6\n+#define FM10K_SW_TX_MAC_FAULT_MODE_FORCE_USER_VAL\t7\n+\n+#define FM10K_SW_EPL_IP(p_)\t\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x300)\n+#define FM10K_SW_EPL_IP_AN_PORT_INTERRUPT_lsb\t0\n+#define FM10K_SW_EPL_IP_AN_PORT_INTERRUPT_msb\t3\n+#define FM10K_SW_EPL_IP_AN_PORT_INTERRUPT(n_)\t(1 << ((n_) + 0))\n+#define FM10K_SW_EPL_IP_LINK_PORT_INTERRUPT_lsb\t4\n+#define FM10K_SW_EPL_IP_LINK_PORT_INTERRUPT_msb\t7\n+#define FM10K_SW_EPL_IP_LINK_PORT_INTERRUPT(n_)\t(1 << ((n_) + 4))\n+#define FM10K_SW_EPL_IP_SERDES_INTERRUPT_lsb\t8\n+#define FM10K_SW_EPL_IP_SERDES_INTERRUPT_msb\t11\n+#define FM10K_SW_EPL_IP_SERDES_INTERRUPT(n_)\t(1 << ((n_) + 8))\n+#define FM10K_SW_EPL_IP_ERROR_INTERRUPT\t\t(1 << 12)\n+\n+#define FM10K_SW_EPL_ERROR_IP(p_)\tFM10K_SW_EPL_PORT_REG((p_), 0x301)\n+#define FM10K_SW_EPL_ERROR_IM(p_)\tFM10K_SW_EPL_PORT_REG((p_), 0x302)\n+#define FM10K_SW_EPL_ERROR_IM_ALL\tFM10K_SW_MASK32(8, 0)\n+#define FM10K_SW_EPL_BIST_STATUS(p_)\tFM10K_SW_EPL_PORT_REG((p_), 0x303)\n+#define FM10K_SW_EPL_CFG_A(p_)\t\tFM10K_SW_EPL_PORT_REG((p_), 0x304)\n+#define FM10K_SW_EPL_CFG_A_SPEED_UP\t(1 << 0)\n+#define FM10K_SW_EPL_CFG_A_TIMEOUT_lsb\t1\n+#define FM10K_SW_EPL_CFG_A_TIMEOUT_msb\t6\n+#define FM10K_SW_EPL_CFG_A_ACTIVE(p_)\t(1 << ((p_) + 7))\n+#define FM10K_SW_EPL_CFG_A_ACTIVE_QUAD\t(0xf << 7)\n+\n+#define FM10K_SW_EPL_CFG_A_SKEW_TOLERANCE_lsb\t11\n+#define FM10K_SW_EPL_CFG_A_SKEW_TOLERANCE_msb\t16\n+\n+#define FM10K_SW_EPL_CFG_B(p_)\t\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x305)\n+#define FM10K_SW_EPL_CFG_B_PCS_SEL_lsb(p_)\t((p_) * 4)\n+#define FM10K_SW_EPL_CFG_B_PCS_SEL_msb(p_)\t(((p_) * 4) + 3)\n+#define FM10K_SW_EPL_CFG_B_QPL_MODE_lsb\t\t16\n+#define FM10K_SW_EPL_CFG_B_QPL_MODE_msb\t\t18\n+#define FM10K_SW_EPL_LED_STATUS(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x306)\n+\n+#define FM10K_SW_EPL_LED_STATUS_PORT_RESET(n_)\t\t(1 << ((n_) * 6 + 0))\n+#define FM10K_SW_EPL_LED_STATUS_PORT_LINK_UP(n_)\t(1 << ((n_) * 6 + 1))\n+#define FM10K_SW_EPL_LED_STATUS_PORT_LOCAL_FAULT(n_)\t(1 << ((n_) * 6 + 2))\n+#define FM10K_SW_EPL_LED_STATUS_PORT_REMOTE_FAULT(n_)\t(1 << ((n_) * 6 + 3))\n+#define FM10K_SW_EPL_LED_STATUS_PORT_TRANSMITTING(n_)\t(1 << ((n_) * 6 + 4))\n+#define FM10K_SW_EPL_LED_STATUS_PORT_RECEIVING(n_)\t(1 << ((n_) * 6 + 5))\n+\n+#define FM10K_SW_EPL_FIFO_ERROR_STATUS(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x307)\n+#define FM10K_SW_EPL_TX_FIFO_RD_STATUS(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x308)\n+#define FM10K_SW_EPL_TX_FIFO_WR_STATUS(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x309)\n+#define FM10K_SW_EPL_TX_FIFO_A_STATUS(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x30A)\n+#define FM10K_SW_EPL_TX_FIFO_B_STATUS(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x30B)\n+#define FM10K_SW_EPL_TX_FIFO_C_STATUS(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x30C)\n+#define FM10K_SW_EPL_TX_FIFO_D_STATUS(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x30D)\n+#define FM10K_SW_EPL_RX_FIFO_RD_STATUS(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x30E)\n+#define FM10K_SW_EPL_RX_FIFO_WR_STATUS(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x30F)\n+#define FM10K_SW_EPL_RX_FIFO_A_STATUS(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x310)\n+#define FM10K_SW_EPL_RX_FIFO_B_STATUS(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x311)\n+#define FM10K_SW_EPL_RX_FIFO_C_STATUS(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x312)\n+#define FM10K_SW_EPL_RX_FIFO_D_STATUS(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x313)\n+#define FM10K_SW_PCS_ML_BASER_CFG(p_)\t\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x314)\n+#define FM10K_SW_PCS_ML_BASER_RX_STATUS(p_) \\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x315)\n+#define FM10K_SW_PCS_100GBASER_BIP_0(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x317)\n+#define FM10K_SW_PCS_100GBASER_BIP_1(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x318)\n+#define FM10K_SW_PCS_100GBASER_BIP_2(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x319)\n+#define FM10K_SW_PCS_100GBASER_BIP_3(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x31A)\n+#define FM10K_SW_PCS_100GBASER_BIP_4(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x31B)\n+#define FM10K_SW_PCS_100GBASER_BIP_5(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x31C)\n+#define FM10K_SW_PCS_100GBASER_BIP_6(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x31D)\n+#define FM10K_SW_PCS_100GBASER_BIP_7(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x31E)\n+#define FM10K_SW_PCS_100GBASER_BIP_8(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x31F)\n+#define FM10K_SW_PCS_100GBASER_BIP_9(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x320)\n+#define FM10K_SW_PCS_100GBASER_BIP_10(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x321)\n+#define FM10K_SW_PCS_100GBASER_BIP_11(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x322)\n+#define FM10K_SW_PCS_100GBASER_BIP_12(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x323)\n+#define FM10K_SW_PCS_100GBASER_BIP_13(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x324)\n+#define FM10K_SW_PCS_100GBASER_BIP_14(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x325)\n+#define FM10K_SW_PCS_100GBASER_BIP_15(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x326)\n+#define FM10K_SW_PCS_100GBASER_BIP_16(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x327)\n+#define FM10K_SW_PCS_100GBASER_BIP_17(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x328)\n+#define FM10K_SW_PCS_100GBASER_BIP_18(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x329)\n+#define FM10K_SW_PCS_100GBASER_BIP_19(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x32A)\n+#define FM10K_SW_PCS_100GBASER_BLOCK_LOCK(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x32B)\n+#define FM10K_SW_PCS_100GBASER_AMPS_LOCK(p_)\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x32C)\n+#define FM10K_SW_RS_FEC_UNCORRECTED(p_)\t\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x33D)\n+#define FM10K_SW_RS_FEC_CFG(p_)\t\t\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x32E)\n+#define FM10K_SW_RS_FEC_STATUS(p_)\t\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x330)\n+#define FM10K_SW_EPL_SYSTIME(p_)\t\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x331)\n+#define FM10K_SW_EPL_SYSTIME0(p_)\t\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x332)\n+#define FM10K_SW_EPL_SYSTIME_CFG(p_)\t\t\t\\\n+\t\tFM10K_SW_EPL_PORT_REG((p_), 0x333)\n+#define FM10K_SW_PORT_STATUS(p_, l_)\t\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x0)\n+#define FM10K_SW_AN_IM(p_, l_)\t\t\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x1)\n+\n+#define FM10K_SW_AN_IM_ALL\t\tFM10K_SW_MASK32(18, 0)\n+#define FM10K_SW_LINK_IM(p_, l_)\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x2)\n+#define FM10K_SW_LINK_IM_ALL\t\tFM10K_SW_MASK32(29, 0)\n+#define FM10K_SW_AN_IP(p_, l_)\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x3)\n+#define FM10K_SW_LINK_IP(p_, l_)\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x4)\n+#define FM10K_SW_MP_CFG(p_, l_)\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x6)\n+#define FM10K_SW_AN_37_PAGE_RX(p_, l_)\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x8)\n+#define FM10K_SW_AN_73_PAGE_RX(p_, l_)\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0xA)\n+#define FM10K_SW_LINK_RULES(p_, l_)\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0xC)\n+\n+#define FM10K_SW_LINK_RULES_FAULT_TIME_SCALE_UP_lsb\t0\n+#define FM10K_SW_LINK_RULES_FAULT_TIME_SCALE_UP_msb\t3\n+#define FM10K_SW_LINK_RULES_FAULT_TICKS_UP_lsb\t\t4\n+#define FM10K_SW_LINK_RULES_FAULT_TICKS_UP_msb\t\t8\n+#define FM10K_SW_LINK_RULES_FAULT_TIME_SCALE_DOWN_lsb\t9\n+#define FM10K_SW_LINK_RULES_FAULT_TIME_SCALE_DOWN_msb\t12\n+#define FM10K_SW_LINK_RULES_FAULT_TICKS_DOWN_lsb\t13\n+#define FM10K_SW_LINK_RULES_FAULT_TICKS_DOWN_msb\t17\n+#define FM10K_SW_LINK_RULES_HEARTBEAT_TIME_SCALE_lsb\t18\n+#define FM10K_SW_LINK_RULES_HEARTBEAT_TIME_SCALE_msb\t21\n+#define FM10K_SW_MAC_CFG(p_, l_)\t\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x10)\n+#define FM10K_SW_MAC_CFG_ARRAY_SIZE\t\t8\n+#define FM10K_SW_MAC_CFG_TX_ANTI_BUBBLE_WATERMARK_lsb\t0\n+#define FM10K_SW_MAC_CFG_TX_ANTI_BUBBLE_WATERMARK_msb\t5\n+#define FM10K_SW_MAC_CFG_TX_RATE_FIFO_WATERMARK_lsb\t6\n+#define FM10K_SW_MAC_CFG_TX_RATE_FIFO_WATERMARK_msb\t9\n+#define FM10K_SW_MAC_CFG_TX_RATE_FIFO_FAST_INC_lsb\t10\n+#define FM10K_SW_MAC_CFG_TX_RATE_FIFO_FAST_INC_msb\t17\n+#define FM10K_SW_MAC_CFG_TX_RATE_FIFO_SLOW_INC_lsb\t18\n+#define FM10K_SW_MAC_CFG_TX_RATE_FIFO_SLOW_INC_msb\t25\n+#define FM10K_SW_MAC_CFG_TX_IDLE_MIN_IFG_BYTES_lsb\t26\n+#define FM10K_SW_MAC_CFG_TX_IDLE_MIN_IFG_BYTES_msb\t31\n+\n+#define FM10K_SW_MAC_CFG_TX_CLOCK_COMPENSATION_TIMEOUT_lsb\t32\n+#define FM10K_SW_MAC_CFG_TX_CLOCK_COMPENSATION_TIMEOUT_msb\t47\n+#define FM10K_SW_MAC_CFG_TX_CLOCK_COMPENSATION_ENABLE_bit\t48\n+\n+#define FM10K_SW_MAC_CFG_TX_FAULT_MODE_lsb\t\t49\n+#define FM10K_SW_MAC_CFG_TX_FAULT_MODE_msb\t\t51\n+#define FM10K_SW_MAC_CFG_TX_PC_ACT_TIME_SCALE_lsb\t52\n+#define FM10K_SW_MAC_CFG_TX_PC_ACT_TIME_SCALE_msb\t55\n+#define FM10K_SW_MAC_CFG_TX_PC_ACT_TIMEOUT_lsb\t\t56\n+#define FM10K_SW_MAC_CFG_TX_PC_ACT_TIMEOUT_msb\t\t63\n+#define FM10K_SW_MAC_CFG_TX_DRAIN_MODE_lsb\t\t64\n+#define FM10K_SW_MAC_CFG_TX_DRAIN_MODE_msb\t\t65\n+#define FM10K_SW_MAC_CFG_TX_MIN_COLUMNS_lsb\t\t66\n+#define FM10K_SW_MAC_CFG_TX_MIN_COLUMNS_msb\t\t71\n+#define FM10K_SW_MAC_CFG_TX_SEG_MIN_SPACING_lsb\t\t72\n+#define FM10K_SW_MAC_CFG_TX_SEG_MIN_SPACING_msb\t\t83\n+#define FM10K_SW_MAC_CFG_TX_SEG_MAX_CREDIT_lsb\t\t84\n+#define FM10K_SW_MAC_CFG_TX_SEG_MAX_CREDIT_msb\t\t95\n+#define FM10K_SW_MAC_CFG_TX_SEG_SIZE_lsb\t\t96\n+#define FM10K_SW_MAC_CFG_TX_SEG_SIZE_msb\t\t107\n+#define FM10K_SW_MAC_CFG_TX_LP_IDLE_REQUEST_bit\t\t108\n+#define FM10K_SW_MAC_CFG_TX_LPI_AUTOMATIC_bit\t\t109\n+#define FM10K_SW_MAC_CFG_TX_LPI_TIMEOUT_lsb\t\t110\n+#define FM10K_SW_MAC_CFG_TX_LPI_TIMEOUT_msb\t\t117\n+#define FM10K_SW_MAC_CFG_TX_LPI_TIME_SCALE_lsb\t\t118\n+#define FM10K_SW_MAC_CFG_TX_LPI_TIME_SCALE_msb\t\t119\n+#define FM10K_SW_MAC_CFG_TX_LPI_HOLD_TIMEOUT_lsb\t120\n+#define FM10K_SW_MAC_CFG_TX_LPI_HOLD_TIMEOUT_msb\t127\n+#define FM10K_SW_MAC_CFG_TX_LPI_HOLD_TIME_SCALE_lsb\t128\n+#define FM10K_SW_MAC_CFG_TX_LPI_HOLD_TIME_SCALE_msb\t129\n+#define FM10K_SW_MAC_CFG_TX_FCS_MODE_lsb\t\t130\n+#define FM10K_SW_MAC_CFG_TX_FCS_MODE_msb\t\t132\n+#define FM10K_SW_MAC_CFG_TX_OBEY_LINT_bit\t\t133\n+#define FM10K_SW_MAC_CFG_TX_IDLE_ENABLE_DIC_bit\t\t134\n+#define FM10K_SW_MAC_CFG_CJPAT_ENABLE_bit\t\t135\n+#define FM10K_SW_MAC_CFG_RX_MIN_FRAME_LENGTH_lsb\t136\n+#define FM10K_SW_MAC_CFG_RX_MIN_FRAME_LENGTH_msb\t143\n+#define FM10K_SW_MAC_CFG_RX_MAX_FRAME_LENGTH_lsb\t144\n+#define FM10K_SW_MAC_CFG_RX_MAX_FRAME_LENGTH_msb\t159\n+#define FM10K_SW_MAC_CFG_START_CHAR_D_lsb\t\t160\n+#define FM10K_SW_MAC_CFG_START_CHAR_D_msb\t\t167\n+#define FM10K_SW_MAC_CFG_IEEE_1588_ENABLE_bit\t\t168\n+#define FM10K_SW_MAC_CFG_FCS_START_bit\t\t\t169\n+#define FM10K_SW_MAC_CFG_PREAMBLE_MODE_bit\t\t170\n+#define FM10K_SW_MAC_CFG_COUNTER_WRAP_bit\t\t171\n+#define FM10K_SW_MAC_CFG_LINK_FAULT_DISABLE_bit\t\t172\n+#define FM10K_SW_MAC_CFG_RX_DRAIN_bit\t\t\t173\n+#define FM10K_SW_MAC_CFG_RX_FCS_FORCE_BAD_bit\t\t174\n+#define FM10K_SW_MAC_CFG_RX_IGNORE_CODE_ERRORS_bit\t175\n+#define FM10K_SW_MAC_CFG_RX_IGNORE_UNDERSIZE_ERRORS_bit\t176\n+#define FM10K_SW_MAC_CFG_RX_IGNORE_OVERSIZE_ERRORS_bit\t177\n+#define FM10K_SW_MAC_CFG_RX_IGNORE_FCS_ERRORS_bit\t178\n+#define FM10K_SW_MAC_CFG_RX_IGNORE_PREAMBLE_ERRORS_bit\t179\n+#define FM10K_SW_MAC_CFG_RX_IGNORE_IFG_ERRORS_bit\t180\n+#define FM10K_SW_MAC_CFG_ERR_WRITE_lsb\t\t\t181\n+#define FM10K_SW_MAC_CFG_ERR_WRITE_msb\t\t\t182\n+#define FM10K_SW_MAC_CFG_RX_MIN_EVENT_RATE_lsb\t\t183\n+#define FM10K_SW_MAC_CFG_RX_MIN_EVENT_RATE_msb\t\t186\n+#define FM10K_SW_MAC_CFG_RX_PC_REQUEST_lsb\t\t187\n+#define FM10K_SW_MAC_CFG_RX_PC_REQUEST_msb\t\t191\n+#define FM10K_SW_MAC_CFG_RX_PC_SEG_SIZE_lsb\t\t192\n+#define FM10K_SW_MAC_CFG_RX_PC_SEG_SIZE_msb\t\t196\n+\n+#define FM10K_SW_TX_SEQUENCE(p_, l_)\t\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x1A)\n+#define FM10K_SW_RX_SEQUENCE(p_, l_)\t\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x1C)\n+#define FM10K_SW_MAC_1588_STATUS(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x1E)\n+#define FM10K_SW_WAKE_ERROR_COUNTER(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x20)\n+#define FM10K_SW_MAC_OVERSIZE_COUNTER(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x21)\n+#define FM10K_SW_MAC_JABBER_COUNTER(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x22)\n+#define FM10K_SW_MAC_UNDERSIZE_COUNTER(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x23)\n+#define FM10K_SW_MAC_RUNT_COUNTER(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x24)\n+#define FM10K_SW_MAC_OVERRUN_COUNTER(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x25)\n+#define FM10K_SW_MAC_UNDERRUN_COUNTER(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x26)\n+#define FM10K_SW_MAC_CODE_ERROR_COUNTER(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x27)\n+#define FM10K_SW_EPL_TX_FRAME_ERROR_COUNTER(p_, l_)\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x28)\n+#define FM10K_SW_MAC_LINK_COUNTER(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x29)\n+#define FM10K_SW_PCS_1000BASEX_CFG(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x2A)\n+#define FM10K_SW_PCS_1000BASEX_RX_STATUS(p_, l_)\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x2B)\n+#define FM10K_SW_PCS_1000BASEX_TX_STATUS(p_, l_)\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x2C)\n+#define FM10K_SW_PCS_10GBASER_CFG(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x2D)\n+#define FM10K_SW_PCS_10GBASER_RX_STATUS(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x2E)\n+#define FM10K_SW_PCS_10GBASER_TX_STATUS(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x2F)\n+#define FM10K_SW_AN_37_CFG(p_, l_)\t\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x30)\n+#define FM10K_SW_AN_37_TIMER_CFG(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x34)\n+#define FM10K_SW_AN_37_BASE_PAGE_TX(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x6)\n+#define FM10K_SW_AN_37_BASE_PAGE_RX(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x8)\n+#define FM10K_SW_AN_37_NEXT_PAGE_TX(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x6)\n+#define FM10K_SW_AN_37_NEXT_PAGE_RX(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x8)\n+#define FM10K_SW_SGMII_AN_TIMER_CFG(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x34)\n+#define FM10K_SW_SGMII_AN_TX_CONFIG(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x6)\n+#define FM10K_SW_SGMII_AN_TX_CONFIG_LOOPBACK(p_, l_) \\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x6)\n+#define FM10K_SW_SGMII_AN_RX_CONFIG(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x8)\n+#define FM10K_SW_AN_37_STATUS(p_, l_)\t\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x32)\n+#define FM10K_SW_AN_73_CFG(p_, l_)\t\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x33)\n+#define FM10K_SW_AN_73_TIMER_CFG(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x34)\n+#define FM10K_SW_AN_73_BASE_PAGE_TX(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x6)\n+#define FM10K_SW_AN_73_BASE_PAGE_RX(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0xA)\n+#define FM10K_SW_AN_73_NEXT_PAGE_TX(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x6)\n+#define FM10K_SW_AN_73_NEXT_PAGE_RX(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0xA)\n+#define FM10K_SW_AN_73_STATUS(p_, l_)\t\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x36)\n+#define FM10K_SW_AN_73_TX_LCW(p_, l_)\t\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x38)\n+#define FM10K_SW_AN_73_RX_LCW(p_, l_)\t\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x3A)\n+#define FM10K_SW_PCSL_CFG(p_, l_)\t\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x3C)\n+\n+#define FM10K_SW_PCSL_CFG_SLIP_TIME_lsb\t\t\t0\n+#define FM10K_SW_PCSL_CFG_SLIP_TIME_msb\t\t\t7\n+#define FM10K_SW_PCSL_CFG_RX_BIT_SLIP_ENABLE\t\t(1 << 8)\n+#define FM10K_SW_PCSL_CFG_RX_BIT_SLIP_INITIAL\t\t(1 << 9)\n+#define FM10K_SW_PCSL_CFG_RX_GB_NARROW\t\t\t(1 << 10)\n+#define FM10K_SW_PCSL_CFG_TX_GB_NARROW\t\t\t(1 << 11)\n+\n+#define FM10K_SW_MP_EEE_CFG(p_, l_)\t\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x40)\n+#define FM10K_SW_PCS_1000BASEX_EEE_CFG(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x40)\n+#define FM10K_SW_PCS_10GBASER_EEE_CFG(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x40)\n+#define FM10K_SW_MP_STATUS(p_, l_)\t\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x44)\n+#define FM10K_SW_PCS_40GBASER_RX_BIP_STATUS(p_, l_)\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x44)\n+#define FM10K_SW_PCS_10GBASER_RX_BER_STATUS(p_, l_)\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x44)\n+#define FM10K_SW_DISPARITY_ERROR_8B10B(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x44)\n+#define FM10K_SW_LANE_CFG(p_, l_)\t\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x45)\n+#define FM10K_SW_LANE_SERDES_CFG(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x46)\n+#define FM10K_SW_LANE_ENERGY_DETECT_CFG(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x47)\n+\n+#define FM10K_SW_LANE_ENERGY_DETECT_CFG_ED_OVERRIDE_lsb\t\t0\n+#define FM10K_SW_LANE_ENERGY_DETECT_CFG_ED_OVERRIDE_msb\t\t1\n+#define FM10K_SW_LANE_ENERGY_DETECT_CFG_ED_MASK_RX_SIGNAL_OK\t(1 << 2)\n+#define FM10K_SW_LANE_ENERGY_DETECT_CFG_ED_MASK_RX_RDY\t\t(1 << 3)\n+#define FM10K_SW_LANE_ENERGY_DETECT_CFG_ED_MASK_RX_ACTIVITY\t(1 << 4)\n+#define FM10K_SW_LANE_ENERGY_DETECT_CFG_ED_MASK_ENERGY_DETECT\t(1 << 5)\n+\n+#define FM10K_SW_LANE_ACTIVITY_CFG(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x48)\n+#define FM10K_SW_LANE_SIGNAL_DETECT_CFG(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x49)\n+#define FM10K_SW_LANE_SIGNAL_DETECT_CFG_SD_OVERRIDE_lsb\t\t0\n+#define FM10K_SW_LANE_SIGNAL_DETECT_CFG_SD_OVERRIDE_msb\t\t1\n+#define FM10K_SW_LANE_SIGNAL_DETECT_CFG_SD_MASK_RX_SIGNAL_OK\t(1 << 2)\n+#define FM10K_SW_LANE_SIGNAL_DETECT_CFG_SD_MASK_RX_RDY\t\t(1 << 3)\n+#define FM10K_SW_LANE_SIGNAL_DETECT_CFG_SD_MASK_RX_ACTIVITY\t(1 << 4)\n+#define FM10K_SW_LANE_SIGNAL_DETECT_CFG_SD_MASK_ENERGY_DETECT\t(1 << 5)\n+#define FM10K_SW_LANE_STATUS(p_, l_)\t\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x4A)\n+#define FM10K_SW_LANE_SERDES_STATUS(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x4B)\n+\n+#define FM10K_SW_LANE_SERDES_STATUS_ANALOG_TO_CORE_lsb\t0\n+#define FM10K_SW_LANE_SERDES_STATUS_ANALOG_TO_CORE_msb\t7\n+#define FM10K_SW_LANE_SERDES_STATUS_CORE_STATUS_lsb\t8\n+#define FM10K_SW_LANE_SERDES_STATUS_CORE_STATUS_msb\t23\n+#define FM10K_SW_LANE_SERDES_STATUS_RX_SIGNAL_OK\t(1 << 12)\n+#define FM10K_SW_LANE_SERDES_STATUS_RX_RDY\t\t(1 << 24)\n+#define FM10K_SW_LANE_SERDES_STATUS_TX_RDY\t\t(1 << 25)\n+#define FM10K_SW_LANE_SERDES_STATUS_RX_IDLE_DETECT\t(1 << 26)\n+#define FM10K_SW_LANE_SERDES_STATUS_RX_ACTIVITY\t\t(1 << 27)\n+#define FM10K_SW_SERDES_IM(p_, l_)\t\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x4C)\n+#define FM10K_SW_SERDES_IM_CORE_STATUS_0\t\t(1 << 0)\n+#define FM10K_SW_SERDES_IM_CORE_STATUS_1\t\t(1 << 1)\n+#define FM10K_SW_SERDES_IM_CORE_STATUS_2\t\t(1 << 2)\n+#define FM10K_SW_SERDES_IM_CORE_STATUS_3\t\t(1 << 3)\n+#define FM10K_SW_SERDES_IM_CORE_STATUS_4\t\t(1 << 4)\n+#define FM10K_SW_SERDES_IM_RX_SIGNAL_OK\t\t\t\\\n+\t\tFM10K_SW_SERDES_IM_CORE_STATUS_4\n+#define FM10K_SW_SERDES_IM_CORE_STATUS_5\t\t(1 << 5)\n+#define FM10K_SW_SERDES_IM_CORE_STATUS_6\t\t(1 << 6)\n+#define FM10K_SW_SERDES_IM_CORE_STATUS_7\t\t(1 << 7)\n+#define FM10K_SW_SERDES_IM_CORE_STATUS_8\t\t(1 << 8)\n+#define FM10K_SW_SERDES_IM_CORE_STATUS_9\t\t(1 << 9)\n+#define FM10K_SW_SERDES_IM_CORE_STATUS_10\t\t(1 << 10)\n+#define FM10K_SW_SERDES_IM_CORE_STATUS_11\t\t(1 << 11)\n+#define FM10K_SW_SERDES_IM_CORE_STATUS_12\t\t(1 << 12)\n+#define FM10K_SW_SERDES_IM_CORE_STATUS_13\t\t(1 << 13)\n+#define FM10K_SW_SERDES_IM_CORE_STATUS_14\t\t(1 << 14)\n+#define FM10K_SW_SERDES_IM_CORE_STATUS_15\t\t(1 << 15)\n+#define FM10K_SW_SERDES_IM_TX_RDY\t\t\t(1 << 16)\n+#define FM10K_SW_SERDES_IM_RX_ENERGY_DETECT\t\t(1 << 17)\n+#define FM10K_SW_SERDES_IM_RX_SIGNAL_DETECT\t\t(1 << 18)\n+#define FM10K_SW_SERDES_IM_RX_RDY\t\t\t(1 << 19)\n+#define FM10K_SW_SERDES_IM_RX_ACTIVITY\t\t\t(1 << 20)\n+#define FM10K_SW_SERDES_IM_RX_IDLE_DETECT\t\t(1 << 21)\n+#define FM10K_SW_SERDES_IM_SAI_COMPLETE\t\t\t(1 << 22)\n+#define FM10K_SW_SERDES_IM_SAI_REQUEST_ERROR\t\t(1 << 23)\n+#define FM10K_SW_SERDES_IM_TX_CDC_FIFO_U_ERR\t\t(1 << 24)\n+#define FM10K_SW_SERDES_IM_TX_CDC_FIFO_ERROR\t\t(1 << 25)\n+#define FM10K_SW_SERDES_IM_RX_CDC_FIFO_U_ERR\t\t(1 << 26)\n+#define FM10K_SW_SERDES_IM_RX_CDC_FIFO_ERROR\t\t(1 << 27)\n+#define FM10K_SW_SERDES_IM_SLIP_REQUEST\t\t\t(1 << 28)\n+#define FM10K_SW_SERDES_IM_ANALOG_IP\t\t\t(1 << 29)\n+#define FM10K_SW_SERDES_IM_ALL\t\t\t\t\\\n+\t\tFM10K_SW_MASK32(29, 0)\n+#define FM10K_SW_SERDES_IP(p_, l_)\t\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x4D)\n+#define FM10K_SW_SERDES_IP_CORE_STATUS_0\t\t(1 << 0)\n+#define FM10K_SW_SERDES_IP_CORE_STATUS_1\t\t(1 << 1)\n+#define FM10K_SW_SERDES_IP_CORE_STATUS_2\t\t(1 << 2)\n+#define FM10K_SW_SERDES_IP_CORE_STATUS_3\t\t(1 << 3)\n+#define FM10K_SW_SERDES_IP_CORE_STATUS_4\t\t(1 << 4)\n+#define FM10K_SW_SERDES_IP_RX_SIGNAL_OK\t\t\t\\\n+\t\tFM10K_SW_SERDES_IP_CORE_STATUS_4\n+#define FM10K_SW_SERDES_IP_CORE_STATUS_5\t\t(1 << 5)\n+#define FM10K_SW_SERDES_IP_CORE_STATUS_6\t\t(1 << 6)\n+#define FM10K_SW_SERDES_IP_CORE_STATUS_7\t\t(1 << 7)\n+#define FM10K_SW_SERDES_IP_CORE_STATUS_8\t\t(1 << 8)\n+#define FM10K_SW_SERDES_IP_CORE_STATUS_9\t\t(1 << 9)\n+#define FM10K_SW_SERDES_IP_CORE_STATUS_10\t\t(1 << 10)\n+#define FM10K_SW_SERDES_IP_CORE_STATUS_11\t\t(1 << 11)\n+#define FM10K_SW_SERDES_IP_CORE_STATUS_12\t\t(1 << 12)\n+#define FM10K_SW_SERDES_IP_CORE_STATUS_13\t\t(1 << 13)\n+#define FM10K_SW_SERDES_IP_CORE_STATUS_14\t\t(1 << 14)\n+#define FM10K_SW_SERDES_IP_CORE_STATUS_15\t\t(1 << 15)\n+#define FM10K_SW_SERDES_IP_TX_RDY\t\t\t(1 << 16)\n+#define FM10K_SW_SERDES_IP_RX_ENERGY_DETECT\t\t(1 << 17)\n+#define FM10K_SW_SERDES_IP_RX_SIGNAL_DETECT\t\t(1 << 18)\n+#define FM10K_SW_SERDES_IP_RX_RDY\t\t\t(1 << 19)\n+#define FM10K_SW_SERDES_IP_RX_ACTIVITY\t\t\t(1 << 20)\n+#define FM10K_SW_SERDES_IP_RX_IDLE_DETECT\t\t(1 << 21)\n+#define FM10K_SW_SERDES_IP_SAI_COMPLETE\t\t\t(1 << 22)\n+#define FM10K_SW_SERDES_IP_SAI_REQUEST_ERROR\t\t(1 << 23)\n+#define FM10K_SW_SERDES_IP_TX_CDC_FIFO_U_ERR\t\t(1 << 24)\n+#define FM10K_SW_SERDES_IP_TX_CDC_FIFO_ERROR\t\t(1 << 25)\n+#define FM10K_SW_SERDES_IP_RX_CDC_FIFO_U_ERR\t\t(1 << 26)\n+#define FM10K_SW_SERDES_IP_RX_CDC_FIFO_ERROR\t\t(1 << 27)\n+#define FM10K_SW_SERDES_IP_SLIP_REQUEST\t\t\t(1 << 28)\n+#define FM10K_SW_SERDES_IP_ANALOG_IP\t\t\t(1 << 29)\n+#define FM10K_SW_SERDES_IP_ALL\t\t\t\t\\\n+\t\tFM10K_SW_MASK32(29, 0)\n+#define FM10K_SW_LANE_ANALOG_IM(p_, l_)\t\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x4E)\n+#define FM10K_SW_LANE_ANALOG_IP(p_, l_)\t\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x4F)\n+#define FM10K_SW_LANE_SAI_CFG(p_, l_)\t\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x50)\n+#define FM10K_SW_LANE_SAI_CFG_CODE_lsb64\t\t0\n+#define FM10K_SW_LANE_SAI_CFG_CODE_msb64\t\t15\n+#define FM10K_SW_LANE_SAI_CFG_DATA_lsb64\t\t16\n+#define FM10K_SW_LANE_SAI_CFG_DATA_msb64\t\t31\n+#define FM10K_SW_LANE_SAI_CFG_RESULT_PATTERN_lsb64\t32\n+#define FM10K_SW_LANE_SAI_CFG_RESULT_PATTERN_msb64\t47\n+#define FM10K_SW_LANE_SAI_CFG_RESULT_MODE_lsb64\t\t48\n+#define FM10K_SW_LANE_SAI_CFG_RESULT_MODE_msb64\t\t49\n+#define FM10K_SW_LANE_SAI_CFG_REQUEST\t\t\t(1ULL << 50)\n+#define FM10K_SW_LANE_SAI_STATUS(p_, l_)\t\t\\\n+\t\tFM10K_SW_EPL_LANE_REG((p_), (l_), 0x52)\n+#define FM10K_SW_LANE_SAI_STATUS_RESULT_lsb\t\t0\n+#define FM10K_SW_LANE_SAI_STATUS_RESULT_msb\t\t15\n+#define FM10K_SW_LANE_SAI_STATUS_COMPLETE\t\t(1 << 16)\n+#define FM10K_SW_LANE_SAI_STATUS_ACCESS_REQUEST\t\t(1 << 17)\n+#define FM10K_SW_LANE_SAI_STATUS_IN_PROGRESS\t\t(1 << 18)\n+#define FM10K_SW_LANE_SAI_STATUS_BUSY\t\t\t(1 << 19)\n+#define FM10K_SW_LANE_SAI_STATUS_REQUEST_ERROR\t\t(1 << 20)\n+\n+#define FM10K_SW_PORTS_MGMT_BASE\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0x0E8000)\n+#define FM10K_SW_PORTS_MGMT_REG(wo_)\t\t\t\\\n+\t\t(FM10K_SW_PORTS_MGMT_BASE + FM10K_SW_REG_OFF(wo_))\n+\n+#define FM10K_SW_PLL_EPL_CTRL\t\t\tFM10K_SW_PORTS_MGMT_REG(0x0)\n+#define FM10K_SW_PLL_EPL_STAT\t\t\tFM10K_SW_PORTS_MGMT_REG(0x1)\n+#define FM10K_SW_PLL_FABRIC_CTRL\t\tFM10K_SW_PORTS_MGMT_REG(0x2)\n+\n+#define FM10K_SW_PLL_FABRIC_REFDIV_lsb\t\t3\n+#define FM10K_SW_PLL_FABRIC_REFDIV_msb\t\t8\n+#define FM10K_SW_PLL_FABRIC_FBDIV4_lsb\t\t9\n+#define FM10K_SW_PLL_FABRIC_FBDIV4_msb\t\t9\n+#define FM10K_SW_PLL_FABRIC_FBDIV255_lsb\t10\n+#define FM10K_SW_PLL_FABRIC_FBDIV255_msb\t17\n+#define FM10K_SW_PLL_FABRIC_OUTDIV_lsb\t\t18\n+#define FM10K_SW_PLL_FABRIC_OUTDIV_msb\t\t23\n+#define FM10K_SW_PLL_FABRIC_STAT\t\tFM10K_SW_PORTS_MGMT_REG(0x3)\n+#define FM10K_SW_PLL_FABRIC_LOCK\t\tFM10K_SW_PORTS_MGMT_REG(0x4)\n+#define FM10K_SW_PLL_FABRIC_FREQSEL_lsb\t\t4\n+#define FM10K_SW_PLL_FABRIC_FREQSEL_msb\t\t7\n+#define\tFM10K_SW_PLL_FABRIC_FREQSEL_CTRL\t0\n+#define\tFM10K_SW_PLL_FABRIC_FREQSEL_F600\t1\n+#define\tFM10K_SW_PLL_FABRIC_FREQSEL_F500\t2\n+#define\tFM10K_SW_PLL_FABRIC_FREQSEL_F400\t3\n+#define\tFM10K_SW_PLL_FABRIC_FREQSEL_F300\t4\n+#define FM10K_SW_SBUS_EPL_CFG\t\t\tFM10K_SW_PORTS_MGMT_REG(0x5)\n+#define FM10K_SW_SBUS_EPL_COMMAND\t\tFM10K_SW_PORTS_MGMT_REG(0x6)\n+#define FM10K_SW_SBUS_EPL_REQUEST\t\tFM10K_SW_PORTS_MGMT_REG(0x7)\n+#define FM10K_SW_SBUS_EPL_RESPONSE\t\tFM10K_SW_PORTS_MGMT_REG(0x8)\n+#define FM10K_SW_SBUS_EPL_SPICO_IN\t\tFM10K_SW_PORTS_MGMT_REG(0x9)\n+#define FM10K_SW_SBUS_EPL_SPICO_OUT\t\tFM10K_SW_PORTS_MGMT_REG(0xA)\n+#define FM10K_SW_SBUS_EPL_IP\t\t\tFM10K_SW_PORTS_MGMT_REG(0xB)\n+#define FM10K_SW_SBUS_EPL_IM\t\t\tFM10K_SW_PORTS_MGMT_REG(0xC)\n+\n+#define FM10K_SW_ETHCLK_CFG(n_)\t\t\t\\\n+\t\tFM10K_SW_PORTS_MGMT_REG(0xE + (n_))\n+#define FM10K_SW_ETHCLK_RATIO(n_)\t\t\\\n+\t\tFM10K_SW_PORTS_MGMT_REG(0x10 + (n_))\n+#define FM10K_SW_PM_CLKOBS_CTRL\t\t\tFM10K_SW_PORTS_MGMT_REG(0x12)\n+\n+#define FM10K_SW_PCIE_CFG_BASE\t\t\tFM10K_SW_REG_OFF(0x120000)\n+#define FM10K_SW_PCIE_CFG_REG(wo_)\t\t\\\n+\t\t(FM10K_SW_PCIE_CFG_BASE + FM10K_SW_REG_OFF(wo_))\n+\n+/*\n+ * These register offsets can also be passed to fm10k_read_config(), which\n+ * will mask off the upper bits\n+ */\n+#define FM10K_SW_PCIE_CFG_ID\t\t\tFM10K_SW_PCIE_CFG_REG(0x0)\n+#define FM10K_SW_PCIE_CFG_CMD\t\t\tFM10K_SW_PCIE_CFG_REG(0x1)\n+#define FM10K_SW_PCIE_CFG_1\t\t\tFM10K_SW_PCIE_CFG_REG(0x2)\n+#define FM10K_SW_PCIE_CFG_2\t\t\tFM10K_SW_PCIE_CFG_REG(0x3)\n+#define FM10K_SW_PCIE_CFG_BAR0\t\t\tFM10K_SW_PCIE_CFG_REG(0x4)\n+#define FM10K_SW_PCIE_CFG_BAR1\t\t\tFM10K_SW_PCIE_CFG_REG(0x5)\n+#define FM10K_SW_PCIE_CFG_BAR2\t\t\tFM10K_SW_PCIE_CFG_REG(0x6)\n+#define FM10K_SW_PCIE_CFG_BAR3\t\t\tFM10K_SW_PCIE_CFG_REG(0x7)\n+#define FM10K_SW_PCIE_CFG_BAR4\t\t\tFM10K_SW_PCIE_CFG_REG(0x8)\n+#define FM10K_SW_PCIE_CFG_BAR5\t\t\tFM10K_SW_PCIE_CFG_REG(0x9)\n+#define FM10K_SW_PCIE_CFG_CARDBUS\t\tFM10K_SW_PCIE_CFG_REG(0xA)\n+#define FM10K_SW_PCIE_CFG_SUBID\t\t\tFM10K_SW_PCIE_CFG_REG(0xB)\n+#define FM10K_SW_PCIE_CFG_EXP_ROM\t\tFM10K_SW_PCIE_CFG_REG(0xC)\n+#define FM10K_SW_PCIE_CFG_CAP_PTR\t\tFM10K_SW_PCIE_CFG_REG(0xD)\n+#define FM10K_SW_PCIE_CFG_RSVD\t\t\tFM10K_SW_PCIE_CFG_REG(0xE)\n+#define FM10K_SW_PCIE_CFG_INT\t\t\tFM10K_SW_PCIE_CFG_REG(0xF)\n+#define FM10K_SW_PCIE_CFG_PM_CAP\t\tFM10K_SW_PCIE_CFG_REG(0x10)\n+#define FM10K_SW_PCIE_CFG_PM_CTRL\t\tFM10K_SW_PCIE_CFG_REG(0x11)\n+#define FM10K_SW_PCIE_CFG_PCIE_CAP\t\tFM10K_SW_PCIE_CFG_REG(0x1C)\n+#define FM10K_SW_PCIE_CFG_PCIE_DEV_CAP\t\tFM10K_SW_PCIE_CFG_REG(0x1D)\n+#define FM10K_SW_PCIE_CFG_PCIE_DEV_CTRL\t\tFM10K_SW_PCIE_CFG_REG(0x1E)\n+#define FM10K_SW_PCIE_CFG_PCIE_LINK_CAP\t\tFM10K_SW_PCIE_CFG_REG(0x1F)\n+#define FM10K_SW_PCIE_CFG_PCIE_LINK_CTRL\tFM10K_SW_PCIE_CFG_REG(0x20)\n+\n+#define FM10K_SW_PCIE_CFG_LINK_SPEED_lsb\t16\n+#define FM10K_SW_PCIE_CFG_LINK_SPEED_msb\t19\n+#define FM10K_SW_PCIE_CFG_LINK_SPEED_2P5\t1\n+#define FM10K_SW_PCIE_CFG_LINK_SPEED_5\t\t2\n+#define FM10K_SW_PCIE_CFG_LINK_SPEED_8\t\t3\n+#define FM10K_SW_PCIE_CFG_LINK_WIDTH_lsb\t20\n+#define FM10K_SW_PCIE_CFG_LINK_WIDTH_msb\t24\n+\n+#define FM10K_SW_PCIE_CFG_PCIE_DEV_CAP2\t\tFM10K_SW_PCIE_CFG_REG(0x25)\n+#define FM10K_SW_PCIE_CFG_PCIE_DEV_CTRL2\tFM10K_SW_PCIE_CFG_REG(0x26)\n+#define FM10K_SW_PCIE_CFG_PCIE_LINK_CTRL2\tFM10K_SW_PCIE_CFG_REG(0x28)\n+#define FM10K_SW_PCIE_CFG_MSIX_CAP\t\tFM10K_SW_PCIE_CFG_REG(0x2C)\n+#define FM10K_SW_PCIE_CFG_MSIX_TABLE_OFFSET\tFM10K_SW_PCIE_CFG_REG(0x2D)\n+#define FM10K_SW_PCIE_CFG_MSIX_PBA\t\tFM10K_SW_PCIE_CFG_REG(0x2E)\n+#define FM10K_SW_PCIE_CFG_VPD_CAP\t\tFM10K_SW_PCIE_CFG_REG(0x34)\n+#define FM10K_SW_PCIE_CFG_VPD_DATA\t\tFM10K_SW_PCIE_CFG_REG(0x35)\n+#define FM10K_SW_PCIE_CFG_AER_HDR\t\tFM10K_SW_PCIE_CFG_REG(0x40)\n+#define FM10K_SW_PCIE_CFG_AER_UNERR_STATUS\tFM10K_SW_PCIE_CFG_REG(0x41)\n+#define FM10K_SW_PCIE_CFG_AER_UNERR_MASK\tFM10K_SW_PCIE_CFG_REG(0x42)\n+#define FM10K_SW_PCIE_CFG_AER_UNERR_SEVERITY\tFM10K_SW_PCIE_CFG_REG(0x43)\n+#define FM10K_SW_PCIE_CFG_AER_COERR_STATUS\tFM10K_SW_PCIE_CFG_REG(0x44)\n+#define FM10K_SW_PCIE_CFG_AER_COERR_MASK\tFM10K_SW_PCIE_CFG_REG(0x45)\n+#define FM10K_SW_PCIE_CFG_AER_CTRL\t\tFM10K_SW_PCIE_CFG_REG(0x46)\n+#define FM10K_SW_PCIE_CFG_AER_HEADER_LOG0\tFM10K_SW_PCIE_CFG_REG(0x47)\n+#define FM10K_SW_PCIE_CFG_AER_HEADER_LOG1\tFM10K_SW_PCIE_CFG_REG(0x48)\n+#define FM10K_SW_PCIE_CFG_AER_HEADER_LOG2\tFM10K_SW_PCIE_CFG_REG(0x49)\n+#define FM10K_SW_PCIE_CFG_AER_HEADER_LOG3\tFM10K_SW_PCIE_CFG_REG(0x4A)\n+#define FM10K_SW_PCIE_CFG_SPD_HDR\t\tFM10K_SW_PCIE_CFG_REG(0x52)\n+#define FM10K_SW_PCIE_CFG_SPD_NUMBER_L\t\tFM10K_SW_PCIE_CFG_REG(0x53)\n+#define FM10K_SW_PCIE_CFG_SPD_NUMBER_H\t\tFM10K_SW_PCIE_CFG_REG(0x54)\n+#define FM10K_SW_PCIE_CFG_ARI_HDR\t\tFM10K_SW_PCIE_CFG_REG(0x56)\n+#define FM10K_SW_PCIE_CFG_ARI_CTRL\t\tFM10K_SW_PCIE_CFG_REG(0x57)\n+#define FM10K_SW_PCIE_CFG_SPCIE_HDR\t\tFM10K_SW_PCIE_CFG_REG(0x5A)\n+#define FM10K_SW_PCIE_CFG_SPCIE_LINK_CTRL3\tFM10K_SW_PCIE_CFG_REG(0x5B)\n+#define FM10K_SW_PCIE_CFG_SPCIE_ERR_STS\t\tFM10K_SW_PCIE_CFG_REG(0x5C)\n+#define FM10K_SW_PCIE_CFG_SPCIE_LINK_EQ01\tFM10K_SW_PCIE_CFG_REG(0x5D)\n+#define FM10K_SW_PCIE_CFG_SPCIE_LINK_EQ23\tFM10K_SW_PCIE_CFG_REG(0x5E)\n+#define FM10K_SW_PCIE_CFG_SPCIE_LINK_EQ45\tFM10K_SW_PCIE_CFG_REG(0x5F)\n+#define FM10K_SW_PCIE_CFG_SPCIE_LINK_EQ67\tFM10K_SW_PCIE_CFG_REG(0x60)\n+#define FM10K_SW_PCIE_CFG_SRIOV_HDR\t\tFM10K_SW_PCIE_CFG_REG(0x62)\n+#define FM10K_SW_PCIE_CFG_SRIOV_CAP\t\tFM10K_SW_PCIE_CFG_REG(0x63)\n+#define FM10K_SW_PCIE_CFG_SRIOV_CTRL\t\tFM10K_SW_PCIE_CFG_REG(0x64)\n+#define FM10K_SW_PCIE_CFG_SRIOV_CFG\t\tFM10K_SW_PCIE_CFG_REG(0x65)\n+#define FM10K_SW_PCIE_CFG_SRIOV_NUM\t\tFM10K_SW_PCIE_CFG_REG(0x66)\n+#define FM10K_SW_PCIE_CFG_SRIOV_MAP\t\tFM10K_SW_PCIE_CFG_REG(0x67)\n+#define FM10K_SW_PCIE_CFG_SRIOV_DEVID\t\tFM10K_SW_PCIE_CFG_REG(0x69)\n+#define FM10K_SW_PCIE_CFG_SRIOV_PAGE_SUP\tFM10K_SW_PCIE_CFG_REG(0x69)\n+#define FM10K_SW_PCIE_CFG_SRIOV_PAGE_CFG\tFM10K_SW_PCIE_CFG_REG(0x6A)\n+#define FM10K_SW_PCIE_CFG_SRIOV_BAR0\t\tFM10K_SW_PCIE_CFG_REG(0x6B)\n+#define FM10K_SW_PCIE_CFG_SRIOV_BAR1\t\tFM10K_SW_PCIE_CFG_REG(0x6C)\n+#define FM10K_SW_PCIE_CFG_SRIOV_BAR2\t\tFM10K_SW_PCIE_CFG_REG(0x6D)\n+#define FM10K_SW_PCIE_CFG_SRIOV_BAR3\t\tFM10K_SW_PCIE_CFG_REG(0x6E)\n+#define FM10K_SW_PCIE_CFG_SRIOV_BAR4\t\tFM10K_SW_PCIE_CFG_REG(0x6F)\n+#define FM10K_SW_PCIE_CFG_SRIOV_BAR5\t\tFM10K_SW_PCIE_CFG_REG(0x70)\n+#define FM10K_SW_PCIE_CFG_SRIOV_MIG\t\tFM10K_SW_PCIE_CFG_REG(0x71)\n+#define FM10K_SW_PCIE_CFG_TPH_HDR\t\tFM10K_SW_PCIE_CFG_REG(0x72)\n+#define FM10K_SW_PCIE_CFG_TPH_CAP\t\tFM10K_SW_PCIE_CFG_REG(0x73)\n+#define FM10K_SW_PCIE_CFG_TPH_CTRL\t\tFM10K_SW_PCIE_CFG_REG(0x74)\n+#define FM10K_SW_PCIE_CFG_ACS_HDR\t\tFM10K_SW_PCIE_CFG_REG(0x76)\n+#define FM10K_SW_PCIE_CFG_ACS_CAP\t\tFM10K_SW_PCIE_CFG_REG(0x77)\n+#define FM10K_SW_PCIE_PORTLOGIC\t\t\tFM10K_SW_PCIE_CFG_REG(0x1C0)\n+#define FM10K_SW_PCIE_PORTLOGIC_LINK_STATE\tFM10K_SW_PCIE_CFG_REG(0x1CA)\n+\n+#define FM10K_SW_FFU_BASE\t\t\tFM10K_SW_REG_OFF(0xC00000)\n+#define FM10K_SW_FFU_REG(wo_)\t\t\t\\\n+\t\t(FM10K_SW_FFU_BASE + FM10K_SW_REG_OFF(wo_))\n+#define FM10K_SW_FFU_NUM_SLICES\t\t\t32\n+#define FM10K_SW_FFU_NUM_SCENARIOS\t\t32\n+\n+/* FFU enumerated types */\n+#define FM10K_SW_FFU_MUX_SEL_MAP_DIP_MAP_SIP\t\t0\n+#define FM10K_SW_FFU_MUX_SEL_MAP_DMAC_MAP_SMAC\t\t1\n+#define FM10K_SW_FFU_MUX_SEL_MAP_PROT_MAP_LENGTH\t2\n+#define FM10K_SW_FFU_MUX_SEL_MAP_SRC_MAP_TYPE\t\t3\n+#define FM10K_SW_FFU_MUX_SEL_USER\t\t\t4\n+#define FM10K_SW_FFU_MUX_SEL_FTYPE_SWPRI\t\t5\n+#define FM10K_SW_FFU_MUX_SEL_IPMISC\t\t\t6\n+#define FM10K_SW_FFU_MUX_SEL_TOS\t\t\t7\n+#define FM10K_SW_FFU_MUX_SEL_PROT\t\t\t8\n+#define FM10K_SW_FFU_MUX_SEL_TTL\t\t\t9\n+#define FM10K_SW_FFU_MUX_SEL_SRC_PORT\t\t\t10\n+#define FM10K_SW_FFU_MUX_SEL_VPRI_VID_11_8\t\t11\n+#define FM10K_SW_FFU_MUX_SEL_VID_7_0\t\t\t12\n+#define FM10K_SW_FFU_MUX_SEL_RXTAG\t\t\t13\n+#define FM10K_SW_FFU_MUX_SEL_L2_DMAC_15_0\t\t14\n+#define FM10K_SW_FFU_MUX_SEL_L2_DMAC_31_16\t\t15\n+#define FM10K_SW_FFU_MUX_SEL_L2_DMAC_47_32\t\t16\n+#define FM10K_SW_FFU_MUX_SEL_L2_SMAC_15_0\t\t17\n+#define FM10K_SW_FFU_MUX_SEL_L2_SMAC_31_16\t\t18\n+#define FM10K_SW_FFU_MUX_SEL_L2_SMAC_47_32\t\t19\n+#define FM10K_SW_FFU_MUX_SEL_DGLORT\t\t\t20\n+#define FM10K_SW_FFU_MUX_SEL_SGLORT\t\t\t21\n+#define FM10K_SW_FFU_MUX_SEL_VPRI_VID\t\t\t22\n+#define FM10K_SW_FFU_MUX_SEL_VPRI2_VID2\t\t\t23\n+#define FM10K_SW_FFU_MUX_SEL_L2_TYPE\t\t\t24\n+#define FM10K_SW_FFU_MUX_SEL_L4_DST\t\t\t25\n+#define FM10K_SW_FFU_MUX_SEL_L4_SRC\t\t\t26\n+#define FM10K_SW_FFU_MUX_SEL_MAP_L4_DST\t\t\t27\n+#define FM10K_SW_FFU_MUX_SEL_MAP_L4_SRC\t\t\t28\n+#define FM10K_SW_FFU_MUX_SEL_L4A\t\t\t29\n+#define FM10K_SW_FFU_MUX_SEL_L4B\t\t\t30\n+#define FM10K_SW_FFU_MUX_SEL_L4C\t\t\t31\n+#define FM10K_SW_FFU_MUX_SEL_L4D\t\t\t32\n+#define FM10K_SW_FFU_MUX_SEL_MAP_VPRI1_VID1\t\t33\n+#define FM10K_SW_FFU_MUX_SEL_L3_DIP_31_0\t\t34\n+#define FM10K_SW_FFU_MUX_SEL_L3_DIP_63_32\t\t35\n+#define FM10K_SW_FFU_MUX_SEL_L3_DIP_95_64\t\t36\n+#define FM10K_SW_FFU_MUX_SEL_L3_DIP_127_96\t\t37\n+#define FM10K_SW_FFU_MUX_SEL_L3_SIP_31_0\t\t38\n+#define FM10K_SW_FFU_MUX_SEL_L3_SIP_63_32\t\t39\n+#define FM10K_SW_FFU_MUX_SEL_L3_SIP_95_64\t\t40\n+#define FM10K_SW_FFU_MUX_SEL_L3_SIP_127_96\t\t41\n+\n+#define\tFM10K_SW_FFU_SLICE_SRAM_ROUTE_ARP_INDEX_lsb\t0\n+#define\tFM10K_SW_FFU_SLICE_SRAM_ROUTE_ARP_INDEX_msb\t15\n+#define\tFM10K_SW_FFU_SLICE_SRAM_ROUTE_ARP_COUNT_lsb\t16\n+#define\tFM10K_SW_FFU_SLICE_SRAM_ROUTE_ARP_COUNT_msb\t19\n+#define FM10K_SW_FFU_SLICE_SRAM_ROUTE_ARP_TYPE_EXP\t(1 << 20)\n+\n+#define\tFM10K_SW_FFU_SLICE_SRAM_ROUTE_GLORT_DGLORT_lsb\t0\n+#define\tFM10K_SW_FFU_SLICE_SRAM_ROUTE_GLORT_DGLORT_msb\t15\n+#define FM10K_SW_FFU_SLICE_SRAM_ROUTE_GLORT_FLOOD_SET\t(1 << 20)\n+\n+#define\tFM10K_SW_FFU_SLICE_SRAM_SET_BITS_BYTE_MASK_lsb\t0\n+#define\tFM10K_SW_FFU_SLICE_SRAM_SET_BITS_BYTE_MASK_msb\t7\n+#define\tFM10K_SW_FFU_SLICE_SRAM_SET_BITS_BYTE_DATA_lsb\t8\n+#define\tFM10K_SW_FFU_SLICE_SRAM_SET_BITS_BYTE_DATA_msb\t15\n+#define\tFM10K_SW_FFU_SLICE_SRAM_SET_BITS_SUB_CMD_lsb\t16\n+#define\tFM10K_SW_FFU_SLICE_SRAM_SET_BITS_SUB_CMD_msb\t20\n+\n+#define\tFM10K_SW_FFU_SLICE_SRAM_SET_VLAN_VLAN_lsb\t0\n+#define\tFM10K_SW_FFU_SLICE_SRAM_SET_VLAN_VLAN_msb\t11\n+#define\tFM10K_SW_FFU_SLICE_SRAM_SET_VLAN_PRI_lsb\t12\n+#define\tFM10K_SW_FFU_SLICE_SRAM_SET_VLAN_PRI_msb\t15\n+#define\tFM10K_SW_FFU_SLICE_SRAM_SET_VLAN_TX_TAG_lsb\t16\n+#define\tFM10K_SW_FFU_SLICE_SRAM_SET_VLAN_TX_TAG_msb\t17\n+#define FM10K_SW_FFU_SLICE_SRAM_SET_VLAN_SET_VPRI\t(1 << 18)\n+#define FM10K_SW_FFU_SLICE_SRAM_SET_VLAN_SET_PRI\t(1 << 19)\n+\n+#define\tFM10K_SW_FFU_SLICE_SRAM_SET_PRI_DSCP_lsb\t0\n+#define\tFM10K_SW_FFU_SLICE_SRAM_SET_PRI_DSCP_msb\t5\n+#define\tFM10K_SW_FFU_SLICE_SRAM_SET_PRI_PRI_lsb\t\t12\n+#define\tFM10K_SW_FFU_SLICE_SRAM_SET_PRI_PRI_msb\t\t15\n+#define FM10K_SW_FFU_SLICE_SRAM_SET_PRI_SET_DSCP\t(1 << 17)\n+#define FM10K_SW_FFU_SLICE_SRAM_SET_PRI_SET_VPRI\t(1 << 18)\n+#define FM10K_SW_FFU_SLICE_SRAM_SET_PRI_SET_PRI\t\t(1 << 19)\n+\n+/* FFU Registers */\n+#define FM10K_SW_FFU_SLICE_TCAM(sl_, n_)\t\t\\\n+\t\tFM10K_SW_FFU_REG(0x2000 * (sl_) + 0x4 * (n_))\n+#define FM10K_SW_FFU_SLICE_TCAM_ENTRIES\t\t\t1024\n+#define FM10K_SW_FFU_SLICE_TCAM_KEY_lsb64\t\t0\n+#define FM10K_SW_FFU_SLICE_TCAM_KEY_msb64\t\t31\n+#define FM10K_SW_FFU_SLICE_TCAM_KEY_TOP_lsb64\t\t32\n+#define FM10K_SW_FFU_SLICE_TCAM_KEY_TOP_msb64\t\t39\n+#define FM10K_SW_FFU_SLICE_SRAM(sl_, n_)\t\t\\\n+\t\tFM10K_SW_FFU_REG(0x1000 + 0x2000 * (sl_) + 0x2 * (n_))\n+#define FM10K_SW_FFU_SLICE_SRAM_COMMAND_lsb64\t\t21\n+#define FM10K_SW_FFU_SLICE_SRAM_COMMAND_msb64\t\t22\n+#define\tFM10K_SW_FFU_SLICE_SRAM_COMMAND_ROUTE_ARP\t0\n+#define\tFM10K_SW_FFU_SLICE_SRAM_COMMAND_ROUTE_GLORT\t1\n+#define\tFM10K_SW_FFU_SLICE_SRAM_COMMAND_BIT_SET\t\t2\n+#define\tFM10K_SW_FFU_SLICE_SRAM_COMMAND_FIELD_SET\t3\n+#define FM10K_SW_FFU_SLICE_SRAM_COUNTER_INDEX_lsb64\t23\n+#define FM10K_SW_FFU_SLICE_SRAM_COUNTER_INDEX_msb64\t34\n+#define FM10K_SW_FFU_SLICE_SRAM_COUNTER_BANK_lsb64\t35\n+#define FM10K_SW_FFU_SLICE_SRAM_COUNTER_BANK_msb64\t36\n+#define FM10K_SW_FFU_SLICE_SRAM_PRECEDENCE_lsb64\t37\n+#define FM10K_SW_FFU_SLICE_SRAM_PRECEDENCE_msb64\t39\n+#define FM10K_SW_FFU_SLICE_VALID(sl_)\t\t\t\\\n+\t\tFM10K_SW_FFU_REG(0x1800 + 0x2000 * (sl_))\n+#define FM10K_SW_FFU_SLICE_VALID_SCENARIO(s_)\t\t(1ULL << (s_))\n+#define FM10K_SW_FFU_SLICE_VALID_ALL_SCENARIOS\t\tFM10K_SW_MASK32(31, 0)\n+#define FM10K_SW_FFU_SLICE_CASCADE_ACTION(sl_)\t\t\\\n+\t\tFM10K_SW_FFU_REG(0x1804 + 0x2000 * (sl_))\n+#define FM10K_SW_FFU_SLICE_CFG(sl_, scen_)\t\t\\\n+\t\tFM10K_SW_FFU_REG(0x1840 + 0x2 * (scen_) + 0x2000 * (sl_))\n+#define FM10K_SW_FFU_SLICE_CFG_SELECT_0_lsb64\t\t0\n+#define FM10K_SW_FFU_SLICE_CFG_SELECT_0_msb64\t\t5\n+#define FM10K_SW_FFU_SLICE_CFG_SELECT_1_lsb64\t\t6\n+#define FM10K_SW_FFU_SLICE_CFG_SELECT_1_msb64\t\t11\n+#define FM10K_SW_FFU_SLICE_CFG_SELECT_2_lsb64\t\t12\n+#define FM10K_SW_FFU_SLICE_CFG_SELECT_2_msb64\t\t17\n+#define FM10K_SW_FFU_SLICE_CFG_SELECT_3_lsb64\t\t18\n+#define FM10K_SW_FFU_SLICE_CFG_SELECT_3_msb64\t\t23\n+#define FM10K_SW_FFU_SLICE_CFG_SELECT_TOP_lsb64\t\t24\n+#define FM10K_SW_FFU_SLICE_CFG_SELECT_TOP_msb64\t\t29\n+#define FM10K_SW_FFU_SLICE_CFG_START_COMPARE\t\t(1ULL << 30)\n+#define FM10K_SW_FFU_SLICE_CFG_START_ACTION\t\t(1ULL << 31)\n+#define FM10K_SW_FFU_SLICE_CFG_VALID_LOW\t\t(1ULL << 32)\n+#define FM10K_SW_FFU_SLICE_CFG_VALID_HIGH\t\t(1ULL << 33)\n+#define FM10K_SW_FFU_SLICE_CFG_CASE_lsb64\t\t34\n+#define FM10K_SW_FFU_SLICE_CFG_CASE_msb64\t\t37\n+#define FM10K_SW_FFU_SLICE_CFG_CASE_LOCATION_lsb64\t38\n+#define FM10K_SW_FFU_SLICE_CFG_CASE_LOCATION_msb64\t39\n+\n+#define\tFM10K_SW_FFU_SLICE_CFG_CASE_LOCATION_NOT_MAPPED\t\t0\n+#define\tFM10K_SW_FFU_SLICE_CFG_CASE_LOCATION_TOP_LOW_NIBBLE\t1\n+#define\tFM10K_SW_FFU_SLICE_CFG_CASE_LOCATION_TOP_HIGH_NIBBLE\t2\n+\n+#define FM10K_SW_FFU_MASTER_VALID\t\t\t\\\n+\t\tFM10K_SW_FFU_REG(0x40000)\n+#define FM10K_SW_FFU_MASTER_VALID_SLICE_VALID(s_)\t(1ULL << (s_))\n+#define FM10K_SW_FFU_MASTER_VALID_ALL_SLICES_VALID\tFM10K_SW_MASK64(31, 0)\n+#define FM10K_SW_FFU_MASTER_VALID_CHUNK_VALID(c_)\t(1ULL << ((c_) + 32))\n+#define FM10K_SW_FFU_MASTER_VALID_ALL_CHUNKS_VALID\tFM10K_SW_MASK64(63, 32)\n+\n+#define FM10K_SW_L2LOOKUP_BASE\t\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0xC80000)\n+#define FM10K_SW_L2LOOKUP_REG(wo_)\t\t\t\\\n+\t\t(FM10K_SW_L2LOOKUP_BASE + FM10K_SW_REG_OFF(wo_))\n+\n+#define FM10K_SW_MA_TABLE(t_, n_)\t\t\t\\\n+\t\tFM10K_SW_L2LOOKUP_REG(0x10000 * (t_) + 0x4 * (n_))\n+#define FM10K_SW_INGRESS_VID_TABLE(v_)\t\t\t\\\n+\t\tFM10K_SW_L2LOOKUP_REG(0x20000 + 0x4 * (v_))\n+#define FM10K_SW_INGRESS_VID_TABLE_ENTRIES\t\t4096\n+#define FM10K_SW_INGRESS_VID_TABLE_MEMBERSHIP(l_)\t(1ULL << (l_))\n+\n+/* note these bit positions are relative\n+ * to the start of the upper 64-bit word\n+ */\n+#define FM10K_SW_INGRESS_VID_TABLE_FID_lsb64\t\t(64 - 64)\n+#define FM10K_SW_INGRESS_VID_TABLE_FID_msb64\t\t(75 - 64)\n+#define FM10K_SW_INGRESS_VID_TABLE_MST_INDEX_lsb64\t(76 - 64)\n+#define FM10K_SW_INGRESS_VID_TABLE_MST_INDEX_msb64\t(83 - 64)\n+#define FM10K_SW_INGRESS_VID_TABLE_COUNTER_INDEX_lsb64\t(84 - 64)\n+#define FM10K_SW_INGRESS_VID_TABLE_COUNTER_INDEX_msb64\t(89 - 64)\n+#define FM10K_SW_INGRESS_VID_TABLE_REFLECT\t\t(1ULL << (90 - 64))\n+#define FM10K_SW_INGRESS_VID_TABLE_TRAP_IGMP\t\t(1ULL << (91 - 64))\n+#define FM10K_SW_EGRESS_VID_TABLE(v_)\t\t\t\\\n+\t\tFM10K_SW_L2LOOKUP_REG(0x24000 + 0x4 * (v_))\n+#define FM10K_SW_EGRESS_VID_TABLE_ENTRIES\t\t4096\n+#define FM10K_SW_EGRESS_VID_TABLE_MEMBERSHIP(l_)\t(1ULL << (l_))\n+\n+/* note these bit positions are relative to\n+ * the start of the upper 64-bit word\n+ */\n+#define FM10K_SW_EGRESS_VID_TABLE_FID_lsb64\t\t(64 - 64)\n+#define FM10K_SW_EGRESS_VID_TABLE_FID_msb64\t\t(75 - 64)\n+#define FM10K_SW_EGRESS_VID_TABLE_MST_INDEX_lsb64\t(76 - 64)\n+#define FM10K_SW_EGRESS_VID_TABLE_MST_INDEX_msb64\t(83 - 64)\n+#define FM10K_SW_EGRESS_VID_TABLE_MTU_INDEX_lsb64\t(84 - 64)\n+#define FM10K_SW_EGRESS_VID_TABLE_MTU_INDEX_msb64\t(86 - 64)\n+#define FM10K_SW_EGRESS_VID_TABLE_TRIG_ID_lsb64\t\t(87 - 64)\n+#define FM10K_SW_EGRESS_VID_TABLE_TRIG_ID_msb64\t\t(92 - 64)\n+\n+#define FM10K_SW_MA_USED_TABLE(t_, n_)\t\t\t\\\n+\t\tFM10K_SW_L2LOOKUP_REG(0x28000 + 0x200 * (t_) + (n_))\n+#define FM10K_SW_INGRESS_MST_TABLE(t_, n_)\t\t\\\n+\t\tFM10K_SW_L2LOOKUP_REG(0x28400 + 0x200 * (t_) + 0x2 * (n_))\n+\n+#define FM10K_SW_INGRESS_MST_TABLE_PORTS_PER_TABLE\t24\n+#define FM10K_SW_INGRESS_MST_TABLE_STP_STATE_lsb64(l_) \\\n+\t\t(((l_) % FM10K_SW_INGRESS_MST_TABLE_PORTS_PER_TABLE) * 2)\n+#define FM10K_SW_INGRESS_MST_TABLE_STP_STATE_msb64(l_) \\\n+\t\t(FM10K_SW_INGRESS_MST_TABLE_STP_STATE_lsb64(l_) + 1)\n+\n+#define\tFM10K_SW_INGRESS_MST_TABLE_STP_STATE_DISABLE\t0\n+#define\tFM10K_SW_INGRESS_MST_TABLE_STP_STATE_LISTENING\t1\n+#define\tFM10K_SW_INGRESS_MST_TABLE_STP_STATE_LEARNING\t2\n+#define\tFM10K_SW_INGRESS_MST_TABLE_STP_STATE_FORWARD\t3\n+\n+#define FM10K_SW_EGRESS_MST_TABLE(t_)\t\t\t\\\n+\t\tFM10K_SW_L2LOOKUP_REG(0x28800 + 0x2 * (t_))\n+#define FM10K_SW_EGRESS_MST_TABLE_FORWARDING(l_)\t(1ULL << (l_))\n+\n+#define FM10K_SW_MA_TABLE_CFG_1\t\t\t\t\\\n+\t\tFM10K_SW_L2LOOKUP_REG(0x28A00)\n+#define FM10K_SW_MA_TABLE_CFG_2\t\t\t\t\\\n+\t\tFM10K_SW_L2LOOKUP_REG(0x28A02)\n+#define FM10K_SW_MTU_TABLE(n_)\t\t\t\t\\\n+\t\tFM10K_SW_L2LOOKUP_REG(0x28A08 + (n_))\n+#define FM10K_SW_IEEE_RESERVED_MAC_ACTION\t\t\\\n+\t\tFM10K_SW_L2LOOKUP_REG(0x28A10)\n+#define FM10K_SW_IEEE_RESERVED_MAC_TRAP_PRIORITY\t\\\n+\t\tFM10K_SW_L2LOOKUP_REG(0x28A14)\n+#define FM10K_SW_IEEE_RESERVED_MAC_CFG\t\t\t\\\n+\t\tFM10K_SW_L2LOOKUP_REG(0x28A16)\n+\n+\n+#define FM10K_SW_GLORT_BASE\t\t\tFM10K_SW_REG_OFF(0xCE0000)\n+#define FM10K_SW_GLORT_REG(wo_)\t\t\t\\\n+\t\t(FM10K_SW_GLORT_BASE + FM10K_SW_REG_OFF(wo_))\n+#define FM10K_SW_GLORT_CAM_ENTRIES\t\t256\n+#define FM10K_SW_GLORT_DEST_TABLE(n_)\t\t\\\n+\t\tFM10K_SW_GLORT_REG(0x0 + 0x2 * (n_))\n+#define FM10K_SW_GLORT_DEST_TABLE_MASK_lsb64\t0\n+#define FM10K_SW_GLORT_DEST_TABLE_MASK_msb64\t47\n+\n+#define FM10K_SW_GLORT_DEST_TABLE_IP_MCAST_IDX_lsb64\t48\n+#define FM10K_SW_GLORT_DEST_TABLE_IP_MCAST_IDX_msb64\t59\n+\n+#define FM10K_SW_GLORT_CAM(n_)\t\t\t\\\n+\t\tFM10K_SW_GLORT_REG(0x2000 + (n_))\n+#define FM10K_SW_GLORT_CAM_MATCH_ANY\t\t0x00000000\n+#define FM10K_SW_GLORT_CAM_MATCH_NONE\t\tFM10K_SW_MASK32(31, 0)\n+#define FM10K_SW_GLORT_CAM_KEY_lsb\t\t0\n+#define FM10K_SW_GLORT_CAM_KEY_msb\t\t15\n+#define FM10K_SW_GLORT_CAM_KEY_INVERT_lsb\t16\n+#define FM10K_SW_GLORT_CAM_KEY_INVERT_msb\t31\n+#define FM10K_SW_GLORT_RAM(n_)\t\t\t\\\n+\t\tFM10K_SW_GLORT_REG(0x2200 + 0x2 * (n_))\n+#define FM10K_SW_GLORT_RAM_STRICT_lsb64\t\t0\n+#define FM10K_SW_GLORT_RAM_STRICT_msb64\t\t1\n+#define\tFM10K_SW_GLORT_RAM_STRICT_FTYPE\t\t0\n+#define\tFM10K_SW_GLORT_RAM_STRICT_RSVD\t\t1\n+#define\tFM10K_SW_GLORT_RAM_STRICT_HASHED\t2\n+#define\tFM10K_SW_GLORT_RAM_STRICT_STRICT\t3\n+#define FM10K_SW_GLORT_RAM_DEST_INDEX_lsb64\t2\n+#define FM10K_SW_GLORT_RAM_DEST_INDEX_msb64\t13\n+#define FM10K_SW_GLORT_RAM_RANGE_SUBIDX_A_lsb64\t14\n+#define FM10K_SW_GLORT_RAM_RANGE_SUBIDX_A_msb64\t21\n+#define FM10K_SW_GLORT_RAM_RANGE_SUBIDX_B_lsb64\t22\n+#define FM10K_SW_GLORT_RAM_RANGE_SUBIDX_B_msb64\t29\n+#define FM10K_SW_GLORT_RAM_DEST_COUNT_lsb64\t30\n+#define FM10K_SW_GLORT_RAM_DEST_COUNT_msb64\t33\n+#define FM10K_SW_GLORT_RAM_HASH_ROTATION\t(1ULL << 34)\n+\n+\n+#define FM10K_SW_PARSER_BASE\t\t\tFM10K_SW_REG_OFF(0xCF0000)\n+#define FM10K_SW_PARSER_REG(wo_)\t\t\\\n+\t\t(FM10K_SW_PARSER_BASE + FM10K_SW_REG_OFF(wo_))\n+#define FM10K_SW_PARSER_PORT_CFG_1(p_)\t\t\\\n+\t\tFM10K_SW_PARSER_REG(0x0 + 0x2 * (p_))\n+#define FM10K_SW_PARSER_PORT_CFG_1_FTAG\t\t(1ULL << 0)\n+\n+#define FM10K_SW_PARSER_PORT_CFG_1_VLAN1_TAG(v_)\t(1ULL << (1 + (v_)))\n+#define FM10K_SW_PARSER_PORT_CFG_1_VLAN2_TAG(v_)\t(1ULL << (5 + (v_)))\n+#define FM10K_SW_PARSER_PORT_CFG_1_VLAN2_FIRST\t\t(1ULL << 9)\n+#define FM10K_SW_PARSER_PORT_CFG_1_DEFAULT_VID_lsb\t10\n+#define FM10K_SW_PARSER_PORT_CFG_1_DEFAULT_VID_msb\t21\n+#define FM10K_SW_PARSER_PORT_CFG_1_DEFAULT_VPRI_lsb\t22\n+#define FM10K_SW_PARSER_PORT_CFG_1_DEFAULT_VPRI_msb\t25\n+#define FM10K_SW_PARSER_PORT_CFG_1_DEFAULT_VID2_lsb\t26\n+#define FM10K_SW_PARSER_PORT_CFG_1_DEFAULT_VID2_msb\t37\n+#define FM10K_SW_PARSER_PORT_CFG_1_DEFAULT_VPRI2_lsb\t38\n+#define FM10K_SW_PARSER_PORT_CFG_1_DEFAULT_VPRI2_msb\t41\n+#define FM10K_SW_PARSER_PORT_CFG_1_USE_DEFAULT_VLAN\t(1ULL << 42)\n+#define FM10K_SW_PARSER_PORT_CFG_2(p_)\t\t\t\\\n+\t\tFM10K_SW_PARSER_REG(0x80 + 0x2 * (p_))\n+#define FM10K_SW_PARSER_PORT_CFG_2_CUSTOM_TAG_1_lsb\t0\n+#define FM10K_SW_PARSER_PORT_CFG_2_CUSTOM_TAG_1_msb\t3\n+#define FM10K_SW_PARSER_PORT_CFG_2_CUSTOM_TAG_2_lsb\t4\n+#define FM10K_SW_PARSER_PORT_CFG_2_CUSTOM_TAG_2_msb\t7\n+#define FM10K_SW_PARSER_PORT_CFG_2_PARSE_MPLS\t\t(1ULL << 8)\n+#define FM10K_SW_PARSER_PORT_CFG_2_STORE_MPLS_lsb\t9\n+#define FM10K_SW_PARSER_PORT_CFG_2_STORE_MPLS_msb\t11\n+#define FM10K_SW_PARSER_PORT_CFG_2_PARSE_L3\t\t(1ULL << 12)\n+#define FM10K_SW_PARSER_PORT_CFG_2_PARSE_L4\t\t(1ULL << 13)\n+#define FM10K_SW_PARSER_PORT_CFG_2_FLAG_IPV4_OPTIONS\t(1ULL << 14)\n+#define FM10K_SW_PARSER_PORT_CFG_2_FLAG_IPV6_HOP_BY_HOP\t(1ULL << 15)\n+#define FM10K_SW_PARSER_PORT_CFG_2_FLAG_IPV6_ROUTING\t(1ULL << 16)\n+#define FM10K_SW_PARSER_PORT_CFG_2_FLAG_IPV6_FRAG\t(1ULL << 17)\n+#define FM10K_SW_PARSER_PORT_CFG_2_FLAG_IPV6_DEST\t(1ULL << 18)\n+#define FM10K_SW_PARSER_PORT_CFG_2_FLAG_IPV6_AUTH\t(1ULL << 19)\n+#define FM10K_SW_PARSER_PORT_CFG_2_DEFAULT_DSCP_lsb\t20\n+#define FM10K_SW_PARSER_PORT_CFG_2_DEFAULT_DSCP_msb\t25\n+#define FM10K_SW_PARSER_PORT_CFG_2_DROP_TAGGED\t\t(1ULL << 26)\n+#define FM10K_SW_PARSER_PORT_CFG_2_DROP_UNTAGGED\t(1ULL << 27)\n+#define FM10K_SW_PARSER_PORT_CFG_2_USE_DEFAULT_DSCP\t(1ULL << 28)\n+#define FM10K_SW_PARSER_PORT_CFG_2_SWITCH_PRI_FROM_VLAN\t(1ULL << 29)\n+#define FM10K_SW_PARSER_PORT_CFG_2_SWITCH_PRI_FROM_DSCP\t(1ULL << 30)\n+#define FM10K_SW_PARSER_PORT_CFG_2_SWITCH_PRI_FROM_ISL\t(1ULL << 31)\n+\n+#define FM10K_SW_PARSER_PORT_CFG_2_SWITCH_PRI_PREFER_DSCP\t(1ULL << 32)\n+\n+#define FM10K_SW_PARSER_PORT_CFG_3(p_)\t\t\\\n+\t\tFM10K_SW_PARSER_REG(0x100 + 0x2 * (p_))\n+#define FM10K_SW_PORT_CFG_ISL(p_)\t\t\\\n+\t\tFM10K_SW_PARSER_REG(0x180 + (p_))\n+\n+#define FM10K_SW_PORT_CFG_ISL_SGLORT_lsb\t0\n+#define FM10K_SW_PORT_CFG_ISL_SGLORT_msb\t15\n+#define FM10K_SW_PORT_CFG_ISL_USR_lsb\t\t16\n+#define FM10K_SW_PORT_CFG_ISL_USR_msb\t\t23\n+#define FM10K_SW_PORT_CFG_ISL_DEFAULT_PRI_lsb\t24\n+#define FM10K_SW_PORT_CFG_ISL_DEFAULT_PRI_msb\t27\n+\n+#define FM10K_SW_PARSER_VLAN_TAG(n_)\t\t\\\n+\t\tFM10K_SW_PARSER_REG(0x1C0 + (n_))\n+#define FM10K_SW_PARSER_CUSTOM_TAG(n_)\t\t\\\n+\t\tFM10K_SW_PARSER_REG(0x1C4 + (n_))\n+#define FM10K_SW_PARSER_MPLS_TAG\t\t\\\n+\t\tFM10K_SW_PARSER_REG(0x1C8)\n+#define FM10K_SW_PARSER_DI_CFG(n_)\t\t\\\n+\t\tFM10K_SW_PARSER_REG(0x1D0 + 0x2 * (n_))\n+#define FM10K_SW_RX_VPRI_MAP(p_)\t\t\\\n+\t\tFM10K_SW_PARSER_REG(0x200 + 0x2 * (p_))\n+#define FM10K_SW_DSCP_PRI_MAP(pri_)\t\t\\\n+\t\tFM10K_SW_PARSER_REG(0x280 + (pri_))\n+#define FM10K_SW_VPRI_PRI_MAP(pri_)\t\t\\\n+\t\tFM10K_SW_PARSER_REG(0x2C0 + (pri_))\n+\n+#define FM10K_SW_HANDLER_BASE\t\t\tFM10K_SW_REG_OFF(0xD50000)\n+#define FM10K_SW_HANDLER_REG(wo_)\t\t\\\n+\t\t(FM10K_SW_HANDLER_BASE + FM10K_SW_REG_OFF(wo_))\n+\n+#define FM10K_SW_SYS_CFG_1\t\t\t\t\\\n+\t\tFM10K_SW_HANDLER_REG(0x0)\n+#define FM10K_SW_SYS_CFG_1_DROP_PAUSE\t\t\t(1 << 0)\n+#define FM10K_SW_SYS_CFG_1_TRAP_MTU_VIOLATIONS\t\t(1 << 1)\n+#define FM10K_SW_SYS_CFG_1_ENABLE_TRAP_PLUS_LOG\t\t(1 << 2)\n+#define FM10K_SW_SYS_CFG_1_DROP_INVALID_SMAC\t\t(1 << 3)\n+#define FM10K_SW_SYS_CFG_1_DROP_MAC_CTRL_ETHERTYPE\t(1 << 4)\n+\n+#define FM10K_SW_CPU_MAC\t\t\tFM10K_SW_HANDLER_REG(0x2)\n+#define FM10K_SW_SYS_CFG_ROUTER\t\t\tFM10K_SW_HANDLER_REG(0x4)\n+#define FM10K_SW_L34_HASH_CFG\t\t\tFM10K_SW_HANDLER_REG(0x5)\n+#define FM10K_SW_L34_HASH_CFG_SYMMETRIC\t\t(1 << 0)\n+#define FM10K_SW_L34_HASH_CFG_USE_SIP\t\t(1 << 1)\n+#define FM10K_SW_L34_HASH_CFG_USE_DIP\t\t(1 << 2)\n+#define FM10K_SW_L34_HASH_CFG_USE_PROT\t\t(1 << 3)\n+#define FM10K_SW_L34_HASH_CFG_USE_TCP\t\t(1 << 4)\n+#define FM10K_SW_L34_HASH_CFG_USE_UDP\t\t(1 << 5)\n+#define FM10K_SW_L34_HASH_CFG_USE_PROT1\t\t(1 << 6)\n+#define FM10K_SW_L34_HASH_CFG_USE_PROT2\t\t(1 << 7)\n+#define FM10K_SW_L34_HASH_CFG_USE_L4SRC\t\t(1 << 8)\n+#define FM10K_SW_L34_HASH_CFG_USE_L4DST\t\t(1 << 9)\n+\n+#define FM10K_SW_L34_HASH_CFG_ECMP_ROTATION_lsb\t\t10\n+#define FM10K_SW_L34_HASH_CFG_ECMP_ROTATION_msb\t\t11\n+#define FM10K_SW_L34_HASH_CFG_PROT1_lsb\t\t\t16\n+#define FM10K_SW_L34_HASH_CFG_PROT1_msb\t\t\t23\n+#define FM10K_SW_L34_HASH_CFG_PROT2_lsb\t\t\t24\n+#define FM10K_SW_L34_HASH_CFG_PROT2_msb\t\t\t31\n+\n+#define FM10K_SW_L34_FLOW_HASH_CFG_1\t\tFM10K_SW_HANDLER_REG(0x6)\n+#define FM10K_SW_L34_FLOW_HASH_CFG_2\t\tFM10K_SW_HANDLER_REG(0x7)\n+#define FM10K_SW_L234_HASH_CFG\t\t\tFM10K_SW_HANDLER_REG(0x8)\n+#define FM10K_SW_L234_HASH_CFG_USE_L2_IF_IP\t(1 << 0)\n+#define FM10K_SW_L234_HASH_CFG_USE_L34\t\t(1 << 1)\n+#define FM10K_SW_L234_HASH_CFG_SYMMETRIC\t(1 << 2)\n+#define FM10K_SW_L234_HASH_CFG_USE_DMAC\t\t(1 << 3)\n+#define FM10K_SW_L234_HASH_CFG_USE_SMAC\t\t(1 << 4)\n+#define FM10K_SW_L234_HASH_CFG_USE_TYPE\t\t(1 << 5)\n+#define FM10K_SW_L234_HASH_CFG_USE_VPRI\t\t(1 << 6)\n+#define FM10K_SW_L234_HASH_CFG_USE_VID\t\t(1 << 8)\n+#define FM10K_SW_L234_HASH_CFG_ROTATION_A_lsb\t8\n+#define FM10K_SW_L234_HASH_CFG_ROTATION_A_msb\t9\n+#define FM10K_SW_L234_HASH_CFG_ROTATION_B_lsb\t10\n+#define FM10K_SW_L234_HASH_CFG_ROTATION_B_msb\t11\n+#define FM10K_SW_CPU_TRAP_MASK_FH\t\tFM10K_SW_HANDLER_REG(0xA)\n+#define FM10K_SW_TRAP_GLORT\t\t\tFM10K_SW_HANDLER_REG(0xC)\n+#define FM10K_SW_RX_MIRROR_CFG\t\t\tFM10K_SW_HANDLER_REG(0xD)\n+#define FM10K_SW_LOG_MIRROR_PROFILE\t\tFM10K_SW_HANDLER_REG(0xE)\n+\n+#define FM10K_SW_FH_MIRROR_PROFILE_TABLE(n_)\t\\\n+\t\tFM10K_SW_HANDLER_REG(0x40 + (n_))\n+#define FM10K_SW_PORT_CFG_2(p_)\t\t\t\\\n+\t\tFM10K_SW_HANDLER_REG(0x80 + 0x2 * (p_))\n+#define FM10K_SW_PORT_CFG_3(p_)\t\t\t\\\n+\t\tFM10K_SW_HANDLER_REG(0x100 + (p_))\n+#define FM10K_SW_FH_LOOPBACK_SUPPRESS(p_)\t\\\n+\t\tFM10K_SW_HANDLER_REG(0x140 + (p_))\n+#define FM10K_SW_FH_HEAD_IP\t\t\tFM10K_SW_HANDLER_REG(0x180)\n+#define FM10K_SW_FH_HEAD_IM\t\t\tFM10K_SW_HANDLER_REG(0x182)\n+#define FM10K_SW_PARSER_EARLY_SRAM_CTRL\t\tFM10K_SW_HANDLER_REG(0x184)\n+#define FM10K_SW_PARSER_LATE_SRAM_CTRL\t\tFM10K_SW_HANDLER_REG(0x185)\n+#define FM10K_SW_MAPPER_SRAM_CTRL\t\tFM10K_SW_HANDLER_REG(0x186)\n+#define FM10K_SW_FFU_SRAM_CTRL(n_)\t\t\\\n+\t\tFM10K_SW_HANDLER_REG(0x1A0 + 0x4 * (n_))\n+#define FM10K_SW_ARP_SRAM_CTRL\t\t\tFM10K_SW_HANDLER_REG(0x1C0)\n+#define FM10K_SW_VLAN_LOOKUP_SRAM_CTRL\t\tFM10K_SW_HANDLER_REG(0x1C1)\n+#define FM10K_SW_MA_TABLE_SRAM_CTRL(n_)\t\t\\\n+\t\tFM10K_SW_HANDLER_REG(0x1C4 + 0x2 * (n_))\n+#define FM10K_SW_FID_GLORT_LOOKUP_SRAM_CTRL\tFM10K_SW_HANDLER_REG(0x1C8)\n+#define FM10K_SW_GLORT_RAM_SRAM_CTRL\t\tFM10K_SW_HANDLER_REG(0x1CA)\n+#define FM10K_SW_GLORT_TABLE_SRAM_CTRL\t\tFM10K_SW_HANDLER_REG(0x1CB)\n+#define FM10K_SW_FH_HEAD_OUTPUT_FIFO_SRAM_CTRL\tFM10K_SW_HANDLER_REG(0x1CC)\n+\n+#define FM10K_SW_LAG_BASE\t\t\tFM10K_SW_REG_OFF(0xD90000)\n+#define FM10K_SW_LAG_REG(wo_)\t\t\t\\\n+\t\t(FM10K_SW_LAG_BASE + FM10K_SW_REG_OFF(wo_))\n+#define\tFM10K_SW_LAG_CFG(l_)\t\t\tFM10K_SW_LAG_REG(l_)\n+#define FM10K_SW_LAG_CFG_LAG_SIZE_lsb\t\t0\n+#define FM10K_SW_LAG_CFG_LAG_SIZE_msb\t\t3\n+#define FM10K_SW_LAG_CFG_INDEX_lsb\t\t4\n+#define FM10K_SW_LAG_CFG_INDEX_msb\t\t7\n+#define FM10K_SW_LAG_CFG_HASH_ROTATION\t\t(1 << 8)\n+#define FM10K_SW_LAG_CFG_IN_LAG\t\t\t(1 << 9)\n+\n+#define\tFM10K_SW_CANONICAL_GLORT_CAM(n_)\t\t\t\\\n+\t\tFM10K_SW_LAG_REG((n_) + 0x40)\n+#define FM10K_SW_CANONICAL_GLORT_CAM_LAG_GLORT_lsb\t\t0\n+#define FM10K_SW_CANONICAL_GLORT_CAM_LAG_GLORT_msb\t\t15\n+#define FM10K_SW_CANONICAL_GLORT_CAM_MASK_SIZE_lsb\t\t16\n+#define FM10K_SW_CANONICAL_GLORT_CAM_MASK_SIZE_msb\t\t19\n+#define FM10K_SW_CANONICAL_GLORT_CAM_PORT_FIELD_SIZE_lsb\t20\n+#define FM10K_SW_CANONICAL_GLORT_CAM_PORT_FIELD_SIZE_msb\t22\n+\n+#define FM10K_SW_RX_STATS_BASE\t\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0xE00000)\n+#define FM10K_SW_RX_STATS_REG(wo_)\t\t\t\\\n+\t\t(FM10K_SW_RX_STATS_BASE + FM10K_SW_REG_OFF(wo_))\n+#define FM10K_SW_RX_STATS_BANK(b_, i_)\t\t\t\\\n+\t\tFM10K_SW_RX_STATS_REG(0x1000 * (b_) + 0x4 * (i_))\n+#define FM10K_SW_RX_STATS_BANK_1_INDEX\t\t\t0\n+#define FM10K_SW_RX_STATS_BANK_2_INDEX\t\t\t1\n+#define FM10K_SW_RX_STATS_BANK_3_INDEX\t\t\t2\n+#define FM10K_SW_RX_STATS_BANK_4_INDEX\t\t\t3\n+#define FM10K_SW_RX_STATS_BANK_5_INDEX\t\t\t4\n+#define FM10K_SW_RX_STATS_BANK_6_INDEX\t\t\t5\n+#define FM10K_SW_RX_STATS_BANK_1_NON_IP_L2_UCAST\t0\n+#define FM10K_SW_RX_STATS_BANK_1_NON_IP_L2_MCAST\t1\n+#define FM10K_SW_RX_STATS_BANK_1_NON_IP_L2_BCAST\t2\n+#define FM10K_SW_RX_STATS_BANK_1_IPV4_L2_UCAST\t\t3\n+#define FM10K_SW_RX_STATS_BANK_1_IPV4_L2_MCAST\t\t4\n+#define FM10K_SW_RX_STATS_BANK_1_IPV4_L2_BCAST\t\t5\n+#define FM10K_SW_RX_STATS_BANK_1_IPV6_L2_UCAST\t\t6\n+#define FM10K_SW_RX_STATS_BANK_1_IPV6_L2_MCAST\t\t7\n+#define FM10K_SW_RX_STATS_BANK_1_IPV6_L2_BCAST\t\t8\n+#define FM10K_SW_RX_STATS_BANK_1_IEEE802_3_PAUSE\t9\n+#define FM10K_SW_RX_STATS_BANK_1_CLASS_BASED_PAUSE\t10\n+#define FM10K_SW_RX_STATS_BANK_1_FRAMING_ERR\t\t11\n+#define FM10K_SW_RX_STATS_BANK_1_FCS_ERR\t\t12\n+#define FM10K_SW_RX_STATS_BANK_2_LEN_LT_64\t\t0\n+#define FM10K_SW_RX_STATS_BANK_2_LEN_EQ_64\t\t1\n+#define FM10K_SW_RX_STATS_BANK_2_LEN_65_127\t\t2\n+#define FM10K_SW_RX_STATS_BANK_2_LEN_128_255\t\t3\n+#define FM10K_SW_RX_STATS_BANK_2_LEN_256_511\t\t4\n+#define FM10K_SW_RX_STATS_BANK_2_LEN_512_1023\t\t5\n+#define FM10K_SW_RX_STATS_BANK_2_LEN_1024_1522\t\t6\n+#define FM10K_SW_RX_STATS_BANK_2_LEN_1523_2047\t\t7\n+#define FM10K_SW_RX_STATS_BANK_2_LEN_2048_4095\t\t8\n+#define FM10K_SW_RX_STATS_BANK_2_LEN_4096_8191\t\t9\n+#define FM10K_SW_RX_STATS_BANK_2_LEN_8192_10239\t\t10\n+#define FM10K_SW_RX_STATS_BANK_2_LEN_GE_10240\t\t11\n+#define FM10K_SW_RX_STATS_BANK_3_PRI(p_)\t\t(p_)\n+#define FM10K_SW_RX_STATS_BANK_4_FID_FORWARDED\t\t0\n+#define FM10K_SW_RX_STATS_BANK_4_FLOOD_FORWARDED\t1\n+#define FM10K_SW_RX_STATS_BANK_4_SPECIALLY_HANDLED\t2\n+#define FM10K_SW_RX_STATS_BANK_4_PARSER_ERROR_DROP\t3\n+#define FM10K_SW_RX_STATS_BANK_4_ECC_ERROR_DROP\t\t4\n+#define FM10K_SW_RX_STATS_BANK_4_TRAPPED\t\t5\n+#define FM10K_SW_RX_STATS_BANK_4_PAUSE_DROPS\t\t6\n+#define FM10K_SW_RX_STATS_BANK_4_STP_DROPS\t\t7\n+#define FM10K_SW_RX_STATS_BANK_4_SECURITY_VIOLATIONS\t8\n+#define FM10K_SW_RX_STATS_BANK_4_VLAN_TAG_DROPS\t\t9\n+#define FM10K_SW_RX_STATS_BANK_4_VLAN_INGRESS_DROPS\t10\n+#define FM10K_SW_RX_STATS_BANK_4_VLAN_EGRESS_DROPS\t11\n+#define FM10K_SW_RX_STATS_BANK_4_GLORT_MISS_DROPS\t12\n+#define FM10K_SW_RX_STATS_BANK_4_FFU_DROPS\t\t13\n+#define FM10K_SW_RX_STATS_BANK_4_TRIGGER_DROPS\t\t14\n+#define FM10K_SW_RX_STATS_BANK_5_POLICER_DROPS\t\t0\n+#define FM10K_SW_RX_STATS_BANK_5_TTL_DROPS\t\t1\n+#define FM10K_SW_RX_STATS_BANK_5_CM_PRIV_DROPS\t\t2\n+#define FM10K_SW_RX_STATS_BANK_5_CM_SMP0_DROPS\t\t3\n+#define FM10K_SW_RX_STATS_BANK_5_CM_SMP1_DROPS\t\t4\n+#define FM10K_SW_RX_STATS_BANK_5_CM_RX_HOG0_DROPS\t5\n+#define FM10K_SW_RX_STATS_BANK_5_CM_RX_HOG1_DROPS\t6\n+#define FM10K_SW_RX_STATS_BANK_5_CM_TX_HOG0_DROPS\t7\n+#define FM10K_SW_RX_STATS_BANK_5_CM_TX_HOG1_DROPS\t8\n+#define FM10K_SW_RX_STATS_BANK_5_TRIGGER_REDIRECTS\t10\n+#define FM10K_SW_RX_STATS_BANK_5_FLOOD_CONTROL_DROPS\t11\n+#define FM10K_SW_RX_STATS_BANK_5_GLORT_FORWARDED\t12\n+#define FM10K_SW_RX_STATS_BANK_5_LOOPBACK_SUPP_DROPS\t13\n+#define FM10K_SW_RX_STATS_BANK_5_OTHER_DROPS\t\t14\n+#define FM10K_SW_RX_PORT_STAT(b_, s_, p_, f_)\t\t\\\n+\t\t(FM10K_SW_RX_STATS_BANK(FM10K_SW_RX_STATS_##b_##_INDEX, \\\n+\t\t16 * (p_) +\tFM10K_SW_RX_STATS_##b_##_##s_) + \\\n+\t\t((f_) ? 0 : FM10K_SW_REG_OFF(2)))\n+\n+#define FM10K_SW_RX_STATS_CFG(p_)\t\t\t\\\n+\t\tFM10K_SW_RX_STATS_REG(0x10000 + (p_))\n+#define FM10K_SW_RX_STATS_CFG_PER_FRAME_ADJUSTMENT_lsb\t0\n+#define FM10K_SW_RX_STATS_CFG_PER_FRAME_ADJUSTMENT_msb\t7\n+#define FM10K_SW_RX_STATS_CFG_ENABLE_ALL_BANKS\t\t0x00003f00\n+#define FM10K_SW_RX_STATS_CFG_ENABLE_BANK_1\t\t(1 << 8)\n+#define FM10K_SW_RX_STATS_CFG_ENABLE_BANK_2\t\t(1 << 9)\n+#define FM10K_SW_RX_STATS_CFG_ENABLE_BANK_3\t\t(1 << 10)\n+#define FM10K_SW_RX_STATS_CFG_ENABLE_BANK_4\t\t(1 << 11)\n+#define FM10K_SW_RX_STATS_CFG_ENABLE_BANK_5\t\t(1 << 12)\n+#define FM10K_SW_RX_STATS_CFG_ENABLE_BANK_6\t\t(1 << 13)\n+#define FM10K_SW_RX_STATS_CFG_SWITCH_PRI\t\t(1 << 14)\n+\n+#define FM10K_SW_HANDLER_TAIL_BASE\t\t\t\\\n+\t\tFM10K_SW_REG_OFF(0xE30000)\n+#define FM10K_SW_HANDLER_TAIL_REG(wo_)\t\t\t\\\n+\t\t(FM10K_SW_HANDLER_TAIL_BASE + FM10K_SW_REG_OFF(wo_))\n+#define FM10K_SW_SAF_MATRIX(l_)\t\t\t\t\\\n+\t\tFM10K_SW_HANDLER_TAIL_REG(0x2 * (l_))\n+#define FM10K_SW_SAF_MATRIX_ENABLE_SNF(l_)\t\t(1ULL << (l_))\n+#define FM10K_SW_SAF_MATRIX_ENABLE_SNF_ALL_PORTS\tFM10K_SW_MASK64(47, 0)\n+#define FM10K_SW_SAF_MATRIX_IGNORE_ERROR\t\t(1ULL << 50)\n+\n+#define FM10K_SW_FRAME_TIME_OUT\t\t\tFM10K_SW_HANDLER_TAIL_REG(0x80)\n+#define FM10K_SW_SAF_SRAM_CTRL\t\t\tFM10K_SW_HANDLER_TAIL_REG(0x81)\n+#define FM10K_SW_EGRESS_PAUSE_SRAM_CTRL\t\tFM10K_SW_HANDLER_TAIL_REG(0x82)\n+#define FM10K_SW_RX_STATS_SRAM_CTRL\t\tFM10K_SW_HANDLER_TAIL_REG(0x84)\n+#define FM10K_SW_POLICER_USAGE_SRAM_CTRL\tFM10K_SW_HANDLER_TAIL_REG(0x88)\n+#define FM10K_SW_TCN_SRAM_CTRL\t\t\tFM10K_SW_HANDLER_TAIL_REG(0x8C)\n+#define FM10K_SW_FH_TAIL_IP\t\t\tFM10K_SW_HANDLER_TAIL_REG(0x8D)\n+#define FM10K_SW_FH_TAIL_IM\t\t\tFM10K_SW_HANDLER_TAIL_REG(0x8E)\n+#define FM10K_SW_TAIL_PERMIT_MGMT\t\tFM10K_SW_HANDLER_TAIL_REG(0x8F)\n+#define FM10K_SW_TAIL_FORCE_IDLE\t\tFM10K_SW_HANDLER_TAIL_REG(0x90)\n+\n+\n+#define FM10K_SW_CM_USAGE_BASE\t\t\tFM10K_SW_REG_OFF(0xE60000)\n+#define FM10K_SW_CM_USAGE_REG(wo_)\t\t\\\n+\t\t(FM10K_SW_CM_USAGE_BASE + FM10K_SW_REG_OFF(wo_))\n+#define FM10K_SW_CM_SWEEPER_SWITCH_PRI_TO_TC\tFM10K_SW_CM_USAGE_REG(0x0)\n+#define FM10K_SW_CM_SWEEPER_TC_TO_SMP\t\tFM10K_SW_CM_USAGE_REG(0x2)\n+#define FM10K_SW_CM_TX_TC_PRIVATE_WM(l_, c_)\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0x200 + 0x8 * (l_) + (c_))\n+#define FM10K_SW_CM_TX_TC_HOG_WM(l_, c_)\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0x400 + 0x8 * (l_) + (c_))\n+#define FM10K_SW_CM_RX_SMP_PAUSE_WM(l_, s_)\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0x600 + 0x2 * (l_) + (s_))\n+#define FM10K_SW_CM_RX_SMP_PRIVATE_WM(l_, s_)\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0x680 + 0x2 * (l_) + (s_))\n+#define FM10K_SW_CM_RX_SMP_HOG_WM(l_, s_)\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0x700 + 0x2 * (l_) + (s_))\n+#define FM10K_SW_CM_PAUSE_RESEND_INTERVAL(l_)\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0x780 + (l_))\n+#define FM10K_SW_CM_PAUSE_BASE_FREQ\t\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0x7C0)\n+#define FM10K_SW_CM_PAUSE_CFG(l_)\t\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0x800 + (l_))\n+#define FM10K_SW_CM_SHARED_WM(p_)\t\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0x840 + (p_))\n+#define FM10K_SW_CM_SHARED_SMP_PAUSE_WM(s_)\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0x850 + (s_))\n+#define FM10K_SW_CM_GLOBAL_WM\t\t\tFM10K_SW_CM_USAGE_REG(0x852)\n+#define FM10K_SW_CM_GLOBAL_WM_WATERMARK_lsb\t0\n+#define FM10K_SW_CM_GLOBAL_WM_WATERMARK_msb\t14\n+#define FM10K_SW_CM_GLOBAL_CFG\t\t\tFM10K_SW_CM_USAGE_REG(0x853)\n+#define FM10K_SW_CM_GLOBAL_CFG_IFG_PENALTY_lsb\t0\n+#define FM10K_SW_CM_GLOBAL_CFG_IFG_PENALTY_msb\t7\n+#define FM10K_SW_CM_GLOBAL_CFG_FORCE_PAUSE_ON\t(1 << 8)\n+#define FM10K_SW_CM_GLOBAL_CFG_FORCE_PAUSE_OFF\t(1 << 9)\n+#define FM10K_SW_CM_GLOBAL_CFG_WM_SWEEP_EN\t(1 << 10)\n+\n+#define FM10K_SW_CM_GLOBAL_CFG_PAUSE_GEN_SWEEP_EN\t(1 << 11)\n+#define FM10K_SW_CM_GLOBAL_CFG_PAUSE_REC_SWEEP_EN\t(1 << 12)\n+#define FM10K_SW_CM_GLOBAL_CFG_NUM_SWEEPER_PORTS_lsb\t13\n+#define FM10K_SW_CM_GLOBAL_CFG_NUM_SWEEPER_PORTS_msb\t18\n+\n+#define FM10K_SW_CM_TC_PC_MAP(l_)\tFM10K_SW_CM_USAGE_REG(0x880 + (l_))\n+#define FM10K_SW_CM_PC_SMP_MAP(l_)\tFM10K_SW_CM_USAGE_REG(0x8C0 + (l_))\n+#define FM10K_SW_CM_SOFTDROP_WM(p_)\tFM10K_SW_CM_USAGE_REG(0x900 + (p_))\n+\n+#define FM10K_SW_CM_SHARED_SMP_PAUSE_CFG(s_)\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0x910 + 0x2 * (s_))\n+#define FM10K_SW_TX_RATE_LIM_CFG(l_, c_)\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0xA00 + 0x8 * (l_) + (c_))\n+#define FM10K_SW_TX_RATE_LIM_USAGE(l_, c_)\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0xC00 + 0x8 * (l_) + (c_))\n+#define FM10K_SW_CM_BSG_MAP(l_)\t\t\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0xE00 + (l_))\n+#define FM10K_SW_CM_TX_TC_USAGE(l_, c_)\t\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0x1000 + 0x8 * (l_) + (c_))\n+#define FM10K_SW_CM_RX_SMP_USAGE(l_, s_)\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0x1200 + 0x2 * (l_) + (s_))\n+#define FM10K_SW_MCAST_EPOCH_USAGE(s_)\t\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0x1280 + (s_))\n+#define FM10K_SW_CM_SHARED_SMP_USAGE(s_)\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0x1282 + (s_))\n+#define FM10K_SW_CM_SMP_USAGE(s_)\t\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0x1284 + (s_))\n+#define FM10K_SW_CM_GLOBAL_USAGE\t\tFM10K_SW_CM_USAGE_REG(0x1286)\n+\n+#define FM10K_SW_CM_PAUSE_GEN_STATE(l_)\t\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0x12C0 + (l_))\n+#define FM10K_SW_CM_PAUSE_RCV_TIMER\t\tFM10K_SW_CM_USAGE_REG(0x1300)\n+#define FM10K_SW_CM_PAUSE_RCV_PORT_TIMER(l_)\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0x1340 + (l_))\n+\n+/* FM10K_SW_CM_EGRESS_PAUSE_COUNT is also\n+ * known as FM10K_SW_CM_PAUSE_RCV_STATE\n+ */\n+#define FM10K_SW_CM_EGRESS_PAUSE_COUNT(l_, dw_)\t\\\n+\t\tFM10K_SW_CM_USAGE_REG(0x1400 + 0x4 * (l_) + 0x2 * (dw_))\n+\n+#define FM10K_SW_MOD_BASE\t\t\tFM10K_SW_REG_OFF(0xE80000)\n+#define FM10K_SW_MOD_REG(wo_)\t\t\t\\\n+\t\t(FM10K_SW_MOD_BASE + FM10K_SW_REG_OFF(wo_))\n+#define FM10K_SW_MOD_MAX_MGMT_WAIT_CYCLE\tFM10K_SW_MOD_REG(0xF8)\n+#define FM10K_SW_MOD_IP\t\t\t\tFM10K_SW_MOD_REG(0x106)\n+#define FM10K_SW_MOD_IM\t\t\t\tFM10K_SW_MOD_REG(0x108)\n+#define FM10K_SW_MOD_SRAM_BIST_OUT\t\tFM10K_SW_MOD_REG(0x10A)\n+#define FM10K_SW_MOD_SRAM_ERROR_WRITE\t\tFM10K_SW_MOD_REG(0x10C)\n+#define FM10K_SW_MOD_PAUSE_SMAC\t\t\tFM10K_SW_MOD_REG(0x10E)\n+#define FM10K_SW_MOD_ROUTER_SMAC(n_)\t\t\\\n+\t\tFM10K_SW_MOD_REG(0x120 + 0x2 * (n_))\n+#define FM10K_SW_MOD_MCAST_VLAN_TABLE(n_)\t\\\n+\t\tFM10K_SW_MOD_REG(0x10000 + 0x2 * (n_))\n+#define FM10K_SW_MOD_VLAN_TAG_VID1_MAP(v_)\t\\\n+\t\tFM10K_SW_MOD_REG(0x20000 + 0x2 * (v_))\n+#define FM10K_SW_MOD_VID2_MAP(v_)\t\t\\\n+\t\tFM10K_SW_MOD_REG(0x22000 + 0x2 * (v_))\n+#define FM10K_SW_MOD_MIRROR_PROFILE_TABLE(n_)\t\\\n+\t\tFM10K_SW_MOD_REG(0x24000 + 0x2 * (n_))\n+#define FM10K_SW_MOD_PER_PORT_CFG_1(p_)\t\t\\\n+\t\tFM10K_SW_MOD_REG(0x24080 + 0x2 * (p_))\n+#define FM10K_SW_MOD_PER_PORT_CFG_2(p_)\t\t\\\n+\t\tFM10K_SW_MOD_REG(0x24100 + 0x2 * (p_))\n+\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_MIRROR_TRUNCATION_LEN_lsb64\t\t0\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_MIRROR_TRUNCATION_LEN_msb64\t\t5\n+\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_ENABLE_PCP1_UPDATE\t\t(1ULL << 6)\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_ENABLE_PCP2_UPDATE\t\t(1ULL << 7)\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_ENABLE_DEI1_UPDATE\t\t(1ULL << 8)\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_ENABLE_DEI2_UPDATE\t\t(1ULL << 9)\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_VLAN1_ETYPE_lsb64\t\t10\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_VLAN1_ETYPE_msb64\t\t11\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_VLAN2_ETYPE_lsb64\t\t12\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_VLAN2_ETYPE_msb64\t\t13\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_ENABLE_DMAC_ROUTING\t\t(1ULL << 14)\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_ENABLE_SMAC_ROUTING\t\t(1ULL << 15)\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_ENABLE_TTL_DECREMENT\t(1ULL << 16)\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_ENABLE_DSCP_MODIFICATION\t(1ULL << 17)\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_FTAG\t\t\t(1ULL << 18)\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_VID2_FIRST\t\t\t(1ULL << 19)\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_VLAN_TAGGING_lsb64\t\t20\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_VLAN_TAGGING_msb64\t\t22\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_TX_PAUSE_PRI_EN_VEC_lsb64\t23\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_TX_PAUSE_PRI_EN_VEC_msb64\t30\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_TX_PAUSE_TYPE\t\t(1ULL << 31)\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_TX_PAUSE_VALUE_lsb64\t32\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_TX_PAUSE_VALUE_msb64\t47\n+#define FM10K_SW_MOD_PER_PORT_CFG_2_MIN_FRAME_SIZE\t\t(1ULL << 48)\n+\n+#define FM10K_SW_MOD_VPRI1_MAP(p_)\t\t\\\n+\t\tFM10K_SW_MOD_REG(0x24180 + 0x2 * (p_))\n+#define FM10K_SW_MOD_VPRI2_MAP(p_)\t\t\\\n+\t\tFM10K_SW_MOD_REG(0x24200 + 0x2 * (p_))\n+#define FM10K_SW_MOD_VLAN_ETYPE(n_)\t\t\\\n+\t\tFM10K_SW_MOD_REG(0x24280 + 0x2 * (n_))\n+#define FM10K_SW_MOD_STATS_CFG(p_)\t\t\\\n+\t\tFM10K_SW_MOD_REG(0x24300 + 0x2 * (p_))\n+\n+#define FM10K_SW_MOD_STATS_CFG_ENABLE_GROUP_7\t(1 << 0)\n+#define FM10K_SW_MOD_STATS_CFG_ENABLE_GROUP_8\t(1 << 1)\n+#define FM10K_SW_MOD_STATS_BANK_FRAME(b_, i_)\t\\\n+\t\tFM10K_SW_MOD_REG(0x25000 + 0x800 * (b_) + 0x2 * (i_))\n+#define FM10K_SW_MOD_STATS_BANK_BYTE(b_, i_)\t\\\n+\t\tFM10K_SW_MOD_REG(0x26000 + 0x800 * (b_) + 0x2 * (i_))\n+\n+#define FM10K_SW_MOD_STATS_BANK_7_INDEX\t\t\t0\n+#define FM10K_SW_MOD_STATS_BANK_8_INDEX\t\t\t1\n+#define FM10K_SW_MOD_STATS_BANK_7_L2_UCAST\t\t0\n+#define FM10K_SW_MOD_STATS_BANK_7_L2_MCAST\t\t1\n+#define FM10K_SW_MOD_STATS_BANK_7_L2_BCAST\t\t2\n+#define FM10K_SW_MOD_STATS_BANK_7_TX_ERROR\t\t3\n+#define FM10K_SW_MOD_STATS_BANK_7_TIMEOUT_DROP\t\t4\n+#define FM10K_SW_MOD_STATS_BANK_7_TX_ERROR_DROP\t\t5\n+#define FM10K_SW_MOD_STATS_BANK_7_TX_ECC_DROP\t\t6\n+#define FM10K_SW_MOD_STATS_BANK_7_LOOPBACK_DROP\t\t7\n+#define FM10K_SW_MOD_STATS_BANK_7_TTL1_DROP\t\t8\n+#define FM10K_SW_MOD_STATS_BANK_7_PAUSE\t\t\t9\n+#define FM10K_SW_MOD_STATS_BANK_7_CB_PAUSE\t\t10\n+#define FM10K_SW_MOD_STATS_BANK_8_LEN_LT_64\t\t0\n+#define FM10K_SW_MOD_STATS_BANK_8_LEN_EQ_64\t\t1\n+#define FM10K_SW_MOD_STATS_BANK_8_LEN_65_127\t\t2\n+#define FM10K_SW_MOD_STATS_BANK_8_LEN_128_255\t\t3\n+#define FM10K_SW_MOD_STATS_BANK_8_LEN_256_511\t\t4\n+#define FM10K_SW_MOD_STATS_BANK_8_LEN_512_1023\t\t5\n+#define FM10K_SW_MOD_STATS_BANK_8_LEN_1024_1522\t\t6\n+#define FM10K_SW_MOD_STATS_BANK_8_LEN_1523_2047\t\t7\n+#define FM10K_SW_MOD_STATS_BANK_8_LEN_2048_4095\t\t8\n+#define FM10K_SW_MOD_STATS_BANK_8_LEN_4096_8191\t\t9\n+#define FM10K_SW_MOD_STATS_BANK_8_LEN_8192_10239\t10\n+#define FM10K_SW_MOD_STATS_BANK_8_LEN_GE_10240\t\t11\n+#define FM10K_SW_TX_PORT_STAT(b_, s_, p_, f_, p1_)\t\\\n+\t\t((f_) ? \\\n+\t\tFM10K_SW_MOD_STATS_BANK_FRAME(FM10K_SW_MOD_STATS_##b_##_INDEX, \\\n+\t\t16 * (p_) + FM10K_SW_MOD_STATS_##b_##_##s_) : \\\n+\t\tFM10K_SW_MOD_STATS_BANK_BYTE(FM10K_SW_MOD_STATS_##b_##_INDEX, \\\n+\t\t16 * (p1_) + FM10K_SW_MOD_STATS_##b_##_##s_))\n+\n+#define FM10K_SW_SCHED_BASE\t\t\tFM10K_SW_REG_OFF(0xF00000)\n+#define FM10K_SW_SCHED_REG(wo_)\t\t\t\\\n+\t\t(FM10K_SW_SCHED_BASE + FM10K_SW_REG_OFF(wo_))\n+\n+/*\n+ * Schedule fields for both FM10K_SW_SCHED_RX_SCHEDULE and\n+ * FM10K_SW_SCHED_TX_SCHEDULE\n+ */\n+#define\tFM10K_SW_SCHED_SCHEDULE_ENTRY(p_, l_, q_)\t\\\n+\t\t(FM10K_SW_MAKE_REG_FIELD(SCHED_SCHEDULE_PHYS_PORT, (p_)) | \\\n+\t\tFM10K_SW_MAKE_REG_FIELD(SCHED_SCHEDULE_LOG_PORT, (l_)) | \\\n+\t\t((q_) ? FM10K_SW_SCHED_SCHEDULE_QUAD : 0))\n+#define FM10K_SW_SCHED_SCHEDULE_PHYS_PORT_lsb\t\t0\n+#define FM10K_SW_SCHED_SCHEDULE_PHYS_PORT_msb\t\t7\n+#define FM10K_SW_SCHED_SCHEDULE_LOG_PORT_lsb\t\t8\n+#define FM10K_SW_SCHED_SCHEDULE_LOG_PORT_msb\t\t13\n+#define FM10K_SW_SCHED_SCHEDULE_QUAD\t\t\t(1 << 14)\n+#define FM10K_SW_SCHED_SCHEDULE_COLOR\t\t\t(1 << 15)\n+#define FM10K_SW_SCHED_SCHEDULE_IDLE\t\t\t(1 << 16)\n+\n+#define FM10K_SW_SCHED_RX_SCHEDULE(p_, n_)\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x20000 + 0x200 * (p_) + (n_))\n+#define FM10K_SW_SCHED_TX_SCHEDULE(p_, n_)\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x20400 + 0x200 * (p_) + (n_))\n+#define FM10K_SW_SCHED_SCHEDULE_CTRL\t\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x20800)\n+#define FM10K_SW_SCHED_SCHEDULE_CTRL_RX_ENABLE\t\t(1 << 0)\n+#define FM10K_SW_SCHED_SCHEDULE_CTRL_RX_PAGE\t\t(1 << 1)\n+#define FM10K_SW_SCHED_SCHEDULE_CTRL_RX_MAX_INDEX_lsb\t2\n+#define FM10K_SW_SCHED_SCHEDULE_CTRL_RX_MAX_INDEX_msb\t10\n+#define FM10K_SW_SCHED_SCHEDULE_CTRL_TX_ENABLE\t\t(1 << 11)\n+#define FM10K_SW_SCHED_SCHEDULE_CTRL_TX_PAGE\t\t(1 << 12)\n+#define FM10K_SW_SCHED_SCHEDULE_CTRL_TX_MAX_INDEX_lsb\t13\n+#define FM10K_SW_SCHED_SCHEDULE_CTRL_TX_MAX_INDEX_msb\t21\n+#define FM10K_SW_SCHED_CONFIG_SRAM_CTRL\t\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x20801)\n+#define FM10K_SW_SCHED_SSCHED_RX_PERPORT(l_)\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x20840 + (l_))\n+#define FM10K_SW_SCHED_SSCHED_RX_PERPORT_NEXT_lsb\t0\n+#define FM10K_SW_SCHED_SSCHED_RX_PERPORT_NEXT_msb\t15\n+#define FM10K_SW_SCHED_SSCHED_SRAM_CTRL\t\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x30050)\n+#define FM10K_SW_SCHED_ESCHED_CFG_1(l_)\t\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x30080 + (l_))\n+#define FM10K_SW_SCHED_ESCHED_CFG_2(l_)\t\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x300C0 + (l_))\n+#define FM10K_SW_SCHED_ESCHED_CFG_3(l_)\t\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x30100 + (l_))\n+#define FM10K_SW_SCHED_MGMT_TIMER_ESCHED\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x30240)\n+#define FM10K_SW_SCHED_ESCHED_SRAM_CTRL\t\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x30242)\n+#define FM10K_SW_SCHED_FREELIST_INIT\t\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x30244)\n+#define FM10K_SW_SCHED_FREELIST_INIT_ENTRIES\t\t(24 * 1024)\n+#define FM10K_SW_SCHED_FREELIST_INIT_ADDRESS_lsb\t0\n+#define FM10K_SW_SCHED_FREELIST_INIT_ADDRESS_msb\t15\n+#define FM10K_SW_SCHED_FREELIST_SRAM_CTRL\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x30246)\n+#define FM10K_SW_SCHED_MONITOR_DRR_Q_PERQ(q_)\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x30400 + (q_))\n+#define FM10K_SW_SCHED_MONITOR_DRR_CFG_PERPORT(l_)\t\\\n+\t\tFM10K_SW_SCHED_REG(0x30600 + (l_))\n+#define FM10K_SW_SCHED_MGMT_TIMER_MONITOR\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x30A40)\n+#define FM10K_SW_SCHED_MONITOR_SRAM_CTRL\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x30A41)\n+#define FM10K_SW_SCHED_MCAST_LEN_TABLE(n_)\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x34000 + (n_))\n+#define FM10K_SW_SCHED_MCAST_DEST_TABLE(n_)\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x38000 + 0x2 * (n_))\n+#define FM10K_SW_SCHED_MCAST_LIMITED_SKEW_MULTICAST\t\\\n+\t\tFM10K_SW_SCHED_REG(0x3A000)\n+#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS(n_)\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x60400 + 0x2 * (n_))\n+\n+#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_ENTRIES\t\t8\n+#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_HEAD_PAGE_lsb\t0\n+#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_HEAD_PAGE_msb\t9\n+#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_TAIL_PAGE_lsb\t10\n+#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_TAIL_PAGE_msb\t19\n+#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_HEAD_IDX_lsb\t20\n+#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_HEAD_IDX_msb\t24\n+#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_TAIL_IDX_lsb\t25\n+#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_TAIL_IDX_msb\t29\n+#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_NEXT_PAGE_lsb\t30\n+#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_NEXT_PAGE_msb\t39\n+#define FM10K_SW_SCHED_RXQ_FREELIST_INIT\t\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x60410)\n+#define FM10K_SW_SCHED_RXQ_FREELIST_INIT_ENTRIES\t\t1024\n+#define FM10K_SW_SCHED_RXQ_FREELIST_INIT_ADDRESS_lsb\t\t0\n+#define FM10K_SW_SCHED_RXQ_FREELIST_INIT_ADDRESS_msb\t\t9\n+\n+#define FM10K_SW_SCHED_MGMT_TIMER_RXQ\t\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x60412)\n+#define FM10K_SW_SCHED_MGMT_TIMER_LG\t\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x60413)\n+#define FM10K_SW_SCHED_RXQ_SRAM_CTRL\t\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x60414)\n+#define FM10K_SW_SCHED_TXQ_TAIL0_PERQ(q_)\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x60600 + (q_))\n+#define FM10K_SW_SCHED_TXQ_TAIL0_PERQ_TAIL_lsb\t\t0\n+#define FM10K_SW_SCHED_TXQ_TAIL0_PERQ_TAIL_msb\t\t15\n+#define FM10K_SW_SCHED_TXQ_TAIL1_PERQ(q_)\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x60800 + (q_))\n+#define FM10K_SW_SCHED_TXQ_TAIL1_PERQ_TAIL_lsb\t\t0\n+#define FM10K_SW_SCHED_TXQ_TAIL1_PERQ_TAIL_msb\t\t15\n+#define FM10K_SW_SCHED_TXQ_HEAD_PERQ(q_)\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x60A00 + (q_))\n+#define FM10K_SW_SCHED_TXQ_HEAD_PERQ_ENTRIES\t\t384\n+#define FM10K_SW_SCHED_TXQ_HEAD_PERQ_HEAD_lsb\t\t0\n+#define FM10K_SW_SCHED_TXQ_HEAD_PERQ_HEAD_msb\t\t15\n+#define FM10K_SW_SCHED_TXQ_FREELIST_INIT\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x62000)\n+#define FM10K_SW_SCHED_TXQ_FREELIST_INIT_ENTRIES\t(24 * 1024)\n+#define FM10K_SW_SCHED_TXQ_FREELIST_INIT_ADDRESS_lsb\t0\n+#define FM10K_SW_SCHED_TXQ_FREELIST_INIT_ADDRESS_msb\t15\n+#define FM10K_SW_SCHED_TXQ_SRAM_CTRL\t\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x62002)\n+#define FM10K_SW_SCHED_FIFO_SRAM_CTRL\t\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x62004)\n+#define FM10K_SW_SCHED_IP\t\t\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x62006)\n+#define FM10K_SW_SCHED_IM\t\t\t\t\\\n+\t\tFM10K_SW_SCHED_REG(0x62007)\n+\n+#endif /* _FM10K_REGS_H_ */\ndiff --git a/drivers/net/fm10k/switch/fm10k_sbus.c b/drivers/net/fm10k/switch/fm10k_sbus.c\nnew file mode 100644\nindex 0000000..d7d656e\n--- /dev/null\n+++ b/drivers/net/fm10k/switch/fm10k_sbus.c\n@@ -0,0 +1,292 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019   Silicom Ltd. Connectivity Solutions\n+ */\n+\n+#include <rte_malloc.h>\n+\n+#include <rte_time.h>\n+#include <rte_kvargs.h>\n+#include <rte_hash.h>\n+#include <rte_flow.h>\n+#include <rte_flow_driver.h>\n+#include <rte_tm_driver.h>\n+\n+#include \"fm10k_debug.h\"\n+#include \"fm10k_regs.h\"\n+#include \"fm10k_sbus.h\"\n+#include \"fm10k_switch.h\"\n+\n+#define FM10K_SW_SBUS_COMMAND_WAIT_LOCK_US_MAX\t4\n+#define FM10K_SW_SBUS_COMMAND_TIMEOUT_US\t\t500000\n+#define FM10K_SW_SBUS_RING_DIVIDER\t\t\t\t0x01\n+\n+static int fm10k_sbus_init(struct fm10k_sbus *);\n+static int fm10k_sbus_exec(struct fm10k_sbus *, struct fm10k_sbus_req *);\n+static int fm10k_sbus_reset_all(struct fm10k_sbus *);\n+static int fm10k_sbus_sbm_reset(struct fm10k_sbus *);\n+\n+struct fm10k_sbus *\n+fm10k_sbus_attach(struct fm10k_switch *sw,\n+\t\tconst char *name,\n+\t\tunsigned int cfg_reg)\n+{\n+\tstruct fm10k_sbus *sb;\n+\tint error;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: attaching\", name);\n+\n+\tsb = (struct fm10k_sbus *)rte_zmalloc\n+\t\t\t(\"fm10k_sbus\", sizeof(struct fm10k_sbus), 0);\n+\tif (sb == NULL) {\n+\t\tFM10K_SW_INFO(\"sbus %s: failed to allocate context\", name);\n+\t\tgoto fail;\n+\t}\n+\n+\tsb->sw = sw;\n+\tsb->name = name;\n+\tpthread_mutex_init(&sb->lock, NULL);\n+\n+\tsb->cfg_reg = cfg_reg;\n+\tsb->cmd_reg = cfg_reg + FM10K_SW_REG_OFF(1);\n+\tsb->req_reg = cfg_reg + FM10K_SW_REG_OFF(2);\n+\tsb->resp_reg = cfg_reg + FM10K_SW_REG_OFF(3);\n+\n+\terror = fm10k_sbus_init(sb);\n+\tif (error)\n+\t\tgoto fail;\n+\n+\tFM10K_SW_TRACE(\"sbus %s: attach successful\", name);\n+\treturn sb;\n+fail:\n+\tif (sb)\n+\t\tfm10k_sbus_detach(sb);\n+\treturn NULL;\n+}\n+\n+void\n+fm10k_sbus_detach(struct fm10k_sbus *sb)\n+{\n+\tFM10K_SW_TRACE(\"sbus %s: detaching\", sb->name);\n+\n+\trte_free(sb);\n+}\n+\n+static int\n+fm10k_sbus_init(struct fm10k_sbus *sb)\n+{\n+\tuint32_t data;\n+\tint error;\n+\n+\terror = fm10k_sbus_sbm_reset(sb);\n+\tif (error)\n+\t\tgoto done;\n+\n+\terror = fm10k_sbus_reset_all(sb);\n+\tif (error)\n+\t\tgoto done;\n+\n+\t/* set clock to REFCLK/2 */\n+\terror = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SBUS_CONTROLLER, 0x0a,\n+\t    FM10K_SW_SBUS_RING_DIVIDER);\n+\tif (error) {\n+\t\tFM10K_SW_ERR(\"sbus %s: failed to set ring divider\", sb->name);\n+\t\tgoto done;\n+\t}\n+\n+\terror = fm10k_sbus_read(sb, FM10K_SW_SBUS_ADDR_SBUS_CONTROLLER, 0x0a,\n+\t    &data);\n+\tif (error) {\n+\t\tFM10K_SW_ERR(\"sbus %s: failed to read back ring divider\",\n+\t\t\t\tsb->name);\n+\t\tgoto done;\n+\t}\n+\tif (data != FM10K_SW_SBUS_RING_DIVIDER) {\n+\t\tFM10K_SW_ERR(\"sbus %s: ring divider \"\n+\t\t\t\t\"verify failed (expected %u, got %u)\",\n+\t\t\t\tsb->name, FM10K_SW_SBUS_RING_DIVIDER, data);\n+\t\terror = -1;\n+\t\tgoto done;\n+\t}\n+\n+done:\n+\treturn error;\n+}\n+\n+static int\n+fm10k_sbus_exec(struct fm10k_sbus *sb, struct fm10k_sbus_req *req)\n+{\n+\tstruct fm10k_switch *sw =  sb->sw;\n+\tunsigned int total_usecs;\n+\tunsigned int drop_lock;\n+\tunsigned int delay_time;\n+\tint error = 0;\n+\tuint32_t data;\n+\tuint8_t expected_result;\n+\n+\tFM10K_SW_SBUS_LOCK(sb);\n+\n+\tFM10K_SW_SWITCH_LOCK(sw);\n+\tdata = fm10k_read_switch_reg(sw, sb->cmd_reg);\n+\tif (data & FM10K_SW_SBUS_COMMAND_BUSY) {\n+\t\tFM10K_SW_INFO(\"sbus %s: bus busy (0x%08x)\",\n+\t\t    sb->name, data);\n+\t\terror = -1;\n+\t\tgoto done;\n+\t}\n+\n+\tswitch (req->op) {\n+\tcase FM10K_SW_SBUS_OP_RESET:\n+\t\tFM10K_SW_TRACE(\"sbus %s: RESET dev=0x%02x reg=0x%02x data=0x%08x\",\n+\t\t    sb->name, req->dev, req->reg, req->data);\n+\t\texpected_result = FM10K_SW_SBUS_RESULT_RESET;\n+\t\tfm10k_write_switch_reg(sw, sb->req_reg, req->data);\n+\t\tbreak;\n+\tcase FM10K_SW_SBUS_OP_WRITE:\n+\t\tFM10K_SW_TRACE(\"sbus %s: WRITE dev=0x%02x reg=0x%02x data=0x%08x\",\n+\t\t    sb->name, req->dev, req->reg, req->data);\n+\t\texpected_result = FM10K_SW_SBUS_RESULT_WRITE;\n+\t\tfm10k_write_switch_reg(sw, sb->req_reg, req->data);\n+\t\tbreak;\n+\tcase FM10K_SW_SBUS_OP_READ:\n+\t\tFM10K_SW_TRACE(\"sbus %s: READ dev=0x%02x reg=0x%02x\",\n+\t\t    sb->name, req->dev, req->reg);\n+\t\texpected_result = FM10K_SW_SBUS_RESULT_READ;\n+\t\treq->data = 0;\n+\t\tbreak;\n+\tdefault:\n+\t\tFM10K_SW_INFO(\"sbus %s: invalid opcode 0x%02x\",\n+\t\t    sb->name, req->op);\n+\t\terror = -1;\n+\t\tgoto done;\n+\t}\n+\n+\t/* Clear the execute bit */\n+\tfm10k_write_switch_reg(sw, sb->cmd_reg, 0);\n+\n+\tdata =\n+\t    FM10K_SW_MAKE_REG_FIELD(SBUS_COMMAND_OP, req->op) |\n+\t    FM10K_SW_MAKE_REG_FIELD(SBUS_COMMAND_ADDRESS, req->dev) |\n+\t    FM10K_SW_MAKE_REG_FIELD(SBUS_COMMAND_REGISTER, req->reg) |\n+\t    FM10K_SW_SBUS_COMMAND_EXECUTE;\n+\tfm10k_write_switch_reg(sw, sb->cmd_reg, data);\n+\tfm10k_write_flush(sw);\n+\n+\ttotal_usecs = 0;\n+\tdelay_time = 1;\n+\tdrop_lock = 0;\n+\tdo {\n+\t\tif (drop_lock)\n+\t\t\tFM10K_SW_SWITCH_UNLOCK(sw);\n+\t\tfm10k_udelay(delay_time);\n+\t\tif (drop_lock)\n+\t\t\tFM10K_SW_SWITCH_LOCK(sw);\n+\t\ttotal_usecs += delay_time;\n+\t\tif (total_usecs >= FM10K_SW_SBUS_COMMAND_WAIT_LOCK_US_MAX) {\n+\t\t\tdrop_lock = 1;\n+\t\t\tdelay_time <<= 1;\n+\t\t}\n+\n+\t\tdata = fm10k_read_switch_reg(sw, sb->cmd_reg);\n+\t\tif (!(data & FM10K_SW_SBUS_COMMAND_BUSY)) {\n+\t\t\tif (FM10K_SW_REG_FIELD(data,\n+\t\t\t\t\tSBUS_COMMAND_RESULT_CODE)\n+\t\t\t\t\t!= expected_result) {\n+\t\t\t\tFM10K_SW_INFO(\"sbus %s: expected \"\n+\t\t\t\t    \"result code %u, got %u\", sb->name,\n+\t\t\t\t    expected_result,\n+\t\t\t\t    FM10K_SW_REG_FIELD(data,\n+\t\t\t\t\tSBUS_COMMAND_RESULT_CODE));\n+\t\t\t\terror = -1;\n+\t\t\t\tgoto done;\n+\t\t\t}\n+\t\t\tif (req->op == FM10K_SW_SBUS_OP_READ) {\n+\t\t\t\treq->data =\n+\t\t\t\t    fm10k_read_switch_reg(sw, sb->resp_reg);\n+\t\t\t\tFM10K_SW_TRACE(\"sbus %s: READ data=0x%02x\",\n+\t\t\t\t\t\tsb->name, req->data);\n+\t\t\t}\n+\t\t\tgoto done;\n+\t\t}\n+\n+\t} while (total_usecs < FM10K_SW_SBUS_COMMAND_TIMEOUT_US);\n+\n+\terror = -1;\n+\tFM10K_SW_INFO(\"sbus %s: command timed out after %u us \"\n+\t    \"(op=0x%02x dev=0x%02x reg=0x%02x data=0x%08x)\", sb->name,\n+\t    total_usecs, req->op, req->dev, req->reg, req->data);\n+\n+done:\n+\tFM10K_SW_SWITCH_UNLOCK(sw);\n+\tFM10K_SW_SBUS_UNLOCK(sb);\n+\treturn error;\n+}\n+\n+static int\n+fm10k_sbus_reset_all(struct fm10k_sbus *sb)\n+{\n+\tstruct fm10k_sbus_req req;\n+\tint error;\n+\n+\treq.op = FM10K_SW_SBUS_OP_RESET;\n+\treq.dev = FM10K_SW_SBUS_ADDR_BROADCAST;\n+\treq.reg = 0;\n+\treq.data = 0;\n+\n+\terror = fm10k_sbus_exec(sb, &req);\n+\n+\tFM10K_SW_TRACE(\"sbus %s: broadcast reset %s (%d)\", sb->name,\n+\t    error ? \"failed\" : \"succeeded\", error);\n+\n+\treturn error;\n+}\n+\n+static int\n+fm10k_sbus_sbm_reset(struct fm10k_sbus *sb)\n+{\n+\tstruct fm10k_sbus_req req;\n+\tint error;\n+\n+\treq.op = FM10K_SW_SBUS_OP_RESET;\n+\treq.dev = FM10K_SW_SBUS_ADDR_SPICO;\n+\treq.reg = 0;\n+\treq.data = 0;\n+\n+\terror = fm10k_sbus_exec(sb, &req);\n+\n+\tFM10K_SW_TRACE(\"sbus %s: SBM reset %s (%d)\", sb->name,\n+\t    error ? \"failed\" : \"succeeded\", error);\n+\n+\treturn error;\n+}\n+\n+int\n+fm10k_sbus_read(struct fm10k_sbus *sb, uint8_t dev, uint8_t reg, uint32_t *data)\n+{\n+\tstruct fm10k_sbus_req req;\n+\tint error;\n+\n+\treq.op = FM10K_SW_SBUS_OP_READ;\n+\treq.dev = dev;\n+\treq.reg = reg;\n+\n+\terror = fm10k_sbus_exec(sb, &req);\n+\t*data = error ? 0 : req.data;\n+\n+\treturn error;\n+}\n+\n+int\n+fm10k_sbus_write(struct fm10k_sbus *sb, uint8_t dev, uint8_t reg, uint32_t data)\n+{\n+\tstruct fm10k_sbus_req req;\n+\tint error;\n+\n+\treq.op = FM10K_SW_SBUS_OP_WRITE;\n+\treq.dev = dev;\n+\treq.reg = reg;\n+\treq.data = data;\n+\n+\terror = fm10k_sbus_exec(sb, &req);\n+\n+\treturn error;\n+}\ndiff --git a/drivers/net/fm10k/switch/fm10k_sbus.h b/drivers/net/fm10k/switch/fm10k_sbus.h\nnew file mode 100644\nindex 0000000..e67967f\n--- /dev/null\n+++ b/drivers/net/fm10k/switch/fm10k_sbus.h\n@@ -0,0 +1,40 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019   Silicom Ltd. Connectivity Solutions\n+ */\n+\n+#ifndef _FM10K_SW_SBUS_H_\n+#define _FM10K_SW_SBUS_H_\n+\n+#include <pthread.h>\n+\n+\n+struct fm10k_sbus {\n+\tstruct fm10k_switch *sw;\n+\tconst char *name;\n+\tpthread_mutex_t lock;\n+\tunsigned int cfg_reg;\n+\tunsigned int cmd_reg;\n+\tunsigned int req_reg;\n+\tunsigned int resp_reg;\n+};\n+\n+#define FM10K_SW_SBUS_LOCK(sb_)\t\tpthread_mutex_lock(&((sb_)->lock))\n+#define FM10K_SW_SBUS_UNLOCK(sb_)\tpthread_mutex_unlock(&((sb_)->lock))\n+\n+struct fm10k_sbus_req {\n+\tuint8_t op;\n+\tuint8_t dev;\n+\tuint8_t reg;\n+\tuint32_t data;\n+};\n+\n+\n+struct fm10k_sbus *fm10k_sbus_attach(struct fm10k_switch *sw,\n+\t\tconst char *name, unsigned int cfg_reg);\n+void fm10k_sbus_detach(struct fm10k_sbus *sb);\n+int fm10k_sbus_read(struct fm10k_sbus *sb,\n+\t\tuint8_t dev, uint8_t reg, uint32_t *data);\n+int fm10k_sbus_write(struct fm10k_sbus *sb,\n+\t\tuint8_t dev, uint8_t reg, uint32_t data);\n+\n+#endif /* _FM10K_SW_SBUS_H_ */\ndiff --git a/drivers/net/fm10k/switch/fm10k_switch.h b/drivers/net/fm10k/switch/fm10k_switch.h\nnew file mode 100644\nindex 0000000..2423dbf\n--- /dev/null\n+++ b/drivers/net/fm10k/switch/fm10k_switch.h\n@@ -0,0 +1,335 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019   Silicom Ltd. Connectivity Solutions\n+ */\n+\n+#ifndef _FM10K_SW_SWITCH_H_\n+#define _FM10K_SW_SWITCH_H_\n+\n+#include <rte_spinlock.h>\n+#include <pthread.h>\n+#include <sys/time.h>\n+#include <semaphore.h>\n+\n+#include \"../fm10k.h\"\n+#include \"fm10k_debug.h\"\n+#include \"fm10k_regs.h\"\n+\n+\n+/*\n+ * EPL\n+ */\n+#define FM10K_SW_EXT_PORTS_MAX\t\t4\n+\n+#define FM10K_SW_EPLS_MAX\t\t9\n+#define FM10K_SW_EPLS_SUPPORTED\t\t2\n+#define FM10K_SW_EPL_LANES\t\t4\n+#define FM10K_SW_EPLS_PEP_MAX\t\t2\n+\n+/*\n+ * PEP\n+ */\n+#define FM10K_SW_PEP_GROUP_MAX\t\t10\n+#define FM10K_SW_LOGICAL_PORTS_MAX\t48\n+\n+#define FM10K_SW_PEPS_MAX\t\t9\n+#define FM10K_SW_PEPS_SUPPORTED\t\t4\n+#define FM10K_SW_PEP_PORTS_MAX\t\t4\n+\n+/*\n+ * GLORT\n+ */\n+#define FM10K_SW_GROUP_MAX\t\t10\n+#define FM10K_SW_VFS_MAX\t\t64\n+#define FM10K_SW_PFS_GLORT_START\t0x1000\n+#define FM10K_SW_VF_GLORT_START\t\t0x2000\n+#define FM10K_SW_MULTI_GLORT_START\t0x3000\n+#define FM10K_SW_DPORT_MASK(lport)\t(1ULL << (lport))\n+\n+\n+/*\n+ * CONFIG\n+ */\n+#define FM10K_SW_CONFIG_MAX\t\t1000\n+#define FM10K_SW_FFU_RULE_MAX\t\t256\n+#define FM10K_SW_FFU_RULE_ITEM_MAX\t10\n+\n+/*\n+ * FFU COUNT\n+ */\n+#define FM10K_SW_FFU_CNT_BANK\t\t3\n+#define FM10K_SW_POLICER_LAST\t\t19\n+#define FM10K_SW_FFU_CNT_START\t\t(FM10K_SW_POLICER_LAST + 1)\n+#define FM10K_SW_FFU_CNT_MAX\t\t100\n+\n+#define FM10K_SW_PEP_QUEUES_MAX\t\t256\n+#define FM10K_SW_VF_QUEUES_MAX\t\t(FM10K_SW_PEP_QUEUES_MAX - 1)\n+\n+#define FM10K_SW_FTAG_SIZE\t\t8\n+#define FM10K_SW_PACKET_SIZE_MIN\t17\n+#define FM10K_SW_PACKET_SIZE_MAX\t(15 * 1024)\n+#define FM10K_SW_MTU_MAX\t\t\\\n+\t(FM10K_SW_PACKET_SIZE_MAX - ETHER_HDR_LEN - ETHER_VLAN_ENCAP_LEN)\n+#define FM10K_SW_SEG_SIZE_MAX\t\t(16 * 1024)\n+#define FM10K_SW_TSO_SIZE_MAX\t\t(256 * 1024 - 1)\n+\n+#define FM10K_SW_MEM_POOL_SEG_SIZE\t192\n+#define FM10K_SW_MEM_POOL_SEGS_MAX\t24576\n+#define FM10K_SW_MEM_POOL_SEGS_RSVD\t256\n+\n+\n+\n+#define FM10K_SW_CARD_ID(v_, d_)\t(((v_) << 16) | (d_))\n+#define FM10K_SW_CARD(vname_, dname_)\t\\\n+\t\tFM10K_SW_CARD_ID(FM10K_SW_VENDOR_ID_##vname_, \\\n+\t\t\t\tFM10K_SW_DEV_ID_##dname_)\n+\n+/*\n+ * All IDs that may appear in the vendor ID or subsystem vendor ID.\n+ */\n+#define FM10K_SW_VENDOR_ID_INTEL\t0x8086\n+#define FM10K_SW_VENDOR_ID_SILICOM\t0x1374\n+#define FM10K_SW_VENDOR_ID_SILICOM_RB\t0x1B2E\n+\n+\n+/*\n+ * All IDs that may appear in the device ID or subsystem device ID.\n+ */\n+#define FM10K_SW_DEV_ID_FM10K\t\t\t\t0x15a4\n+\n+/* Silicom cards */\n+#define FM10K_SW_DEV_ID_PE310G4DBIR_T\t\t\t0x01B0\n+#define FM10K_SW_DEV_ID_PE310G4DBIR_SRD\t\t\t0x01B1\n+#define FM10K_SW_DEV_ID_PE310G4DBIR_LRD\t\t\t0x01B2\n+#define FM10K_SW_DEV_ID_PE310G4DBIR_ER\t\t\t0x01B3\n+#define FM10K_SW_DEV_ID_PE310G4DBIR_DA\t\t\t0x01B4\n+#define FM10K_SW_DEV_ID_PE340G2DBIR_QS41\t\t0x01B8\n+#define FM10K_SW_DEV_ID_PE340G2DBIR_QS43\t\t0x01B9\n+#define FM10K_SW_DEV_ID_PE340G2DBIR_QL4\t\t\t0x01BA\n+#define FM10K_SW_DEV_ID_PE3100G2DQIR_QXSL4\t\t0x01C0\n+#define FM10K_SW_DEV_ID_PE3100G2DQIR_QXSL4_REV_2\t0x01C4\n+#define FM10K_SW_DEV_ID_PE3100G2DQIRL_QXSL4\t\t0x01C1\n+#define FM10K_SW_DEV_ID_PE3100G2DQIRM_QXSL4\t\t0x01C2\n+#define FM10K_SW_DEV_ID_PE325G2DSIR\t\t\t0x01C8\n+\n+/*\n+ * SWITCH\n+ */\n+\n+struct fm10k_device_info {\n+\tuint16_t subvendor;\n+\tuint16_t subdevice;\n+\tconst char *desc;\n+\tuint8_t num_ext_ports;\n+\tuint8_t ext_port_speed;\n+\tuint8_t num_epls;\n+\tuint8_t num_peps;\n+};\n+\n+\n+struct fm10k_i2c;\n+struct fm10k_sbus;\n+struct fm10k_hw;\n+struct fm10k_ext_ports;\n+struct fm10k_dpdk_cfg;\n+\n+struct fm10k_sw_port_map {\n+\tuint32_t glort;\n+\tuint16_t logical_port; /* logical port number */\n+\tuint16_t physical_port; /*  */\n+};\n+\n+struct fm10k_switch {\n+\tuint32_t *hw_addr;\n+\tuint32_t *sw_addr;\n+\tstruct fm10k_hw *master_hw;\n+\tstruct fm10k_device_info *info;\n+\tpthread_mutex_t lock;\n+\tstruct fm10k_i2c *i2c;\n+\tstruct fm10k_sbus *epl_sbus;\n+\tstruct fm10k_ext_ports *ext_ports;\n+\tsem_t intr_tq;\n+\tpthread_t intr_task;\n+\tpthread_t led_task;\n+\tpthread_t stats_task;\n+\tuint32_t detaching;\n+\tuint32_t glort_cam_ram_idx;\n+\tuint32_t glort_dest_table_idx;\n+\tuint32_t mcast_dest_table_idx;\n+\tuint32_t mcast_len_table_idx;\n+\tuint32_t mcast_vlan_table_idx;\n+\tuint32_t epl_serdes_code_version_build_id;\n+\tuint16_t pep_mask; /* mask of non-master peps */\n+\tuint8_t pepno;\n+\tuint8_t serdes_loopback;\n+\tuint8_t epla_no;\n+\tuint8_t eplb_no;\n+\tuint8_t mac_addr[6];\n+\tstruct fm10k_dpdk_cfg *dpdk_cfg;\n+\tstruct fm10k_sw_port_map *pep_map;\n+\tstruct fm10k_sw_port_map *epl_map;\n+\tint inited;\n+};\n+\n+#define FM10K_SW_SWITCH_LOCK(sw_)\tpthread_mutex_lock(&((sw_)->lock))\n+#define FM10K_SW_SWITCH_UNLOCK(sw_)\tpthread_mutex_unlock(&((sw_)->lock))\n+\n+#define FM10K_SW_HOWMANY(x, y, y1)\t(((x) + (y) - 1) / (y1))\n+\n+\n+static inline uint64_t\n+fm10k_uptime_us(void)\n+{\n+\tstruct timeval tv;\n+\n+\tgettimeofday(&tv, NULL);\n+\treturn ((uint64_t)tv.tv_sec * 1000000 + tv.tv_usec);\n+}\n+\n+\n+static inline uint32_t\n+fm10k_read_switch_reg(struct fm10k_switch *sw, uint32_t reg)\n+{\n+\treturn ((volatile uint32_t *)sw->master_hw->sw_addr)[reg];\n+}\n+\n+static inline uint64_t\n+fm10k_read_switch_reg64(struct fm10k_switch *sw, uint32_t reg)\n+{\n+\tuint64_t temp, result;\n+\n+\tresult = ((volatile uint32_t *)sw->master_hw->sw_addr)[reg];\n+\ttemp = ((volatile uint32_t *)sw->master_hw->sw_addr)[reg + 1];\n+\tresult |= temp << 32;\n+\n+\treturn result;\n+}\n+\n+static inline void\n+fm10k_read_switch_array(struct fm10k_switch *sw,\n+\t\tuint32_t reg, uint32_t *results, uint32_t count)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < count; i++)\n+\t\tresults[i] =\n+\t\t\t((volatile uint32_t *)sw->master_hw->sw_addr)[reg + i];\n+}\n+\n+\n+static inline void\n+fm10k_write_switch_reg(struct fm10k_switch *sw, uint32_t reg, uint32_t val)\n+{\n+\t((volatile uint32_t *)sw->master_hw->sw_addr)[reg] = val;\n+}\n+\n+static inline void\n+fm10k_write_switch_reg64(struct fm10k_switch *sw, uint32_t reg, uint64_t val)\n+{\n+\t((volatile uint32_t *)sw->master_hw->sw_addr)[reg] = val & 0xffffffff;\n+\t((volatile uint32_t *)sw->master_hw->sw_addr)[reg + 1] = val >> 32;\n+}\n+\n+static inline void\n+fm10k_write_switch_reg128(struct fm10k_switch *sw,\n+\t\tuint32_t reg, uint64_t val_hi, uint64_t val_lo)\n+{\n+\t((volatile uint32_t *)sw->master_hw->sw_addr)[reg] =\n+\t\t\tval_lo & 0xffffffff;\n+\t((volatile uint32_t *)sw->master_hw->sw_addr)[reg + 1] =\n+\t\t\tval_lo >> 32;\n+\t((volatile uint32_t *)sw->master_hw->sw_addr)[reg + 2] =\n+\t\t\tval_hi & 0xffffffff;\n+\t((volatile uint32_t *)sw->master_hw->sw_addr)[reg + 3] =\n+\t\t\tval_hi >> 32;\n+}\n+\n+static inline void\n+fm10k_write_switch_array(struct fm10k_switch *sw,\n+\t\tuint32_t reg, uint32_t *data, uint32_t count)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < count; i++)\n+\t\t((volatile uint32_t *)sw->master_hw->sw_addr)[reg + i] =\n+\t\t\t\tdata[i];\n+}\n+\n+static inline uint32_t\n+fm10k_write_flush(struct fm10k_switch *sw)\n+{\n+\treturn ((volatile uint32_t *)sw->master_hw->hw_addr)[FM10K_SW_CTRL];\n+}\n+\n+static inline void\n+fm10k_gpio_output_set(struct fm10k_switch *sw, int gpio_pin, int value)\n+{\n+\tuint32_t data;\n+\n+\tdata = fm10k_read_switch_reg(sw, FM10K_SW_GPIO_CFG);\n+\tdata |= 1 << gpio_pin;\n+\tdata &= ~(1 << (gpio_pin + 16));\n+\n+\t/* set gpio output */\n+\tfm10k_write_switch_reg(sw, FM10K_SW_GPIO_CFG, data);\n+\n+\t/*\n+\t * Wait 1 msec (PCA spec specifies reset pulse width = 4 ns and\n+\t *  and reset time = 100 ns)\n+\t */\n+\tusec_delay(1000);\n+\t/* set reset */\n+\tdata = fm10k_read_switch_reg(sw, FM10K_SW_GPIO_DATA);\n+\tif (value == 0)\n+\t\tdata &= ~(1 << gpio_pin);\n+\telse\n+\t\tdata |= 1 << gpio_pin;\n+\n+\tfm10k_write_switch_reg(sw, FM10K_SW_GPIO_DATA, data);\n+}\n+\n+#define fm10k_udelay\tusec_delay\n+typedef int eth_fm10k_dev_init_half_func(struct fm10k_hw *hw);\n+\n+unsigned int fm10k_switch_eplidx_to_eplno\n+\t(struct fm10k_switch *sw, unsigned int eplidx);\n+void fm10k_switch_intr(struct fm10k_hw *hw);\n+\n+struct fm10k_switch *fm10k_switch_get(void);\n+struct fm10k_device_info *fm10k_get_device_info(struct fm10k_hw *hw);\n+int fm10k_switch_dpdk_port_start(struct fm10k_hw *hw, void *rte_dev,\n+\t\tuint8_t is_pf, bool master, eth_fm10k_dev_init_half_func *func);\n+void fm10k_switch_dpdk_port_stop(struct fm10k_hw *hw);\n+int fm10k_switch_dpdk_hw_queue_map(struct fm10k_hw *hw,\n+\t\tuint16_t queue, uint16_t max_queue,\n+\t\tstruct fm10k_hw **map_hw, uint16_t *map_queue);\n+int fm10k_switch_dpdk_mapped_hw_get(struct fm10k_hw *hw,\n+\t\tstruct fm10k_hw *hw_list[]);\n+int fm10k_switch_dpdk_pf_no_get(struct fm10k_hw *hw);\n+int fm10k_switch_dpdk_port_no_get(struct fm10k_hw *hw);\n+void *fm10k_switch_dpdk_port_rte_dev_get(struct fm10k_hw *hw);\n+struct fm10k_flow_list *\n+fm10k_switch_dpdk_port_flow_list_get(struct fm10k_hw *hw);\n+void fm10k_switch_dpdk_tx_queue_num_set(struct fm10k_hw *hw, uint8_t num);\n+void fm10k_switch_dpdk_rx_queue_num_set(struct fm10k_hw *hw, uint8_t num);\n+\n+uint32_t fm10k_switch_pf_logical_get(uint8_t pf_no);\n+uint32_t fm10k_switch_epl_logical_get(uint8_t epl_no);\n+uint32_t fm10k_switch_vf_glort_get(uint8_t vf_no);\n+uint32_t fm10k_switch_pf_glort_get(uint8_t pf_no);\n+uint32_t fm10k_switch_pfs_glort_get(uint8_t pf1, uint8_t pf2);\n+uint32_t fm10k_switch_epl_glort_get(uint8_t epl_no);\n+uint32_t fm10k_switch_multi_glort_get(uint8_t pf1, uint8_t pf2,\n+\t\tuint16_t vlan1, uint16_t vlan2, bool *p_new);\n+\n+int fm10k_switch_mirror_set(struct fm10k_hw *hw, u16 dest_port, u16 vlan);\n+int fm10k_switch_mirror_reset(struct fm10k_hw *hw);\n+\n+void fm10k_switch_flowset_switchto(const char *name);\n+void fm10k_switch_show_port(void);\n+void fm10k_switch_show_ffu(void);\n+void fm10k_switch_show_bank(void);\n+\n+void fm10k_flow_list_init(void *flow_list);\n+const struct rte_flow_ops *fm10k_flow_ops_get(void);\n+\n+#endif\n",
    "prefixes": [
        "v1",
        "1/5"
    ]
}