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{
    "id": 65763,
    "url": "http://patches.dpdk.org/api/patches/65763/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200212134745.5723-2-konstantin.ananyev@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20200212134745.5723-2-konstantin.ananyev@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20200212134745.5723-2-konstantin.ananyev@intel.com",
    "date": "2020-02-12T13:47:44",
    "name": "[1/2] acl: fix 32-bit range field doesn't work properly",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "5e7375284867cee5b226be8d13d9898cffbfd29c",
    "submitter": {
        "id": 33,
        "url": "http://patches.dpdk.org/api/people/33/?format=api",
        "name": "Ananyev, Konstantin",
        "email": "konstantin.ananyev@intel.com"
    },
    "delegate": {
        "id": 24651,
        "url": "http://patches.dpdk.org/api/users/24651/?format=api",
        "username": "dmarchand",
        "first_name": "David",
        "last_name": "Marchand",
        "email": "david.marchand@redhat.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200212134745.5723-2-konstantin.ananyev@intel.com/mbox/",
    "series": [
        {
            "id": 8515,
            "url": "http://patches.dpdk.org/api/series/8515/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8515",
            "date": "2020-02-12T13:47:43",
            "name": "acl: fix 32-bit range field doesn't work properly",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/8515/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/65763/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/65763/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D0D5FA0534;\n\tWed, 12 Feb 2020 14:48:00 +0100 (CET)",
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            "from orsmga002.jf.intel.com ([10.7.209.21])\n by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 12 Feb 2020 05:47:53 -0800",
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        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.70,433,1574150400\"; d=\"scan'208\";a=\"251914319\"",
        "From": "Konstantin Ananyev <konstantin.ananyev@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "Ido@cgstowernetworks.com,\n Konstantin Ananyev <konstantin.ananyev@intel.com>, stable@dpdk.org",
        "Date": "Wed, 12 Feb 2020 13:47:44 +0000",
        "Message-Id": "<20200212134745.5723-2-konstantin.ananyev@intel.com>",
        "X-Mailer": "git-send-email 2.18.0",
        "In-Reply-To": "<20200212134745.5723-1-konstantin.ananyev@intel.com>",
        "References": "<20200212134745.5723-1-konstantin.ananyev@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 1/2] acl: fix 32-bit range field doesn't work\n\tproperly",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "ACL build phase for range fields that are bigger then\n16 bits might generate wrong trie.\nFor more details please refer to:\nhttps://bugs.dpdk.org/show_bug.cgi?id=307\n\nFixes: dc276b5780c2 (\"acl: new library\")\nCc: stable@dpdk.org\n\nReported-by: Ido Goshen <Ido@cgstowernetworks.com>\nSigned-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>\n---\n lib/librte_acl/acl_bld.c | 148 ++++++++++++++++++++++++++++-----------\n 1 file changed, 106 insertions(+), 42 deletions(-)",
    "diff": "diff --git a/lib/librte_acl/acl_bld.c b/lib/librte_acl/acl_bld.c\nindex b06bbe920..0ae143e4e 100644\n--- a/lib/librte_acl/acl_bld.c\n+++ b/lib/librte_acl/acl_bld.c\n@@ -778,9 +778,8 @@ acl_build_reset(struct rte_acl_ctx *ctx)\n }\n \n static void\n-acl_gen_range(struct acl_build_context *context,\n-\tconst uint8_t *hi, const uint8_t *lo, int size, int level,\n-\tstruct rte_acl_node *root, struct rte_acl_node *end)\n+acl_gen_full_range(struct acl_build_context *context, struct rte_acl_node *root,\n+\tstruct rte_acl_node *end, int size, int level)\n {\n \tstruct rte_acl_node *node, *prev;\n \tuint32_t n;\n@@ -788,10 +787,71 @@ acl_gen_range(struct acl_build_context *context,\n \tprev = root;\n \tfor (n = size - 1; n > 0; n--) {\n \t\tnode = acl_alloc_node(context, level++);\n-\t\tacl_add_ptr_range(context, prev, node, lo[n], hi[n]);\n+\t\tacl_add_ptr_range(context, prev, node, 0, UINT8_MAX);\n \t\tprev = node;\n \t}\n-\tacl_add_ptr_range(context, prev, end, lo[0], hi[0]);\n+\tacl_add_ptr_range(context, prev, end, 0, UINT8_MAX);\n+}\n+\n+static void\n+acl_gen_range_mdl(struct acl_build_context *context, struct rte_acl_node *root,\n+\tstruct rte_acl_node *end, uint8_t lo, uint8_t hi, int size, int level)\n+{\n+\tstruct rte_acl_node *node;\n+\n+\tnode = acl_alloc_node(context, level++);\n+\tacl_add_ptr_range(context, root, node, lo, hi);\n+\tacl_gen_full_range(context, node, end, size - 1, level);\n+}\n+\n+static void\n+acl_gen_range_low(struct acl_build_context *context, struct rte_acl_node *root,\n+\tstruct rte_acl_node *end, const uint8_t *lo, int size, int level)\n+{\n+\tstruct rte_acl_node *node;\n+\tuint32_t n;\n+\n+\tn = size - 1;\n+\tif (n == 0) {\n+\t\tacl_add_ptr_range(context, root, end, lo[0], UINT8_MAX);\n+\t\treturn;\n+\t}\n+\n+\tnode = acl_alloc_node(context, level++);\n+\tacl_add_ptr_range(context, root, node, lo[n], lo[n]);\n+\n+\t/* generate lower-bound sub-trie */\n+\tacl_gen_range_low(context, node, end, lo, n, level);\n+\n+\t/* generate middle sub-trie */\n+\tif (n > 1 && lo[n - 1] != UINT8_MAX)\n+\t\tacl_gen_range_mdl(context, node, end, lo[n - 1] + 1, UINT8_MAX,\n+\t\t\tn, level);\n+}\n+\n+static void\n+acl_gen_range_high(struct acl_build_context *context, struct rte_acl_node *root,\n+\tstruct rte_acl_node *end, const uint8_t *hi, int size, int level)\n+{\n+\tstruct rte_acl_node *node;\n+\tuint32_t n;\n+\n+\tn = size - 1;\n+\tif (n == 0) {\n+\t\tacl_add_ptr_range(context, root, end, 0, hi[0]);\n+\t\treturn;\n+\t}\n+\n+\tnode = acl_alloc_node(context, level++);\n+\tacl_add_ptr_range(context, root, node, hi[n], hi[n]);\n+\n+\t/* generate upper-bound sub-trie */\n+\tacl_gen_range_high(context, node, end, hi, n, level);\n+\n+\t/* generate middle sub-trie */\n+\tif (n > 1 && hi[n - 1] != 0)\n+\t\tacl_gen_range_mdl(context, node, end, 0, hi[n - 1] - 1,\n+\t\t\tn, level);\n }\n \n static struct rte_acl_node *\n@@ -799,52 +859,56 @@ acl_gen_range_trie(struct acl_build_context *context,\n \tconst void *min, const void *max,\n \tint size, int level, struct rte_acl_node **pend)\n {\n-\tint32_t n;\n-\tstruct rte_acl_node *root;\n-\tconst uint8_t *lo = min;\n-\tconst uint8_t *hi = max;\n+\tint32_t k, n;\n+\tuint8_t hi_ff, lo_00;\n+\tstruct rte_acl_node *node, *prev, *root;\n+\tconst uint8_t *lo;\n+\tconst uint8_t *hi;\n+\n+\tlo = min;\n+\thi = max;\n \n-\t*pend = acl_alloc_node(context, level+size);\n+\t*pend = acl_alloc_node(context, level + size);\n \troot = acl_alloc_node(context, level++);\n+\tprev = root;\n \n-\tif (lo[size - 1] == hi[size - 1]) {\n-\t\tacl_gen_range(context, hi, lo, size, level, root, *pend);\n-\t} else {\n-\t\tuint8_t limit_lo[64];\n-\t\tuint8_t limit_hi[64];\n-\t\tuint8_t hi_ff = UINT8_MAX;\n-\t\tuint8_t lo_00 = 0;\n+\t/* build common sub-trie till possilbe */\n+\tfor (n = size - 1; n > 0 && lo[n] == hi[n]; n--) {\n+\t\tnode = acl_alloc_node(context, level++);\n+\t\tacl_add_ptr_range(context, prev, node, lo[n], hi[n]);\n+\t\tprev = node;\n+\t}\n \n-\t\tmemset(limit_lo, 0, RTE_DIM(limit_lo));\n-\t\tmemset(limit_hi, UINT8_MAX, RTE_DIM(limit_hi));\n+\t/* no branchs needed, just one sub-trie */\n+\tif (n == 0) {\n+\t\tacl_add_ptr_range(context, prev, *pend, lo[0], hi[0]);\n+\t\treturn root;\n+\t}\n \n-\t\tfor (n = size - 2; n >= 0; n--) {\n-\t\t\thi_ff = (uint8_t)(hi_ff & hi[n]);\n-\t\t\tlo_00 = (uint8_t)(lo_00 | lo[n]);\n-\t\t}\n+\t/* gather information about divirgent paths */\n+\tlo_00 = 0;\n+\thi_ff = UINT8_MAX;\n+\tfor (k = n - 1; k >= 0; k--) {\n+\t\thi_ff &= hi[k];\n+\t\tlo_00 |= lo[k];\n+\t}\n \n-\t\tif (hi_ff != UINT8_MAX) {\n-\t\t\tlimit_lo[size - 1] = hi[size - 1];\n-\t\t\tacl_gen_range(context, hi, limit_lo, size, level,\n-\t\t\t\troot, *pend);\n-\t\t}\n+\t/* generate left (lower-bound) sub-trie */\n+\tif (lo_00 != 0)\n+\t\tacl_gen_range_low(context, prev, *pend, lo, n + 1, level);\n \n-\t\tif (lo_00 != 0) {\n-\t\t\tlimit_hi[size - 1] = lo[size - 1];\n-\t\t\tacl_gen_range(context, limit_hi, lo, size, level,\n-\t\t\t\troot, *pend);\n-\t\t}\n+\t/* generate right (upper-bound) sub-trie */\n+\tif (hi_ff != UINT8_MAX)\n+\t\tacl_gen_range_high(context, prev, *pend, hi, n + 1, level);\n \n-\t\tif (hi[size - 1] - lo[size - 1] > 1 ||\n-\t\t\t\tlo_00 == 0 ||\n-\t\t\t\thi_ff == UINT8_MAX) {\n-\t\t\tlimit_lo[size-1] = (uint8_t)(lo[size-1] + (lo_00 != 0));\n-\t\t\tlimit_hi[size-1] = (uint8_t)(hi[size-1] -\n-\t\t\t\t(hi_ff != UINT8_MAX));\n-\t\t\tacl_gen_range(context, limit_hi, limit_lo, size,\n-\t\t\t\tlevel, root, *pend);\n-\t\t}\n+\t/* generate sub-trie in the middle */\n+\tif (lo[n] + 1 != hi[n] || lo_00 == 0 || hi_ff == UINT8_MAX) {\n+\t\tlo_00 = lo[n] + (lo_00 != 0);\n+\t\thi_ff = hi[n] - (hi_ff != UINT8_MAX);\n+\t\tacl_gen_range_mdl(context, prev, *pend, lo_00, hi_ff,\n+\t\t\tn + 1, level);\n \t}\n+\n \treturn root;\n }\n \n",
    "prefixes": [
        "1/2"
    ]
}