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GET /api/patches/65538/?format=api
{ "id": 65538, "url": "http://patches.dpdk.org/api/patches/65538/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200204131258.17632-5-marcinx.smoczynski@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200204131258.17632-5-marcinx.smoczynski@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200204131258.17632-5-marcinx.smoczynski@intel.com", "date": "2020-02-04T13:12:54", "name": "[v6,4/8] test/crypto: add cpu crypto mode to tests", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "6a7712976eab39ad6bd421937863ffbbac612e6e", "submitter": { "id": 1293, "url": "http://patches.dpdk.org/api/people/1293/?format=api", "name": "Marcin Smoczynski", "email": "marcinx.smoczynski@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200204131258.17632-5-marcinx.smoczynski@intel.com/mbox/", "series": [ { "id": 8413, "url": "http://patches.dpdk.org/api/series/8413/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8413", "date": "2020-02-04T13:12:50", "name": "Introduce CPU crypto mode", "version": 6, "mbox": "http://patches.dpdk.org/series/8413/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/65538/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/65538/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 74F1BA0534;\n\tTue, 4 Feb 2020 14:13:48 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DDF3B1C1A8;\n\tTue, 4 Feb 2020 14:13:14 +0100 (CET)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by dpdk.org (Postfix) with ESMTP id 398AA1C1B5\n for <dev@dpdk.org>; Tue, 4 Feb 2020 14:13:13 +0100 (CET)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 04 Feb 2020 05:13:12 -0800", "from msmoczyx-mobl.ger.corp.intel.com ([10.103.102.190])\n by fmsmga005.fm.intel.com with ESMTP; 04 Feb 2020 05:13:11 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.70,401,1574150400\"; d=\"scan'208\";a=\"429800420\"", "From": "Marcin Smoczynski <marcinx.smoczynski@intel.com>", "To": "akhil.goyal@nxp.com, konstantin.ananyev@intel.com,\n roy.fan.zhang@intel.com,\n declan.doherty@intel.com, radu.nicolau@intel.com,\n pablo.de.lara.guarch@intel.com", "Cc": "dev@dpdk.org,\n\tMarcin Smoczynski <marcinx.smoczynski@intel.com>", "Date": "Tue, 4 Feb 2020 14:12:54 +0100", "Message-Id": "<20200204131258.17632-5-marcinx.smoczynski@intel.com>", "X-Mailer": "git-send-email 2.21.0.windows.1", "In-Reply-To": "<20200204131258.17632-1-marcinx.smoczynski@intel.com>", "References": "<20200128142220.16644-1-marcinx.smoczynski@intel.com>\n <20200204131258.17632-1-marcinx.smoczynski@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v6 4/8] test/crypto: add cpu crypto mode to tests", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds ability to run unit tests in cpu crypto mode and\nprovides test for aesni_gcm's cpu crypto implementation.\n\nSigned-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>\nSigned-off-by: Marcin Smoczynski <marcinx.smoczynski@intel.com>\n---\n app/test/test_cryptodev.c | 161 +++++++++++++++++++++++++++++++++++---\n 1 file changed, 151 insertions(+), 10 deletions(-)", "diff": "diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c\nindex b5aaca131..8748a6796 100644\n--- a/app/test/test_cryptodev.c\n+++ b/app/test/test_cryptodev.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2015-2019 Intel Corporation\n+ * Copyright(c) 2015-2020 Intel Corporation\n */\n \n #include <time.h>\n@@ -52,6 +52,9 @@\n \n static int gbl_driver_id;\n \n+static enum rte_security_session_action_type gbl_action_type =\n+\tRTE_SECURITY_ACTION_TYPE_NONE;\n+\n struct crypto_testsuite_params {\n \tstruct rte_mempool *mbuf_pool;\n \tstruct rte_mempool *large_mbuf_pool;\n@@ -139,9 +142,95 @@ ceil_byte_length(uint32_t num_bits)\n \t\treturn (num_bits >> 3);\n }\n \n+static void\n+process_cpu_gmac_op(uint8_t dev_id, struct rte_crypto_op *op)\n+{\n+\tint32_t n, st;\n+\tvoid *iv;\n+\tstruct rte_crypto_sym_op *sop;\n+\tunion rte_crypto_sym_ofs ofs;\n+\tstruct rte_crypto_sgl sgl;\n+\tstruct rte_crypto_sym_vec symvec;\n+\tstruct rte_crypto_vec vec[UINT8_MAX];\n+\n+\tsop = op->sym;\n+\n+\tn = rte_crypto_mbuf_to_vec(sop->m_src, sop->auth.data.offset,\n+\t\tsop->auth.data.length, vec, RTE_DIM(vec));\n+\n+\tif (n < 0 || n != sop->m_src->nb_segs) {\n+\t\top->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\treturn;\n+\t}\n+\n+\tsgl.vec = vec;\n+\tsgl.num = n;\n+\tsymvec.sgl = &sgl;\n+\tiv = rte_crypto_op_ctod_offset(op, void *, IV_OFFSET);\n+\tsymvec.iv = &iv;\n+\tsymvec.aad = NULL;\n+\tsymvec.digest = (void **)&sop->auth.digest.data;\n+\tsymvec.status = &st;\n+\tsymvec.num = 1;\n+\n+\tofs.raw = 0;\n+\n+\tn = rte_cryptodev_sym_cpu_crypto_process(dev_id, sop->session, ofs,\n+\t\t&symvec);\n+\n+\tif (n != 1)\n+\t\top->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;\n+\telse\n+\t\top->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+}\n+\n+\n+static void\n+process_cpu_aead_op(uint8_t dev_id, struct rte_crypto_op *op)\n+{\n+\tint32_t n, st;\n+\tvoid *iv;\n+\tstruct rte_crypto_sym_op *sop;\n+\tunion rte_crypto_sym_ofs ofs;\n+\tstruct rte_crypto_sgl sgl;\n+\tstruct rte_crypto_sym_vec symvec;\n+\tstruct rte_crypto_vec vec[UINT8_MAX];\n+\n+\tsop = op->sym;\n+\n+\tn = rte_crypto_mbuf_to_vec(sop->m_src, sop->aead.data.offset,\n+\t\tsop->aead.data.length, vec, RTE_DIM(vec));\n+\n+\tif (n < 0 || n != sop->m_src->nb_segs) {\n+\t\top->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\treturn;\n+\t}\n+\n+\tsgl.vec = vec;\n+\tsgl.num = n;\n+\tsymvec.sgl = &sgl;\n+\tiv = rte_crypto_op_ctod_offset(op, void *, IV_OFFSET);\n+\tsymvec.iv = &iv;\n+\tsymvec.aad = (void **)&sop->aead.aad.data;\n+\tsymvec.digest = (void **)&sop->aead.digest.data;\n+\tsymvec.status = &st;\n+\tsymvec.num = 1;\n+\n+\tofs.raw = 0;\n+\n+\tn = rte_cryptodev_sym_cpu_crypto_process(dev_id, sop->session, ofs,\n+\t\t&symvec);\n+\n+\tif (n != 1)\n+\t\top->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;\n+\telse\n+\t\top->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+}\n+\n static struct rte_crypto_op *\n process_crypto_request(uint8_t dev_id, struct rte_crypto_op *op)\n {\n+\n \tif (rte_cryptodev_enqueue_burst(dev_id, 0, &op, 1) != 1) {\n \t\tRTE_LOG(ERR, USER1, \"Error sending packet for encryption\\n\");\n \t\treturn NULL;\n@@ -7862,7 +7951,11 @@ test_authenticated_encryption(const struct aead_test_data *tdata)\n \tut_params->op->sym->m_src = ut_params->ibuf;\n \n \t/* Process crypto operation */\n-\tTEST_ASSERT_NOT_NULL(process_crypto_request(ts_params->valid_devs[0],\n+\tif (gbl_action_type == RTE_SECURITY_ACTION_TYPE_CPU_CRYPTO)\n+\t\tprocess_cpu_aead_op(ts_params->valid_devs[0], ut_params->op);\n+\telse\n+\t\tTEST_ASSERT_NOT_NULL(\n+\t\t\tprocess_crypto_request(ts_params->valid_devs[0],\n \t\t\tut_params->op), \"failed to process sym crypto op\");\n \n \tTEST_ASSERT_EQUAL(ut_params->op->status, RTE_CRYPTO_OP_STATUS_SUCCESS,\n@@ -8760,7 +8853,11 @@ test_authenticated_decryption(const struct aead_test_data *tdata)\n \tut_params->op->sym->m_src = ut_params->ibuf;\n \n \t/* Process crypto operation */\n-\tTEST_ASSERT_NOT_NULL(process_crypto_request(ts_params->valid_devs[0],\n+\tif (gbl_action_type == RTE_SECURITY_ACTION_TYPE_CPU_CRYPTO)\n+\t\tprocess_cpu_aead_op(ts_params->valid_devs[0], ut_params->op);\n+\telse\n+\t\tTEST_ASSERT_NOT_NULL(\n+\t\t\tprocess_crypto_request(ts_params->valid_devs[0],\n \t\t\tut_params->op), \"failed to process sym crypto op\");\n \n \tTEST_ASSERT_EQUAL(ut_params->op->status, RTE_CRYPTO_OP_STATUS_SUCCESS,\n@@ -10467,7 +10564,11 @@ test_AES_GMAC_authentication(const struct gmac_test_data *tdata)\n \n \tut_params->op->sym->m_src = ut_params->ibuf;\n \n-\tTEST_ASSERT_NOT_NULL(process_crypto_request(ts_params->valid_devs[0],\n+\tif (gbl_action_type == RTE_SECURITY_ACTION_TYPE_CPU_CRYPTO)\n+\t\tprocess_cpu_gmac_op(ts_params->valid_devs[0], ut_params->op);\n+\telse\n+\t\tTEST_ASSERT_NOT_NULL(\n+\t\t\tprocess_crypto_request(ts_params->valid_devs[0],\n \t\t\tut_params->op), \"failed to process sym crypto op\");\n \n \tTEST_ASSERT_EQUAL(ut_params->op->status, RTE_CRYPTO_OP_STATUS_SUCCESS,\n@@ -10571,14 +10672,17 @@ test_AES_GMAC_authentication_verify(const struct gmac_test_data *tdata)\n \n \tut_params->op->sym->m_src = ut_params->ibuf;\n \n-\tTEST_ASSERT_NOT_NULL(process_crypto_request(ts_params->valid_devs[0],\n+\tif (gbl_action_type == RTE_SECURITY_ACTION_TYPE_CPU_CRYPTO)\n+\t\tprocess_cpu_gmac_op(ts_params->valid_devs[0], ut_params->op);\n+\telse\n+\t\tTEST_ASSERT_NOT_NULL(\n+\t\t\tprocess_crypto_request(ts_params->valid_devs[0],\n \t\t\tut_params->op), \"failed to process sym crypto op\");\n \n \tTEST_ASSERT_EQUAL(ut_params->op->status, RTE_CRYPTO_OP_STATUS_SUCCESS,\n \t\t\t\"crypto op processing failed\");\n \n \treturn 0;\n-\n }\n \n static int\n@@ -11176,10 +11280,16 @@ test_authentication_verify_GMAC_fail_when_corruption(\n \telse\n \t\ttag_corruption(plaintext, reference->aad.len);\n \n-\tut_params->op = process_crypto_request(ts_params->valid_devs[0],\n+\tif (gbl_action_type == RTE_SECURITY_ACTION_TYPE_CPU_CRYPTO) {\n+\t\tprocess_cpu_gmac_op(ts_params->valid_devs[0], ut_params->op);\n+\t\tTEST_ASSERT_NOT_EQUAL(ut_params->op->status,\n+\t\t\tRTE_CRYPTO_OP_STATUS_SUCCESS,\n+\t\t\t\"authentication not failed\");\n+\t} else {\n+\t\tut_params->op = process_crypto_request(ts_params->valid_devs[0],\n \t\t\tut_params->op);\n-\n-\tTEST_ASSERT_NULL(ut_params->op, \"authentication not failed\");\n+\t\tTEST_ASSERT_NULL(ut_params->op, \"authentication not failed\");\n+\t}\n \n \treturn 0;\n }\n@@ -11708,7 +11818,12 @@ test_authenticated_encryption_SGL(const struct aead_test_data *tdata,\n \t\tut_params->op->sym->m_dst = ut_params->obuf;\n \n \t/* Process crypto operation */\n-\tTEST_ASSERT_NOT_NULL(process_crypto_request(ts_params->valid_devs[0],\n+\tif (oop == IN_PLACE &&\n+\t\t\tgbl_action_type == RTE_SECURITY_ACTION_TYPE_CPU_CRYPTO)\n+\t\tprocess_cpu_aead_op(ts_params->valid_devs[0], ut_params->op);\n+\telse\n+\t\tTEST_ASSERT_NOT_NULL(\n+\t\t\tprocess_crypto_request(ts_params->valid_devs[0],\n \t\t\tut_params->op), \"failed to process sym crypto op\");\n \n \tTEST_ASSERT_EQUAL(ut_params->op->status, RTE_CRYPTO_OP_STATUS_SUCCESS,\n@@ -14620,6 +14735,30 @@ test_cryptodev_aesni_gcm(void)\n \treturn unit_test_suite_runner(&cryptodev_aesni_gcm_testsuite);\n }\n \n+static int\n+test_cryptodev_cpu_aesni_gcm(void)\n+{\n+\tint32_t rc;\n+\tenum rte_security_session_action_type at;\n+\n+\tgbl_driver_id = rte_cryptodev_driver_id_get(\n+\t\t\tRTE_STR(CRYPTODEV_NAME_AESNI_GCM_PMD));\n+\n+\tif (gbl_driver_id == -1) {\n+\t\tRTE_LOG(ERR, USER1, \"AESNI GCM PMD must be loaded. Check if \"\n+\t\t\t\t\"CONFIG_RTE_LIBRTE_PMD_AESNI_GCM is enabled \"\n+\t\t\t\t\"in config file to run this testsuite.\\n\");\n+\t\treturn TEST_SKIPPED;\n+\t}\n+\n+\tat = gbl_action_type;\n+\tgbl_action_type = RTE_SECURITY_ACTION_TYPE_CPU_CRYPTO;\n+\trc = unit_test_suite_runner(&cryptodev_aesni_gcm_testsuite);\n+\tgbl_action_type = at;\n+\treturn rc;\n+}\n+\n+\n static int\n test_cryptodev_null(void)\n {\n@@ -14858,6 +14997,8 @@ REGISTER_TEST_COMMAND(cryptodev_qat_autotest, test_cryptodev_qat);\n REGISTER_TEST_COMMAND(cryptodev_aesni_mb_autotest, test_cryptodev_aesni_mb);\n REGISTER_TEST_COMMAND(cryptodev_openssl_autotest, test_cryptodev_openssl);\n REGISTER_TEST_COMMAND(cryptodev_aesni_gcm_autotest, test_cryptodev_aesni_gcm);\n+REGISTER_TEST_COMMAND(cryptodev_cpu_aesni_gcm_autotest,\n+\ttest_cryptodev_cpu_aesni_gcm);\n REGISTER_TEST_COMMAND(cryptodev_null_autotest, test_cryptodev_null);\n REGISTER_TEST_COMMAND(cryptodev_sw_snow3g_autotest, test_cryptodev_sw_snow3g);\n REGISTER_TEST_COMMAND(cryptodev_sw_kasumi_autotest, test_cryptodev_sw_kasumi);\n", "prefixes": [ "v6", "4/8" ] }