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GET /api/patches/65536/?format=api
{ "id": 65536, "url": "http://patches.dpdk.org/api/patches/65536/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200204131258.17632-3-marcinx.smoczynski@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200204131258.17632-3-marcinx.smoczynski@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200204131258.17632-3-marcinx.smoczynski@intel.com", "date": "2020-02-04T13:12:52", "name": "[v6,2/8] crypto/aesni_gcm: cpu crypto support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "bf0a9a8c669278cfa3f7b44b6eab2b59101be96b", "submitter": { "id": 1293, "url": "http://patches.dpdk.org/api/people/1293/?format=api", "name": "Marcin Smoczynski", "email": "marcinx.smoczynski@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200204131258.17632-3-marcinx.smoczynski@intel.com/mbox/", "series": [ { "id": 8413, "url": "http://patches.dpdk.org/api/series/8413/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8413", "date": "2020-02-04T13:12:50", "name": "Introduce CPU crypto mode", "version": 6, "mbox": "http://patches.dpdk.org/series/8413/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/65536/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/65536/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B846CA0534;\n\tTue, 4 Feb 2020 14:13:26 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B7DC01C19E;\n\tTue, 4 Feb 2020 14:13:10 +0100 (CET)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by dpdk.org (Postfix) with ESMTP id E2EAC1C139\n for <dev@dpdk.org>; Tue, 4 Feb 2020 14:13:08 +0100 (CET)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 04 Feb 2020 05:13:08 -0800", "from msmoczyx-mobl.ger.corp.intel.com ([10.103.102.190])\n by fmsmga005.fm.intel.com with ESMTP; 04 Feb 2020 05:13:06 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.70,401,1574150400\"; d=\"scan'208\";a=\"429800378\"", "From": "Marcin Smoczynski <marcinx.smoczynski@intel.com>", "To": "akhil.goyal@nxp.com, konstantin.ananyev@intel.com,\n roy.fan.zhang@intel.com,\n declan.doherty@intel.com, radu.nicolau@intel.com,\n pablo.de.lara.guarch@intel.com", "Cc": "dev@dpdk.org,\n\tMarcin Smoczynski <marcinx.smoczynski@intel.com>", "Date": "Tue, 4 Feb 2020 14:12:52 +0100", "Message-Id": "<20200204131258.17632-3-marcinx.smoczynski@intel.com>", "X-Mailer": "git-send-email 2.21.0.windows.1", "In-Reply-To": "<20200204131258.17632-1-marcinx.smoczynski@intel.com>", "References": "<20200128142220.16644-1-marcinx.smoczynski@intel.com>\n <20200204131258.17632-1-marcinx.smoczynski@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v6 2/8] crypto/aesni_gcm: cpu crypto support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support for CPU crypto mode by introducing required handler.\nAuthenticated encryption and decryption are supported with tag\ngeneration/verification.\n\nCPU crypto support include both AES-GCM and GMAC algorithms.\n\nSigned-off-by: Marcin Smoczynski <marcinx.smoczynski@intel.com>\nAcked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>\nAcked-by: Fan Zhang <roy.fan.zhang@intel.com>\nTested-by: Konstantin Ananyev <konstantin.ananyev@intel.com>\nAcked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>\n---\n doc/guides/cryptodevs/aesni_gcm.rst | 7 +-\n doc/guides/cryptodevs/features/aesni_gcm.ini | 1 +\n drivers/crypto/aesni_gcm/aesni_gcm_ops.h | 11 +-\n drivers/crypto/aesni_gcm/aesni_gcm_pmd.c | 222 +++++++++++++++++-\n drivers/crypto/aesni_gcm/aesni_gcm_pmd_ops.c | 4 +-\n .../crypto/aesni_gcm/aesni_gcm_pmd_private.h | 13 +-\n 6 files changed, 247 insertions(+), 11 deletions(-)", "diff": "diff --git a/doc/guides/cryptodevs/aesni_gcm.rst b/doc/guides/cryptodevs/aesni_gcm.rst\nindex 151aa3060..a25b63109 100644\n--- a/doc/guides/cryptodevs/aesni_gcm.rst\n+++ b/doc/guides/cryptodevs/aesni_gcm.rst\n@@ -1,5 +1,5 @@\n .. SPDX-License-Identifier: BSD-3-Clause\n- Copyright(c) 2016-2019 Intel Corporation.\n+ Copyright(c) 2016-2020 Intel Corporation.\n \n AES-NI GCM Crypto Poll Mode Driver\n ==================================\n@@ -9,6 +9,11 @@ The AES-NI GCM PMD (**librte_pmd_aesni_gcm**) provides poll mode crypto driver\n support for utilizing Intel multi buffer library (see AES-NI Multi-buffer PMD documentation\n to learn more about it, including installation).\n \n+The AES-NI GCM PMD supports synchronous mode of operation with\n+``rte_cryptodev_sym_cpu_crypto_process`` function call for both AES-GCM and\n+GMAC, however GMAC support is limited to one segment per operation. Please\n+refer to ``rte_crypto`` programmer's guide for more detail.\n+\n Features\n --------\n \ndiff --git a/doc/guides/cryptodevs/features/aesni_gcm.ini b/doc/guides/cryptodevs/features/aesni_gcm.ini\nindex 87eac0fbf..949d6a088 100644\n--- a/doc/guides/cryptodevs/features/aesni_gcm.ini\n+++ b/doc/guides/cryptodevs/features/aesni_gcm.ini\n@@ -14,6 +14,7 @@ CPU AVX512 = Y\n In Place SGL = Y\n OOP SGL In LB Out = Y\n OOP LB In LB Out = Y\n+CPU crypto = Y\n ;\n ; Supported crypto algorithms of the 'aesni_gcm' crypto driver.\n ;\ndiff --git a/drivers/crypto/aesni_gcm/aesni_gcm_ops.h b/drivers/crypto/aesni_gcm/aesni_gcm_ops.h\nindex e272f1067..74acac09c 100644\n--- a/drivers/crypto/aesni_gcm/aesni_gcm_ops.h\n+++ b/drivers/crypto/aesni_gcm/aesni_gcm_ops.h\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2016-2017 Intel Corporation\n+ * Copyright(c) 2016-2020 Intel Corporation\n */\n \n #ifndef _AESNI_GCM_OPS_H_\n@@ -65,4 +65,13 @@ struct aesni_gcm_ops {\n \taesni_gcm_finalize_t finalize_dec;\n };\n \n+/** GCM per-session operation handlers */\n+struct aesni_gcm_session_ops {\n+\taesni_gcm_t cipher;\n+\taesni_gcm_pre_t pre;\n+\taesni_gcm_init_t init;\n+\taesni_gcm_update_t update;\n+\taesni_gcm_finalize_t finalize;\n+};\n+\n #endif /* _AESNI_GCM_OPS_H_ */\ndiff --git a/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c b/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c\nindex 1a03be31d..a1caab993 100644\n--- a/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c\n+++ b/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2016-2017 Intel Corporation\n+ * Copyright(c) 2016-2020 Intel Corporation\n */\n \n #include <rte_common.h>\n@@ -15,6 +15,31 @@\n \n static uint8_t cryptodev_driver_id;\n \n+/* setup session handlers */\n+static void\n+set_func_ops(struct aesni_gcm_session *s, const struct aesni_gcm_ops *gcm_ops)\n+{\n+\ts->ops.pre = gcm_ops->pre;\n+\ts->ops.init = gcm_ops->init;\n+\n+\tswitch (s->op) {\n+\tcase AESNI_GCM_OP_AUTHENTICATED_ENCRYPTION:\n+\t\ts->ops.cipher = gcm_ops->enc;\n+\t\ts->ops.update = gcm_ops->update_enc;\n+\t\ts->ops.finalize = gcm_ops->finalize_enc;\n+\t\tbreak;\n+\tcase AESNI_GCM_OP_AUTHENTICATED_DECRYPTION:\n+\t\ts->ops.cipher = gcm_ops->dec;\n+\t\ts->ops.update = gcm_ops->update_dec;\n+\t\ts->ops.finalize = gcm_ops->finalize_dec;\n+\t\tbreak;\n+\tcase AESNI_GMAC_OP_GENERATE:\n+\tcase AESNI_GMAC_OP_VERIFY:\n+\t\ts->ops.finalize = gcm_ops->finalize_enc;\n+\t\tbreak;\n+\t}\n+}\n+\n /** Parse crypto xform chain and set private session parameters */\n int\n aesni_gcm_set_session_parameters(const struct aesni_gcm_ops *gcm_ops,\n@@ -65,6 +90,7 @@ aesni_gcm_set_session_parameters(const struct aesni_gcm_ops *gcm_ops,\n \t\t/* Select Crypto operation */\n \t\tif (aead_xform->aead.op == RTE_CRYPTO_AEAD_OP_ENCRYPT)\n \t\t\tsess->op = AESNI_GCM_OP_AUTHENTICATED_ENCRYPTION;\n+\t\t/* op == RTE_CRYPTO_AEAD_OP_DECRYPT */\n \t\telse\n \t\t\tsess->op = AESNI_GCM_OP_AUTHENTICATED_DECRYPTION;\n \n@@ -78,7 +104,6 @@ aesni_gcm_set_session_parameters(const struct aesni_gcm_ops *gcm_ops,\n \t\treturn -ENOTSUP;\n \t}\n \n-\n \t/* IV check */\n \tif (sess->iv.length != 16 && sess->iv.length != 12 &&\n \t\t\tsess->iv.length != 0) {\n@@ -102,6 +127,10 @@ aesni_gcm_set_session_parameters(const struct aesni_gcm_ops *gcm_ops,\n \t\treturn -EINVAL;\n \t}\n \n+\t/* setup session handlers */\n+\tset_func_ops(sess, &gcm_ops[sess->key]);\n+\n+\t/* pre-generate key */\n \tgcm_ops[sess->key].pre(key, &sess->gdata_key);\n \n \t/* Digest check */\n@@ -356,6 +385,191 @@ process_gcm_crypto_op(struct aesni_gcm_qp *qp, struct rte_crypto_op *op,\n \treturn 0;\n }\n \n+static inline void\n+aesni_gcm_fill_error_code(struct rte_crypto_sym_vec *vec, int32_t errnum)\n+{\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < vec->num; i++)\n+\t\tvec->status[i] = errnum;\n+}\n+\n+\n+static inline int32_t\n+aesni_gcm_sgl_op_finalize_encryption(const struct aesni_gcm_session *s,\n+\tstruct gcm_context_data *gdata_ctx, uint8_t *digest)\n+{\n+\tif (s->req_digest_length != s->gen_digest_length) {\n+\t\tuint8_t tmpdigest[s->gen_digest_length];\n+\n+\t\ts->ops.finalize(&s->gdata_key, gdata_ctx, tmpdigest,\n+\t\t\ts->gen_digest_length);\n+\t\tmemcpy(digest, tmpdigest, s->req_digest_length);\n+\t} else {\n+\t\ts->ops.finalize(&s->gdata_key, gdata_ctx, digest,\n+\t\t\ts->gen_digest_length);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static inline int32_t\n+aesni_gcm_sgl_op_finalize_decryption(const struct aesni_gcm_session *s,\n+\tstruct gcm_context_data *gdata_ctx, uint8_t *digest)\n+{\n+\tuint8_t tmpdigest[s->gen_digest_length];\n+\n+\ts->ops.finalize(&s->gdata_key, gdata_ctx, tmpdigest,\n+\t\ts->gen_digest_length);\n+\n+\treturn memcmp(digest, tmpdigest, s->req_digest_length) == 0 ? 0 :\n+\t\tEBADMSG;\n+}\n+\n+static inline void\n+aesni_gcm_process_gcm_sgl_op(const struct aesni_gcm_session *s,\n+\tstruct gcm_context_data *gdata_ctx, struct rte_crypto_sgl *sgl,\n+\tvoid *iv, void *aad)\n+{\n+\tuint32_t i;\n+\n+\t/* init crypto operation */\n+\ts->ops.init(&s->gdata_key, gdata_ctx, iv, aad,\n+\t\t(uint64_t)s->aad_length);\n+\n+\t/* update with sgl data */\n+\tfor (i = 0; i < sgl->num; i++) {\n+\t\tstruct rte_crypto_vec *vec = &sgl->vec[i];\n+\n+\t\ts->ops.update(&s->gdata_key, gdata_ctx, vec->base, vec->base,\n+\t\t\tvec->len);\n+\t}\n+}\n+\n+static inline void\n+aesni_gcm_process_gmac_sgl_op(const struct aesni_gcm_session *s,\n+\tstruct gcm_context_data *gdata_ctx, struct rte_crypto_sgl *sgl,\n+\tvoid *iv)\n+{\n+\ts->ops.init(&s->gdata_key, gdata_ctx, iv, sgl->vec[0].base,\n+\t\tsgl->vec[0].len);\n+}\n+\n+static inline uint32_t\n+aesni_gcm_sgl_encrypt(struct aesni_gcm_session *s,\n+\tstruct gcm_context_data *gdata_ctx, struct rte_crypto_sym_vec *vec)\n+{\n+\tuint32_t i, processed;\n+\n+\tprocessed = 0;\n+\tfor (i = 0; i < vec->num; ++i) {\n+\t\taesni_gcm_process_gcm_sgl_op(s, gdata_ctx,\n+\t\t\t&vec->sgl[i], vec->iv[i], vec->aad[i]);\n+\t\tvec->status[i] = aesni_gcm_sgl_op_finalize_encryption(s,\n+\t\t\tgdata_ctx, vec->digest[i]);\n+\t\tprocessed += (vec->status[i] == 0);\n+\t}\n+\n+\treturn processed;\n+}\n+\n+static inline uint32_t\n+aesni_gcm_sgl_decrypt(struct aesni_gcm_session *s,\n+\tstruct gcm_context_data *gdata_ctx, struct rte_crypto_sym_vec *vec)\n+{\n+\tuint32_t i, processed;\n+\n+\tprocessed = 0;\n+\tfor (i = 0; i < vec->num; ++i) {\n+\t\taesni_gcm_process_gcm_sgl_op(s, gdata_ctx,\n+\t\t\t&vec->sgl[i], vec->iv[i], vec->aad[i]);\n+\t\t vec->status[i] = aesni_gcm_sgl_op_finalize_decryption(s,\n+\t\t\tgdata_ctx, vec->digest[i]);\n+\t\tprocessed += (vec->status[i] == 0);\n+\t}\n+\n+\treturn processed;\n+}\n+\n+static inline uint32_t\n+aesni_gmac_sgl_generate(struct aesni_gcm_session *s,\n+\tstruct gcm_context_data *gdata_ctx, struct rte_crypto_sym_vec *vec)\n+{\n+\tuint32_t i, processed;\n+\n+\tprocessed = 0;\n+\tfor (i = 0; i < vec->num; ++i) {\n+\t\tif (vec->sgl[i].num != 1) {\n+\t\t\tvec->status[i] = ENOTSUP;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\taesni_gcm_process_gmac_sgl_op(s, gdata_ctx,\n+\t\t\t&vec->sgl[i], vec->iv[i]);\n+\t\tvec->status[i] = aesni_gcm_sgl_op_finalize_encryption(s,\n+\t\t\tgdata_ctx, vec->digest[i]);\n+\t\tprocessed += (vec->status[i] == 0);\n+\t}\n+\n+\treturn processed;\n+}\n+\n+static inline uint32_t\n+aesni_gmac_sgl_verify(struct aesni_gcm_session *s,\n+\tstruct gcm_context_data *gdata_ctx, struct rte_crypto_sym_vec *vec)\n+{\n+\tuint32_t i, processed;\n+\n+\tprocessed = 0;\n+\tfor (i = 0; i < vec->num; ++i) {\n+\t\tif (vec->sgl[i].num != 1) {\n+\t\t\tvec->status[i] = ENOTSUP;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\taesni_gcm_process_gmac_sgl_op(s, gdata_ctx,\n+\t\t\t&vec->sgl[i], vec->iv[i]);\n+\t\tvec->status[i] = aesni_gcm_sgl_op_finalize_decryption(s,\n+\t\t\tgdata_ctx, vec->digest[i]);\n+\t\tprocessed += (vec->status[i] == 0);\n+\t}\n+\n+\treturn processed;\n+}\n+\n+/** Process CPU crypto bulk operations */\n+uint32_t\n+aesni_gcm_pmd_cpu_crypto_process(struct rte_cryptodev *dev,\n+\tstruct rte_cryptodev_sym_session *sess,\n+\t__rte_unused union rte_crypto_sym_ofs ofs,\n+\tstruct rte_crypto_sym_vec *vec)\n+{\n+\tvoid *sess_priv;\n+\tstruct aesni_gcm_session *s;\n+\tstruct gcm_context_data gdata_ctx;\n+\n+\tsess_priv = get_sym_session_private_data(sess, dev->driver_id);\n+\tif (unlikely(sess_priv == NULL)) {\n+\t\taesni_gcm_fill_error_code(vec, EINVAL);\n+\t\treturn 0;\n+\t}\n+\n+\ts = sess_priv;\n+\tswitch (s->op) {\n+\tcase AESNI_GCM_OP_AUTHENTICATED_ENCRYPTION:\n+\t\treturn aesni_gcm_sgl_encrypt(s, &gdata_ctx, vec);\n+\tcase AESNI_GCM_OP_AUTHENTICATED_DECRYPTION:\n+\t\treturn aesni_gcm_sgl_decrypt(s, &gdata_ctx, vec);\n+\tcase AESNI_GMAC_OP_GENERATE:\n+\t\treturn aesni_gmac_sgl_generate(s, &gdata_ctx, vec);\n+\tcase AESNI_GMAC_OP_VERIFY:\n+\t\treturn aesni_gmac_sgl_verify(s, &gdata_ctx, vec);\n+\tdefault:\n+\t\taesni_gcm_fill_error_code(vec, EINVAL);\n+\t\treturn 0;\n+\t}\n+}\n+\n /**\n * Process a completed job and return rte_mbuf which job processed\n *\n@@ -527,7 +741,8 @@ aesni_gcm_create(const char *name,\n \t\t\tRTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |\n \t\t\tRTE_CRYPTODEV_FF_IN_PLACE_SGL |\n \t\t\tRTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |\n-\t\t\tRTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT;\n+\t\t\tRTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT |\n+\t\t\tRTE_CRYPTODEV_FF_SYM_CPU_CRYPTO;\n \n \t/* Check CPU for support for AES instruction set */\n \tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AES))\n@@ -672,7 +887,6 @@ RTE_PMD_REGISTER_PARAM_STRING(CRYPTODEV_NAME_AESNI_GCM_PMD,\n RTE_PMD_REGISTER_CRYPTO_DRIVER(aesni_gcm_crypto_drv, aesni_gcm_pmd_drv.driver,\n \t\tcryptodev_driver_id);\n \n-\n RTE_INIT(aesni_gcm_init_log)\n {\n \taesni_gcm_logtype_driver = rte_log_register(\"pmd.crypto.aesni_gcm\");\ndiff --git a/drivers/crypto/aesni_gcm/aesni_gcm_pmd_ops.c b/drivers/crypto/aesni_gcm/aesni_gcm_pmd_ops.c\nindex 2f66c7c58..c5e0878f5 100644\n--- a/drivers/crypto/aesni_gcm/aesni_gcm_pmd_ops.c\n+++ b/drivers/crypto/aesni_gcm/aesni_gcm_pmd_ops.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2016 Intel Corporation\n+ * Copyright(c) 2016-2020 Intel Corporation\n */\n \n #include <string.h>\n@@ -331,6 +331,8 @@ struct rte_cryptodev_ops aesni_gcm_pmd_ops = {\n \t\t.queue_pair_release\t= aesni_gcm_pmd_qp_release,\n \t\t.queue_pair_count\t= aesni_gcm_pmd_qp_count,\n \n+\t\t.sym_cpu_process = aesni_gcm_pmd_cpu_crypto_process,\n+\n \t\t.sym_session_get_size\t= aesni_gcm_pmd_sym_session_get_size,\n \t\t.sym_session_configure\t= aesni_gcm_pmd_sym_session_configure,\n \t\t.sym_session_clear\t= aesni_gcm_pmd_sym_session_clear\ndiff --git a/drivers/crypto/aesni_gcm/aesni_gcm_pmd_private.h b/drivers/crypto/aesni_gcm/aesni_gcm_pmd_private.h\nindex 2039adb53..080d4f7e4 100644\n--- a/drivers/crypto/aesni_gcm/aesni_gcm_pmd_private.h\n+++ b/drivers/crypto/aesni_gcm/aesni_gcm_pmd_private.h\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2016-2017 Intel Corporation\n+ * Copyright(c) 2016-2020 Intel Corporation\n */\n \n #ifndef _AESNI_GCM_PMD_PRIVATE_H_\n@@ -92,6 +92,8 @@ struct aesni_gcm_session {\n \t/**< GCM key type */\n \tstruct gcm_key_data gdata_key;\n \t/**< GCM parameters */\n+\tstruct aesni_gcm_session_ops ops;\n+\t/**< Session handlers */\n };\n \n \n@@ -109,10 +111,13 @@ aesni_gcm_set_session_parameters(const struct aesni_gcm_ops *ops,\n \t\tstruct aesni_gcm_session *sess,\n \t\tconst struct rte_crypto_sym_xform *xform);\n \n-\n-/**\n- * Device specific operations function pointer structure */\n+/* Device specific operations function pointer structure */\n extern struct rte_cryptodev_ops *rte_aesni_gcm_pmd_ops;\n \n+/** CPU crypto bulk process handler */\n+uint32_t\n+aesni_gcm_pmd_cpu_crypto_process(struct rte_cryptodev *dev,\n+\tstruct rte_cryptodev_sym_session *sess, union rte_crypto_sym_ofs ofs,\n+\tstruct rte_crypto_sym_vec *vec);\n \n #endif /* _AESNI_GCM_PMD_PRIVATE_H_ */\n", "prefixes": [ "v6", "2/8" ] }